Changeset 145 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp

Timestamp:

Oct 13, 2010, 8:15:51 PM (14 years ago)

Author:

rosiere

Message:

1) add test with SPECINT2K
2) new config of Selftest
3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table)
4) add Function_pointer but need fix

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (modified) (5 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp

@@ -33 +33 @@
   (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR                ) or  \
     (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND             ) or  \
+    (state == CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE          ) or  \
     (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE         ))?PRIORITY_MISS_BRANCH: \
    ((state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:                           \
@@ -112 +113 @@
 //                  state = CONTEXT_STATE_OK;
                     state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE :
+                {
+                  if (inst_all == 0)
+//                  state = CONTEXT_STATE_OK;
+                    state = CONTEXT_STATE_OK;
                   break;
                 }
@@ -321 +329 @@
                       if (can_continue)
                         reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
-                      else
-                        {
-// #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)
-//                           reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
-// #else
-                          reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;
-// #endif
-                        }
+                      else 
+                        // cf UPT : dest_val = direction, accurate depend of jump type (e.g. jr is inacurate)
+                        // reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;
+                        reg_STATE                [i] =  CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE;
 
                       reg_EVENT_ADDRESS          [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
@@ -647 +651 @@
                         case CONTEXT_STATE_KO_MISS_BRANCH_ADDR             :
                         case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND          :
+                        case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE       :
                         case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR    :
                         case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND :
@@ -752 +757 @@
           case CONTEXT_STATE_KO_EXCEP_SPR                       : (*_stat_nb_cycle_state_ko_excep                [i])++; break;
 
+          case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE          : 
           case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE         : 
           case CONTEXT_STATE_KO_MISS_BRANCH_ADDR                :