Ignore:
Timestamp:
Oct 13, 2010, 8:15:51 PM (14 years ago)
Author:
rosiere
Message:

1) add test with SPECINT2K
2) new config of Selftest
3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table)
4) add Function_pointer but need fix

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic
Files:
52 added
14 edited
45 moved

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile

    r88 r145  
    22# $Id$
    33#
    4 # [ Description ]
     4# [ Description ]
    55#
    66# Makefile
    77#
    88
    9 #-----[ Directory ]----------------------------------------
    10 DIR_MORPHEO                     = ../../../../..
     9#-----[ Directory ]----------------------------------------
     10DIR_COMPONENT                   = ../
     11include                         $(DIR_COMPONENT)/Makefile.defs
    1112
    1213LIBRARY                         = $(RegisterFile_Monolithic_LIBRARY)
    … …  
    1415DIR_LIBRARY                     = $(RegisterFile_Monolithic_DIR_LIBRARY)
    1516
    16 #-----[ include ]------------------------------------------
     17#-----[ include ]------------------------------------------
    1718
    18 all                             : library
     19all                             :
    1920                                @$(MAKE) all_selftest
    2021

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info

    r139 r145  
    11
    2 # RegisterFile_Monolithic_0
    3 target_dep      all     RegisterFile_Monolithic_0.ngc
    4 target_dep      RegisterFile_Monolithic_0.ngc   RegisterFile_Monolithic_0.prj
    5 target_dep      RegisterFile_Monolithic_0.prj   RegisterFile_Monolithic_0_Pack.vhdl RegisterFile_Monolithic_0.vhdl
     2# debug_0
     3target_dep      all     debug_0.ngc
     4target_dep      debug_0.ngc     debug_0.prj
     5target_dep      debug_0.prj     debug_0_Pack.vhdl debug_0.vhdl
    66

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h

    r138 r145  
    2222#include "Behavioural/include/Stat.h"
    2323#endif
    24 #include "Behavioural/include/Component.h"
     24// #include "Behavioural/include/Component.h"
    2525#ifdef VHDL
    2626#include "Behavioural/include/Vhdl.h"
    … …  
    2828#include "Behavioural/include/Usage.h"
    2929
     30
     31
    3032namespace morpheo                    {
    3133namespace behavioural                {
     34
     35  class Component;
     36  class Interfaces;
     37
    3238namespace generic                    {
    3339namespace registerfile               {
    3440namespace registerfile_monolithic    {
     41
     42// #define VHDL_GAISLER
    3543
    3644  typedef enum {RW_READ, RW_WRITE} rw_t;

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Types.h

    r128 r145  
    1717namespace registerfile_monolithic    {
    1818
    19 //   typedef uint32_t Taddress_t;
     19//typedef uint32_t Taddress_t;
     20//typedef uint64_t Tdata_t;
    2021  typedef Tgeneral_data_t Tdata_t;
    2122 

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp

    r112 r145  
    88#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h"
    99#include "Behavioural/include/Allocation.h"
     10#include "Behavioural/include/Component.h"
    1011
    1112namespace morpheo                    {

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp

    r112 r145  
    88#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h"
    99#include "Behavioural/include/Allocation.h"
     10#include "Behavioural/include/Component.h"
    1011
    1112namespace morpheo                    {

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl.cpp

    r81 r145  
    1010#include "Behavioural/include/Vhdl.h"
    1111#include "Common/include/ToString.h"
     12#include "Behavioural/include/Component.h"
     13
    1214namespace morpheo                    {
    1315namespace behavioural                {

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp

    r101 r145  
    1717  void RegisterFile_Monolithic::vhdl_body (Vhdl * & vhdl)
    1818  {
     19#ifndef VHDL_GAISLER
     20
    1921    vhdl->set_body   (0,"");
    2022    vhdl->set_comment(0,"---------------------------------------------------------------------------");
    … …  
    107109    if (_param->_have_init_value)
    108110      vhdl->set_body   (1,"end if;");
    109 
    110111    vhdl->set_body   (0,"end process RegisterFile_write;");
     112
     113#else
     114    // vhdl->set_body   (0,"");
     115    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
     116    // vhdl->set_comment(0," Ackitement");
     117    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
     118    // vhdl->set_body   (0,"");
     119
     120    // for (uint32_t i = 0; i < _param->_nb_port_read; i++)
     121    //   vhdl->set_body   (0,"out_READ_"+toString(i)+"_ACK  <= '1';");
     122    // for (uint32_t i = 0; i < _param->_nb_port_write; i++)
     123    //   vhdl->set_body   (0,"out_WRITE_"+toString(i)+"_ACK <= '1';");
     124    // for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
     125    //   vhdl->set_body   (0,"out_READ_WRITE_"+toString(i)+"_ACK  <= '1';");
     126
     127    // vhdl->set_body   (0,"");
     128    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
     129    // vhdl->set_comment(0," Read RegisterFile");
     130    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
     131    // vhdl->set_body   (0,"");
     132
     133    // for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
     134    //   {
     135    //     vhdl->set_body   (0,"with in_READ_"+toString(num_read)+"_ADDRESS select");
     136    //       vhdl->set_body   (1,"out_READ_"+toString(num_read)+"_DATA <=");
     137    //       for (uint32_t num_word=0; num_word<_param->_nb_word-1; ++num_word)
     138    //         vhdl->set_body   (1,"reg_DATA_"+toString(num_word)+" when "+std_logic_cst(_param->_size_address,num_word)+",");
     139    //       vhdl->set_body   (1,"reg_DATA_"+toString(_param->_nb_word-1)+" when others;");
     140    //   }
     141
     142    // vhdl->set_body   (0,"");
     143    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
     144    // vhdl->set_comment(0," Write RegisterFile");
     145    // vhdl->set_comment(0,"---------------------------------------------------------------------------");
     146    // vhdl->set_body   (0,"");
     147
     148    // vhdl->set_body   (0,"RegisterFile_write: process (in_CLOCK)");
     149    // vhdl->set_body   (0,"begin  -- process RegisterFile_write");
     150    // vhdl->set_body   (1,"if in_CLOCK'event and in_CLOCK = '1' then");
     151
     152    // for (uint32_t num_write = 0; num_write < _param->_nb_port_write; num_write++)
     153    //   {
     154    //     vhdl->set_body   (2,"if (in_WRITE_"+toString(num_write)+"_VAL = '1') then");
     155    //     for (uint32_t num_word=0; num_word<_param->_nb_word; ++num_word)
     156    //       {
     157    //         vhdl->set_body   (3,"if (in_WRITE_"+toString(num_write)+"_ADDRESS = "+std_logic_cst(_param->_size_address,num_word)+") then");
     158    //         vhdl->set_body   (4,"reg_DATA_"+toString(num_word)+" <= in_WRITE_"+toString(num_write)+"_DATA;");
     159    //         vhdl->set_body   (3,"end if;");
     160    //       }
     161    //     vhdl->set_body   (2,"end if;");
     162    //   }
     163   
     164    // vhdl->set_body   (1,"end if;");
     165    // vhdl->set_body   (0,"end process RegisterFile_write;");
     166
     167    vhdl->set_body   (0,"combinatory : process (");
     168    for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read)
     169      {
     170        vhdl->set_body   (1,"in_READ_"+toString(num_read)+"_VAL,");
     171        if (_param->_have_port_address)
     172        vhdl->set_body   (1,"in_READ_"+toString(num_read)+"_ADDRESS,");
     173      }
     174    for (uint32_t num_write=0; num_write<_param->_nb_port_write; ++num_write)
     175      {
     176        vhdl->set_body   (1,"in_WRITE_"+toString(num_write)+"_VAL,");
     177        if (_param->_have_port_address)
     178        vhdl->set_body   (1,"in_WRITE_"+toString(num_write)+"_ADDRESS,");
     179        vhdl->set_body   (1,"in_WRITE_"+toString(num_write)+"_DATA,");
     180      }
     181    for (uint32_t num_write = 0; num_write < _param->_nb_port_write; num_write++)
     182    vhdl->set_body   (1,"in_NRESET,");
     183    vhdl->set_body   (1,"reg_DATA)");
     184    vhdl->set_body   (1,"variable sig_DATA : Treg;");
     185    vhdl->set_body   (0,"begin");
     186    vhdl->set_body   (1,"");
     187    vhdl->set_body   (1,"sig_DATA := reg_DATA;");
     188
     189    vhdl->set_body   (1,"");
     190    vhdl->set_body   (1," -- ack");
     191    vhdl->set_body   (1,"");
     192   
     193    for (uint32_t i = 0; i < _param->_nb_port_read; i++)
     194      vhdl->set_body   (1,"out_READ_"+toString(i)+"_ACK  <= '1';");
     195    for (uint32_t i = 0; i < _param->_nb_port_write; i++)
     196      vhdl->set_body   (1,"out_WRITE_"+toString(i)+"_ACK <= '1';");
     197    for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
     198      vhdl->set_body   (1,"out_READ_WRITE_"+toString(i)+"_ACK  <= '1';");
     199    vhdl->set_body   (1,"");
     200    vhdl->set_body   (1," -- Read");
     201    vhdl->set_body   (1,"");
     202
     203    for (uint32_t i = 0; i < _param->_nb_port_read; i++)
     204      {
     205        std::string str_address;
     206        if (_param->_have_port_address)
     207          str_address = "conv_integer(in_READ_"+toString(i)+"_ADDRESS)";
     208        else
     209          str_address = "0";
     210
     211        vhdl->set_body   (1,"if (in_READ_"+toString(i)+"_VAL = '1') then"),
     212        vhdl->set_body   (2,"out_READ_"+toString(i)+"_DATA <= sig_DATA.reg ("+str_address+");");
     213        vhdl->set_body   (1,"else"),
     214        vhdl->set_body   (2,"out_READ_"+toString(i)+"_DATA <= "+std_logic_others(_param->_size_word,0)+";");
     215        vhdl->set_body   (1,"end if;");
     216      }
     217    vhdl->set_body   (1,"");
     218    vhdl->set_body   (1," -- write");
     219    vhdl->set_body   (1,"");
     220
     221    for (uint32_t i = 0; i < _param->_nb_port_write; i++)
     222      {
     223        std::string str_address;
     224        if (_param->_have_port_address)
     225          str_address = "conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)";
     226        else
     227          str_address = "0";
     228
     229        vhdl->set_body   (1,"if (in_WRITE_"+toString(i)+"_VAL = '1') then");
     230        vhdl->set_body   (2,"sig_DATA.reg("+str_address+") := in_WRITE_"+toString(i)+"_DATA;");
     231        vhdl->set_body   (1,"end if;");
     232      }
     233
     234    vhdl->set_body   (1,"");
     235    vhdl->set_body   (1,"reg_DATA_next <= sig_DATA;");
     236    vhdl->set_body   (1,"");
     237    vhdl->set_body   (0,"end process combinatory;");
     238
     239
     240    vhdl->set_body   (0,"sequential: process (in_CLOCK)");
     241    vhdl->set_body   (0,"begin");
     242    vhdl->set_body   (1,"if rising_edge(in_CLOCK) then");
     243    vhdl->set_body   (2,"reg_DATA <= reg_DATA_NEXT;");
     244    vhdl->set_body   (1,"end if;");
     245    vhdl->set_body   (0,"end process sequential;");
     246
     247#endif
     248
    111249  };
    112250

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_declaration.cpp

    r97 r145  
    1818  void RegisterFile_Monolithic::vhdl_declaration (Vhdl * & vhdl)
    1919  {
     20#ifndef VHDL_GAISLER
    2021    vhdl->set_type ("Tregfile", "array " + _std_logic_range(_param->_nb_word) + " of " + std_logic(_param->_size_word));
    2122
    2223    vhdl->set_signal ("reg_DATA", "Tregfile");
     24#else
     25    // for (uint32_t i=0; i<_param->_nb_word; ++i)
     26    //   vhdl->set_signal ("reg_DATA_"+toString(i), _param->_size_word);
     27
     28    vhdl->set_type ("Tregfile", "array " + _std_logic_range(_param->_nb_word) + " of " + std_logic(_param->_size_word));
     29    vhdl->set_type ("Treg", "record reg : Tregfile; end record");
     30
     31    vhdl->set_signal ("reg_DATA"     , "Treg");
     32    vhdl->set_signal ("reg_DATA_next", "Treg");
     33#endif
    2334  };
    2435

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile

    r88 r145  
    99#-----[ Directory ]----------------------------------------
    1010DIR_COMPONENT                   = ../
    11 include                         $(DIR_COMPONENT)/Makefile.defs
     11include                         $(DIR_COMPONENT)/Makefile.defs                                                                                                                                                   
    1212
    1313LIBRARY                         = $(RegisterFile_Multi_Banked_LIBRARY)

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info

    r139 r145  
    11
    2 # RegisterFile_Multi_Banked_0
    3 target_dep      all     RegisterFile_Multi_Banked_0.ngc
    4 target_dep      RegisterFile_Multi_Banked_0.ngc RegisterFile_Multi_Banked_0.prj
    5 target_dep      RegisterFile_Multi_Banked_0.prj RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports.vhdl RegisterFile_Multi_Banked_0_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_2_ports.vhdl RegisterFile_Multi_Banked_0.vhdl
     2# info_00
     3target_dep      all     info_00.ngc
     4target_dep      info_00.ngc     info_00.prj
     5target_dep      info_00.prj     info_00_bank_Pack.vhdl info_00_bank.vhdl info_00_Pack.vhdl info_00_select_4_ports_Pack.vhdl info_00_select_4_ports.vhdl info_00_select_8_ports_Pack.vhdl info_00_select_8_ports.vhdl info_00.vhdl
    66
    7 # RegisterFile_Multi_Banked_1
    8 target_dep      all     RegisterFile_Multi_Banked_1.ngc
    9 target_dep      RegisterFile_Multi_Banked_1.ngc RegisterFile_Multi_Banked_1.prj
    10 target_dep      RegisterFile_Multi_Banked_1.prj RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports.vhdl RegisterFile_Multi_Banked_1_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_2_ports.vhdl RegisterFile_Multi_Banked_1.vhdl
     7# info_01
     8target_dep      all     info_01.ngc
     9target_dep      info_01.ngc     info_01.prj
     10target_dep      info_01.prj     info_01_bank_Pack.vhdl info_01_bank.vhdl info_01_Pack.vhdl info_01_select_4_ports_Pack.vhdl info_01_select_4_ports.vhdl info_01_select_8_ports_Pack.vhdl info_01_select_8_ports.vhdl info_01.vhdl
    1111
     12# info_02
     13target_dep      all     info_02.ngc
     14target_dep      info_02.ngc     info_02.prj
     15target_dep      info_02.prj     info_02_bank_Pack.vhdl info_02_bank.vhdl info_02_Pack.vhdl info_02_select_4_ports_Pack.vhdl info_02_select_4_ports.vhdl info_02_select_8_ports_Pack.vhdl info_02_select_8_ports.vhdl info_02.vhdl
     16
     17# info_03
     18target_dep      all     info_03.ngc
     19target_dep      info_03.ngc     info_03.prj
     20target_dep      info_03.prj     info_03_bank_Pack.vhdl info_03_bank.vhdl info_03_Pack.vhdl info_03_select_16_ports_Pack.vhdl info_03_select_16_ports.vhdl info_03_select_4_ports_Pack.vhdl info_03_select_4_ports.vhdl info_03.vhdl
     21
     22# info_04
     23target_dep      all     info_04.ngc
     24target_dep      info_04.ngc     info_04.prj
     25target_dep      info_04.prj     info_04_bank_Pack.vhdl info_04_bank.vhdl info_04_Pack.vhdl info_04_select_16_ports_Pack.vhdl info_04_select_16_ports.vhdl info_04_select_4_ports_Pack.vhdl info_04_select_4_ports.vhdl info_04.vhdl
     26
     27# info_05
     28target_dep      all     info_05.ngc
     29target_dep      info_05.ngc     info_05.prj
     30target_dep      info_05.prj     info_05_bank_Pack.vhdl info_05_bank.vhdl info_05_Pack.vhdl info_05_select_16_ports_Pack.vhdl info_05_select_16_ports.vhdl info_05_select_4_ports_Pack.vhdl info_05_select_4_ports.vhdl info_05.vhdl
     31
     32# result_06
     33target_dep      all     result_06.ngc
     34target_dep      result_06.ngc   result_06.prj
     35target_dep      result_06.prj   result_06_bank_Pack.vhdl result_06_bank.vhdl result_06_Pack.vhdl result_06_select_4_ports_Pack.vhdl result_06_select_4_ports.vhdl result_06_select_8_ports_Pack.vhdl result_06_select_8_ports.vhdl result_06.vhdl
     36
     37# result_07
     38target_dep      all     result_07.ngc
     39target_dep      result_07.ngc   result_07.prj
     40target_dep      result_07.prj   result_07_bank_Pack.vhdl result_07_bank.vhdl result_07_Pack.vhdl result_07_select_4_ports_Pack.vhdl result_07_select_4_ports.vhdl result_07_select_8_ports_Pack.vhdl result_07_select_8_ports.vhdl result_07.vhdl
     41
     42# result_08
     43target_dep      all     result_08.ngc
     44target_dep      result_08.ngc   result_08.prj
     45target_dep      result_08.prj   result_08_bank_Pack.vhdl result_08_bank.vhdl result_08_Pack.vhdl result_08_select_4_ports_Pack.vhdl result_08_select_4_ports.vhdl result_08_select_8_ports_Pack.vhdl result_08_select_8_ports.vhdl result_08.vhdl
     46
     47# result_09
     48target_dep      all     result_09.ngc
     49target_dep      result_09.ngc   result_09.prj
     50target_dep      result_09.prj   result_09_bank_Pack.vhdl result_09_bank.vhdl result_09_Pack.vhdl result_09_select_16_ports_Pack.vhdl result_09_select_16_ports.vhdl result_09_select_4_ports_Pack.vhdl result_09_select_4_ports.vhdl result_09.vhdl
     51
     52# result_10
     53target_dep      all     result_10.ngc
     54target_dep      result_10.ngc   result_10.prj
     55target_dep      result_10.prj   result_10_bank_Pack.vhdl result_10_bank.vhdl result_10_Pack.vhdl result_10_select_16_ports_Pack.vhdl result_10_select_16_ports.vhdl result_10_select_4_ports_Pack.vhdl result_10_select_4_ports.vhdl result_10.vhdl
     56
     57# result_11
     58target_dep      all     result_11.ngc
     59target_dep      result_11.ngc   result_11.prj
     60target_dep      result_11.prj   result_11_bank_Pack.vhdl result_11_bank.vhdl result_11_Pack.vhdl result_11_select_16_ports_Pack.vhdl result_11_select_16_ports.vhdl result_11_select_4_ports_Pack.vhdl result_11_select_4_ports.vhdl result_11.vhdl
     61

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/main.cpp

    r81 r145  
    88#include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h"
    99
    10 #define NB_PARAMS 0
     10#define NB_PARAMS 8
    1111
    1212void usage (int argc, char * argv[])
    … …  
    4040    usage (argc, argv);
    4141
    42   const string   name      = argv[1];
     42  const string      name                  = argv[1];
    4343  const uint32_t    nb_port_read          = atoi(argv[2]);
    4444  const uint32_t    nb_port_write         = atoi(argv[3]);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp

    r131 r145  
    4242     _param,
    4343     _usage);
    44  
    45 #ifdef SYSTEMC
     44
     45#if 0 
     46// #ifdef SYSTEMC
     47
    4648  /*********************************************************************
    4749   * Déclarations des signaux
    … …  
    229231   ********************************************************/
    230232
    231   TEST_OK("End of Simulation");
    232233  delete _time;
    233234  cout << "<" << name << "> ............ Stop Simulation" << endl;
    … …  
    236237  delete NRESET;
    237238#endif
     239  TEST_OK("End of Simulation");
    238240
    239241  delete _RegisterFile_Multi_Banked;

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Types.h

    r128 r145  
    1919
    2020//typedef uint32_t Taddress_t;
     21//typedef uint64_t Tdata_t;
    2122  typedef Tgeneral_data_t Tdata_t;
    2223
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