Ignore:
Timestamp:
Jun 5, 2007, 11:06:46 PM (17 years ago)
Author:
rosiere
Message:

Interface et Signal, c'est deux classes enregistres la valeurs des signaux à chaque cycle ... étape préparatoire avan le changement de la classe Vhdl_Testbench

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/New_Component.h

    r15 r40  
    2121#ifdef STATISTICS
    2222#include "Behavioural/@DIRECTORY/include/Statistics.h"
     23#endif
     24#ifdef POSITION
     25#include "Behavioural/include/Position.h"
     26#else
     27#include "Behavioural/include/Interfaces.h"
    2328#endif
    2429#ifdef VHDL
     
    5661  private   : Vhdl_Testbench                 * _vhdl_testbench;
    5762#endif
     63
     64#ifdef POSITION
     65  private   : Position                       * _position;
     66#endif
     67
     68  private   : Interfaces                     * _interfaces;
    5869
    5970#ifdef SYSTEMC
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component.cpp

    r15 r40  
    2929    log_printf(FUNC,@COMPONENT,"@COMPONENT","Begin");
    3030
     31#ifdef SYSTEMC
     32    log_printf(INFO,@COMPONENT,"@COMPONENT","Allocation");
     33
     34    allocation ();
     35#endif
     36
    3137#ifdef STATISTICS
    3238    log_printf(INFO,@COMPONENT,"@COMPONENT","Allocation of statistics");
     
    4147    log_printf(INFO,@COMPONENT,"@COMPONENT","Creation of a testbench");
    4248
    43     // Creation of a testbench
    44     //  -> port
    45     //  -> clock's signals
    4649    _vhdl_testbench = new Vhdl_Testbench (_name);
    4750#endif
     
    5457#endif
    5558
    56 #ifdef VHDL_TESTBENCH
    57     // must be invoke after affect of port
    58     _vhdl_testbench->set_clock    ("in_CLOCK",true);
    59 #endif
    60 
    6159#ifdef SYSTEMC
    62     log_printf(INFO,@COMPONENT,"@COMPONENT","Allocation");
    63 
    64     allocation ();
    65 
    6660//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
    6761    log_printf(INFO,@COMPONENT,"@COMPONENT","Method - transition");
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_allocation.cpp

    r15 r40  
    1919    log_printf(FUNC,@COMPONENT,"allocation","Begin");
    2020
    21 //#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
    22     in_CLOCK  = new SC_CLOCK           ("in_CLOCK");
    23 //#endif
    24     in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET");
     21#ifdef POSITION
     22    _position   = new Position ();
     23
     24    Entity * entity = _position->set_entity (_name       ,
     25                                             "@COMPONENT",
     26                                             COMBINATORY );
     27
     28    _interfaces = entity->set_interfaces();
     29#else
     30    _interfaces = new Interfaces();
     31#endif
     32
     33    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     34
     35    Interface * interface_ = _interfaces->set_interface("", IN  ,WEST, "Generalist interface");
     36
     37     in_CLOCK        = interface_->set_signal_clk              ("clock" ,1, PORT_VHDL_YES_TESTBENCH_NO);
     38     in_NRESET       = interface_->set_signal_in  <Tcontrol_t> ("nreset",1);
     39
    2540
    2641    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
     42
     43#ifdef POSITION
     44    _position->generate_file();
     45#endif
    2746
    2847    log_printf(FUNC,@COMPONENT,"allocation","End");
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_deallocation.cpp

    r15 r40  
    2424    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    2525
     26#ifdef POSITION
     27    delete _position;
     28#else
     29    delete _interfaces;
     30#endif
     31
    2632    log_printf(FUNC,@COMPONENT,"deallocation","End");
    2733  };
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl.cpp

    r2 r40  
    1717  {
    1818    log_printf(FUNC,@COMPONENT,"vhdl","Begin");
     19
    1920    Vhdl vhdl (_name);
    2021
     
    2627
    2728    vhdl.generate_file();
     29
     30    delete vhdl;
     31
    2832    log_printf(FUNC,@COMPONENT,"vhdl","End");
    29 
    3033  };
    3134
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_port.cpp

    r15 r40  
    99#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
    1010
    11 #ifdef VHDL_TESTBENCH
    12 # define VHDL_SET_PORT(name,direction,size) do {vhdl.set_port (name,direction,size); _vhdl_testbench->set_port (name,direction,size);} while(0)
    13 #else
    14 # define VHDL_SET_PORT(name,direction,size)     vhdl.set_port (name,direction,size)
    15 #endif
    16 
    1711namespace morpheo                    {
    1812namespace behavioural {
     
    2317    log_printf(FUNC,@COMPONENT,"vhdl_port","Begin");
    2418
    25     vhdl.set_port (" in_CLOCK" , IN, 1);
    26     VHDL_SET_PORT (" in_NRESET", IN, 1);
     19    _interfaces->set_port(vhdl);
     20
     21#ifdef VHDL_TESTBENCH
     22    _interfaces->set_port(_vhdl_testbench);                     
     23   _vhdl_testbench->set_clock    ("in_CLOCK",true);
     24#endif   
    2725
    2826    log_printf(FUNC,@COMPONENT,"vhdl_port","End");
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_transition.cpp

    r2 r40  
    2020    sc_start(0);
    2121
    22     // In order with file @COMPONENT_vhdl_testbench_port.cpp
    23     // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
    24     // (because we have no control on the ordonnancer's policy)
    25 
    26     _vhdl_testbench->add_input (PORT_READ( in_NRESET));
     22    _interfaces->testbench(_vhdl_testbench);
    2723   
    2824    // add_test :
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