Changeset 40 for trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_port.cpp

Timestamp:

Jun 5, 2007, 11:06:46 PM (17 years ago)

Author:

rosiere

Message:

Interface et Signal, c'est deux classes enregistres la valeurs des signaux à chaque cycle ... étape préparatoire avan le changement de la classe Vhdl_Testbench

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_port.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_port.cpp

@@ -9 +9 @@
 #include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
 
-#ifdef VHDL_TESTBENCH
-# define VHDL_SET_PORT(name,direction,size) do {vhdl.set_port (name,direction,size); _vhdl_testbench->set_port (name,direction,size);} while(0)
-#else
-# define VHDL_SET_PORT(name,direction,size)     vhdl.set_port (name,direction,size)
-#endif
-
 namespace morpheo                    {
 namespace behavioural {
@@ -23 +17 @@
     log_printf(FUNC,@COMPONENT,"vhdl_port","Begin");
 
-    vhdl.set_port (" in_CLOCK" , IN, 1);
-    VHDL_SET_PORT (" in_NRESET", IN, 1);
+    _interfaces->set_port(vhdl);
+
+#ifdef VHDL_TESTBENCH
+    _interfaces->set_port(_vhdl_testbench);                     
+   _vhdl_testbench->set_clock    ("in_CLOCK",true);
+#endif    
 
     log_printf(FUNC,@COMPONENT,"vhdl_port","End");