Changeset 42 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic
- Timestamp:
- Jul 5, 2007, 5:50:19 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic
- Files:
-
- 1 added
- 4 deleted
- 41 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp
r2 r42 43 43 *********************************************************************/ 44 44 sc_clock CLOCK ("clock", 1.0, 0.5); 45 sc_signal<Tcontrol_t> RESET; 45 46 sc_signal<Tdata_t> DATA_IN [param._nb_port]; 46 47 sc_signal<Tcontrol_t> ADDSUB [param._nb_port]; … … 53 54 cout << "<" << name << "> Instanciation of _Counter" << endl; 54 55 55 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)56 56 (*(_Counter->in_CLOCK)) (CLOCK); 57 #endif 57 (*(_Counter->in_NRESET)) (RESET); 58 58 59 59 for (uint32_t i=0; i<param._nb_port; i++) … … 79 79 80 80 sc_start(0); 81 _Counter->vhdl_testbench_label("Initialisation"); 81 82 RESET.write(1); 83 82 84 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 83 85 84 _Counter->vhdl_testbench_label("Loop of Test");85 86 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; 86 87 87 88 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 88 89 { 89 _Counter->vhdl_testbench_label("Iteration "+toString(iteration));90 90 cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} Itération " << iteration << endl; 91 91 for (uint32_t i=0; i<param._nb_port; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Counter.h
r2 r42 25 25 #include "Behavioural/include/Vhdl.h" 26 26 #endif 27 #ifdef VHDL_TESTBENCH 28 #include "Behavioural/include/Vhdl_Testbench.h" 29 #endif 27 #include "Behavioural/include/Component.h" 30 28 31 29 using namespace std; 32 30 33 namespace morpheo 31 namespace morpheo { 34 32 namespace behavioural { 35 33 namespace generic { 36 34 namespace counter { 37 38 35 39 36 class Counter … … 55 52 #endif 56 53 57 #ifdef VHDL_TESTBENCH 58 private : Vhdl_Testbench * _vhdl_testbench; 59 #endif 54 public : Component * _component; 55 private : Interfaces * _interfaces; 60 56 61 57 #ifdef SYSTEMC … … 63 59 // Interface 64 60 public : SC_CLOCK * in_CLOCK ; 65 61 public : SC_IN (Tcontrol_t) * in_NRESET ; 66 62 public : SC_IN (Tdata_t) ** in_COUNTER_DATA ; 67 63 public : SC_IN (Tcontrol_t) ** in_COUNTER_ADDSUB ; … … 107 103 #if VHDL 108 104 public : void vhdl (void); 109 private : void vhdl_port (Vhdl & vhdl);110 private : void vhdl_declaration (Vhdl & vhdl);111 private : void vhdl_body (Vhdl & vhdl);105 private : void vhdl_port (Vhdl * & vhdl); 106 private : void vhdl_declaration (Vhdl * & vhdl); 107 private : void vhdl_body (Vhdl * & vhdl); 112 108 #endif 113 109 114 110 #ifdef VHDL_TESTBENCH 115 private : void vhdl_testbench_port (void);116 111 private : void vhdl_testbench_transition (void); 117 112 #endif 118 public : void vhdl_testbench_label (string label);119 113 }; 120 114 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter.cpp
r2 r42 31 31 log_printf(FUNC,Counter,"Counter","Begin"); 32 32 33 #ifdef SYSTEMC 34 allocation (); 35 #endif 36 33 37 #ifdef STATISTICS 34 38 // Allocation of statistics … … 36 40 param_statistics , 37 41 param); 38 #endif39 40 #ifdef VHDL_TESTBENCH41 // Creation of a testbench42 // -> port43 // -> clock's signals44 _vhdl_testbench = new Vhdl_Testbench (_name);45 vhdl_testbench_port ();46 _vhdl_testbench->set_clock ("in_CLOCK",false);47 42 #endif 48 43 … … 53 48 54 49 #ifdef SYSTEMC 55 allocation ();56 57 50 SC_METHOD (transition); 58 51 dont_initialize (); … … 85 78 #endif 86 79 87 #ifdef VHDL_TESTBENCH88 // generate the test bench89 _vhdl_testbench->generate_file();90 delete _vhdl_testbench;91 #endif92 93 80 #ifdef STATISTICS 94 81 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp
r2 r42 21 21 log_printf(FUNC,Counter,"allocation","Begin"); 22 22 23 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 23 _component = new Component (); 24 25 Entity * entity = _component->set_entity (_name 26 ,"Counter" 27 #ifdef POSITION 28 ,COMBINATORY 25 29 #endif 30 ); 31 32 _interfaces = entity->set_interfaces(); 26 33 27 in_COUNTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; 28 in_COUNTER_ADDSUB= new SC_IN (Tcontrol_t) * [_param._nb_port]; 29 out_COUNTER_DATA = new SC_OUT(Tdata_t) * [_param._nb_port]; 30 31 for (uint32_t i=0; i<_param._nb_port; i++) 32 { 33 rename = " in_COUNTER_DATA_" +toString(i); 34 in_COUNTER_DATA [i] = new SC_IN (Tdata_t) (rename.c_str()); 34 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 35 { 36 Interface * interface = _interfaces->set_interface("" 37 #ifdef POSITION 38 , IN 39 , SOUTH 40 , "Generalist interface" 41 #endif 42 ); 43 44 in_CLOCK = interface->set_signal_clk ("clock" ,1,CLOCK_VHDL_NO); 45 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_NO); 46 } 35 47 36 rename = " in_COUNTER_ADDSUB_"+toString(i); 37 in_COUNTER_ADDSUB[i] = new SC_IN (Tcontrol_t) (rename.c_str()); 38 39 rename = "out_COUNTER_DATA_" +toString(i); 40 out_COUNTER_DATA [i] = new SC_OUT(Tdata_t) (rename.c_str()); 41 } 48 // ~~~~~[ Interface : "counter" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 49 { 50 in_COUNTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; 51 in_COUNTER_ADDSUB= new SC_IN (Tcontrol_t) * [_param._nb_port]; 52 out_COUNTER_DATA = new SC_OUT(Tdata_t) * [_param._nb_port]; 53 54 for (uint32_t i=0; i<_param._nb_port; i++) 55 { 56 Interface_fifo * interface = _interfaces->set_interface("counter_"+toString(i) 57 #ifdef POSITION 58 , IN 59 , SOUTH 60 , "Counter interface" 61 #endif 62 ); 63 64 in_COUNTER_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param._size_data); 65 in_COUNTER_ADDSUB [i] = interface->set_signal_in <Tcontrol_t> ("addsub", 1 ); 66 out_COUNTER_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param._size_data); 67 } 68 } 69 #ifdef POSITION 70 _component->generate_file(); 71 #endif 42 72 43 73 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp
r2 r42 19 19 log_printf(FUNC,Counter,"deallocation","Begin"); 20 20 21 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 22 delete in_CLOCK; 23 #endif 21 delete in_CLOCK; 22 delete in_NRESET; 24 23 25 for (uint32_t i=0; i<_param._nb_port; i++) 26 { 27 delete in_COUNTER_DATA [i]; 28 delete in_COUNTER_ADDSUB[i]; 29 delete out_COUNTER_DATA [i]; 30 } 31 delete in_COUNTER_DATA ; 32 delete in_COUNTER_ADDSUB; 33 delete out_COUNTER_DATA ; 24 delete [] in_COUNTER_DATA ; 25 delete [] in_COUNTER_ADDSUB; 26 delete [] out_COUNTER_DATA ; 34 27 35 28 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 30 delete _component; 36 31 37 32 log_printf(FUNC,Counter,"deallocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_genMealy.cpp
r3 r42 1 1 #ifdef SYSTEMC 2 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)3 2 /* 4 3 * $Id$ … … 51 50 }; // end namespace morpheo 52 51 #endif 53 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl.cpp
r2 r42 19 19 { 20 20 log_printf(FUNC,Counter,"vhdl","Begin"); 21 Vhdl vhdl (_name);21 Vhdl * vhdl = new Vhdl (_name); 22 22 23 vhdl .set_library_work (_name + "_Pack");23 vhdl->set_library_work (_name + "_Pack"); 24 24 25 25 vhdl_port (vhdl); … … 27 27 vhdl_body (vhdl); 28 28 29 vhdl.generate_file(); 29 vhdl->generate_file(); 30 31 delete vhdl; 30 32 log_printf(FUNC,Counter,"vhdl","End"); 31 33 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_body.cpp
r2 r42 14 14 namespace counter { 15 15 16 17 void Counter::vhdl_body (Vhdl & vhdl) 16 void Counter::vhdl_body (Vhdl * & vhdl) 18 17 { 19 18 log_printf(FUNC,Counter,"vhdl_body","Begin"); 20 vhdl .set_body ("");19 vhdl->set_body (""); 21 20 22 21 for (uint32_t i=0; i<_param._nb_port; i++) … … 26 25 if (_param._size_data > 1) 27 26 { 28 counter_inc = "in_COUNTER_ DATA_"+toString(i)+"+1";29 counter_dec = "in_COUNTER_ DATA_"+toString(i)+"-1";27 counter_inc = "in_COUNTER_"+toString(i)+"_DATA+1"; 28 counter_dec = "in_COUNTER_"+toString(i)+"_DATA-1"; 30 29 } 31 30 else 32 31 { 33 counter_inc = "in_COUNTER_ DATA_"+toString(i)+"+1";34 counter_dec = "in_COUNTER_ DATA_"+toString(i)+"-1";32 counter_inc = "in_COUNTER_"+toString(i)+"_DATA+1"; 33 counter_dec = "in_COUNTER_"+toString(i)+"_DATA-1"; 35 34 } 36 35 37 vhdl .set_body ("out_COUNTER_DATA_"+toString(i)+"<=");36 vhdl->set_body ("out_COUNTER_"+toString(i)+"_DATA <="); 38 37 if (_param._size_data > 1) 39 38 { 40 vhdl .set_body ("\tin_COUNTER_DATA_"+toString(i)+"+1 when in_COUNTER_ADDSUB_"+toString(i)+" = '1' and in_COUNTER_DATA_"+toString(i)+"< cst_max else");41 vhdl .set_body ("\tin_COUNTER_DATA_"+toString(i)+"-1 when in_COUNTER_ADDSUB_"+toString(i)+" = '0' and in_COUNTER_DATA_"+toString(i)+"> cst_min else");42 vhdl .set_body ("\tin_COUNTER_DATA_"+toString(i)+";");39 vhdl->set_body ("\tin_COUNTER_"+toString(i)+"_DATA+1 when in_COUNTER_"+toString(i)+"_ADDSUB = '1' and in_COUNTER_"+toString(i)+"_DATA < cst_max else"); 40 vhdl->set_body ("\tin_COUNTER_"+toString(i)+"_DATA-1 when in_COUNTER_"+toString(i)+"_ADDSUB = '0' and in_COUNTER_"+toString(i)+"_DATA > cst_min else"); 41 vhdl->set_body ("\tin_COUNTER_"+toString(i)+"_DATA;"); 43 42 } 44 43 else 45 44 { 46 vhdl .set_body ("\tin_COUNTER_ADDSUB_"+toString(i)+";");45 vhdl->set_body ("\tin_COUNTER_"+toString(i)+"_ADDSUB;"); 47 46 } 48 47 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_declaration.cpp
r2 r42 15 15 16 16 17 void Counter::vhdl_declaration (Vhdl & vhdl)17 void Counter::vhdl_declaration (Vhdl * & vhdl) 18 18 { 19 19 log_printf(FUNC,Counter,"vhdl_declaration","Begin"); … … 21 21 if (_param._size_data > 1) 22 22 { 23 vhdl .set_constant ("cst_min",_param._size_data,std_logic_others(_param._size_data,0));24 vhdl .set_constant ("cst_max",_param._size_data,std_logic_others(_param._size_data,1));23 vhdl->set_constant ("cst_min",_param._size_data,std_logic_others(_param._size_data,0)); 24 vhdl->set_constant ("cst_max",_param._size_data,std_logic_others(_param._size_data,1)); 25 25 } 26 26 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_port.cpp
r2 r42 15 15 16 16 17 void Counter::vhdl_port (Vhdl & vhdl)17 void Counter::vhdl_port (Vhdl * & vhdl) 18 18 { 19 19 log_printf(FUNC,Counter,"vhdl_port","Begin"); 20 20 21 for (uint32_t i=0; i<_param._nb_port; i++) 22 { 23 vhdl.set_port (" in_COUNTER_DATA_" +toString(i), IN, _param._size_data); 24 vhdl.set_port (" in_COUNTER_ADDSUB_"+toString(i), IN, 1 ); 25 vhdl.set_port ("out_COUNTER_DATA_" +toString(i),OUT, _param._size_data); 26 } 27 21 _interfaces->set_port(vhdl); 22 28 23 log_printf(FUNC,Counter,"vhdl_port","End"); 29 24 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_transition.cpp
r2 r42 21 21 sc_start(0); 22 22 23 // In order with file Counter_vhdl_testbench_port.cpp 24 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent 25 // (because we have no control on the ordonnancer's policy) 26 27 for (uint32_t i=0; i<_param._nb_port; i++) 28 { 29 _vhdl_testbench->add_input (PORT_READ( in_COUNTER_DATA [i])); 30 _vhdl_testbench->add_input (PORT_READ( in_COUNTER_ADDSUB[i])); 31 _vhdl_testbench->add_output(PORT_READ(out_COUNTER_DATA [i])); 32 } 33 34 // add_test : 35 // - True : the cycle must be compare with the output of systemC 36 // - False : no test 37 _vhdl_testbench->add_test(true); 38 39 _vhdl_testbench->new_cycle (); // always at the end 23 _interfaces->testbench(); 40 24 41 25 log_printf(FUNC,Counter,"vhdl_testbench_transition","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp
r15 r42 94 94 READ_VAL [i] .write (0); 95 95 96 NRESET.write(0); 97 96 98 sc_start(5); 99 100 NRESET.write(1); 97 101 98 102 cout << "<" << name << "> Write the RegisterFile (no read)" << endl; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h
r41 r42 23 23 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Statistics.h" 24 24 #endif 25 #ifdef POSITION 26 #include "Behavioural/include/Position.h" 27 #else 28 #include "Behavioural/include/Interfaces.h" 29 #endif 25 #include "Behavioural/include/Component.h" 30 26 #ifdef VHDL 31 27 #include "Behavioural/include/Vhdl.h" … … 57 53 #endif 58 54 59 #ifdef POSITION 60 private : Position * _position; 61 #endif 62 55 public : Component * _component; 63 56 private : Interfaces * _interfaces; 64 57 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp
r41 r42 17 17 void RegisterFile_Monolithic::allocation (void) 18 18 { 19 _component = new Component (); 20 21 Entity * entity = _component->set_entity (_name 22 ,"RegisterFile_Monolithic" 19 23 #ifdef POSITION 20 _position = new Position (); 21 22 Entity * entity = _position->set_entity (_name , 23 "RegisterFile_Monolithic", 24 REGISTER ); 24 ,REGISTER 25 #endif 26 ); 25 27 26 28 _interfaces = entity->set_interfaces(); 27 #else28 _interfaces = new Interfaces();29 #endif30 29 31 30 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 Interface * interface_ = _interfaces->set_interface("", IN ,SOUTH, "Generalist interface"); 33 34 in_CLOCK = interface_->set_signal_clk ("clock" ,1); 35 in_NRESET = interface_->set_signal_in <Tcontrol_t> ("nreset",1); 36 31 { 32 Interface * interface = _interfaces->set_interface("" 33 #ifdef POSITION 34 , IN 35 ,SOUTH 36 , "Generalist interface" 37 #endif 38 ); 39 40 in_CLOCK = interface->set_signal_clk ("clock" ,1); 41 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 42 } 37 43 // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 38 44 … … 44 50 for (uint32_t i=0; i<_param._nb_port_read; i++) 45 51 { 46 Interface_fifo * interface_read = _interfaces->set_interface("read_"+toString(i), IN ,WEST, "Interface Read"); 52 Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) 53 #ifdef POSITION 54 , IN 55 ,WEST 56 , "Interface Read" 57 #endif 58 ); 47 59 48 in_READ_VAL [i] = interface _read->set_signal_valack_in ("val" , VAL);49 out_READ_ACK [i] = interface _read->set_signal_valack_out ("ack" , ACK);50 in_READ_ADDRESS [i] = interface _read->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param._nb_word)));51 out_READ_DATA [i] = interface _read->set_signal_out <Tdata_t > ("data" , _param._size_word);60 in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 61 out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 62 in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param._nb_word))); 63 out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param._size_word); 52 64 } 53 65 … … 61 73 for (uint32_t i=0; i<_param._nb_port_write; i++) 62 74 { 63 Interface_fifo * interface_write = _interfaces->set_interface("write_"+toString(i), IN ,EAST, "Interface Write"); 75 Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) 76 #ifdef POSITION 77 , IN 78 ,EAST 79 , "Interface Write" 80 #endif 81 ); 64 82 65 in_WRITE_VAL [i] = interface _write->set_signal_valack_in ("val" , VAL);66 out_WRITE_ACK [i] = interface _write->set_signal_valack_out ("ack" , ACK);67 in_WRITE_ADDRESS [i] = interface _write->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param._nb_word)));68 in_WRITE_DATA [i] = interface _write->set_signal_in <Tdata_t > ("data" , _param._size_word);83 in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 84 out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 85 in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param._nb_word))); 86 in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param._size_word); 69 87 } 70 88 … … 79 97 80 98 #ifdef POSITION 81 _ position->generate_file();99 _component->generate_file(); 82 100 #endif 83 101 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp
r41 r42 17 17 void RegisterFile_Monolithic::deallocation (void) 18 18 { 19 delete _component; 20 19 21 delete in_CLOCK; 20 22 delete in_NRESET; … … 33 35 // ----- Register 34 36 delete [] reg_DATA; 35 36 #ifdef POSITION37 delete _position;38 #else39 delete _interfaces;40 #endif41 37 }; 42 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h
r41 r42 22 22 #include "Behavioural/Generic/Select/Select_Priority_Fixed/include/Statistics.h" 23 23 #endif 24 #ifdef POSITION 25 #include "Behavioural/include/Position.h" 26 #else 27 #include "Behavioural/include/Interfaces.h" 28 #endif 24 #include "Behavioural/include/Component.h" 29 25 #ifdef VHDL 30 26 #include "Behavioural/include/Vhdl.h" … … 58 54 #endif 59 55 60 #ifdef POSITION 61 private : Position * _position; 62 #endif 63 56 private : Component * _component; 64 57 private : Interfaces * _interfaces; 65 58 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp
r41 r42 71 71 sensitive << *(in_VAL [i]); 72 72 73 # ifdef SYSTEMCASS_SPECIFIC73 # ifdef SYSTEMCASS_SPECIFIC 74 74 // List dependency information 75 75 … … 85 85 } 86 86 87 # endif87 # endif 88 88 #endif 89 89 log_printf(FUNC,Select_Priority_Fixed,"Select_Priority_Fixed","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp
r41 r42 19 19 log_printf(FUNC,Select_Priority_Fixed,"allocation","Begin"); 20 20 21 _component = new Component (); 22 23 Entity * entity = _component->set_entity (_name 21 24 #ifdef POSITION 22 _position = new Position (); 23 24 Entity * entity = _position->set_entity (_name , 25 "Select_Priority_Fixed", 26 COMBINATORY ); 25 ,"Select_Priority_Fixed" 26 ,COMBINATORY 27 #endif 28 ); 27 29 28 30 _interfaces = entity->set_interfaces(); 29 #else30 _interfaces = new Interfaces();31 #endif32 31 33 32 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 34 33 35 Interface_fifo * interface_ = _interfaces->set_interface("", IN ,WEST, "Generalist interface"); 34 Interface_fifo * interface = _interfaces->set_interface("" 35 #ifdef POSITION 36 ,IN 37 ,WEST 38 ,"Generalist interface" 39 #endif 40 ); 36 41 37 in_CLOCK = interface _->set_signal_clk ("clock" ,1, CLOCK_VHDL_NO);38 in_NRESET = interface _->set_signal_in <Tcontrol_t> ("nreset",1);42 in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_NO); 43 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1); 39 44 in_VAL = new SC_IN (Tcontrol_t) * [_param._nb_entity]; 40 45 if (_param._encoding_one_hot) … … 43 48 for (uint32_t i=0; i<_param._nb_entity; i++) 44 49 { 45 in_VAL [i] = interface _->set_signal_in <Tcontrol_t> ("val_"+toString(i),1);50 in_VAL [i] = interface->set_signal_in <Tcontrol_t> ("val_"+toString(i),1); 46 51 if (_param._encoding_one_hot) 47 out_ACK [i] = interface _->set_signal_out <Tcontrol_t> ("ack_"+toString(i),1);52 out_ACK [i] = interface->set_signal_out <Tcontrol_t> ("ack_"+toString(i),1); 48 53 } 49 54 50 55 if (_param._encoding_compact) 51 56 { 52 out_ENTITY = interface _->set_signal_out <Tentity_t > ("entity" , _param._size_entity);53 out_ENTITY_ACK = interface _->set_signal_out <Tcontrol_t> ("entity_ack", 1);57 out_ENTITY = interface->set_signal_out <Tentity_t > ("entity" , _param._size_entity); 58 out_ENTITY_ACK = interface->set_signal_out <Tcontrol_t> ("entity_ack", 1); 54 59 } 55 60 … … 57 62 58 63 #ifdef POSITION 59 _ position->generate_file();64 _component->generate_file(); 60 65 #endif 61 66 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp
r41 r42 34 34 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 35 35 36 #ifdef POSITION 37 delete _position; 38 #else 39 delete _interfaces; 40 #endif 36 delete _component; 37 41 38 log_printf(FUNC,Select_Priority_Fixed,"deallocation","End"); 42 39 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp
r2 r42 44 44 *********************************************************************/ 45 45 sc_clock CLOCK ("clock", 1.0, 0.5); 46 sc_signal <Tdirection_t> NRESET("nreset"); 46 47 sc_signal <Tdata_t > SHIFTER_DATA_IN [param._nb_port]; 47 48 sc_signal <Tshift_t > SHIFTER_SHIFT [param._nb_port]; … … 61 62 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 62 63 (*(_Shifter->in_CLOCK)) (CLOCK); 64 (*(_Shifter->in_NRESET)) (NRESET); 63 65 #endif 64 66 for (uint32_t i=0; i<param._nb_port; i++) … … 116 118 117 119 sc_start(0); 120 121 NRESET.write(1); 118 122 119 123 for (uint32_t x=0; x<6; x++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Shifter.h
r2 r42 24 24 #include "Behavioural/include/Vhdl.h" 25 25 #endif 26 #ifdef VHDL_TESTBENCH 27 #include "Behavioural/include/Vhdl_Testbench.h" 28 #endif 26 #include "Behavioural/include/Component.h" 29 27 30 28 using namespace std; … … 50 48 #endif 51 49 52 #ifdef VHDL_TESTBENCH 53 private : Vhdl_Testbench * _vhdl_testbench; 54 #endif 50 public : Component * _component; 51 private : Interfaces * _interfaces; 55 52 56 53 #ifdef SYSTEMC 57 54 // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 55 public : SC_CLOCK * in_CLOCK ; 56 public : SC_IN (Tcontrol_t) * in_NRESET ; 57 59 58 // Interface "shifter" 60 59 public : SC_IN (Tdata_t) ** in_SHIFTER_DATA ; … … 104 103 #if VHDL 105 104 public : void vhdl (void); 106 private : void vhdl_port (Vhdl & vhdl);107 private : void vhdl_declaration (Vhdl & vhdl);108 private : void vhdl_body (Vhdl & vhdl);105 private : void vhdl_port (Vhdl * & vhdl); 106 private : void vhdl_declaration (Vhdl * & vhdl); 107 private : void vhdl_body (Vhdl * & vhdl); 109 108 #endif 110 109 #ifdef STATISTICS … … 113 112 114 113 #ifdef VHDL_TESTBENCH 115 private : void vhdl_testbench (Vhdl_Testbench & vhdl_testbench); 116 private : void vhdl_testbench_port (Vhdl_Testbench & vhdl_testbench); 117 private : void vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench); 114 private : void vhdl_testbench_transition (void); 118 115 #endif 119 116 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter.cpp
r2 r42 15 15 16 16 #ifdef SYSTEMC 17 Shifter::Shifter (sc_module_name name ,17 Shifter::Shifter (sc_module_name name 18 18 #else 19 Shifter::Shifter (string name ,19 Shifter::Shifter (string name 20 20 #endif 21 21 #ifdef STATISTICS 22 morpheo::behavioural::Parameters_Statistics param_statistics,22 ,morpheo::behavioural::Parameters_Statistics param_statistics 23 23 #endif 24 morpheo::behavioural::generic::shifter::Parameters param ):24 ,morpheo::behavioural::generic::shifter::Parameters param ): 25 25 _name (name) 26 26 ,_param (param) 27 27 { 28 #ifdef SYSTEMC 29 allocation (); 30 #endif 31 28 32 #ifdef STATISTICS 29 33 // Allocation of statistics … … 31 35 param_statistics , 32 36 param); 33 #endif34 35 #ifdef VHDL_TESTBENCH36 // Creation of a testbench37 // -> port38 // -> clock's signals39 _vhdl_testbench = new Vhdl_Testbench (_name);40 vhdl_testbench_port (*_vhdl_testbench);41 _vhdl_testbench->set_clock ("in_CLOCK",false);42 37 #endif 43 38 … … 48 43 49 44 #ifdef SYSTEMC 50 allocation ();51 52 45 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 53 46 SC_METHOD (transition); … … 107 100 #endif 108 101 109 #ifdef VHDL_TESTBENCH110 // generate the test bench111 _vhdl_testbench->generate_file();112 delete _vhdl_testbench;113 #endif114 115 102 #ifdef STATISTICS 116 103 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp
r2 r42 17 17 void Shifter::allocation (void) 18 18 { 19 string rename; 19 _component = new Component (); 20 21 Entity * entity = _component->set_entity (_name 22 ,"Shifter" 23 #ifdef POSITION 24 ,COMBINATORY 25 #endif 26 ); 27 28 _interfaces = entity->set_interfaces(); 20 29 21 30 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 22 in_CLOCK = new SC_CLOCK ("SC_CLOCK"); 31 { 32 Interface_fifo * interface = _interfaces->set_interface("" 33 #ifdef POSITION 34 , IN 35 , SOUTH 36 , "Generalist interface" 23 37 #endif 24 // Interface "shifter" 25 in_SHIFTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; 26 if (_param._shift_value == 0) 27 in_SHIFTER_SHIFT = new SC_IN (Tshift_t) * [_param._nb_port]; 28 if (_param._direction == external_direction) 29 in_SHIFTER_DIRECTION = new SC_IN (Tdirection_t) * [_param._nb_port]; 30 if (_param._rotate == external_rotate) 31 in_SHIFTER_TYPE = new SC_IN (Ttype_t) * [_param._nb_port]; 32 if (_param._carry == external_carry) 33 in_SHIFTER_CARRY = new SC_IN (Tcarry_t) * [_param._nb_port]; 34 if (_param._carry == external_completion) 35 if (_param._type_completion_bool == true) 36 in_SHIFTER_CARRY_IN = new SC_IN (Tcontrol_t) * [_param._nb_port]; 37 else 38 in_SHIFTER_COMPLETION= new SC_IN (Tdata_t) * [_param._nb_port]; 39 out_SHIFTER_DATA = new SC_OUT(Tdata_t) * [_param._nb_port]; 38 ); 39 40 in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_NO); 41 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_NO); 42 } 43 #endif 40 44 41 for (uint32_t i=0; i<_param._nb_port; i++) 42 { 43 rename = "in_SHIFTER_DATA[" + toString(i) + "]"; 44 in_SHIFTER_DATA [i] = new SC_IN (Tdata_t) (rename.c_str()); 45 { 46 // Interface "shifter" 47 in_SHIFTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; 48 if (_param._shift_value == 0) 49 in_SHIFTER_SHIFT = new SC_IN (Tshift_t) * [_param._nb_port]; 50 if (_param._direction == external_direction) 51 in_SHIFTER_DIRECTION = new SC_IN (Tdirection_t) * [_param._nb_port]; 52 if (_param._rotate == external_rotate) 53 in_SHIFTER_TYPE = new SC_IN (Ttype_t) * [_param._nb_port]; 54 if (_param._carry == external_carry) 55 in_SHIFTER_CARRY = new SC_IN (Tcarry_t) * [_param._nb_port]; 56 if (_param._carry == external_completion) 57 if (_param._type_completion_bool == true) 58 in_SHIFTER_CARRY_IN = new SC_IN (Tcontrol_t) * [_param._nb_port]; 59 else 60 in_SHIFTER_COMPLETION= new SC_IN (Tdata_t) * [_param._nb_port]; 61 out_SHIFTER_DATA = new SC_OUT(Tdata_t) * [_param._nb_port]; 62 63 for (uint32_t i=0; i<_param._nb_port; i++) 64 { 65 Interface_fifo * interface = _interfaces->set_interface("shifter_"+toString(i) 66 #ifdef POSITION 67 , IN 68 , SOUTH 69 , "Generalist interface" 70 #endif 71 ); 72 73 in_SHIFTER_DATA [i] = interface->set_signal_in <Tdata_t > ("data" ,_param._size_data); 74 if (_param._shift_value == 0) 75 in_SHIFTER_SHIFT [i] = interface->set_signal_in <Tshift_t > ("shift" ,static_cast<uint32_t>(ceil(log2(_param._size_data)))); 76 if (_param._direction == external_direction) 77 in_SHIFTER_DIRECTION [i] = interface->set_signal_in <Tdirection_t> ("direction" ,1); 78 if (_param._rotate == external_rotate) 79 in_SHIFTER_TYPE [i] = interface->set_signal_in <Ttype_t > ("type" ,1); 80 if (_param._carry == external_carry) 81 in_SHIFTER_CARRY [i] = interface->set_signal_in <Tcarry_t > ("carry" ,1); 82 if (_param._carry == external_completion) 83 if (_param._type_completion_bool == true) 84 in_SHIFTER_CARRY_IN [i] = interface->set_signal_in <Tcontrol_t > ("carry_in" ,1); 85 else 86 in_SHIFTER_COMPLETION [i] = interface->set_signal_in <Tdata_t > ("completion",_param._size_data_completion); 87 out_SHIFTER_DATA [i] = interface->set_signal_out <Tdata_t > ("data" ,_param._size_data); 88 } 89 } 45 90 46 if (_param._shift_value == 0) 47 { 48 rename = "in_SHIFTER_SHIFT[" + toString(i) + "]"; 49 in_SHIFTER_SHIFT [i] = new SC_IN (Tshift_t) (rename.c_str()); 50 } 51 if (_param._direction == external_direction) 52 { 53 rename = "in_SHIFTER_DIRECTION[" + toString(i) + "]"; 54 in_SHIFTER_DIRECTION [i] = new SC_IN (Tdirection_t) (rename.c_str()); 55 } 56 if (_param._rotate == external_rotate) 57 { 58 rename = "in_SHIFTER_TYPE[" + toString(i) + "]"; 59 in_SHIFTER_TYPE [i] = new SC_IN (Ttype_t) (rename.c_str()); 60 } 61 if (_param._carry == external_carry) 62 { 63 rename = "in_SHIFTER_CARRY[" + toString(i) + "]"; 64 in_SHIFTER_CARRY [i] = new SC_IN (Tcarry_t) (rename.c_str()); 65 } 91 #ifdef POSITION 92 _component->generate_file(); 93 #endif 66 94 67 if (_param._carry == external_completion)68 if (_param._type_completion_bool == true)69 {70 rename = "in_SHIFTER_CARRY_IN[" + toString(i) + "]";71 in_SHIFTER_CARRY_IN [i] = new SC_IN (Tcontrol_t) (rename.c_str());72 }73 else74 {75 rename = "in_SHIFTER_COMPLETION[" + toString(i) + "]";76 in_SHIFTER_COMPLETION [i] = new SC_IN (Tdata_t) (rename.c_str());77 }78 79 rename = "out_SHIFTER_DATA[" + toString(i) + "]";80 out_SHIFTER_DATA [i] = new SC_OUT(Tdata_t) (rename.c_str());81 }82 95 }; 83 96 84 97 }; // end namespace shifter 85 98 }; // end namespace generic -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp
r2 r42 18 18 { 19 19 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 20 delete in_CLOCK;20 delete in_CLOCK; 21 21 #endif 22 22 23 // Interface "shifter" 24 for (uint32_t i=0; i<_param._nb_port; i++) 25 { 26 delete in_SHIFTER_DATA [i]; 27 if (_param._shift_value == 0) 28 delete in_SHIFTER_SHIFT [i]; 29 if (_param._direction == external_direction) 30 delete in_SHIFTER_DIRECTION [i]; 31 if (_param._rotate == external_rotate) 32 delete in_SHIFTER_TYPE [i]; 33 if (_param._carry == external_carry) 34 delete in_SHIFTER_CARRY [i]; 35 if (_param._carry == external_completion) 36 if (_param._type_completion_bool == true) 37 delete in_SHIFTER_CARRY_IN [i]; 38 else 39 delete in_SHIFTER_COMPLETION[i]; 40 delete out_SHIFTER_DATA [i]; 41 } 23 delete [] in_SHIFTER_DATA ; 24 if (_param._shift_value == 0) 25 delete [] in_SHIFTER_SHIFT ; 26 if (_param._direction == external_direction ) 27 delete [] in_SHIFTER_DIRECTION ; 28 if (_param._rotate == external_rotate ) 29 delete [] in_SHIFTER_TYPE ; 30 if (_param._carry == external_carry ) 31 delete [] in_SHIFTER_CARRY ; 32 if (_param._carry == external_completion) 33 if (_param._type_completion_bool == true) 34 delete [] in_SHIFTER_CARRY_IN ; 35 else 36 delete [] in_SHIFTER_COMPLETION; 37 delete [] out_SHIFTER_DATA ; 42 38 43 delete in_SHIFTER_DATA ; 44 if (_param._shift_value == 0) 45 delete in_SHIFTER_SHIFT ; 46 if (_param._direction == external_direction ) 47 delete in_SHIFTER_DIRECTION ; 48 if (_param._rotate == external_rotate ) 49 delete in_SHIFTER_TYPE ; 50 if (_param._carry == external_carry ) 51 delete in_SHIFTER_CARRY ; 52 if (_param._carry == external_completion) 53 if (_param._type_completion_bool == true) 54 delete in_SHIFTER_CARRY_IN ; 55 else 56 delete in_SHIFTER_COMPLETION; 57 delete out_SHIFTER_DATA ; 39 delete _component; 40 58 41 }; 59 42 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_transition.cpp
r2 r42 23 23 24 24 #ifdef VHDL_TESTBENCH 25 vhdl_testbench_transition ( *_vhdl_testbench);25 vhdl_testbench_transition (); 26 26 #endif 27 27 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl.cpp
r2 r42 18 18 void Shifter::vhdl (void) 19 19 { 20 Vhdl vhdl (_name);20 Vhdl * vhdl = new Vhdl (_name); 21 21 22 vhdl .set_library_work (_name + "_Pack");22 vhdl->set_library_work (_name + "_Pack"); 23 23 24 24 vhdl_port (vhdl); … … 26 26 vhdl_body (vhdl); 27 27 28 vhdl.generate_file(); 28 vhdl->generate_file(); 29 30 delete vhdl; 29 31 }; 30 32 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_body.cpp
r2 r42 15 15 16 16 17 void Shifter::vhdl_body (Vhdl & vhdl)17 void Shifter::vhdl_body (Vhdl * & vhdl) 18 18 { 19 19 //uint32_t log2_size_data = static_cast<uint32_t>(ceil(log2(_param._size_data))); 20 20 21 vhdl .set_body ("-- Compute all case of shift");21 vhdl->set_body ("-- Compute all case of shift"); 22 22 23 23 for (uint32_t i=0; i<_param._nb_port; i++) … … 25 25 //-----[ Shift logic Left ]-------------------------------------------- 26 26 if (_param._have_shift_logic_left) 27 vhdl .set_body ("shift_logic_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") sll CONV_INTEGER(shift_"+toString(i)+"));");27 vhdl->set_body ("shift_logic_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) sll CONV_INTEGER(shift_"+toString(i)+"));"); 28 28 //-----[ Shift logic Right ]------------------------------------------- 29 29 if (_param._have_shift_logic_right) 30 vhdl .set_body ("shift_logic_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") srl CONV_INTEGER(shift_"+toString(i)+"));");30 vhdl->set_body ("shift_logic_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) srl CONV_INTEGER(shift_"+toString(i)+"));"); 31 31 //-----[ Shift arithmetic Left ]--------------------------------------- 32 32 if (_param._have_shift_arithmetic_left) 33 vhdl .set_body ("shift_arithmetic_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") sla CONV_INTEGER(shift_"+toString(i)+"));");33 vhdl->set_body ("shift_arithmetic_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) sla CONV_INTEGER(shift_"+toString(i)+"));"); 34 34 //-----[ Shift arithmetic Right ]-------------------------------------- 35 35 if (_param._have_shift_arithmetic_right) 36 vhdl .set_body ("shift_arithmetic_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") sra CONV_INTEGER(shift_"+toString(i)+"));");36 vhdl->set_body ("shift_arithmetic_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) sra CONV_INTEGER(shift_"+toString(i)+"));"); 37 37 //-----[ Rotate Left ]------------------------------------------------- 38 38 if (_param._have_rotate_left) 39 vhdl .set_body ("rotate_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") rol CONV_INTEGER(shift_"+toString(i)+"));");39 vhdl->set_body ("rotate_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) rol CONV_INTEGER(shift_"+toString(i)+"));"); 40 40 //-----[ Rotate Right ]------------------------------------------------ 41 41 if (_param._have_rotate_right) 42 vhdl .set_body ("rotate_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") ror CONV_INTEGER(shift_"+toString(i)+"));");42 vhdl->set_body ("rotate_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) ror CONV_INTEGER(shift_"+toString(i)+"));"); 43 43 } 44 44 45 45 if (_param._size_data_completion > 0) 46 46 { 47 vhdl .set_body ("");48 vhdl .set_body ("-- Mask");47 vhdl->set_body (""); 48 vhdl->set_body ("-- Mask"); 49 49 50 50 for (uint32_t i=0; i<_param._nb_port; i++) … … 53 53 54 54 if (_param._type_completion_bool == true) 55 print_shifter_completion = "in_SHIFTER_ CARRY_IN";55 print_shifter_completion = "in_SHIFTER_"+toString(i)+"_CARRY_IN"; 56 56 else 57 print_shifter_completion = "in_SHIFTER_ COMPLETION";57 print_shifter_completion = "in_SHIFTER_"+toString(i)+"_COMPLETION"; 58 58 59 59 if (_param._size_data == _param._size_data_completion) 60 60 { 61 vhdl .set_body ("shifter_completion_left_"+toString(i)+" <= "+print_shifter_completion+"_"+toString(i)+";");62 vhdl .set_body ("shifter_completion_right_"+toString(i)+" <= "+print_shifter_completion+"_"+toString(i)+";");61 vhdl->set_body ("shifter_completion_left_"+toString(i)+" <= "+print_shifter_completion+";"); 62 vhdl->set_body ("shifter_completion_right_"+toString(i)+" <= "+print_shifter_completion+";"); 63 63 } 64 64 else 65 65 { 66 vhdl .set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data_completion)+" <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";");67 vhdl .set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data_completion )+" <= "+print_shifter_completion+"_"+toString(i)+";");68 69 vhdl .set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data-_param._size_data_completion)+" <= "+print_shifter_completion+"_"+toString(i)+";");70 vhdl .set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-_param._size_data_completion )+" <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";");71 } 72 73 vhdl .set_body ("mask_completion_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) sll CONV_INTEGER(shift_"+toString(i)+"));");74 vhdl .set_body ("mask_completion_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) srl CONV_INTEGER(shift_"+toString(i)+"));");66 vhdl->set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data_completion)+" <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";"); 67 vhdl->set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data_completion )+" <= "+print_shifter_completion+";"); 68 69 vhdl->set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data-_param._size_data_completion)+" <= "+print_shifter_completion+";"); 70 vhdl->set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-_param._size_data_completion )+" <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";"); 71 } 72 73 vhdl->set_body ("mask_completion_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) sll CONV_INTEGER(shift_"+toString(i)+"));"); 74 vhdl->set_body ("mask_completion_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) srl CONV_INTEGER(shift_"+toString(i)+"));"); 75 75 } 76 76 } 77 77 78 78 79 vhdl .set_body ("");80 vhdl .set_body ("-- Multiplexor");79 vhdl->set_body (""); 80 vhdl->set_body ("-- Multiplexor"); 81 81 82 82 for (uint32_t i=0; i<_param._nb_port; i++) 83 83 { 84 vhdl .set_body ("out_SHIFTER_DATA_"+toString(i)+"<=");84 vhdl->set_body ("out_SHIFTER_"+toString(i)+"_DATA <="); 85 85 string print_else = " "; 86 86 … … 95 95 { 96 96 have_when = true; 97 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_left ";98 print_and = " and "; 99 } 100 if (_param._rotate == external_rotate) 101 { 102 have_when = true; 103 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_shift ";97 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_left "; 98 print_and = " and "; 99 } 100 if (_param._rotate == external_rotate) 101 { 102 have_when = true; 103 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_shift "; 104 104 print_and = " and "; 105 105 } … … 107 107 { 108 108 have_when = true; 109 print_when += print_and+" in_SHIFTER_ CARRY_"+toString(i)+"= cst_is_carry_arithmetic";110 } 111 112 if (have_when) 113 print_when = "when " + print_when; 114 115 vhdl .set_body ("\t"+print_else+" shift_arithmetic_left_"+toString(i)+" "+print_when);109 print_when += print_and+" in_SHIFTER_"+toString(i)+"_CARRY = cst_is_carry_arithmetic"; 110 } 111 112 if (have_when) 113 print_when = "when " + print_when; 114 115 vhdl->set_body ("\t"+print_else+" shift_arithmetic_left_"+toString(i)+" "+print_when); 116 116 print_else = "else"; 117 117 } … … 126 126 { 127 127 have_when = true; 128 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_right";129 print_and = " and "; 130 } 131 if (_param._rotate == external_rotate) 132 { 133 have_when = true; 134 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_shift ";128 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_right"; 129 print_and = " and "; 130 } 131 if (_param._rotate == external_rotate) 132 { 133 have_when = true; 134 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_shift "; 135 135 print_and = " and "; 136 136 } … … 138 138 { 139 139 have_when = true; 140 print_when += print_and+" in_SHIFTER_ CARRY_"+toString(i)+"= cst_is_carry_arithmetic";141 } 142 143 if (have_when) 144 print_when = "when " + print_when; 145 146 vhdl .set_body ("\t"+print_else+" shift_arithmetic_right_"+toString(i)+" "+print_when);140 print_when += print_and+" in_SHIFTER_"+toString(i)+"_CARRY = cst_is_carry_arithmetic"; 141 } 142 143 if (have_when) 144 print_when = "when " + print_when; 145 146 vhdl->set_body ("\t"+print_else+" shift_arithmetic_right_"+toString(i)+" "+print_when); 147 147 print_else = "else"; 148 148 } … … 157 157 { 158 158 have_when = true; 159 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_left ";160 print_and = " and "; 161 } 162 if (_param._rotate == external_rotate) 163 { 164 have_when = true; 165 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_shift ";159 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_left "; 160 print_and = " and "; 161 } 162 if (_param._rotate == external_rotate) 163 { 164 have_when = true; 165 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_shift "; 166 166 print_and = " and "; 167 167 } … … 169 169 { 170 170 have_when = true; 171 print_when += print_and+" in_SHIFTER_ CARRY_"+toString(i)+"= cst_is_carry_logic ";171 print_when += print_and+" in_SHIFTER_"+toString(i)+"_CARRY = cst_is_carry_logic "; 172 172 } 173 173 … … 182 182 print_expr_completion = "(shift_logic_left_"+toString(i)+" and mask_completion_left_"+toString(i)+" ) or ( shifter_completion_left_"+toString(i)+" and not mask_completion_left_"+toString(i)+" )"; 183 183 184 vhdl .set_body ("\t"+print_else+" "+print_expr_completion+" "+print_when);184 vhdl->set_body ("\t"+print_else+" "+print_expr_completion+" "+print_when); 185 185 print_else = "else"; 186 186 } … … 195 195 { 196 196 have_when = true; 197 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_right";198 print_and = " and "; 199 } 200 if (_param._rotate == external_rotate) 201 { 202 have_when = true; 203 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_shift ";197 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_right"; 198 print_and = " and "; 199 } 200 if (_param._rotate == external_rotate) 201 { 202 have_when = true; 203 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_shift "; 204 204 print_and = " and "; 205 205 } … … 207 207 { 208 208 have_when = true; 209 print_when += print_and+" in_SHIFTER_ CARRY_"+toString(i)+"= cst_is_carry_logic ";209 print_when += print_and+" in_SHIFTER_"+toString(i)+"_CARRY = cst_is_carry_logic "; 210 210 } 211 211 … … 220 220 print_expr_completion = "(shift_logic_right_"+toString(i)+" and mask_completion_right_"+toString(i)+") or ( shifter_completion_right_"+toString(i)+" and not mask_completion_right_"+toString(i)+")"; 221 221 222 vhdl .set_body ("\t"+print_else+" "+print_expr_completion+" "+print_when);222 vhdl->set_body ("\t"+print_else+" "+print_expr_completion+" "+print_when); 223 223 print_else = "else"; 224 224 } … … 233 233 { 234 234 have_when = true; 235 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_left ";236 print_and = " and "; 237 } 238 if (_param._rotate == external_rotate) 239 { 240 have_when = true; 241 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_rotate";242 print_and = " and "; 243 } 244 245 if (have_when) 246 print_when = "when " + print_when; 247 248 vhdl .set_body ("\t"+print_else+" rotate_left_"+toString(i)+" "+print_when);235 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_left "; 236 print_and = " and "; 237 } 238 if (_param._rotate == external_rotate) 239 { 240 have_when = true; 241 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_rotate"; 242 print_and = " and "; 243 } 244 245 if (have_when) 246 print_when = "when " + print_when; 247 248 vhdl->set_body ("\t"+print_else+" rotate_left_"+toString(i)+" "+print_when); 249 249 print_else = "else"; 250 250 } … … 259 259 { 260 260 have_when = true; 261 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_right";262 print_and = " and "; 263 } 264 if (_param._rotate == external_rotate) 265 { 266 have_when = true; 267 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_rotate";268 print_and = " and "; 269 } 270 271 if (have_when) 272 print_when = "when " + print_when; 273 274 vhdl .set_body ("\t"+print_else+" rotate_right_"+toString(i)+" "+print_when);275 print_else = "else"; 276 } 277 vhdl .set_body (";");261 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_right"; 262 print_and = " and "; 263 } 264 if (_param._rotate == external_rotate) 265 { 266 have_when = true; 267 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_rotate"; 268 print_and = " and "; 269 } 270 271 if (have_when) 272 print_when = "when " + print_when; 273 274 vhdl->set_body ("\t"+print_else+" rotate_right_"+toString(i)+" "+print_when); 275 print_else = "else"; 276 } 277 vhdl->set_body (";"); 278 278 } 279 279 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_declaration.cpp
r2 r42 15 15 16 16 17 void Shifter::vhdl_declaration (Vhdl & vhdl)17 void Shifter::vhdl_declaration (Vhdl * & vhdl) 18 18 { 19 19 uint32_t log2_size_data = static_cast<uint32_t>(ceil(log2(_param._size_data))); 20 20 21 vhdl .set_constant("cst_is_direction_left ",1,_left );22 vhdl .set_constant("cst_is_direction_right ",1,_right );23 vhdl .set_constant("cst_is_type_shift ",1,_shift );24 vhdl .set_constant("cst_is_type_rotate ",1,_rotate );25 vhdl .set_constant("cst_is_carry_arithmetic",1,_arithmetic);26 vhdl .set_constant("cst_is_carry_logic ",1,_logic );27 vhdl .set_constant("cst_completion ",_param._size_data,"(others => '1')");21 vhdl->set_constant("cst_is_direction_left ",1,_left ); 22 vhdl->set_constant("cst_is_direction_right ",1,_right ); 23 vhdl->set_constant("cst_is_type_shift ",1,_shift ); 24 vhdl->set_constant("cst_is_type_rotate ",1,_rotate ); 25 vhdl->set_constant("cst_is_carry_arithmetic",1,_arithmetic); 26 vhdl->set_constant("cst_is_carry_logic ",1,_logic ); 27 vhdl->set_constant("cst_completion ",_param._size_data,"(others => '1')"); 28 28 29 29 for (uint32_t i=0; i<_param._nb_port; i++) 30 30 { 31 31 if (_param._shift_value != 0) 32 vhdl .set_constant("shift_"+toString(i),log2_size_data, _param._shift_value);32 vhdl->set_constant("shift_"+toString(i),log2_size_data, _param._shift_value); 33 33 else 34 vhdl .set_alias ("shift_"+toString(i),std_logic(log2_size_data), "in_SHIFTER_SHIFT_"+toString(i),std_logic_range(log2_size_data));34 vhdl->set_alias ("shift_"+toString(i),std_logic(log2_size_data), "in_SHIFTER_"+toString(i)+"_SHIFT",std_logic_range(log2_size_data)); 35 35 36 36 if (_param._size_data_completion > 0) 37 37 { 38 vhdl .set_signal ("shifter_completion_left_"+toString(i)+" ",_param._size_data);39 vhdl .set_signal ("shifter_completion_right_"+toString(i)+"",_param._size_data);40 vhdl .set_signal ("mask_completion_left_"+toString(i)+" ",_param._size_data);41 vhdl .set_signal ("mask_completion_right_"+toString(i)+" ",_param._size_data);38 vhdl->set_signal ("shifter_completion_left_"+toString(i)+" ",_param._size_data); 39 vhdl->set_signal ("shifter_completion_right_"+toString(i)+"",_param._size_data); 40 vhdl->set_signal ("mask_completion_left_"+toString(i)+" ",_param._size_data); 41 vhdl->set_signal ("mask_completion_right_"+toString(i)+" ",_param._size_data); 42 42 } 43 43 44 44 //-----[ Shift logic Left ]-------------------------------------------- 45 45 if (_param._have_shift_logic_left) 46 vhdl .set_signal ("shift_logic_left_"+toString(i)+" ",_param._size_data);46 vhdl->set_signal ("shift_logic_left_"+toString(i)+" ",_param._size_data); 47 47 48 48 //-----[ Shift logic Right ]------------------------------------------- 49 49 if (_param._have_shift_logic_right) 50 vhdl .set_signal ("shift_logic_right_"+toString(i)+" ",_param._size_data);50 vhdl->set_signal ("shift_logic_right_"+toString(i)+" ",_param._size_data); 51 51 52 52 //-----[ Shift arithmetic Left ]--------------------------------------- 53 53 if (_param._have_shift_arithmetic_left) 54 vhdl .set_signal ("shift_arithmetic_left_"+toString(i)+" ",_param._size_data);54 vhdl->set_signal ("shift_arithmetic_left_"+toString(i)+" ",_param._size_data); 55 55 56 56 //-----[ Shift arithmetic Right ]-------------------------------------- 57 57 if (_param._have_shift_arithmetic_right) 58 vhdl .set_signal ("shift_arithmetic_right_"+toString(i)+"",_param._size_data);58 vhdl->set_signal ("shift_arithmetic_right_"+toString(i)+"",_param._size_data); 59 59 60 60 //-----[ Rotate Left ]------------------------------------------------- 61 61 if (_param._have_rotate_left) 62 vhdl .set_signal ("rotate_left_"+toString(i)+" ",_param._size_data);62 vhdl->set_signal ("rotate_left_"+toString(i)+" ",_param._size_data); 63 63 64 64 //-----[ Rotate Right ]------------------------------------------------ 65 65 if (_param._have_rotate_right) 66 vhdl .set_signal ("rotate_right_"+toString(i)+" ",_param._size_data);66 vhdl->set_signal ("rotate_right_"+toString(i)+" ",_param._size_data); 67 67 } 68 68 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_port.cpp
r2 r42 15 15 16 16 17 void Shifter::vhdl_port (Vhdl & vhdl)17 void Shifter::vhdl_port (Vhdl * & vhdl) 18 18 { 19 for (uint32_t i=0; i<_param._nb_port; i++) 20 { 21 vhdl.set_port (" in_SHIFTER_DATA_"+toString(i)+" ", IN, _param._size_data); 22 if (_param._shift_value == 0) 23 vhdl.set_port (" in_SHIFTER_SHIFT_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._size_data)))); 24 if (_param._direction == external_direction) 25 vhdl.set_port (" in_SHIFTER_DIRECTION_"+toString(i)+" ", IN, 1); 26 if (_param._rotate == external_rotate) 27 vhdl.set_port (" in_SHIFTER_TYPE_"+toString(i)+" ", IN, 1); 28 if (_param._carry == external_carry) 29 vhdl.set_port (" in_SHIFTER_CARRY_"+toString(i)+" ", IN, 1); 30 if (_param._carry == external_completion) 31 if (_param._type_completion_bool == true) 32 vhdl.set_port (" in_SHIFTER_CARRY_IN_"+toString(i)+" ", IN, 1); 33 else 34 vhdl.set_port (" in_SHIFTER_COMPLETION_"+toString(i)+"", IN, _param._size_data_completion); 35 36 vhdl.set_port ("out_SHIFTER_DATA_"+toString(i)+" ",OUT, _param._size_data); 37 } 19 _interfaces->set_port(vhdl); 38 20 }; 39 21 }; // end namespace shifter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_testbench_transition.cpp
r2 r42 15 15 16 16 17 void Shifter::vhdl_testbench_transition ( Vhdl_Testbench & vhdl_testbench)17 void Shifter::vhdl_testbench_transition (void) 18 18 { 19 #ifndef SYSTEMCASS_SPECIFIC 20 sc_cycle(0); 21 #endif 19 sc_start(0); 22 20 23 // In order with file Shifter_vhdl_testbench_port.cpp 24 25 for (uint32_t i=0; i<_param._nb_port; i++) 26 { 27 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_DATA [i])); 28 if (_param._shift_value == 0) 29 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_SHIFT [i])); 30 if (_param._direction == external_direction) 31 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_DIRECTION [i])); 32 if (_param._rotate == external_rotate) 33 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_TYPE [i])); 34 if (_param._carry == external_carry) 35 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_CARRY [i])); 36 if (_param._carry == external_completion) 37 if (_param._type_completion_bool == true) 38 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_CARRY_IN [i])); 39 else 40 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_COMPLETION[i])); 41 vhdl_testbench.add_output (PORT_READ(out_SHIFTER_DATA [i])); 42 } 43 44 // add_test : 45 // - True : the cycle must be compare with the output of systemC 46 // - False : no test 47 vhdl_testbench.add_test(true); 48 49 vhdl_testbench.new_cycle (); // always at the end 21 _interfaces->testbench(); 50 22 }; 51 23 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/configuration.cfg
r15 r42 1 1 Victim_Pseudo_LRU 2 4 4*2 # nb_entity3 1 1 +2 # nb_access4 1 1 +2 # nb_update5 1 1 2 4 16 *2 # nb_entity 3 1 4 *2 # nb_access 4 1 4 *2 # nb_update 5 1 16 *2 # size_table -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h
r15 r42 40 40 #include "Behavioural/include/Vhdl.h" 41 41 #endif 42 #ifdef VHDL_TESTBENCH 43 #include "Behavioural/include/Vhdl_Testbench.h" 42 #ifdef POSITION 43 #include "Behavioural/include/Component.h" 44 #else 45 #include "Behavioural/include/Interfaces.h" 44 46 #endif 45 47 … … 175 177 #endif 176 178 177 #ifdef VHDL_TESTBENCH 178 private : Vhdl_Testbench * _vhdl_testbench; 179 #endif 179 #ifdef POSITION 180 private : Component * _component; 181 #endif 182 private : Interfaces * _interfaces; 180 183 181 184 #ifdef SYSTEMC … … 237 240 #if VHDL 238 241 public : void vhdl (void); 239 private : void vhdl_port (Vhdl & vhdl);240 private : void vhdl_declaration (Vhdl & vhdl);241 private : void vhdl_body (Vhdl & vhdl);242 private : void vhdl_port (Vhdl * & vhdl); 243 private : void vhdl_declaration (Vhdl * & vhdl); 244 private : void vhdl_body (Vhdl * & vhdl); 242 245 #endif 243 246 244 247 #ifdef VHDL_TESTBENCH 245 private : void vhdl_testbench (Vhdl_Testbench & vhdl_testbench); 246 private : void vhdl_testbench_port (Vhdl_Testbench & vhdl_testbench); 247 private : void vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench); 248 private : void vhdl_testbench_transition (void); 248 249 #endif 249 250 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU.cpp
r15 r42 28 28 log_printf(FUNC,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Begin"); 29 29 30 #ifdef SYSTEMC 31 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation"); 32 allocation (); 33 #endif 34 30 35 #ifdef STATISTICS 31 36 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation of statistics"); … … 37 42 #endif 38 43 39 #ifdef VHDL_TESTBENCH40 // Creation of a testbench41 // -> port42 // -> clock's signals43 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Creation of Testbench");44 _vhdl_testbench = new Vhdl_Testbench (_name);45 vhdl_testbench_port (*_vhdl_testbench);46 _vhdl_testbench->set_clock ("in_CLOCK",true);47 #endif48 49 44 #ifdef VHDL 50 45 // generate the vhdl … … 54 49 55 50 #ifdef SYSTEMC 56 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation");57 allocation ();58 59 51 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Definition of sc_method"); 60 52 SC_METHOD (transition); … … 100 92 #endif 101 93 102 #ifdef VHDL_TESTBENCH103 // generate the test bench104 _vhdl_testbench->generate_file();105 delete _vhdl_testbench;106 #endif107 108 94 #ifdef STATISTICS 109 95 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp
r15 r42 17 17 void Victim_Pseudo_LRU::allocation (void) 18 18 { 19 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 20 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET");19 #ifdef POSITION 20 _component = new Component (); 21 21 22 // -----[ Interface access ]------------------------------------------- 23 in_ACCESS_VAL = new SC_IN (Tcontrol_t) * [_param._nb_access]; 24 out_ACCESS_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_access]; 25 if (_param._size_table>1) 26 in_ACCESS_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_access]; 27 out_ACCESS_ENTITY = new SC_OUT(Tentity_t ) * [_param._nb_access]; 22 Entity * entity = _component->set_entity (_name , 23 "Select_Priority_Fixed", 24 COMBINATORY ); 28 25 29 for (uint32_t i=0; i<_param._nb_access; i++) 30 { 31 string rename; 26 _interfaces = entity->set_interfaces(); 27 #else 28 _interfaces = new Interfaces(); 29 #endif 32 30 33 rename = "in_ACCESS_VAL[" + toString(i) + "]"; 34 in_ACCESS_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 31 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 { 33 Interface_fifo * interface = _interfaces->set_interface("", IN ,WEST, "Generalist interface"); 34 35 in_CLOCK = interface->set_signal_clk ("clock" ,1); 36 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1); 37 } 35 38 36 rename = "out_ACCESS_ACK[" + toString(i) + "]"; 37 out_ACCESS_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 39 // ~~~~~[ Interface : "access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 40 { 41 in_ACCESS_VAL = new SC_IN (Tcontrol_t) * [_param._nb_access]; 42 out_ACCESS_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_access]; 43 if (_param._size_table>1) 44 in_ACCESS_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_access]; 45 out_ACCESS_ENTITY = new SC_OUT(Tentity_t ) * [_param._nb_access]; 46 47 for (uint32_t i=0; i<_param._nb_access; i++) 48 { 49 Interface_fifo * interface = _interfaces->set_interface("access_"+toString(i), IN ,WEST, "Access"); 38 50 39 if (_param._size_table>1)40 {41 rename = "in_ACCESS_ADDRESS[" + toString(i) + "]";42 in_ACCESS_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());43 }44 rename = "out_ACCESS_ENTITY[" + toString(i) + "]";45 out_ACCESS_ENTITY [i] = new SC_OUT(Tentity_t ) (rename.c_str());46 51 in_ACCESS_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 52 out_ACCESS_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 53 54 if (_param._size_table>1) 55 in_ACCESS_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address",static_cast<uint32_t>(log2(_param._size_table))); 56 out_ACCESS_ENTITY [i] = interface->set_signal_out <Tentity_t> ("entity" ,static_cast<uint32_t>(log2(_param._nb_entity ))); 57 } 58 } 47 59 48 // -----[ Interface update ]------------------------------------------- 49 in_UPDATE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_update]; 50 out_UPDATE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_update]; 51 if (_param._size_table>1) 52 in_UPDATE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_update]; 53 in_UPDATE_ENTITY = new SC_IN (Tentity_t ) * [_param._nb_update]; 60 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 61 62 { 63 in_UPDATE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_update]; 64 out_UPDATE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_update]; 65 if (_param._size_table>1) 66 in_UPDATE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_update]; 67 in_UPDATE_ENTITY = new SC_IN (Tentity_t ) * [_param._nb_update]; 68 69 for (uint32_t i=0; i<_param._nb_update; i++) 70 { 71 Interface_fifo * interface = _interfaces->set_interface("update_"+toString(i), IN ,EAST, "Update"); 54 72 55 for (uint32_t i=0; i<_param._nb_update; i++) 56 { 57 string rename; 58 59 rename = "in_UPDATE_VAL[" + toString(i) + "]"; 60 in_UPDATE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 61 62 rename = "out_UPDATE_ACK[" + toString(i) + "]";; 63 out_UPDATE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 64 65 if (_param._size_table>1) 66 { 67 rename = "in_UPDATE_ADDRESS[" + toString(i) + "]"; 68 in_UPDATE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 69 } 70 71 rename = "in_UPDATE_ENTITY[" + toString(i) + "]"; 72 in_UPDATE_ENTITY [i] = new SC_IN (Tentity_t ) (rename.c_str()); 73 } 74 73 in_UPDATE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 74 out_UPDATE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 75 if (_param._size_table>1) 76 in_UPDATE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address",static_cast<uint32_t>(log2(_param._size_table))); 77 in_UPDATE_ENTITY [i] = interface->set_signal_in <Tentity_t> ("entity" ,static_cast<uint32_t>(log2(_param._nb_entity ))); 78 } 79 } 75 80 // -----[ Register ]--------------------------------------------------- 76 81 reg_TABLE = new entry_t * [_param._size_table]; … … 81 86 // -----[ Internal ]--------------------------------------------------- 82 87 internal_ACCESS_ENTITY = new Tentity_t [_param._nb_entity]; 88 89 #ifdef POSITION 90 _component->generate_file(); 91 #endif 83 92 }; 84 93 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_deallocation.cpp
r15 r42 17 17 void Victim_Pseudo_LRU::deallocation (void) 18 18 { 19 delete in_CLOCK;20 delete in_NRESET;19 delete in_CLOCK; 20 delete in_NRESET; 21 21 // -----[ Interface access ]------------------------------------------- 22 for (uint32_t i=0; i<_param._nb_access; i++) 23 { 24 delete in_ACCESS_VAL [i]; 25 delete out_ACCESS_ACK [i]; 26 if (_param._size_table>1) 27 delete in_ACCESS_ADDRESS [i]; 28 delete out_ACCESS_ENTITY [i]; 29 } 30 31 delete in_ACCESS_VAL ; 32 delete out_ACCESS_ACK ; 22 delete [] in_ACCESS_VAL ; 23 delete [] out_ACCESS_ACK ; 33 24 if (_param._size_table>1) 34 delete in_ACCESS_ADDRESS;35 delete out_ACCESS_ENTITY ;25 delete [] in_ACCESS_ADDRESS; 26 delete [] out_ACCESS_ENTITY ; 36 27 37 28 // -----[ Interface update ]------------------------------------------- 38 for (uint32_t i=0; i<_param._nb_update; i++) 39 { 40 delete in_UPDATE_VAL [i]; 41 delete out_UPDATE_ACK [i]; 42 if (_param._size_table>1) 43 delete in_UPDATE_ADDRESS [i]; 44 delete in_UPDATE_ENTITY [i]; 45 } 46 delete in_UPDATE_VAL ; 47 delete out_UPDATE_ACK ; 29 delete [] in_UPDATE_VAL ; 30 delete [] out_UPDATE_ACK ; 48 31 if (_param._size_table>1) 49 delete in_UPDATE_ADDRESS;50 delete in_UPDATE_ENTITY ;32 delete [] in_UPDATE_ADDRESS; 33 delete [] in_UPDATE_ENTITY ; 51 34 52 35 // -----[ Register ]--------------------------------------------------- 53 for (uint32_t i=0; i<_param._size_table; i++) 54 { 55 delete reg_TABLE [i]; 56 } 57 delete reg_TABLE; 36 delete [] reg_TABLE; 58 37 59 38 // -----[ Internal ]--------------------------------------------------- 60 delete internal_ACCESS_ENTITY; 39 delete [] internal_ACCESS_ENTITY; 40 41 #ifdef POSITION 42 delete _component; 43 #else 44 delete _interfaces; 45 #endif 61 46 }; 62 47 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_transition.cpp
r15 r42 67 67 68 68 #ifdef VHDL_TESTBENCH 69 vhdl_testbench_transition ( *_vhdl_testbench);69 vhdl_testbench_transition (); 70 70 #endif 71 71 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl.cpp
r15 r42 22 22 23 23 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Construction of vhdl"); 24 Vhdl vhdl (_name);24 Vhdl * vhdl = new Vhdl (_name); 25 25 26 26 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Set library"); 27 vhdl .set_library_work (_name + "_Pack");27 vhdl->set_library_work (_name + "_Pack"); 28 28 29 29 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Set port"); … … 34 34 vhdl_body (vhdl); 35 35 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Generate File"); 36 vhdl.generate_file(); 36 vhdl->generate_file(); 37 38 delete vhdl; 37 39 log_printf(FUNC,Victim_Pseudo_LRU,"vhdl","End"); 38 40 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_body.cpp
r15 r42 15 15 namespace victim_pseudo_lru { 16 16 17 void Victim_Pseudo_LRU::vhdl_body (Vhdl & vhdl)17 void Victim_Pseudo_LRU::vhdl_body (Vhdl * & vhdl) 18 18 { 19 vhdl .set_body ("");20 vhdl .set_body ("-----------------------------------------------------------------------------");21 vhdl .set_body ("-- Access");22 vhdl .set_body ("-----------------------------------------------------------------------------");23 vhdl .set_body ("");24 vhdl .set_body ("-- Tree of Pseudo-LRU - example to 8 entity");25 vhdl .set_body ("--");26 vhdl .set_body ("-- 4-5-6-7? ");27 vhdl .set_body ("-- 0_______|_______1 ");28 vhdl .set_body ("-- | | ");29 vhdl .set_body ("-- 2-3? 6-7? ");30 vhdl .set_body ("-- 0___|___1 0___|___1 ");31 vhdl .set_body ("-- | | | | ");32 vhdl .set_body ("-- 1? 3? 5? 7? ");33 vhdl .set_body ("-- 0_|_1 0_|_1 0_|_1 0_|_1 ");34 vhdl .set_body ("-- | | | | | | | | ");35 vhdl .set_body ("-- Way Way Way Way Way Way Way Way ");36 vhdl .set_body ("-- 0 1 2 3 4 5 6 7 ");37 for (uint32_t i=0; i<_param._nb_access; i++) 38 { 39 vhdl .set_body ("");19 vhdl->set_body (""); 20 vhdl->set_body ("-----------------------------------------------------------------------------"); 21 vhdl->set_body ("-- Access"); 22 vhdl->set_body ("-----------------------------------------------------------------------------"); 23 vhdl->set_body (""); 24 vhdl->set_body ("-- Tree of Pseudo-LRU - example to 8 entity"); 25 vhdl->set_body ("--"); 26 vhdl->set_body ("-- 4-5-6-7? "); 27 vhdl->set_body ("-- 0_______|_______1 "); 28 vhdl->set_body ("-- | | "); 29 vhdl->set_body ("-- 2-3? 6-7? "); 30 vhdl->set_body ("-- 0___|___1 0___|___1 "); 31 vhdl->set_body ("-- | | | | "); 32 vhdl->set_body ("-- 1? 3? 5? 7? "); 33 vhdl->set_body ("-- 0_|_1 0_|_1 0_|_1 0_|_1 "); 34 vhdl->set_body ("-- | | | | | | | | "); 35 vhdl->set_body ("-- Way Way Way Way Way Way Way Way "); 36 vhdl->set_body ("-- 0 1 2 3 4 5 6 7 "); 37 for (uint32_t i=0; i<_param._nb_access; i++) 38 { 39 vhdl->set_body (""); 40 40 // Read the table 41 41 … … 43 43 44 44 if (_param._size_table>1) 45 access_address = "conv_integer(in_ACCESS_ ADDRESS_"+toString(i)+")";45 access_address = "conv_integer(in_ACCESS_"+toString(i)+"_ADDRESS)"; 46 46 else 47 47 access_address = "0"; 48 48 49 vhdl .set_body ("access_entry_"+toString(i)+" <= reg_TABLE ("+access_address+");");50 vhdl .set_body ("");49 vhdl->set_body ("access_entry_"+toString(i)+" <= reg_TABLE ("+access_address+");"); 50 vhdl->set_body (""); 51 51 52 52 for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--) 53 53 { 54 vhdl .set_body ("access_entity_"+toString(i)+"("+toString(j)+") <= ");54 vhdl->set_body ("access_entity_"+toString(i)+"("+toString(j)+") <= "); 55 55 56 56 uint32_t cpt=0; … … 72 72 string print_else = (k==(1<<j)-1)?" ":"else "; 73 73 74 vhdl .set_body ("\t"+print_else+"access_entry_"+toString(i)+"("+toString(k)+") "+cond);74 vhdl->set_body ("\t"+print_else+"access_entry_"+toString(i)+"("+toString(k)+") "+cond); 75 75 cpt ++; 76 76 } 77 vhdl .set_body ("\t;");77 vhdl->set_body ("\t;"); 78 78 } 79 79 } 80 80 81 vhdl .set_body ("");82 vhdl .set_body ("-----------------------------------------------------------------------------");83 vhdl .set_body ("-- Update");84 vhdl .set_body ("-----------------------------------------------------------------------------");85 vhdl .set_body ("");86 vhdl .set_body ("-- port access");81 vhdl->set_body (""); 82 vhdl->set_body ("-----------------------------------------------------------------------------"); 83 vhdl->set_body ("-- Update"); 84 vhdl->set_body ("-----------------------------------------------------------------------------"); 85 vhdl->set_body (""); 86 vhdl->set_body ("-- port access"); 87 87 for (uint32_t i=0; i<_param._nb_access; i++) 88 88 for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--) … … 107 107 } 108 108 109 vhdl .set_body ("access_next_entry_"+toString(i)+"("+toString(k)+") <=");110 vhdl .set_body ("\tnot access_entity_"+toString(i)+"("+toString(j)+") "+cond);109 vhdl->set_body ("access_next_entry_"+toString(i)+"("+toString(k)+") <="); 110 vhdl->set_body ("\tnot access_entity_"+toString(i)+"("+toString(j)+") "+cond); 111 111 if (have_cond == true) 112 vhdl .set_body ("\telse access_entry_"+toString(i)+"("+toString(k)+")");113 vhdl .set_body ("\t;");112 vhdl->set_body ("\telse access_entry_"+toString(i)+"("+toString(k)+")"); 113 vhdl->set_body ("\t;"); 114 114 cpt ++; 115 115 } 116 116 } 117 117 118 vhdl .set_body ("");119 vhdl .set_body ("-- port update");118 vhdl->set_body (""); 119 vhdl->set_body ("-- port update"); 120 120 for (uint32_t i=0; i<_param._nb_update; i++) 121 121 for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--) … … 137 137 else 138 138 cond += " and"; 139 cond += " in_UPDATE_ ENTITY_"+toString(i)+"("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'";139 cond += " in_UPDATE_"+toString(i)+"_ENTITY("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'"; 140 140 } 141 141 142 vhdl .set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <=");143 vhdl .set_body ("\tnot in_UPDATE_ENTITY_"+toString(i)+"("+toString(j)+") "+cond);142 vhdl->set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <="); 143 vhdl->set_body ("\tnot in_UPDATE_"+toString(i)+"_ENTITY("+toString(j)+") "+cond); 144 144 if (have_cond == true) 145 145 { … … 147 147 148 148 if (_param._size_table>1) 149 update_address = "conv_integer(in_UPDATE_ ADDRESS_"+toString(i)+")";149 update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; 150 150 else 151 151 update_address = "0"; 152 152 153 vhdl .set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")");153 vhdl->set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")"); 154 154 } 155 vhdl .set_body ("\t;");155 vhdl->set_body ("\t;"); 156 156 cpt ++; 157 157 } 158 158 } 159 159 160 vhdl .set_body ("");161 vhdl .set_body ("-----------------------------------------------------------------------------");162 vhdl .set_body ("-- Transition");163 vhdl .set_body ("-----------------------------------------------------------------------------");164 vhdl .set_body ("");165 166 vhdl .set_body ("reg_TABLE_write: process (in_CLOCK)");167 vhdl .set_body ("begin");168 vhdl .set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then");169 vhdl .set_body ("\t\t-- Access port");160 vhdl->set_body (""); 161 vhdl->set_body ("-----------------------------------------------------------------------------"); 162 vhdl->set_body ("-- Transition"); 163 vhdl->set_body ("-----------------------------------------------------------------------------"); 164 vhdl->set_body (""); 165 166 vhdl->set_body ("reg_TABLE_write: process (in_CLOCK)"); 167 vhdl->set_body ("begin"); 168 vhdl->set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then"); 169 vhdl->set_body ("\t\t-- Access port"); 170 170 for (uint32_t i=0; i<_param._nb_access; i++) 171 171 { … … 173 173 174 174 if (_param._size_table>1) 175 access_address = "conv_integer(in_ACCESS_ ADDRESS_"+toString(i)+")";175 access_address = "conv_integer(in_ACCESS_"+toString(i)+"_ADDRESS)"; 176 176 else 177 177 access_address = "0"; 178 178 179 vhdl .set_body ("\t\tif (in_ACCESS_VAL_"+toString(i)+"= '1') then");180 vhdl .set_body ("\t\t\treg_TABLE ("+access_address+") <= access_next_entry_"+toString(i)+";");181 vhdl .set_body ("\t\tend if;");182 } 183 184 vhdl .set_body ("\t\t-- Update port");179 vhdl->set_body ("\t\tif (in_ACCESS_"+toString(i)+"_VAL = '1') then"); 180 vhdl->set_body ("\t\t\treg_TABLE ("+access_address+") <= access_next_entry_"+toString(i)+";"); 181 vhdl->set_body ("\t\tend if;"); 182 } 183 184 vhdl->set_body ("\t\t-- Update port"); 185 185 for (uint32_t i=0; i<_param._nb_update; i++) 186 186 { … … 188 188 189 189 if (_param._size_table>1) 190 update_address = "conv_integer(in_UPDATE_ ADDRESS_"+toString(i)+")";190 update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; 191 191 else 192 192 update_address = "0"; 193 193 194 vhdl .set_body ("\t\tif (in_UPDATE_VAL_"+toString(i)+"= '1') then");195 vhdl .set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";");196 vhdl .set_body ("\t\tend if;");197 } 198 199 vhdl .set_body ("\tend if;");200 vhdl .set_body ("end process reg_TABLE_write;");201 202 vhdl .set_body ("");203 vhdl .set_body ("-----------------------------------------------------------------------------");204 vhdl .set_body ("-- Output");205 vhdl .set_body ("-----------------------------------------------------------------------------");206 vhdl .set_body ("");207 vhdl .set_body ("-- Ack is always ");208 vhdl .set_body ("");209 for (uint32_t i=0; i<_param._nb_access; i++) 210 { 211 vhdl .set_body ("out_ACCESS_ACK_"+toString(i)+"<= '1';");212 vhdl .set_body ("out_ACCESS_ENTITY_"+toString(i)+" <= access_entity_"+toString(i)+" when in_ACCESS_VAL_"+toString(i)+"= '1' else (others => '0');");213 } 214 vhdl .set_body ("");194 vhdl->set_body ("\t\tif (in_UPDATE_"+toString(i)+"_VAL = '1') then"); 195 vhdl->set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";"); 196 vhdl->set_body ("\t\tend if;"); 197 } 198 199 vhdl->set_body ("\tend if;"); 200 vhdl->set_body ("end process reg_TABLE_write;"); 201 202 vhdl->set_body (""); 203 vhdl->set_body ("-----------------------------------------------------------------------------"); 204 vhdl->set_body ("-- Output"); 205 vhdl->set_body ("-----------------------------------------------------------------------------"); 206 vhdl->set_body (""); 207 vhdl->set_body ("-- Ack is always "); 208 vhdl->set_body (""); 209 for (uint32_t i=0; i<_param._nb_access; i++) 210 { 211 vhdl->set_body ("out_ACCESS_"+toString(i)+"_ACK <= '1';"); 212 vhdl->set_body ("out_ACCESS_"+toString(i)+"_ENTITY <= access_entity_"+toString(i)+" when in_ACCESS_"+toString(i)+"_VAL = '1' else (others => '0');"); 213 } 214 vhdl->set_body (""); 215 215 for (uint32_t i=0; i<_param._nb_update; i++) 216 216 { 217 vhdl .set_body ("out_UPDATE_ACK_"+toString(i)+"<= '1';");217 vhdl->set_body ("out_UPDATE_"+toString(i)+"_ACK <= '1';"); 218 218 } 219 219 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_declaration.cpp
r15 r42 16 16 17 17 18 void Victim_Pseudo_LRU::vhdl_declaration (Vhdl & vhdl)18 void Victim_Pseudo_LRU::vhdl_declaration (Vhdl * & vhdl) 19 19 { 20 vhdl .set_type ("Ttable", "array (" + toString(_param._size_table-1) + " downto 0) of "+std_logic(_param._nb_entity-1));20 vhdl->set_type ("Ttable", "array (" + toString(_param._size_table-1) + " downto 0) of "+std_logic(_param._nb_entity-1)); 21 21 22 22 23 vhdl .set_signal ("reg_TABLE", "Ttable");23 vhdl->set_signal ("reg_TABLE", "Ttable"); 24 24 for (uint32_t i=0; i<_param._nb_access; i++) 25 25 { 26 vhdl .set_signal ("access_entry_"+toString(i)+" ",std_logic(_param._nb_entity-1));27 vhdl .set_signal ("access_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1));28 vhdl .set_signal ("access_entity_"+toString(i)+" ",std_logic(static_cast<uint32_t>(log2(_param._nb_entity))));26 vhdl->set_signal ("access_entry_"+toString(i)+" ",std_logic(_param._nb_entity-1)); 27 vhdl->set_signal ("access_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1)); 28 vhdl->set_signal ("access_entity_"+toString(i)+" ",std_logic(static_cast<uint32_t>(log2(_param._nb_entity)))); 29 29 } 30 30 31 31 for (uint32_t i=0; i<_param._nb_update; i++) 32 32 { 33 vhdl .set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1));33 vhdl->set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1)); 34 34 } 35 35 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_port.cpp
r15 r42 16 16 17 17 18 void Victim_Pseudo_LRU::vhdl_port (Vhdl & vhdl)18 void Victim_Pseudo_LRU::vhdl_port (Vhdl * & vhdl) 19 19 { 20 vhdl.set_port ("in_CLOCK ", IN, 1); 21 vhdl.set_port ("in_NRESET", IN, 1); 22 23 for (uint32_t i = 0; i < _param._nb_access; i ++) 24 { 25 vhdl.set_port (" in_ACCESS_VAL_"+toString(i)+" ",IN ,std_logic(1)); 26 vhdl.set_port ("out_ACCESS_ACK_"+toString(i)+" ",OUT,std_logic(1)); 27 if (_param._size_table>1) 28 vhdl.set_port (" in_ACCESS_ADDRESS_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._size_table)))); 29 vhdl.set_port ("out_ACCESS_ENTITY_"+toString(i)+" ",OUT,std_logic(static_cast<uint32_t>(log2(_param._nb_entity)))); 30 } 31 32 for (uint32_t i = 0; i < _param._nb_update; i ++) 33 { 34 vhdl.set_port (" in_UPDATE_VAL_"+toString(i)+" ",IN ,std_logic(1)); 35 vhdl.set_port ("out_UPDATE_ACK_"+toString(i)+" ",OUT,std_logic(1)); 36 if (_param._size_table>1) 37 vhdl.set_port (" in_UPDATE_ADDRESS_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._size_table)))); 38 vhdl.set_port (" in_UPDATE_ENTITY_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._nb_entity)))); 39 } 20 _interfaces->set_port(vhdl); 40 21 }; 41 22 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_testbench_transition.cpp
r15 r42 16 16 17 17 18 void Victim_Pseudo_LRU::vhdl_testbench_transition ( Vhdl_Testbench & vhdl_testbench)18 void Victim_Pseudo_LRU::vhdl_testbench_transition (void) 19 19 { 20 #ifndef SYSTEMCASS_SPECIFIC 21 sc_cycle(0); 22 #endif 23 vhdl_testbench.add_input (PORT_READ(in_NRESET)); 20 // Evaluation before read the ouput signal 21 sc_start(0); 24 22 25 for (uint32_t i = 0; i < _param._nb_access; i ++) 26 { 27 vhdl_testbench.add_input (PORT_READ( in_ACCESS_VAL [i])); 28 vhdl_testbench.add_output (PORT_READ(out_ACCESS_ACK [i])); 29 if (_param._size_table>1) 30 vhdl_testbench.add_input (PORT_READ( in_ACCESS_ADDRESS [i])); 31 vhdl_testbench.add_output (PORT_READ(out_ACCESS_ENTITY [i])); 32 } 33 34 for (uint32_t i = 0; i < _param._nb_update; i ++) 35 { 36 vhdl_testbench.add_input (PORT_READ( in_UPDATE_VAL [i])); 37 vhdl_testbench.add_output (PORT_READ(out_UPDATE_ACK [i])); 38 if (_param._size_table>1) 39 vhdl_testbench.add_input (PORT_READ( in_UPDATE_ADDRESS [i])); 40 vhdl_testbench.add_input (PORT_READ( in_UPDATE_ENTITY [i])); 41 } 42 43 vhdl_testbench.add_test(true); 44 45 vhdl_testbench.new_cycle (); // always at the end 23 _interfaces->testbench(); 46 24 }; 47 25
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