Changeset 42 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags

Timestamp:

Jul 5, 2007, 5:50:19 PM (17 years ago)

Author:

rosiere

Message:

Modification des classes d'encapsulation des interfaces :

• gère les signaux à écrire dans le vhdl
• les traces pour le testbench
• la génération des vhdl structurelles

-> test sur la Pattern History Table

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags

@@ -17 +17 @@
                                         -DVHDL                  \
                                         -DVHDL_TESTBENCH        \
-                                        -DCONFIGURATION         \
-                                        -DPOSITION              \
-                                        -DSTATISTICS            \
+                                        -DVHDL_TESTBENCH_ASSERT \
                                         -DDEBUG=DEBUG_NONE
 
+#                                       -DCONFIGURATION         \
+#                                       -DSTATISTICS            \
+#                                       -DPOSITION              \
+
 # Flags :
-# DEBUG={level}                 - Print Debug Message
-# SYSTEMC                       - To generate a systemc's model
-# VHDL                          - To generate a vhdl's    models
-# VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model
-# STATISTICS     (need SYSTEMC) - In the simulation, generate a statistics's file
-# POSITION                      - To generate a position's files     (it's input of viewer)
-# CONFIGURATION                 - To generate a configuration's file (it's input of viewer and generator)
+# DEBUG={level}                        - Print Debug Message
+# SYSTEMC                              - To generate a systemc's model
+# VHDL                                 - To generate a vhdl's    models
+# VHDL_TESTBENCH        (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model
+# VHDL_TESTBENCH_ASSERT (need SYSTEMC) - In the simulation, generate in  testbench's file an serie of assert
+# STATISTICS            (need SYSTEMC) - In the simulation, generate a statistics's file
+# POSITION                             - To generate a position's files     (it's input of viewer)
+# CONFIGURATION                        - To generate a configuration's file (it's input of viewer and generator)