Ignore:
Timestamp:
Jul 17, 2007, 4:47:56 PM (17 years ago)
Author:
rosiere
Message:

Modification des classes d'encapsulation des interfaces.
Stable sur tous les composants actuels

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_vhdl_testbench_transition.cpp

    r5 r44  
    2121    log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_transition","Begin");
    2222
    23     // Evaluation before read the ouput signal
    24     sc_start(0);
    25 
    26     // In order with file Meta_Predictor_Glue_vhdl_testbench_port.cpp
    27     // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
    28     // (because we have no control on the ordonnancer's policy)
    29 
    30     for (uint32_t i=0; i<_param._nb_prediction; i++)
    31       {
    32         if (_param._have_meta_predictor)
    33           {
    34         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_0_ACK [i]));
    35         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_1_ACK [i]));
    36           }
    37         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_2_ACK [i]));
    38         _vhdl_testbench->add_output(PORT_READ(out_PREDICT_ACK [i]));
    39 
    40         if (_param._have_meta_predictor)
    41           {
    42         if (_param._predictor_0_have_bht)
    43         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_0_BHT_HISTORY [i]));
    44         if (_param._predictor_0_have_pht)
    45         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_0_PHT_HISTORY [i]));
    46         if (_param._predictor_1_have_bht)
    47         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_1_BHT_HISTORY [i]));
    48         if (_param._predictor_1_have_pht)
    49         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_1_PHT_HISTORY [i]));
    50           }
    51         if (_param._predictor_2_have_bht)
    52         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_2_BHT_HISTORY [i]));
    53         if (_param._predictor_2_have_pht)
    54         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_2_PHT_HISTORY [i]));
    55 
    56         _vhdl_testbench->add_output(PORT_READ(out_PREDICT_HISTORY [i]));
    57         _vhdl_testbench->add_output(PORT_READ(out_PREDICT_DIRECTION [i]));
    58       }
    59 
    60     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    61       {
    62         if (_param._have_meta_predictor)
    63           {
    64         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL             [i]));
    65         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_VAL [i]));
    66 
    67         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PREDICTOR_0_ACK [i]));
    68         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PREDICTOR_1_ACK [i]));
    69           }
    70         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PREDICTOR_2_ACK [i]));
    71         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_ACK [i]));
    72 
    73         if (_param._have_meta_predictor)
    74           {
    75         if (_param._predictor_0_have_bht)
    76         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i]));
    77         if (_param._predictor_0_have_pht)
    78         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i]));
    79         if (_param._predictor_1_have_bht)
    80         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i]));
    81         if (_param._predictor_1_have_pht)
    82         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i]));
    83           }
    84         if (_param._predictor_2_have_bht)
    85         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i]));
    86         if (_param._predictor_2_have_pht)
    87         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i]));
    88 
    89         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY   [i]));
    90         if (_param._have_meta_predictor)
    91           {
    92         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION [i]));
    93         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i]));
    94           }
    95       }
    96    
    97     // add_test :
    98     //  - True  : the cycle must be compare with the output of systemC
    99     //  - False : no test
    100     _vhdl_testbench->add_test(true);
    101 
    102     _vhdl_testbench->new_cycle (); // always at the end
     23//  sc_start(0);
     24    _interfaces->testbench();
    10325
    10426    log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_transition","End");
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