Changeset 44 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp
- Timestamp:
- Jul 17, 2007, 4:47:56 PM (17 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp
r42 r44 20 20 void Branch_History_Table::vhdl_body (Vhdl * & vhdl) 21 21 { 22 // vhdl->set_body ("-- Output : always at '1'");23 // for (uint32_t i=0; i<_param._nb_branch_complete; i++)24 // vhdl->set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");25 // for (uint32_t i=0; i<_param._nb_prediction ; i++)26 // vhdl->set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';");27 // vhdl->set_body ("");28 29 list<string> list_port_map;30 31 for (uint32_t i=0; i<_param._nb_branch_complete; i++)32 {33 vhdl->set_body_component_port_map (list_port_map," in_SHIFTER_"+toString(i)+"_DATA "," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" );34 vhdl->set_body_component_port_map (list_port_map," in_SHIFTER_"+toString(i)+"_CARRY_IN "," in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION");35 vhdl->set_body_component_port_map (list_port_map,"out_SHIFTER_"+toString(i)+"_DATA ","signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" );36 }37 38 vhdl->set_body_component ("component_Shifter",_name+"_Shifter",list_port_map);39 40 list_port_map.clear();41 vhdl->set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK");42 vhdl->set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET");43 44 for (uint32_t i=0; i<_param._nb_prediction; i++)45 {46 vhdl->set_body_component_port_map (list_port_map," in_READ_"+toString(i)+"_VAL "," In_PREDICT_"+toString(i)+"_VAL");47 vhdl->set_body_component_port_map (list_port_map,"out_READ_"+toString(i)+"_ACK ","out_PREDICT_"+toString(i)+"_ACK");48 vhdl->set_body_component_port_map (list_port_map," in_READ_"+toString(i)+"_ADDRESS "," in_PREDICT_"+toString(i)+"_ADDRESS");49 vhdl->set_body_component_port_map (list_port_map,"out_READ_"+toString(i)+"_DATA ","out_PREDICT_"+toString(i)+"_HISTORY");50 }51 52 for (uint32_t i=0; i<_param._nb_branch_complete; i++)53 {54 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_VAL "," in_BRANCH_COMPLETE_"+toString(i)+"_VAL");55 vhdl->set_body_component_port_map (list_port_map,"out_WRITE_"+toString(i)+"_ACK "," out_BRANCH_COMPLETE_"+toString(i)+"_ACK");56 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_ADDRESS"," in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS");57 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_DATA ","signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY");58 }59 vhdl->set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map);60 22 }; 61 23
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