Ignore:
Timestamp:
Jul 17, 2007, 4:47:56 PM (17 years ago)
Author:
rosiere
Message:

Modification des classes d'encapsulation des interfaces.
Stable sur tous les composants actuels

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/src/Meta_Predictor_vhdl_testbench_transition.cpp

    r15 r44  
    2020    log_printf(FUNC,Meta_Predictor,"vhdl_testbench_transition","Begin");
    2121
    22     // Evaluation before read the ouput signal
    23     sc_start(0);
     22//  sc_start(0);
    2423
    25     // In order with file Meta_Predictor_vhdl_testbench_port.cpp
    26     // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
    27     // (because we have no control on the ordonnancer's policy)
    28 
    29     _vhdl_testbench->add_input (PORT_READ( in_NRESET));
    30 
    31     for (uint32_t i=0; i<_param._nb_prediction; i++)
    32       {
    33         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL                          [i]));
    34         _vhdl_testbench->add_output(PORT_READ(out_PREDICT_ACK                          [i]));
    35         _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS                      [i]));
    36         _vhdl_testbench->add_output(PORT_READ(out_PREDICT_HISTORY                      [i]));
    37         _vhdl_testbench->add_output(PORT_READ(out_PREDICT_DIRECTION                    [i]));
    38       }
    39 
    40     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    41       {
    42         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL                  [i]));
    43         _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_ACK                  [i]));
    44         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS              [i]));
    45         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY              [i]));
    46         _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION            [i]));
    47       }
    48    
    49     // add_test :
    50     //  - True  : the cycle must be compare with the output of systemC
    51     //  - False : no test
    52     _vhdl_testbench->add_test(true);
    53 
    54     _vhdl_testbench->new_cycle (); // always at the end
     24    _interfaces->testbench();
    5525
    5626    log_printf(FUNC,Meta_Predictor,"vhdl_testbench_transition","End");
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