Changeset 62 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core
- Timestamp:
- Dec 4, 2007, 2:31:54 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop
- Files:
-
- 1 deleted
- 10 edited
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Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp (modified) (18 diffs)
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Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h (modified) (5 diffs)
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Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h (modified) (2 diffs)
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Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h (modified) (4 diffs)
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Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp (modified) (2 diffs)
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Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp (modified) (2 diffs)
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Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (modified) (5 diffs)
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Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (modified) (3 diffs)
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Multi_Register_unit (deleted)
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Register_unit/SelfTest/src/test.cpp (modified) (1 diff)
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Register_unit/src/Register_unit_allocation.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp
r59 r62 10 10 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h" 11 11 #include "Common/include/Test.h" 12 #include "Common/include/BitManipulation.h" 12 13 13 14 #define NB_ITERATION 1 … … 43 44 44 45 46 //========================================================={MemoryRequest_t} 45 47 class MemoryRequest_t 46 48 { … … 146 148 return os << "<" << toString(x._cycle) << "> : " 147 149 << "{" << toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl 148 << "\t * " << toString(static_cast<uint32_t>(x._context_id)) << endl149 << "\t * " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl150 << "\t * " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl151 << "\t * " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl152 << "\t * " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;150 << "\t * context_id : " << toString(static_cast<uint32_t>(x._context_id)) << endl 151 << "\t * operation / type / write_spec_ko : " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl 152 << "\t * ptr_write store/load : " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl 153 << "\t * immediat / data_ra / data_rb : " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl 154 << "\t * write_rd / num_reg_rd : " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl; 153 155 } 154 156 157 //================================================================{Memory_t} 158 class Memory_t 159 { 160 private : const uint32_t _nb_context; 161 private : const uint32_t _nb_word ; 162 private : const uint32_t _size_data ; 163 private : const Tdcache_address_t _mask_addr ; 164 private : Tdcache_data_t ** _data; 165 166 public : Memory_t (uint32_t nb_context, 167 uint32_t nb_word, 168 uint32_t size_data): 169 _nb_context (nb_context), 170 _nb_word (nb_word ), 171 _size_data (size_data ), 172 _mask_addr (gen_mask<Tdcache_address_t>(static_cast<uint32_t>(log2(ceil(static_cast<double>(size_data)))))) 173 { 174 _data = new Tdcache_data_t * [nb_context]; 175 176 for (uint32_t i=0; i<nb_context; i++) 177 { 178 _data [i] = new Tdcache_data_t [nb_word]; 179 180 for (uint32_t j=0; j<nb_word; j++) 181 _data [i][j] = rand()%(size_data); 182 } 183 } 184 185 public : ~Memory_t (void) 186 { 187 delete [] _data; 188 } 189 190 public : Tdcache_data_t access (uint32_t context, 191 Tdcache_address_t address, 192 Tdcache_type_t type, 193 Tdcache_data_t data) 194 { 195 return 0; 196 } 197 198 public : Tdcache_data_t read (uint32_t context, 199 Tdcache_address_t address, 200 Tdcache_type_t type) 201 { 202 // Address's Read must be aligned 203 204 if ((address & _mask_addr) != 0) 205 TEST_KO("<Memory_t::read> Address is not aligned"); 206 207 if (context>_nb_context) 208 TEST_KO("<Memory_t::read> nb context is too high"); 209 210 if (address>_nb_word) 211 TEST_KO("<Memory_t::read> address is too high"); 212 213 return _data [context][address]; 214 } 215 216 public : void write (uint32_t context, 217 Tdcache_address_t address, 218 Tdcache_type_t type, 219 Tdcache_data_t data) 220 { 221 if (context>_nb_context) 222 TEST_KO("<Memory_t::read> nb context is too high"); 223 224 if (address>_nb_word) 225 TEST_KO("<Memory_t::read> address is too high"); 226 227 Tdcache_address_t LSB = address & _mask; 228 Tdcache_address_t MSB = address & ~_mask; 229 230 Tdcache_data_t write_data = data; 231 Tdcache_data_t read_data = _data [context][MSB]; 232 233 // exemple to size_data = 32b 234 // LSB index_min 235 // 0 0 236 // 1 8 237 // 2 16 238 // 3 24 239 uint32_t index_min = LSB<<3; 240 uint32_t index_max = index_min; 241 // index max, dependant of access's size 242 243 switch (type) 244 { 245 246 247 } 248 } 249 }; 250 251 //===================================================================={test} 155 252 void test (string name, 156 253 morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param) … … 252 349 (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(*( in_MEMORY_IN_PACKET_ID )); 253 350 (*(_Load_store_unit-> in_MEMORY_IN_OPERATION ))(*( in_MEMORY_IN_OPERATION )); 254 (*(_Load_store_unit-> in_MEMORY_IN_TYPE ))(*( in_MEMORY_IN_TYPE ));255 351 (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE)); 256 352 (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE )); … … 269 365 (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID )); 270 366 (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID )); 271 (*(_Load_store_unit->out_MEMORY_OUT_OPERATION ))(*(out_MEMORY_OUT_OPERATION ));272 (*(_Load_store_unit->out_MEMORY_OUT_TYPE ))(*(out_MEMORY_OUT_TYPE ));273 367 (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))(*(out_MEMORY_OUT_WRITE_RD )); 274 368 (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD )); … … 322 416 const uint32_t nb_word = nb_request; 323 417 324 const uint32_t cst_max_cycle = 2; 325 326 const int32_t percent_transaction_memory_in = 100; 418 //const int32_t percent_transaction_memory_in = 100; 327 419 const int32_t percent_transaction_memory_out = 100; 328 420 const int32_t percent_transaction_dcache = 100; … … 331 423 const int32_t percent_type_load = 0; 332 424 const int32_t percent_type_store = 100; 333 const int32_t percent_miss_spec = 100;425 const int32_t percent_miss_spec = 0; 334 426 335 427 if ((percent_type_load + … … 337 429 TEST_KO("sum of percent_type > 100"); 338 430 339 const int32_t seuil_type_load = seuil_type_load;340 const int32_t seuil_type_store = seuil_type_store+percent_type_load;431 const int32_t seuil_type_load = percent_type_load; 432 const int32_t seuil_type_store = percent_type_store+percent_type_load; 341 433 342 434 uint32_t nb_request_memory_in ; … … 347 439 priority_queue<MemoryRequest_t> fifo_request; 348 440 441 // emulation of cache 349 442 Tdcache_data_t cache_data [_param->_nb_context][nb_word]; 350 443 … … 371 464 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 372 465 { 466 LABEL("Iteration "+toString(iteration)); 467 468 LABEL("Structure's initialisation"); 469 373 470 nb_request_memory_in = 0; 374 471 nb_request_memory_out = 0; 375 472 nb_request_dcache = 0; 376 473 377 LABEL("Iteration "+toString(iteration));378 379 474 // Fill the request_queue 380 475 … … 390 485 load_queue_use [i] = false; 391 486 392 double store_queue_cycle [_param->_size_store_queue];393 double load_queue_cycle [_param->_size_load_queue ];394 487 double current_cycle = sc_simulation_time(); 395 396 for (uint32_t i=0; i<_param->_size_store_queue; i++) 397 store_queue_cycle [i] = current_cycle; 398 for (uint32_t i=0; i<_param->_size_load_queue ; i++) 399 load_queue_cycle [i] = current_cycle; 400 488 double cycle_min = current_cycle; 489 490 LABEL("Fifo request initialisation"); 401 491 // Init fifo_request 402 492 for (uint32_t i=0; i<nb_request; i++) 403 493 { 404 double cycle = current_cycle+(rand()%(cst_max_cycle*nb_request));494 double cycle; 405 495 Tcontext_t context_id = rand () % _param->_nb_context; 406 496 Tpacket_t packet_id = i; … … 411 501 int32_t percent = rand()%100; 412 502 413 if (percent < seuil_type_load) 503 uint32_t size_queue; 504 505 if (percent <= seuil_type_load) 414 506 { 415 operation = OPERATION_MEMORY_LOAD_16_S; 416 load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue); 417 } 418 else 419 if (percent < seuil_type_store) 420 { 421 operation = OPERATION_MEMORY_STORE_16; 422 store_queue_ptr_write = (store_queue_ptr_write+1) % (_param->_size_store_queue); 423 } 424 else 425 { 426 operation = OPERATION_MEMORY_PREFETCH; 427 load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue); 428 } 429 430 // Valid nb cycle ? 431 if (is_operation_memory_store(operation)) 432 { 433 if (cycle <= store_queue_cycle[packet_id]) 434 cycle = store_queue_cycle[packet_id]+1; 507 // LABEL(" * LOAD"); 508 operation = OPERATION_MEMORY_LOAD_16_S; 509 size_queue = _param->_size_load_queue; 510 load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue); 435 511 } 436 512 else 437 513 { 438 if (cycle <= load_queue_cycle[packet_id]) 439 cycle = load_queue_cycle[packet_id]+1; 514 if (percent <= seuil_type_store) 515 { 516 // LABEL(" * STORE"); 517 operation = OPERATION_MEMORY_STORE_16; 518 size_queue = _param->_size_store_queue; 519 store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue); 520 } 521 else 522 { 523 // LABEL(" * OTHERS"); 524 operation = OPERATION_MEMORY_PREFETCH; 525 size_queue = _param->_size_load_queue; 526 load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue); 527 } 440 528 } 441 529 530 cycle = cycle_min; 531 cycle_min ++; 532 442 533 Ttype_t type = TYPE_MEMORY; 443 444 Tgeneral_data_t address = rand()%(1<<_param->_size_general_data); 445 Tgeneral_data_t offset = rand()%(1<<_param->_size_general_data); 534 Tgeneral_data_t address = rand()%(nb_word); 535 Tgeneral_data_t offset = rand()%(nb_word); 446 536 447 537 percent = rand()%100; … … 474 564 ); 475 565 566 cout << tab_request [i] << endl; 567 476 568 fifo_request.push(tab_request [i]); 477 569 570 double cycle_head = 0; 571 478 572 if (is_operation_memory_store(operation)) 479 573 { 480 cycle = cycle+((rand()%(10))-4); 481 482 if (cycle <= store_queue_cycle[packet_id]) 483 cycle = store_queue_cycle[packet_id]+1; 484 485 fifo_request.push(MemoryRequest_t(cycle, 574 cycle_head = cycle_min; 575 cycle_min ++; 576 577 cout << " * Write head : " << toString(cycle_head) 578 << endl 579 << endl; 580 581 fifo_request.push(MemoryRequest_t(cycle_head, 486 582 context_id, 487 583 packet_id, … … 497 593 write_spec_ko)); 498 594 } 499 500 // update nb cycle ? 501 if (is_operation_memory_store(operation)) 502 { 503 store_queue_cycle[packet_id] = cycle; 504 } 505 else 506 { 507 load_queue_cycle [packet_id] = cycle; 508 } 509 } 510 595 } 596 597 LABEL("Simulation of this iteration ..."); 598 511 599 while (nb_request_memory_out < nb_request) 512 600 { 601 // ***** MEMORY_IN ***** 602 603 // memory_in_val depends of three factors : 604 // 1) request's fifo is not empty ? 605 // 2) the slot destination is free ? 606 // 3) The head of request's fifo can be issue : the number of cycle is more than current cycle 607 513 608 bool can_execute = false; 514 609 … … 535 630 536 631 in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out); 537 632 633 // ***** DCACHE_REQ ***** 634 in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache); 635 538 636 SC_START(0); 539 637 … … 541 639 542 640 LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read())); 641 LABEL(" * fifo_request.empty : "+toString(fifo_request.empty())); 642 LABEL(" * fifo_request.top.cycle : "+toString(fifo_request.top()._cycle)); 643 LABEL(" * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write))); 644 LABEL(" * fifo_request.top.load_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write))); 645 LABEL(" * fifo_request.top.operation : "+toString(static_cast<uint32_t>(fifo_request.top()._operation ))); 646 LABEL(" * can_execute : "+toString(can_execute)); 647 543 648 if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read()) 544 649 { … … 562 667 if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read()) 563 668 { 564 LABEL(" * Accepted MEMORY_OUT : " + toString( out_MEMORY_OUT_PACKET_ID->read()));669 LABEL(" * Accepted MEMORY_OUT : " + toString(static_cast<uint32_t>(out_MEMORY_OUT_PACKET_ID->read()))); 565 670 566 671 if (is_operation_memory_store(tab_request[out_MEMORY_OUT_PACKET_ID->read()]._operation)) … … 571 676 nb_request_memory_out ++; 572 677 } 678 679 LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read())); 680 if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read()) 681 { 682 LABEL(" * Accepted DCACHE_REQ : " + toString(static_cast<uint32_t>(out_DCACHE_REQ_PACKET_ID->read()))); 683 684 // test type : send or not a respons ! 685 } 686 573 687 } 574 688 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r59 r62 7 7 * [ Description ] 8 8 * 9 * Ce composant peut être amélioré en placant deux ptr de lecture au lieu d'un : un pour l'accès au cache et un pour le commit 9 10 */ 10 11 … … 12 13 #include "systemc.h" 13 14 #endif 14 15 #define HAVE_MEMORY_OUT_OPERATION16 #define HAVE_MEMORY_OUT_TYPE17 15 18 16 #include <iostream> … … 79 77 public : SC_IN (Tpacket_t ) * in_MEMORY_IN_PACKET_ID ; 80 78 public : SC_IN (Toperation_t ) * in_MEMORY_IN_OPERATION ; 81 #ifdef HAVE_MEMORY_OUT_TYPE82 public : SC_IN (Ttype_t ) * in_MEMORY_IN_TYPE ;83 #endif84 79 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 85 80 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE; … … 99 94 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_CONTEXT_ID; 100 95 public : SC_OUT(Tpacket_t ) * out_MEMORY_OUT_PACKET_ID ; 101 #ifdef HAVE_MEMORY_OUT_OPERATION102 public : SC_OUT(Toperation_t ) * out_MEMORY_OUT_OPERATION ;103 #endif104 #ifdef HAVE_MEMORY_OUT_TYPE105 public : SC_OUT(Ttype_t ) * out_MEMORY_OUT_TYPE ;106 #endif107 96 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RD ; // = (operation==load) 108 97 public : SC_OUT(Tgeneral_address_t) * out_MEMORY_OUT_NUM_REG_RD; // destination (load) … … 154 143 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 155 144 145 // Registers 156 146 public : Tlsq_ptr_t internal_MEMORY_STORE_QUEUE_PTR_READ; 157 public : Tlsq_ptr_t internal_MEMORY_LOAD_QUEUE_PTR_READ; 158 147 public : Tlsq_ptr_t internal_MEMORY_LOAD_QUEUE_PTR_READ ; 148 149 // signal 159 150 private : Tcontrol_t internal_MEMORY_IN_ACK; 160 151 private : Tcontrol_t internal_MEMORY_OUT_VAL; 161 152 private : Tselect_queue_t internal_MEMORY_OUT_SELECT_QUEUE; 153 154 private : Tcontrol_t internal_DCACHE_REQ_VAL; 155 private : Tselect_queue_t internal_DCACHE_REQ_SELECT_QUEUE; 162 156 #endif 163 157 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h
r59 r62 26 26 { 27 27 //-----[ fields ]------------------------------------------------------------ 28 public : const uint32_t _size_store_queue ;29 public : const uint32_t _size_load_queue ;28 public : const uint32_t _size_store_queue ; 29 public : const uint32_t _size_load_queue ; 30 30 public : const uint32_t _size_speculative_access_queue; 31 public : const uint32_t _nb_port_check ; 32 public : const Tspeculative_load_t _speculative_load ; 33 public : const uint32_t _nb_context ; 34 public : const uint32_t _nb_packet ; 35 public : const uint32_t _size_general_data ; 36 public : const uint32_t _nb_general_register ; 37 public : const uint32_t _nb_operation ; 38 public : const uint32_t _nb_type ; 31 public : const uint32_t _nb_port_check ; 32 public : const Tspeculative_load_t _speculative_load ; 33 //public : const uint32_t _nb_cache_port ; 34 public : const uint32_t _nb_context ; 35 public : const uint32_t _nb_packet ; 36 public : const uint32_t _size_general_data ; 37 public : const uint32_t _nb_general_register ; 38 public : const uint32_t _nb_operation ; 39 public : const uint32_t _nb_type ; 39 40 40 41 public : const uint32_t _size_address_store_queue ; 41 42 public : const uint32_t _size_address_load_queue ; 42 43 public : const uint32_t _size_address_speculative_access_queue; 43 public : const uint32_t _size_context_id ;44 public : const uint32_t _size_packet_id ;45 public : const uint32_t _size_general_register ;46 public : const uint32_t _size_operation ;47 public : const uint32_t _size_type ;44 public : const uint32_t _size_context_id ; 45 public : const uint32_t _size_packet_id ; 46 public : const uint32_t _size_general_register ; 47 public : const uint32_t _size_operation ; 48 public : const uint32_t _size_type ; 48 49 49 50 //-----[ methods ]----------------------------------------------------------- … … 60 61 uint32_t nb_type 61 62 ); 63 62 64 public : Parameters (Parameters & param) ; 63 65 public : ~Parameters () ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
r59 r62 56 56 public : Tcontext_t _context_id ; 57 57 public : Tpacket_t _packet_id ; 58 public : T access_t _access;58 public : Tdcache_type_t _dcache_type ; 59 59 public : Tcontrol_t _uncached ; 60 #ifdef HAVE_MEMORY_OUT_OPERATION61 public : Toperation_t _operation ;62 #endif63 #ifdef HAVE_MEMORY_OUT_TYPE64 public : Ttype_t _type ;65 #endif66 60 public : Tlsq_ptr_t _load_queue_ptr_write; 67 61 public : Tdcache_data_t _address ; … … 70 64 //public : Tgeneral_address_t _num_reg_rd ; 71 65 public : Texception_t _exception ; 66 67 friend ostream & operator << (ostream& os, const Tstore_queue_entry_t & x) 68 { 69 return os << " * state : " << x._state << endl 70 << " * packet - context_id : " << toString(static_cast<uint32_t>(x._packet_id )) << " - " << toString(static_cast<uint32_t>(x._context_id)) << endl 71 << " * type - uncached : " << toString(static_cast<uint32_t>(x._dcache_type )) << " - " << toString(static_cast<uint32_t>(x._uncached )) << endl 72 << " * load_ptr - execption : " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << " - " << toString(static_cast<uint32_t>(x._exception )) << endl 73 << " * address - wdata : " << toString(static_cast<uint32_t>(x._address )) << " - " << toString(static_cast<uint32_t>(x._wdata )) << endl; 74 } 72 75 }; 76 77 73 78 74 79 // ---------------------------------------------------------- … … 91 96 public : Tcontrol_t _uncached ; 92 97 public : Tcontrol_t _sign_extension ; 93 #ifdef HAVE_MEMORY_OUT_OPERATION94 public : Toperation_t _operation ;95 #endif96 #ifdef HAVE_MEMORY_OUT_TYPE97 public : Ttype_t _type ;98 #endif99 98 public : Tlsq_ptr_t _load_queue_ptr_write ; 100 99 public : Tlsq_ptr_t _store_queue_ptr_write; … … 128 127 public : Tcontrol_t _uncached ; 129 128 public : Tcontrol_t _sign_extension ; 130 #ifdef HAVE_MEMORY_OUT_OPERATION131 public : Toperation_t _operation ;132 #endif133 #ifdef HAVE_MEMORY_OUT_TYPE134 public : Ttype_t _type ;135 #endif136 129 public : Tlsq_ptr_t _store_queue_ptr_write; 137 130 public : Tdcache_address_t _address ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r59 r62 67 67 in_MEMORY_IN_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 68 68 in_MEMORY_IN_OPERATION = interface->set_signal_in <Toperation_t > ("operation" ,_param->_size_operation ); 69 #ifdef HAVE_MEMORY_OUT_TYPE70 in_MEMORY_IN_TYPE = interface->set_signal_in <Ttype_t > ("type" ,_param->_size_type );71 #endif72 69 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("store_queue_ptr_write" ,_param->_size_address_store_queue); 73 70 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("load_queue_ptr_write" ,_param->_size_address_load_queue ); … … 97 94 out_MEMORY_OUT_CONTEXT_ID = interface->set_signal_out <Tcontext_t > ("context_id" ,_param->_size_context_id ); 98 95 out_MEMORY_OUT_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 99 #ifdef HAVE_MEMORY_OUT_OPERATION100 out_MEMORY_OUT_OPERATION = interface->set_signal_out <Toperation_t > ("operation" ,_param->_size_operation );101 #endif102 #ifdef HAVE_MEMORY_OUT_TYPE103 out_MEMORY_OUT_TYPE = interface->set_signal_out <Ttype_t > ("type" ,_param->_size_type );104 #endif105 96 out_MEMORY_OUT_WRITE_RD = interface->set_signal_out <Tcontrol_t > ("write_rd" ,1 ); 106 97 out_MEMORY_OUT_NUM_REG_RD = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r59 r62 38 38 delete in_MEMORY_IN_PACKET_ID ; 39 39 delete in_MEMORY_IN_OPERATION ; 40 #ifdef HAVE_MEMORY_OUT_TYPE41 delete in_MEMORY_IN_TYPE ;42 #endif43 40 delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 44 41 delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; … … 57 54 delete out_MEMORY_OUT_CONTEXT_ID; 58 55 delete out_MEMORY_OUT_PACKET_ID ; 59 #ifdef HAVE_MEMORY_OUT_OPERATION60 delete out_MEMORY_OUT_OPERATION ;61 #endif62 #ifdef HAVE_MEMORY_OUT_TYPE63 delete out_MEMORY_OUT_TYPE ;64 #endif65 56 delete out_MEMORY_OUT_WRITE_RD ; 66 57 delete out_MEMORY_OUT_NUM_REG_RD; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r59 r62 28 28 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 29 30 // Test store and load queue31 30 Tcontext_t memory_out_context_id = 0; 32 31 Tpacket_t memory_out_packet_id = 0; 33 #ifdef HAVE_MEMORY_OUT_OPERATION34 Toperation_t memory_out_operation = 0;35 #endif36 #ifdef HAVE_MEMORY_OUT_TYPE37 Ttype_t memory_out_type = 0;38 #endif39 32 Tcontrol_t memory_out_write_rd = 0; 40 33 Tgeneral_address_t memory_out_num_reg_rd = 0; … … 47 40 internal_MEMORY_OUT_VAL = 0; 48 41 49 // TODO : now only store queue 42 // Test store and load queue 43 // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!! 50 44 51 45 // Test an store must be commited. 52 53 54 46 if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) 55 47 { … … 59 51 memory_out_context_id= _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id; 60 52 memory_out_packet_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ; 61 #ifdef HAVE_MEMORY_OUT_OPERATION62 memory_out_operation = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._operation;63 #endif64 #ifdef HAVE_MEMORY_OUT_TYPE65 memory_out_type = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._type;66 #endif67 53 // memory_out_write_rd 68 54 // memory_out_num_reg_rd … … 71 57 } 72 58 59 // write output 73 60 PORT_WRITE(out_MEMORY_OUT_VAL , internal_MEMORY_OUT_VAL); 74 61 75 62 PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID, memory_out_context_id); 76 63 PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id ); 77 #ifdef HAVE_MEMORY_OUT_OPERATION78 PORT_WRITE(out_MEMORY_OUT_OPERATION , memory_out_operation );79 #endif80 #ifdef HAVE_MEMORY_OUT_TYPE81 PORT_WRITE(out_MEMORY_OUT_TYPE , memory_out_type );82 #endif83 64 PORT_WRITE(out_MEMORY_OUT_WRITE_RD , memory_out_write_rd ); 84 65 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD, memory_out_num_reg_rd); … … 89 70 PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception ); 90 71 72 // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 91 73 74 Tcontext_t dcache_req_context_id; 75 Tpacket_t dcache_req_packet_id ; 76 Tdcache_address_t dcache_req_address ; 77 Tdcache_type_t dcache_req_type ; 78 Tcontrol_t dcache_req_uncached ; 79 Tdcache_data_t dcache_req_wdata ; 80 81 internal_DCACHE_REQ_VAL = 0; 82 83 // Test store and load queue 84 85 // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!! 86 87 // Test an store must be commited. 88 if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE) 89 { 90 internal_DCACHE_REQ_VAL = 1; 91 internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE; 92 93 dcache_req_context_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id; 94 dcache_req_packet_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ; 95 dcache_req_address = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._address ; 96 dcache_req_type = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._dcache_type; 97 dcache_req_uncached = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._uncached ; 98 dcache_req_wdata = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._wdata ; 99 } 100 101 PORT_WRITE(out_DCACHE_REQ_VAL , internal_DCACHE_REQ_VAL); 102 PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID, dcache_req_context_id); 103 PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id ); 104 PORT_WRITE(out_DCACHE_REQ_ADDRESS , dcache_req_address ); 105 PORT_WRITE(out_DCACHE_REQ_TYPE , dcache_req_type ); 106 PORT_WRITE(out_DCACHE_REQ_UNCACHED , dcache_req_uncached ); 107 PORT_WRITE(out_DCACHE_REQ_WDATA , dcache_req_wdata ); 108 92 109 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 93 110 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r59 r62 57 57 // others in speculation_access_queue 58 58 59 Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION); 60 Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT) + 61 PORT_READ(in_MEMORY_IN_DATA_RA )); 62 63 bool exception_alignement= (mask_memory_access(operation) & address) != 0; 59 Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION); 60 Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT) + 61 PORT_READ(in_MEMORY_IN_DATA_RA )); 62 bool exception_alignement = (mask_memory_access(operation) & address) != 0; 64 63 65 64 if (is_operation_memory_store(operation) == true) … … 159 158 _store_queue [index]._context_id = PORT_READ(in_MEMORY_IN_CONTEXT_ID ); 160 159 _store_queue [index]._packet_id = PORT_READ(in_MEMORY_IN_PACKET_ID ); 161 #ifdef HAVE_MEMORY_OUT_OPERATION 162 _store_queue [index]._operation = operation; 163 #endif 164 #ifdef HAVE_MEMORY_OUT_TYPE 165 _store_queue [index]._type = PORT_READ(in_MEMORY_IN_TYPE ); 166 #endif 160 _store_queue [index]._dcache_type = operation_to_dcache_type(operation); 161 _store_queue [index]._uncached = 0; // is the MMU that have this info 167 162 _store_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE); 168 163 _store_queue [index]._address = address; … … 217 212 } 218 213 } 214 215 //================================================================ 216 // Interface "DCACHE_REQ" 217 //================================================================ 218 if (( internal_DCACHE_REQ_VAL == 1) and 219 (PORT_READ(in_DCACHE_REQ_ACK) == 1)) 220 { 221 switch (internal_DCACHE_REQ_SELECT_QUEUE) 222 { 223 case SELECT_STORE_QUEUE : 224 { 225 // ======================= 226 // ===== STORE_QUEUE ===== 227 // ======================= 228 229 // Entry flush and increase the read pointer 230 231 _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT; 232 233 break; 234 } 235 case SELECT_LOAD_QUEUE : 236 case SELECT_LOAD_QUEUE_SPECULATIVE : 237 break; 238 } 239 } 240 241 #if DEBUG>=DEBUG_TRACE 242 // ***** dump store queue 243 cout << "Dump store queue" << endl 244 << "ptr_read : " << toString(static_cast<uint32_t>(internal_MEMORY_STORE_QUEUE_PTR_READ)) << endl; 245 246 for (uint32_t i=0; i<_param->_size_store_queue; i++) 247 { 248 uint32_t j = (internal_MEMORY_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; 249 cout << "{" << j << "}" << endl 250 << _store_queue[j] << endl; 251 } 252 #endif 219 253 } 220 254 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp
r60 r62 112 112 sc_signal<Tspecial_address_t> *** in_RETIRE_ROB_RE_NEW_NUM_REG ; 113 113 114 string rename ;114 string rename = "signal"; 115 115 116 116 in_CLOCK = new sc_clock ("clock", 1.0, 0.5); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp
r60 r62 370 370 #endif 371 371 372 _component->port_map(name_component,"in_CLOCK" , _name, "in_CLOCK");373 _component->port_map(name_component,"in_NRESET" , _name, "in_NRESET");372 _component->port_map(name_component,"in_CLOCK" , _name, "in_CLOCK"); 373 _component->port_map(name_component,"in_NRESET" , _name, "in_NRESET"); 374 374 375 375 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) … … 733 733 _component->port_map(name_component,"in_CLOCK" , _name, "in_CLOCK" ); 734 734 _component->port_map(name_component,"in_NRESET", _name, "in_NRESET"); 735 735 _component->port_map(name_component,"out_CONST_0"); 736 _component->port_map(name_component,"out_CONST_1"); 737 736 738 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 737 739 {
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