Changeset 71 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp
- Timestamp:
- Jan 19, 2008, 12:09:01 PM (16 years ago)
- File:
-
- 1 moved
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp) (15 diffs)
Legend:
- Unmodified
- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp
r62 r71 9 9 #include <queue> 10 10 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h" 11 #include "Common/include/Test.h"12 #include "Common/include/BitManipulation.h"13 11 14 12 #define NB_ITERATION 1 15 #define CYCLE_MAX (128*NB_ITERATION) 16 17 #define LABEL(str) \ 18 { \ 19 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \ 20 } while(0) 21 22 static uint32_t cycle = 0; 23 24 #define SC_START(cycle_offset) \ 25 do \ 26 { \ 27 /*cout << "SC_START (begin)" << endl;*/ \ 28 \ 29 uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ 30 if (cycle_current != cycle) \ 31 { \ 32 cycle = cycle_current; \ 33 cout << "##########[ cycle "<< cycle << " ]" << endl; \ 34 } \ 35 \ 36 if (cycle_current > CYCLE_MAX) \ 37 { \ 38 TEST_KO("Maximal cycles Reached"); \ 39 } \ 40 sc_start(cycle_offset); \ 41 /*cout << "SC_START (end )" << endl;*/ \ 42 } while(0) 43 44 45 46 //========================================================={MemoryRequest_t} 47 class MemoryRequest_t 48 { 49 public : double _cycle ; 50 public : Tcontext_t _context_id ; 51 public : Tpacket_t _packet_id ; 52 public : Toperation_t _operation ; 53 public : Ttype_t _type ; 54 public : Tlsq_ptr_t _store_queue_ptr_write; 55 public : Tlsq_ptr_t _load_queue_ptr_write ; 56 public : Tgeneral_data_t _immediat ; 57 public : Tgeneral_data_t _data_ra ; 58 public : Tgeneral_data_t _data_rb ; 59 public : Tcontrol_t _write_rd ; 60 public : Tgeneral_address_t _num_reg_rd ; 61 public : bool _write_spec_ko ; 62 63 MemoryRequest_t (void) 64 { 65 _cycle = 0; 66 _context_id = 0; 67 _packet_id = 0; 68 _operation = 0; 69 _type = 0; 70 _store_queue_ptr_write = 0; 71 _load_queue_ptr_write = 0; 72 _immediat = 0; 73 _data_ra = 0; 74 _data_rb = 0; 75 _write_rd = 0; 76 _num_reg_rd = 0; 77 _write_spec_ko = 0; 78 }; 79 80 MemoryRequest_t (double cycle , 81 Tcontext_t context_id , 82 Tpacket_t packet_id , 83 Toperation_t operation , 84 Ttype_t type , 85 Tlsq_ptr_t store_queue_ptr_write, 86 Tlsq_ptr_t load_queue_ptr_write , 87 Tgeneral_data_t immediat , 88 Tgeneral_data_t data_ra , 89 Tgeneral_data_t data_rb , 90 Tcontrol_t write_rd , 91 Tgeneral_address_t num_reg_rd , 92 bool write_spec_ko ) 93 { 94 _cycle = cycle ; 95 _context_id = context_id ; 96 _packet_id = packet_id ; 97 _operation = operation ; 98 _type = type ; 99 _store_queue_ptr_write = store_queue_ptr_write; 100 _load_queue_ptr_write = load_queue_ptr_write ; 101 _immediat = immediat ; 102 _data_ra = data_ra ; 103 _data_rb = data_rb ; 104 _write_rd = write_rd ; 105 _num_reg_rd = num_reg_rd ; 106 _write_spec_ko = write_spec_ko ; 107 } 108 109 void modif (double cycle , 110 Tcontext_t context_id , 111 Tpacket_t packet_id , 112 Toperation_t operation , 113 Ttype_t type , 114 Tlsq_ptr_t store_queue_ptr_write, 115 Tlsq_ptr_t load_queue_ptr_write , 116 Tgeneral_data_t immediat , 117 Tgeneral_data_t data_ra , 118 Tgeneral_data_t data_rb , 119 Tcontrol_t write_rd , 120 Tgeneral_address_t num_reg_rd , 121 bool write_spec_ko ) 122 { 123 _cycle = cycle ; 124 _context_id = context_id ; 125 _packet_id = packet_id ; 126 _operation = operation ; 127 _type = type ; 128 _store_queue_ptr_write = store_queue_ptr_write; 129 _load_queue_ptr_write = load_queue_ptr_write ; 130 _immediat = immediat ; 131 _data_ra = data_ra ; 132 _data_rb = data_rb ; 133 _write_rd = write_rd ; 134 _num_reg_rd = num_reg_rd ; 135 _write_spec_ko = write_spec_ko ; 136 } 137 138 bool operator< (const MemoryRequest_t & right) const 139 { 140 return _cycle > right._cycle; 141 } 142 143 friend ostream& operator<<(ostream &, const MemoryRequest_t &); 144 }; 145 146 ostream & operator << (ostream& os, const MemoryRequest_t & x) 147 { 148 return os << "<" << toString(x._cycle) << "> : " 149 << "{" << toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl 150 << "\t * context_id : " << toString(static_cast<uint32_t>(x._context_id)) << endl 151 << "\t * operation / type / write_spec_ko : " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl 152 << "\t * ptr_write store/load : " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl 153 << "\t * immediat / data_ra / data_rb : " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl 154 << "\t * write_rd / num_reg_rd : " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl; 155 } 156 157 //================================================================{Memory_t} 158 class Memory_t 159 { 160 private : const uint32_t _nb_context; 161 private : const uint32_t _nb_word ; 162 private : const uint32_t _size_data ; 163 private : const Tdcache_address_t _mask_addr ; 164 private : Tdcache_data_t ** _data; 165 166 public : Memory_t (uint32_t nb_context, 167 uint32_t nb_word, 168 uint32_t size_data): 169 _nb_context (nb_context), 170 _nb_word (nb_word ), 171 _size_data (size_data ), 172 _mask_addr (gen_mask<Tdcache_address_t>(static_cast<uint32_t>(log2(ceil(static_cast<double>(size_data)))))) 173 { 174 _data = new Tdcache_data_t * [nb_context]; 175 176 for (uint32_t i=0; i<nb_context; i++) 177 { 178 _data [i] = new Tdcache_data_t [nb_word]; 179 180 for (uint32_t j=0; j<nb_word; j++) 181 _data [i][j] = rand()%(size_data); 182 } 183 } 184 185 public : ~Memory_t (void) 186 { 187 delete [] _data; 188 } 189 190 public : Tdcache_data_t access (uint32_t context, 191 Tdcache_address_t address, 192 Tdcache_type_t type, 193 Tdcache_data_t data) 194 { 195 return 0; 196 } 197 198 public : Tdcache_data_t read (uint32_t context, 199 Tdcache_address_t address, 200 Tdcache_type_t type) 201 { 202 // Address's Read must be aligned 203 204 if ((address & _mask_addr) != 0) 205 TEST_KO("<Memory_t::read> Address is not aligned"); 206 207 if (context>_nb_context) 208 TEST_KO("<Memory_t::read> nb context is too high"); 209 210 if (address>_nb_word) 211 TEST_KO("<Memory_t::read> address is too high"); 212 213 return _data [context][address]; 214 } 215 216 public : void write (uint32_t context, 217 Tdcache_address_t address, 218 Tdcache_type_t type, 219 Tdcache_data_t data) 220 { 221 if (context>_nb_context) 222 TEST_KO("<Memory_t::read> nb context is too high"); 223 224 if (address>_nb_word) 225 TEST_KO("<Memory_t::read> address is too high"); 226 227 Tdcache_address_t LSB = address & _mask; 228 Tdcache_address_t MSB = address & ~_mask; 229 230 Tdcache_data_t write_data = data; 231 Tdcache_data_t read_data = _data [context][MSB]; 232 233 // exemple to size_data = 32b 234 // LSB index_min 235 // 0 0 236 // 1 8 237 // 2 16 238 // 3 24 239 uint32_t index_min = LSB<<3; 240 uint32_t index_max = index_min; 241 // index max, dependant of access's size 242 243 switch (type) 244 { 245 246 247 } 248 } 249 }; 13 #define CYCLE_MAX (1024*NB_ITERATION) 14 15 #define LABEL(str) \ 16 { \ 17 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \ 18 } while(0) 19 20 #define SC_START(cycle_offset) \ 21 do \ 22 { \ 23 /*cout << "SC_START (begin)" << endl;*/ \ 24 \ 25 uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ 26 if (cycle_offset != 0) \ 27 { \ 28 cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \ 29 } \ 30 \ 31 if (cycle_current > CYCLE_MAX) \ 32 { \ 33 TEST_KO("Maximal cycles Reached"); \ 34 } \ 35 sc_start(cycle_offset); \ 36 /*cout << "SC_START (end )" << endl;*/ \ 37 } while(0) 38 250 39 251 40 //===================================================================={test} 252 void test (string name,41 void test1 (string name, 253 42 morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param) 254 43 { … … 256 45 257 46 #ifdef STATISTICS 258 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5, 50);47 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); 259 48 #endif 260 49 261 50 Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(), 262 51 #ifdef STATISTICS 263 52 _parameters_statistics, 264 53 #endif 265 54 _param); 266 55 267 56 #ifdef SYSTEMC … … 277 66 sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str()); 278 67 sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str()); 68 sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str()); 69 sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str()); 279 70 sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str()); 280 71 sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str()); … … 282 73 sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); 283 74 sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); 284 //sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());75 //sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str()); 285 76 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str()); 286 77 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str()); 287 78 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str()); 288 //sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());289 sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());79 //sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str()); 80 // sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str()); 290 81 sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str()); 291 //sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());292 //sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());293 294 sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t>(rename.c_str());295 sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t>(rename.c_str());296 sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());297 sc_signal<T packet_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t>(rename.c_str());298 sc_signal<T operation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t>(rename.c_str());299 sc_signal<T type_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t>(rename.c_str());300 sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());301 sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());302 sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());303 //sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE= new sc_signal<Tcontrol_t >(rename.c_str());304 //sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE= new sc_signal<Tspecial_address_t>(rename.c_str());305 //sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE= new sc_signal<Tspecial_data_t >(rename.c_str());306 sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());82 //sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str()); 83 //sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str()); 84 85 sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); 86 sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); 87 sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); 88 sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str()); 89 sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str()); 90 sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); 91 sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str()); 92 sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str()); 93 sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str()); 94 //sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str()); 95 //sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str()); 96 //sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str()); 97 sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str()); 307 98 308 99 sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); … … 312 103 sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str()); 313 104 sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str()); 314 sc_signal<Tcontrol_t > * out_DCACHE_REQ_UNCACHED = new sc_signal<Tcontrol_t >(rename.c_str());315 105 sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str()); 316 106 … … 322 112 sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str()); 323 113 324 sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_size_load_queue];325 sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_ CONTEXT_ID = new sc_signal<Tcontext_t > * [_param->_size_load_queue];326 sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];327 sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_size_load_queue];114 sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_size_load_queue]; 115 sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_size_load_queue]; 116 sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue]; 117 sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_size_load_queue]; 328 118 329 330 331 out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >;332 out_BYPASS_MEMORY_CONTEXT_ID [i] = new sc_signal<Tcontext_t >;333 out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>;334 out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >;335 119 for (uint32_t i=0; i<_param->_size_load_queue; i++) 120 { 121 out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str()); 122 out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str()); 123 out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str()); 124 out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str()); 125 } 336 126 337 127 /******************************************************** … … 346 136 (*(_Load_store_unit-> in_MEMORY_IN_VAL ))(*( in_MEMORY_IN_VAL )); 347 137 (*(_Load_store_unit->out_MEMORY_IN_ACK ))(*(out_MEMORY_IN_ACK )); 348 (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(*( in_MEMORY_IN_CONTEXT_ID )); 349 (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(*( in_MEMORY_IN_PACKET_ID )); 138 if (_param->_have_port_context_id) 139 (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(*( in_MEMORY_IN_CONTEXT_ID )); 140 if (_param->_have_port_front_end_id) 141 (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(*( in_MEMORY_IN_FRONT_END_ID )); 142 if (_param->_have_port_ooo_engine_id) 143 (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(*( in_MEMORY_IN_OOO_ENGINE_ID )); 144 if (_param->_have_port_packet_id) 145 (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(*( in_MEMORY_IN_PACKET_ID )); 350 146 (*(_Load_store_unit-> in_MEMORY_IN_OPERATION ))(*( in_MEMORY_IN_OPERATION )); 351 147 (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE)); 352 148 (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE )); 353 //(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT ));149 //(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT )); 354 150 (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(*( in_MEMORY_IN_IMMEDIAT )); 355 151 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(*( in_MEMORY_IN_DATA_RA )); 356 152 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(*( in_MEMORY_IN_DATA_RB )); 357 //(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC ));358 (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD ));153 //(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC )); 154 // (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD )); 359 155 (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(*( in_MEMORY_IN_NUM_REG_RD )); 360 //(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE )); 361 //(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE )); 362 363 (*(_Load_store_unit->out_MEMORY_OUT_VAL ))(*(out_MEMORY_OUT_VAL )); 364 (*(_Load_store_unit-> in_MEMORY_OUT_ACK ))(*( in_MEMORY_OUT_ACK )); 365 (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID )); 366 (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID )); 367 (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))(*(out_MEMORY_OUT_WRITE_RD )); 368 (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD )); 369 (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD ))(*(out_MEMORY_OUT_DATA_RD )); 370 //(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE )); 371 //(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE )); 372 //(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE )); 373 (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))(*(out_MEMORY_OUT_EXCEPTION )); 156 //(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE )); 157 //(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE )); 158 159 (*(_Load_store_unit->out_MEMORY_OUT_VAL ))(*(out_MEMORY_OUT_VAL )); 160 (*(_Load_store_unit-> in_MEMORY_OUT_ACK ))(*( in_MEMORY_OUT_ACK )); 161 if (_param->_have_port_context_id) 162 (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID )); 163 if (_param->_have_port_front_end_id) 164 (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))(*(out_MEMORY_OUT_FRONT_END_ID )); 165 if (_param->_have_port_ooo_engine_id) 166 (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID )); 167 if (_param->_have_port_packet_id) 168 (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID )); 169 (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))(*(out_MEMORY_OUT_WRITE_RD )); 170 (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD )); 171 (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD ))(*(out_MEMORY_OUT_DATA_RD )); 172 //(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE )); 173 //(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE )); 174 //(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE )); 175 (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))(*(out_MEMORY_OUT_EXCEPTION )); 374 176 375 177 (*(_Load_store_unit->out_DCACHE_REQ_VAL ))(*(out_DCACHE_REQ_VAL )); 376 178 (*(_Load_store_unit-> in_DCACHE_REQ_ACK ))(*( in_DCACHE_REQ_ACK )); 377 (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID)); 179 if (_param->_have_port_dcache_context_id) 180 (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID)); 378 181 (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID )); 379 182 (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS ))(*(out_DCACHE_REQ_ADDRESS )); 380 183 (*(_Load_store_unit->out_DCACHE_REQ_TYPE ))(*(out_DCACHE_REQ_TYPE )); 381 (*(_Load_store_unit->out_DCACHE_REQ_UNCACHED ))(*(out_DCACHE_REQ_UNCACHED ));382 184 (*(_Load_store_unit->out_DCACHE_REQ_WDATA ))(*(out_DCACHE_REQ_WDATA )); 383 185 384 186 (*(_Load_store_unit-> in_DCACHE_RSP_VAL ))(*( in_DCACHE_RSP_VAL )); 385 187 (*(_Load_store_unit->out_DCACHE_RSP_ACK ))(*(out_DCACHE_RSP_ACK )); 386 (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID)); 188 if (_param->_have_port_dcache_context_id) 189 (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID)); 387 190 (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID )); 388 191 (*(_Load_store_unit-> in_DCACHE_RSP_RDATA ))(*( in_DCACHE_RSP_RDATA )); … … 393 196 for (uint32_t i=0; i<_param->_size_load_queue; i++) 394 197 { 395 (*(_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))(*(out_BYPASS_MEMORY_VAL [i])); 396 (*(_Load_store_unit->out_BYPASS_MEMORY_CONTEXT_ID [i]))(*(out_BYPASS_MEMORY_CONTEXT_ID [i])); 397 (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))(*(out_BYPASS_MEMORY_NUM_REG [i])); 398 (*(_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))(*(out_BYPASS_MEMORY_DATA [i])); 198 (*(_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))(*(out_BYPASS_MEMORY_VAL [i])); 199 if (_param->_have_port_ooo_engine_id) 200 (*(_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))(*(out_BYPASS_MEMORY_OOO_ENGINE_ID [i])); 201 (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))(*(out_BYPASS_MEMORY_NUM_REG [i])); 202 (*(_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))(*(out_BYPASS_MEMORY_DATA [i])); 399 203 } 400 204 } … … 409 213 410 214 const uint32_t seed = 0; 411 //const uint32_t seed = static_cast<uint32_t>(time(NULL));215 //const uint32_t seed = static_cast<uint32_t>(time(NULL)); 412 216 413 217 srand(seed); … … 416 220 const uint32_t nb_word = nb_request; 417 221 418 //const int32_t percent_transaction_memory_in = 100;419 const int32_t percent_transaction_memory_out = 100;420 const int32_t percent_transaction_dcache = 100;421 422 const int32_t percent_exception = 5;222 //const int32_t percent_transaction_memory_in = 100; 223 const int32_t percent_transaction_memory_out = 75; 224 const int32_t percent_transaction_dcache = 75; 225 226 const int32_t percent_exception = 0; 423 227 const int32_t percent_type_load = 0; 424 const int32_t percent_type_store = 100; 425 const int32_t percent_miss_spec = 0; 228 const int32_t percent_type_store = 50; 229 const int32_t percent_miss_spec = 20; 230 231 const uint32_t miss_rate = 10; 232 const uint32_t miss_penality = 5; 426 233 427 234 if ((percent_type_load + … … 439 246 priority_queue<MemoryRequest_t> fifo_request; 440 247 441 // emulation of cache 442 Tdcache_data_t cache_data [_param->_nb_context][nb_word]; 248 // emulation of memory 249 Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, nb_word, _param->_size_general_data); 250 Cache_t * _cache = new Cache_t (miss_rate, miss_penality); 251 443 252 444 253 SC_START(0); 445 254 446 255 LABEL("Initialisation"); 447 448 // emulate a memory449 for (uint32_t i=0; i<_param->_nb_context; i++)450 for (uint32_t j=0; j<nb_word; j++)451 cache_data [i][j] = rand()%(1<<_param->_size_general_data);452 256 453 257 in_MEMORY_IN_VAL ->write(0); … … 462 266 LABEL("Loop of Test"); 463 267 464 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)268 try 465 269 { 466 LABEL("Iteration "+toString(iteration)); 467 468 LABEL("Structure's initialisation"); 469 470 nb_request_memory_in = 0; 471 nb_request_memory_out = 0; 472 nb_request_dcache = 0; 270 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 271 { 272 LABEL("Iteration "+toString(iteration)); 273 274 LABEL("Structure's initialisation"); 275 276 nb_request_memory_in = 0; 277 nb_request_memory_out = 0; 278 nb_request_dcache = 0; 473 279 474 280 // Fill the request_queue 475 281 476 Tlsq_ptr_t store_queue_ptr_write = 0; 477 Tlsq_ptr_t load_queue_ptr_write = 0; 478 479 bool store_queue_use [_param->_size_store_queue]; 480 bool load_queue_use [_param->_size_load_queue ]; 481 482 for (uint32_t i=0; i<_param->_size_store_queue; i++) 483 store_queue_use [i] = false; 484 for (uint32_t i=0; i<_param->_size_load_queue ; i++) 485 load_queue_use [i] = false; 486 487 double current_cycle = sc_simulation_time(); 488 double cycle_min = current_cycle; 489 490 LABEL("Fifo request initialisation"); 491 // Init fifo_request 492 for (uint32_t i=0; i<nb_request; i++) 493 { 494 double cycle; 495 Tcontext_t context_id = rand () % _param->_nb_context; 496 Tpacket_t packet_id = i; 497 Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write; 498 Tlsq_ptr_t load_queue_ptr_write_old = load_queue_ptr_write ; 499 Toperation_t operation; 282 Tlsq_ptr_t store_queue_ptr_write = 0; 283 Tlsq_ptr_t load_queue_ptr_write = 0; 284 285 bool store_queue_use [_param->_size_store_queue]; 286 uint32_t nb_store_slot_use = 0; 287 bool load_queue_use [_param->_size_load_queue ]; 288 289 for (uint32_t i=0; i<_param->_size_store_queue; i++) 290 store_queue_use [i] = false; 291 for (uint32_t i=0; i<_param->_size_load_queue ; i++) 292 load_queue_use [i] = false; 293 294 double current_cycle = sc_simulation_time(); 295 double cycle_min = current_cycle; 296 297 Toperation_t operation_store [4] = {OPERATION_MEMORY_STORE_8, 298 OPERATION_MEMORY_STORE_16, 299 OPERATION_MEMORY_STORE_32, 300 OPERATION_MEMORY_STORE_64}; 301 302 Toperation_t operation_load [8] = {OPERATION_MEMORY_LOAD_8_Z, 303 OPERATION_MEMORY_LOAD_8_S, 304 OPERATION_MEMORY_LOAD_16_Z, 305 OPERATION_MEMORY_LOAD_16_S, 306 OPERATION_MEMORY_LOAD_32_Z, 307 OPERATION_MEMORY_LOAD_32_S, 308 OPERATION_MEMORY_LOAD_64_Z, 309 OPERATION_MEMORY_LOAD_64_S}; 310 311 Toperation_t operation_other [5] = {OPERATION_MEMORY_LOCK , 312 OPERATION_MEMORY_INVALIDATE , 313 OPERATION_MEMORY_PREFETCH , 314 OPERATION_MEMORY_FLUSH , 315 OPERATION_MEMORY_SYNCHRONIZATION}; 316 317 318 const uint32_t nb_operation_store = (log2(_param->_size_general_data/8)+1); 319 const uint32_t nb_operation_load = 2*(log2(_param->_size_general_data/8)+1); 320 const uint32_t nb_operation_other = 5; 321 322 LABEL("Fifo request initialisation"); 323 // Init fifo_request 324 for (uint32_t i=0; i<nb_request; i++) 325 { 326 double cycle; 327 Tcontext_t context_id = 0; 328 Tcontext_t front_end_id = 0; 329 Tcontext_t ooo_engine_id = rand () % _param->_nb_ooo_engine; 330 Tpacket_t packet_id = i; 331 Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write; 332 Tlsq_ptr_t load_queue_ptr_write_old = load_queue_ptr_write ; 333 Toperation_t operation; 500 334 501 int32_tpercent = rand()%100;502 503 uint32_tsize_queue;335 int32_t percent = rand()%100; 336 337 uint32_t size_queue; 504 338 505 if (percent <= seuil_type_load) 506 { 507 // LABEL(" * LOAD"); 508 operation = OPERATION_MEMORY_LOAD_16_S; 509 size_queue = _param->_size_load_queue; 510 load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue); 511 } 512 else 513 { 514 if (percent <= seuil_type_store) 339 if (percent < seuil_type_load) 515 340 { 516 // LABEL(" * STORE");517 operation = OPERATION_MEMORY_STORE_16;518 size_queue = _param->_size_store_queue;519 store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);341 LABEL(" * LOAD"); 342 operation = operation_load[(rand()%nb_operation_load)]; 343 size_queue = _param->_size_load_queue; 344 load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue); 520 345 } 521 346 else 522 347 { 523 // LABEL(" * OTHERS"); 524 operation = OPERATION_MEMORY_PREFETCH; 525 size_queue = _param->_size_load_queue; 526 load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue); 348 if (percent < seuil_type_store) 349 { 350 LABEL(" * STORE"); 351 352 353 operation = operation_store[(rand()%nb_operation_store)]; 354 size_queue = _param->_size_store_queue; 355 store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue); 356 } 357 else 358 { 359 LABEL(" * OTHERS"); 360 operation = operation_other[(rand()%nb_operation_other)]; 361 // operation = operation_other[4]; 362 size_queue = _param->_size_load_queue; 363 load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue); 364 } 365 } 366 367 cycle = cycle_min; 368 cycle_min ++; 369 370 Ttype_t type = TYPE_MEMORY; 371 Tgeneral_data_t address = rand()%(nb_word); 372 Tgeneral_data_t offset = rand()%(nb_word); 373 374 // LABEL ("Address step 1 : "+toString(address)+" - "+toString(offset)); 375 376 percent = rand()%100; 377 if (percent > percent_exception) 378 address = address & (~ mask_memory_access(operation)); 379 380 // LABEL ("Address step 2 : "+toString(address)+" - mask : "+toString((~ mask_memory_access(operation)))); 381 382 if (offset > address) // max 383 offset = address; 384 385 Tgeneral_data_t immediat = offset; 386 Tgeneral_data_t data_ra = address - offset; 387 388 // LABEL ("Address step 3 : "+toString(address)+", "+toString(data_ra)+" - "+toString(immediat)); 389 390 Tgeneral_data_t data_rb = static_cast<Tgeneral_data_t>(rand()); 391 Tcontrol_t write_rd = 0; 392 Tgeneral_address_t num_reg_rd = 0; 393 bool write_spec_ko = is_operation_memory_store(operation) and ((rand()%100)<percent_miss_spec); 394 395 tab_request [i].modif(cycle , 396 context_id , 397 front_end_id , 398 ooo_engine_id , 399 packet_id , 400 operation , 401 type , 402 store_queue_ptr_write_old, 403 load_queue_ptr_write_old , 404 immediat , 405 data_ra , 406 data_rb , 407 write_rd , 408 num_reg_rd , 409 write_spec_ko); 410 411 cout << tab_request [i] << endl; 412 413 fifo_request.push(tab_request [i]); 414 415 double cycle_head = 0; 416 417 if (is_operation_memory_store(operation)) 418 { 419 cycle_head = cycle_min; 420 cycle_min ++; 421 422 cout << " * Write head : " << toString(cycle_head) 423 << endl 424 << endl; 425 426 fifo_request.push(MemoryRequest_t(cycle_head, 427 context_id, 428 front_end_id, 429 ooo_engine_id, 430 packet_id, 431 (write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK, 432 type, 433 store_queue_ptr_write_old, 434 0, 435 0, 436 0, 437 0, 438 0, 439 0, 440 write_spec_ko)); 527 441 } 528 442 } 529 530 cycle = cycle_min; 531 cycle_min ++; 532 533 Ttype_t type = TYPE_MEMORY; 534 Tgeneral_data_t address = rand()%(nb_word); 535 Tgeneral_data_t offset = rand()%(nb_word); 536 537 percent = rand()%100; 538 if (percent > percent_exception) 539 address = address & (not mask_memory_access(operation)); 540 541 if (offset > address) // max 542 offset = address; 543 544 Tgeneral_data_t immediat = offset; 545 Tgeneral_data_t data_ra = address - offset; 546 Tgeneral_data_t data_rb = rand()%(1<<_param->_size_general_data); 547 Tcontrol_t write_rd = 0; 548 Tgeneral_address_t num_reg_rd = 0; 549 bool write_spec_ko = ((rand()%100)<percent_miss_spec); 550 551 tab_request [i].modif(cycle , 552 context_id , 553 packet_id , 554 operation , 555 type , 556 store_queue_ptr_write_old, 557 load_queue_ptr_write_old , 558 immediat , 559 data_ra , 560 data_rb , 561 write_rd , 562 num_reg_rd , 563 write_spec_ko 564 ); 565 566 cout << tab_request [i] << endl; 567 568 fifo_request.push(tab_request [i]); 569 570 double cycle_head = 0; 571 572 if (is_operation_memory_store(operation)) 443 444 LABEL("Simulation of this iteration ..."); 445 446 while (nb_request_memory_out < nb_request) 573 447 { 574 cycle_head = cycle_min; 575 cycle_min ++; 576 577 cout << " * Write head : " << toString(cycle_head) 578 << endl 579 << endl; 448 cout << "*********************************************" << endl; 449 cout << "Dump STORE_QUEUE_USE : " << endl; 450 cout << " use " << nb_store_slot_use << endl; 451 for (uint32_t i=0; i<_param->_size_store_queue; i++) 452 cout << " [" << i << "] " << store_queue_use [i] << endl; 453 cout << "Dump LOAD_QUEUE_USE : " << endl; 454 for (uint32_t i=0; i<_param->_size_load_queue ; i++) 455 cout << " [" << i << "] " << load_queue_use [i] << endl; 456 cout << "*********************************************" << endl; 457 458 459 // ***** MEMORY_IN ***** 460 461 // memory_in_val depends of three factors : 462 // 1) request's fifo is not empty ? 463 // 2) the slot destination is free ? 464 // 3) The head of request's fifo can be issue : the number of cycle is more than current cycle 465 466 bool can_execute = false; 467 468 if (is_operation_memory_store(fifo_request.top()._operation)) 469 can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation); 470 else 471 can_execute = not load_queue_use [fifo_request.top()._load_queue_ptr_write]; 472 473 in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and 474 can_execute and 475 (sc_simulation_time() >= fifo_request.top()._cycle)); 476 477 if (_param->_have_port_context_id) 478 in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id ); 479 if (_param->_have_port_front_end_id) 480 in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id ); 481 if (_param->_have_port_ooo_engine_id) 482 in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id ); 483 if (_param->_have_port_packet_id) 484 in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id ); 485 in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation ); 486 in_MEMORY_IN_TYPE ->write (fifo_request.top()._type ); 487 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write); 488 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write ); 489 in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat ); 490 in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra ); 491 in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb ); 492 // in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd ); 493 in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd ); 494 495 in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out); 496 497 // ***** DCACHE_REQ ***** 498 in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache); 499 500 // ***** DCACHE_RSP ***** 501 bool have_rsp = _cache->have_rsp (); 502 in_DCACHE_RSP_VAL->write(have_rsp); 503 504 if (have_rsp) 505 { 506 in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id); 507 in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id ); 508 in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata ); 509 in_DCACHE_RSP_ERROR ->write(_cache->front()._error ); 510 } 511 512 SC_START(0); 513 514 LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read())); 515 LABEL(" * fifo_request.empty : "+toString(fifo_request.empty())); 516 LABEL(" * fifo_request.top.cycle : "+toString(fifo_request.top()._cycle)); 517 LABEL(" * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write))); 518 LABEL(" * fifo_request.top.load_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write))); 519 LABEL(" * fifo_request.top.operation : "+toString(static_cast<uint32_t>(fifo_request.top()._operation ))); 520 LABEL(" * can_execute : "+toString(can_execute)); 521 522 if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read()) 523 { 524 LABEL(" * Accepted MEMORY_IN : " + toString(nb_request_memory_in)); 525 cout << fifo_request.top(); 526 527 if (is_operation_memory_store(fifo_request.top()._operation)) 528 { 529 if (not is_operation_memory_store_head(fifo_request.top()._operation)) 530 { 531 store_queue_use [fifo_request.top()._store_queue_ptr_write] = true; 532 nb_store_slot_use ++; 533 } 534 } 535 else 536 load_queue_use [fifo_request.top()._load_queue_ptr_write] = true; 537 538 fifo_request.pop(); 580 539 581 fifo_request.push(MemoryRequest_t(cycle_head, 582 context_id, 583 packet_id, 584 (write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK, 585 type, 586 store_queue_ptr_write_old, 587 0, 588 0, 589 0, 590 0, 591 0, 592 0, 593 write_spec_ko)); 540 nb_request_memory_in ++; 541 } 542 543 LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read())); 544 if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read()) 545 { 546 Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read(); 547 548 LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id)); 549 550 if (is_operation_memory_store(tab_request[packet_id]._operation)) 551 { 552 store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false; 553 nb_store_slot_use --; 554 } 555 else 556 load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false; 557 558 nb_request_memory_out ++; 559 560 // a lot of test 561 TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id ); 562 TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id ); 563 TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id); 564 TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id ); 565 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), tab_request[packet_id]._write_rd ); 566 TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd ); 567 568 Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat; 569 if (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation)))) 570 TEST(Texception_t , out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_ALIGNMENT); 571 else 572 { 573 if (tab_request[packet_id]._write_spec_ko) 574 TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_MISS_SPECULATION); 575 else 576 { 577 TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_NONE); 578 579 if (is_operation_memory_load(tab_request[packet_id]._operation)) 580 { 581 Tgeneral_data_t read_lsq = _memory->read_lsq (((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) | 582 (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) | 583 (tab_request[packet_id]._context_id)), 584 (tab_request[packet_id]._immediat + 585 tab_request[packet_id]._data_ra), 586 tab_request[packet_id]._operation); 587 cout << "MEMORY_OUT is a LOAD" << endl 588 << " * operation : " << tab_request[packet_id]._operation << endl 589 << std::hex 590 << " * address : " << (tab_request[packet_id]._immediat + 591 tab_request[packet_id]._data_ra) << endl 592 << " * read_lsq : " << read_lsq << endl 593 << " * memory_out_data : " << out_MEMORY_OUT_DATA_RD->read() << endl 594 << std::dec; 595 596 // TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), read_lsq); 597 } 598 } 599 } 600 } 601 602 LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read())); 603 if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read()) 604 { 605 Tcontext_t context_id; 606 Tpacket_t packet_id ; 607 if (_param->_have_port_dcache_context_id) 608 context_id = out_DCACHE_REQ_CONTEXT_ID->read(); 609 else 610 context_id = 0; 611 612 packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1; 613 614 LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id)); 615 616 // TEST(Tcontext_t ,out_DCACHE_REQ_CONTEXT_ID->read(),((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) | 617 // (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) | 618 // (tab_request[packet_id]._context_id))); 619 // TEST(Tdcache_address_t,out_DCACHE_REQ_ADDRESS ->read(),(tab_request[packet_id]._immediat + 620 // tab_request[packet_id]._data_ra) ); 621 // TEST(Tdcache_type_t ,out_DCACHE_REQ_TYPE ->read(), operation_to_dcache_type(operation)); 622 623 // if (is_operation_memory_store(operation)) 624 // TEST(Tdcache_data_t ,out_DCACHE_REQ_WDATA ->read(),tab_request[packet_id]._data_rb); 625 626 Tdcache_data_t rdata = _memory->access (context_id, out_DCACHE_REQ_ADDRESS->read(), out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read()); 627 628 // test type : send or not a respons ! 629 LABEL(" * rdata : " + toString(rdata)); 630 631 if ((out_DCACHE_REQ_TYPE->read() == DCACHE_SYNCHRONIZATION) or 632 (out_DCACHE_REQ_TYPE->read() == DCACHE_LOAD)) 633 { 634 LABEL(" * have_dcache_rsp"); 635 636 _cache->push (context_id, 637 out_DCACHE_REQ_PACKET_ID ->read(), 638 rdata , 639 0); 640 } 641 } 642 643 LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read())); 644 if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read()) 645 { 646 _cache->pop(); 647 } 648 649 _cache->end_cycle(); 650 651 SC_START(1); 594 652 } 595 }596 597 LABEL("Simulation of this iteration ...");598 599 while (nb_request_memory_out < nb_request)600 {601 // ***** MEMORY_IN *****602 603 // memory_in_val depends of three factors :604 // 1) request's fifo is not empty ?605 // 2) the slot destination is free ?606 // 3) The head of request's fifo can be issue : the number of cycle is more than current cycle607 608 bool can_execute = false;609 610 if (is_operation_memory_store(fifo_request.top()._operation))611 can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write]) or is_operation_memory_store_head(fifo_request.top()._operation);612 else613 can_execute = not load_queue_use [fifo_request.top()._load_queue_ptr_write];614 615 in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and616 can_execute and617 (sc_simulation_time() >= fifo_request.top()._cycle));618 619 in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );620 in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );621 in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );622 in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );623 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);624 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );625 in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );626 in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );627 in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );628 in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );629 in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );630 631 in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);632 633 // ***** DCACHE_REQ *****634 in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);635 636 SC_START(0);637 638 SC_START(1);639 640 LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));641 LABEL(" * fifo_request.empty : "+toString(fifo_request.empty()));642 LABEL(" * fifo_request.top.cycle : "+toString(fifo_request.top()._cycle));643 LABEL(" * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));644 LABEL(" * fifo_request.top.load_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));645 LABEL(" * fifo_request.top.operation : "+toString(static_cast<uint32_t>(fifo_request.top()._operation )));646 LABEL(" * can_execute : "+toString(can_execute));647 648 if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())649 {650 LABEL(" * Accepted MEMORY_IN : " + toString(nb_request_memory_in));651 cout << fifo_request.top();652 653 if (is_operation_memory_store(fifo_request.top()._operation))654 {655 if (not is_operation_memory_store_head(fifo_request.top()._operation))656 store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;657 }658 else659 load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;660 661 fifo_request.pop();662 663 nb_request_memory_in ++;664 }665 666 LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));667 if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())668 {669 LABEL(" * Accepted MEMORY_OUT : " + toString(static_cast<uint32_t>(out_MEMORY_OUT_PACKET_ID->read())));670 671 if (is_operation_memory_store(tab_request[out_MEMORY_OUT_PACKET_ID->read()]._operation))672 store_queue_use [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._store_queue_ptr_write] = false;673 else674 load_queue_use [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._load_queue_ptr_write] = false;675 676 nb_request_memory_out ++;677 }678 679 LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));680 if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read())681 {682 LABEL(" * Accepted DCACHE_REQ : " + toString(static_cast<uint32_t>(out_DCACHE_REQ_PACKET_ID->read())));683 684 // test type : send or not a respons !685 }686 687 653 } 688 654 } 655 catch (morpheo::ErrorMorpheo & error) 656 { 657 _memory->trace(); 658 throw (error); 659 } 660 661 _memory->trace(); 662 689 663 690 664 /******************************************************** … … 699 673 delete in_NRESET; 700 674 701 delete in_MEMORY_IN_VAL ; 702 delete out_MEMORY_IN_ACK ; 703 delete in_MEMORY_IN_CONTEXT_ID ; 704 delete in_MEMORY_IN_PACKET_ID ; 705 delete in_MEMORY_IN_OPERATION ; 706 delete in_MEMORY_IN_TYPE ; 675 delete in_MEMORY_IN_VAL ; 676 delete out_MEMORY_IN_ACK ; 677 delete in_MEMORY_IN_CONTEXT_ID ; 678 delete in_MEMORY_IN_FRONT_END_ID ; 679 delete in_MEMORY_IN_OOO_ENGINE_ID ; 680 delete in_MEMORY_IN_PACKET_ID ; 681 delete in_MEMORY_IN_OPERATION ; 707 682 delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 708 683 delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 709 //delete in_MEMORY_IN_HAS_IMMEDIAT;710 delete in_MEMORY_IN_IMMEDIAT 711 delete in_MEMORY_IN_DATA_RA 712 delete in_MEMORY_IN_DATA_RB 713 //delete in_MEMORY_IN_DATA_RC;714 delete in_MEMORY_IN_WRITE_RD;715 delete in_MEMORY_IN_NUM_REG_RD 716 //delete in_MEMORY_IN_WRITE_RE;717 //delete in_MEMORY_IN_NUM_REG_RE;718 684 //delete in_MEMORY_IN_HAS_IMMEDIAT; 685 delete in_MEMORY_IN_IMMEDIAT ; 686 delete in_MEMORY_IN_DATA_RA ; 687 delete in_MEMORY_IN_DATA_RB ; 688 //delete in_MEMORY_IN_DATA_RC ; 689 // delete in_MEMORY_IN_WRITE_RD ; 690 delete in_MEMORY_IN_NUM_REG_RD ; 691 //delete in_MEMORY_IN_WRITE_RE ; 692 //delete in_MEMORY_IN_NUM_REG_RE ; 693 719 694 delete out_MEMORY_OUT_VAL ; 720 695 delete in_MEMORY_OUT_ACK ; 721 696 delete out_MEMORY_OUT_CONTEXT_ID; 697 delete out_MEMORY_OUT_FRONT_END_ID; 698 delete out_MEMORY_OUT_OOO_ENGINE_ID; 722 699 delete out_MEMORY_OUT_PACKET_ID ; 723 delete out_MEMORY_OUT_OPERATION ;724 delete out_MEMORY_OUT_TYPE ;725 700 delete out_MEMORY_OUT_WRITE_RD ; 726 701 delete out_MEMORY_OUT_NUM_REG_RD; 727 702 delete out_MEMORY_OUT_DATA_RD ; 728 //delete out_MEMORY_OUT_WRITE_RE ;729 //delete out_MEMORY_OUT_NUM_REG_RE;730 //delete out_MEMORY_OUT_DATA_RE ;703 //delete out_MEMORY_OUT_WRITE_RE ; 704 //delete out_MEMORY_OUT_NUM_REG_RE; 705 //delete out_MEMORY_OUT_DATA_RE ; 731 706 delete out_MEMORY_OUT_EXCEPTION ; 732 707 733 708 delete out_DCACHE_REQ_VAL ; 734 709 delete in_DCACHE_REQ_ACK ; … … 737 712 delete out_DCACHE_REQ_ADDRESS ; 738 713 delete out_DCACHE_REQ_TYPE ; 739 delete out_DCACHE_REQ_UNCACHED ;740 714 delete out_DCACHE_REQ_WDATA ; 741 715 742 716 delete in_DCACHE_RSP_VAL ; 743 717 delete out_DCACHE_RSP_ACK ; … … 746 720 delete in_DCACHE_RSP_RDATA ; 747 721 delete in_DCACHE_RSP_ERROR ; 748 749 delete [] out_BYPASS_MEMORY_VAL ; 750 delete [] out_BYPASS_MEMORY_CONTEXT_ID; 751 delete [] out_BYPASS_MEMORY_NUM_REG ; 752 delete [] out_BYPASS_MEMORY_DATA ; 753 722 723 if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS) 724 { 725 delete [] out_BYPASS_MEMORY_VAL ; 726 delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; 727 delete [] out_BYPASS_MEMORY_NUM_REG ; 728 delete [] out_BYPASS_MEMORY_DATA ; 729 } 754 730 #endif 755 731 756 732 delete _Load_store_unit; 733 delete _memory; 734 delete _cache; 757 735 #ifdef STATISTICS 758 736 delete _parameters_statistics;
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