- Timestamp:
- Mar 27, 2008, 11:04:49 AM (16 years ago)
- File:
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- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
r77 r78 161 161 # define OPERATION_FIND_L_FL1 0x2 // 000_0000 l.fl1 162 162 163 # define OPERATION_SPECIAL_L_MFSPR 0x1 // 000_0000 l.mfspr 164 # define OPERATION_SPECIAL_L_MTSPR 0x2 // 000_0000 l.mtspr 165 # define OPERATION_SPECIAL_L_MAC 0x4 // 000_0000 l.mac , l.maci 166 # define OPERATION_SPECIAL_L_MACRC 0x8 // 000_0000 l.macrc 167 # define OPERATION_SPECIAL_L_MSB 0x10 // 000_0000 l.msb 168 169 # define OPERATION_BRANCH_L_TEST_NF 0x1 // 000_0000 l.bnf 170 # define OPERATION_BRANCH_L_TEST_F 0x2 // 000_0000 l.bf 171 # define OPERATION_BRANCH_L_JALR 0x4 // 000_0000 l.jal , l.jalr , l.jr 163 # define OPERATION_SPECIAL_L_NOP 0xff // 000_0000 l.nop 164 # define OPERATION_SPECIAL_L_MFSPR 0x1 // 000_0001 l.mfspr 165 # define OPERATION_SPECIAL_L_MTSPR 0x2 // 000_0010 l.mtspr 166 # define OPERATION_SPECIAL_L_RFE 0x4 // 000_0100 l.rfe 167 # define OPERATION_SPECIAL_L_MAC 0x11 // 001_0001 l.mac , l.maci 168 # define OPERATION_SPECIAL_L_MACRC 0x12 // 001_0010 l.macrc 169 # define OPERATION_SPECIAL_L_MSB 0x14 // 001_0100 l.msb 170 # define OPERATION_SPECIAL_L_MSYNC 0x21 // 010_0001 l.msync 171 # define OPERATION_SPECIAL_L_PSYNC 0x22 // 010_0010 l.psync 172 # define OPERATION_SPECIAL_L_CSYNC 0x24 // 010_0100 l.csync 173 # define OPERATION_SPECIAL_L_SYS 0x41 // 100_0001 l.sys 174 # define OPERATION_SPECIAL_L_TRAP 0x42 // 100_0010 l.trap 175 176 177 # define OPERATION_BRANCH_NONE 0x1 // 000_0000 l.j 178 # define OPERATION_BRANCH_L_TEST_NF 0x2 // 000_0000 l.bnf 179 # define OPERATION_BRANCH_L_TEST_F 0x4 // 000_0000 l.bf 180 # define OPERATION_BRANCH_L_JALR 0x8 // 000_0000 l.jal , l.jalr , l.jr 172 181 173 182 //-------------------------------------------------------[ Custom ]----- … … 195 204 196 205 # define SIZE_EXCEPTION 5 206 # define SIZE_EXCEPTION_USE 4 207 # define SIZE_EXCEPTION_MEMORY 3 208 # define SIZE_EXCEPTION_CUSTOM 3 209 # define SIZE_EXCEPTION_ALU 2 210 # define SIZE_EXCEPTION_DECOD 2 211 # define SIZE_EXCEPTION_IFETCH 2 197 212 198 213 # define EXCEPTION_NONE 0x00 // none exception … … 229 244 # define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions 230 245 246 231 247 #define exception_to_address(x) (x<<8) 232 248 … … 253 269 # define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x2 // SPR present in ALU but not compatible privilege 254 270 # define EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE 0x3 // SPR not present in ALU 271 272 # define EXCEPTION_DECOD_NONE 0x0 // none exception 273 # define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x1 // Instruction is illegal (no implemented) 274 # define EXCEPTION_DECOD_SYSCALL 0x2 // System Call 275 //#define EXCEPTION_DECOD_TRAP 0x4 // L.trap or debug unit (note : must read SR !) 276 277 # define EXCEPTION_IFETCH_NONE 0x0 // Fetch Unit generate none exception 278 # define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x1 // ITLB miss 279 # define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x2 // No matching or page violation protection in pages tables 280 # define EXCEPTION_IFETCH_BUS_ERROR 0x3 // Access at a invalid physical address 281 282 # define EXCEPTION_USE_NONE 0x0 // 283 # define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x1 // illegal_instruction 284 # define EXCEPTION_USE_RANGE 0x2 // range 285 # define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x3 // TLB miss, page fault, bus error, alignment 286 # define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x4 // TLB miss, page fault, bus error 287 # define EXCEPTION_USE_SYSCALL 0x5 // syscall 288 # define EXCEPTION_USE_TRAP 0x6 // trap 289 # define EXCEPTION_USE_CUSTOM_0 0x7 // 290 # define EXCEPTION_USE_CUSTOM_1 0x8 // 291 # define EXCEPTION_USE_CUSTOM_2 0x9 // 292 # define EXCEPTION_USE_CUSTOM_3 0xa // 293 # define EXCEPTION_USE_CUSTOM_4 0xb // 294 # define EXCEPTION_USE_CUSTOM_5 0xc // 295 # define EXCEPTION_USE_CUSTOM_6 0xd // 296 297 //=======================================================[ icache ]===== 298 299 //--------------------------------------------------[ icache_type ]----- 300 301 # define SIZE_ICACHE_TYPE 2 302 303 # define ICACHE_TYPE_LOAD 0x0 // 0000 304 # define ICACHE_TYPE_LOCK 0x1 // 0001 305 # define ICACHE_TYPE_INVALIDATE 0x2 // 0010 306 # define ICACHE_TYPE_PREFETCH 0x3 // 0011 307 308 // just take the 2 less significative bits. 309 #define operation_to_icache_type(x) (x&0x3) 310 311 //-------------------------------------------------[ icache_error ]----- 312 313 # define SIZE_ICACHE_ERROR 1 314 315 # define ICACHE_ERROR_NONE 0x0 316 # define ICACHE_ERROR_BUS_ERROR 0x1 255 317 256 318 //=======================================================[ dcache ]===== … … 377 439 # define SPR_MACHI 2 // MAC High 378 440 441 # define NB_SPR_LOGIC 2 442 # define LOG2_NB_SPR_LOGIC 1 443 // SPR_LOGIC[0] = F 444 // SPR_LOGIC[1] = Carry, Overflow 445 # define SPR_LOGIC_SR_F 0x0 // Status register bit F (size = 1) 446 # define SPR_LOGIC_SR_CY_OV 0x1 // Status register bit overflow and carry (size = 2) 447 379 448 //----------------------------------------------[ spr_mode_access ]----- 380 449 … … 385 454 # define SPR_ACCESS_MODE_READ_ONLY_COND 0x5 // 101 special read 386 455 456 //--------------------------------------------------------[ event ]----- 457 # define SIZE_EVENT_STATE 2 458 459 # define EVENT_STATE_NO_EVENT 0 // no event : current case 460 # define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event 461 # define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context) 462 # define EVENT_STATE_END 3 // CPU can continue 463 464 # define SIZE_EVENT_TYPE 3 465 466 # define EVENT_TYPE_NONE 0 // no event 467 # define EVENT_TYPE_MISS_SPECULATION 1 // miss of speculation (load or branch miss speculation) 468 # define EVENT_TYPE_EXCEPTION 2 // exception or interruption occure 469 # define EVENT_TYPE_BRANCH_NO_ACCURATE 3 // branch is no accurate (old speculation is a miss) 470 # define EVENT_TYPE_SPR_ACCESS 4 // decod a mtspr or mfspr instruction 471 # define EVENT_TYPE_MSYNC 5 // decod a memory synchronization 472 # define EVENT_TYPE_PSYNC 6 // decod a pipeline synchronization 473 # define EVENT_TYPE_CSYNC 7 // decod a context synchronization 474 475 //-------------------------------------------------[ branch_state ]----- 476 # define SIZE_BRANCH_STATE 2 477 478 # define BRANCH_STATE_NONE 0x0 // 0 0 479 # define BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal 480 # define BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0 481 # define BRANCH_STATE_SPEC_TAKE 0x3 // 1 1 482 483 //---------------------------------------------[ branch_condition ]----- 484 485 # define SIZE_BRANCH_CONDITION 4 486 487 # define BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK 0x0 // None condition (jump) 488 # define BRANCH_CONDITION_NONE_WITH_WRITE_STACK 0x8 // None condition (jump) 489 # define BRANCH_CONDITION_FLAG_UNSET 0x2 // Branch if Flag is clear 490 # define BRANCH_CONDITION_FLAG_SET 0x3 // Branch if Flag is set 491 # define BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK 0x4 // Branch if a register is read 492 # define BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK 0xc // Branch if a register is read 493 # define BRANCH_CONDITION_READ_STACK 0xf // Branch with pop in stack pointer 494 495 //--------------------------------------------------[ instruction ]----- 496 # define NB_INSTRUCTION 213 // 92 ORBIS, 30 ORFPX (15 simple, 15 double), 91 ORVDX (38 on byte, 41 on half, 12 independant format) 497 498 enum 499 { 500 // ORBIS 501 INSTRUCTION_L_ADD, 502 INSTRUCTION_L_ADDC, 503 INSTRUCTION_L_ADDI, 504 INSTRUCTION_L_ADDIC, 505 INSTRUCTION_L_AND, 506 INSTRUCTION_L_ANDI, 507 INSTRUCTION_L_BF, 508 INSTRUCTION_L_BNF, 509 INSTRUCTION_L_CMOV, 510 INSTRUCTION_L_CSYNC, 511 INSTRUCTION_L_CUST1, 512 INSTRUCTION_L_CUST2, 513 INSTRUCTION_L_CUST3, 514 INSTRUCTION_L_CUST4, 515 INSTRUCTION_L_CUST5, 516 INSTRUCTION_L_CUST6, 517 INSTRUCTION_L_CUST7, 518 INSTRUCTION_L_CUST8, 519 INSTRUCTION_L_DIV, 520 INSTRUCTION_L_DIVU, 521 INSTRUCTION_L_EXTBS, 522 INSTRUCTION_L_EXTBZ, 523 INSTRUCTION_L_EXTHS, 524 INSTRUCTION_L_EXTHZ, 525 INSTRUCTION_L_EXTWS, 526 INSTRUCTION_L_EXTWZ, 527 INSTRUCTION_L_FF1, 528 INSTRUCTION_L_FL1, 529 INSTRUCTION_L_J, 530 INSTRUCTION_L_JAL, 531 INSTRUCTION_L_JALR, 532 INSTRUCTION_L_JR, 533 INSTRUCTION_L_LBS, 534 INSTRUCTION_L_LBZ, 535 INSTRUCTION_L_LD, 536 INSTRUCTION_L_LHS, 537 INSTRUCTION_L_LHZ, 538 INSTRUCTION_L_LWS, 539 INSTRUCTION_L_LWZ, 540 INSTRUCTION_L_MAC, 541 INSTRUCTION_L_MACI, 542 INSTRUCTION_L_MACRC, 543 INSTRUCTION_L_MFSPR, 544 INSTRUCTION_L_MOVHI, 545 INSTRUCTION_L_MSB, 546 INSTRUCTION_L_MSYNC, 547 INSTRUCTION_L_MTSPR, 548 INSTRUCTION_L_MUL, 549 INSTRUCTION_L_MULI, 550 INSTRUCTION_L_MULU, 551 INSTRUCTION_L_NOP, 552 INSTRUCTION_L_OR, 553 INSTRUCTION_L_ORI, 554 INSTRUCTION_L_PSYNC, 555 INSTRUCTION_L_RFE, 556 INSTRUCTION_L_ROR, 557 INSTRUCTION_L_RORI, 558 INSTRUCTION_L_SB, 559 INSTRUCTION_L_SD, 560 INSTRUCTION_L_SFEQ, 561 INSTRUCTION_L_SFEQI, 562 INSTRUCTION_L_SFGES, 563 INSTRUCTION_L_SFGESI, 564 INSTRUCTION_L_SFGEU, 565 INSTRUCTION_L_SFGEUI, 566 INSTRUCTION_L_SFGTS, 567 INSTRUCTION_L_SFGTSI, 568 INSTRUCTION_L_SFGTU, 569 INSTRUCTION_L_SFGTUI, 570 INSTRUCTION_L_SFLES, 571 INSTRUCTION_L_SFLESI, 572 INSTRUCTION_L_SFLEU, 573 INSTRUCTION_L_SFLEUI, 574 INSTRUCTION_L_SFLTS, 575 INSTRUCTION_L_SFLTSI, 576 INSTRUCTION_L_SFLTU, 577 INSTRUCTION_L_SFLTUI, 578 INSTRUCTION_L_SFNE, 579 INSTRUCTION_L_SFNEI, 580 INSTRUCTION_L_SH, 581 INSTRUCTION_L_SLL, 582 INSTRUCTION_L_SLLI, 583 INSTRUCTION_L_SRA, 584 INSTRUCTION_L_SRAI, 585 INSTRUCTION_L_SRL, 586 INSTRUCTION_L_SRLI, 587 INSTRUCTION_L_SUB, 588 INSTRUCTION_L_SW, 589 INSTRUCTION_L_SYS, 590 INSTRUCTION_L_TRAP, 591 INSTRUCTION_L_XOR, 592 INSTRUCTION_L_XORI, 593 // ORFPX 594 INSTRUCTION_LF_ADD_D, 595 INSTRUCTION_LF_ADD_S, 596 INSTRUCTION_LF_CUST1_D, 597 INSTRUCTION_LF_CUST1_S, 598 INSTRUCTION_LF_DIV_D, 599 INSTRUCTION_LF_DIV_S, 600 INSTRUCTION_LF_FTOI_D, 601 INSTRUCTION_LF_FTOI_S, 602 INSTRUCTION_LF_ITOF_D, 603 INSTRUCTION_LF_ITOF_S, 604 INSTRUCTION_LF_MADD_D, 605 INSTRUCTION_LF_MADD_S, 606 INSTRUCTION_LF_MUL_D, 607 INSTRUCTION_LF_MUL_S, 608 INSTRUCTION_LF_REM_D, 609 INSTRUCTION_LF_REM_S, 610 INSTRUCTION_LF_SFEQ_D, 611 INSTRUCTION_LF_SFEQ_S, 612 INSTRUCTION_LF_SFGE_D, 613 INSTRUCTION_LF_SFGE_S, 614 INSTRUCTION_LF_SFGT_D, 615 INSTRUCTION_LF_SFGT_S, 616 INSTRUCTION_LF_SFLE_D, 617 INSTRUCTION_LF_SFLE_S, 618 INSTRUCTION_LF_SFLT_D, 619 INSTRUCTION_LF_SFLT_S, 620 INSTRUCTION_LF_SFNE_D, 621 INSTRUCTION_LF_SFNE_S, 622 INSTRUCTION_LF_SUB_D, 623 INSTRUCTION_LF_SUB_S, 624 // ORVDX 625 INSTRUCTION_LV_ADD_B, 626 INSTRUCTION_LV_ADD_H, 627 INSTRUCTION_LV_ADDS_B, 628 INSTRUCTION_LV_ADDS_H, 629 INSTRUCTION_LV_ADDU_B, 630 INSTRUCTION_LV_ADDU_H, 631 INSTRUCTION_LV_ADDUS_B, 632 INSTRUCTION_LV_ADDUS_H, 633 INSTRUCTION_LV_ALL_EQ_B, 634 INSTRUCTION_LV_ALL_EQ_H, 635 INSTRUCTION_LV_ALL_GE_B, 636 INSTRUCTION_LV_ALL_GE_H, 637 INSTRUCTION_LV_ALL_GT_B, 638 INSTRUCTION_LV_ALL_GT_H, 639 INSTRUCTION_LV_ALL_LE_B, 640 INSTRUCTION_LV_ALL_LE_H, 641 INSTRUCTION_LV_ALL_LT_B, 642 INSTRUCTION_LV_ALL_LT_H, 643 INSTRUCTION_LV_ALL_NE_B, 644 INSTRUCTION_LV_ALL_NE_H, 645 INSTRUCTION_LV_AND, 646 INSTRUCTION_LV_ANY_EQ_B, 647 INSTRUCTION_LV_ANY_EQ_H, 648 INSTRUCTION_LV_ANY_GE_B, 649 INSTRUCTION_LV_ANY_GE_H, 650 INSTRUCTION_LV_ANY_GT_B, 651 INSTRUCTION_LV_ANY_GT_H, 652 INSTRUCTION_LV_ANY_LE_B, 653 INSTRUCTION_LV_ANY_LE_H, 654 INSTRUCTION_LV_ANY_LT_B, 655 INSTRUCTION_LV_ANY_LT_H, 656 INSTRUCTION_LV_ANY_NE_B, 657 INSTRUCTION_LV_ANY_NE_H, 658 INSTRUCTION_LV_AVG_B, 659 INSTRUCTION_LV_AVG_H, 660 INSTRUCTION_LV_CMP_EQ_B, 661 INSTRUCTION_LV_CMP_EQ_H, 662 INSTRUCTION_LV_CMP_GE_B, 663 INSTRUCTION_LV_CMP_GE_H, 664 INSTRUCTION_LV_CMP_GT_B, 665 INSTRUCTION_LV_CMP_GT_H, 666 INSTRUCTION_LV_CMP_LE_B, 667 INSTRUCTION_LV_CMP_LE_H, 668 INSTRUCTION_LV_CMP_LT_B, 669 INSTRUCTION_LV_CMP_LT_H, 670 INSTRUCTION_LV_CMP_NE_B, 671 INSTRUCTION_LV_CMP_NE_H, 672 INSTRUCTION_LV_CUST1, 673 INSTRUCTION_LV_CUST2, 674 INSTRUCTION_LV_CUST3, 675 INSTRUCTION_LV_CUST4, 676 INSTRUCTION_LV_MADDS_H, 677 INSTRUCTION_LV_MAX_B, 678 INSTRUCTION_LV_MAX_H, 679 INSTRUCTION_LV_MERGE_B, 680 INSTRUCTION_LV_MERGE_H, 681 INSTRUCTION_LV_MIN_B, 682 INSTRUCTION_LV_MIN_H, 683 INSTRUCTION_LV_MSUBS_H, 684 INSTRUCTION_LV_MULS_H, 685 INSTRUCTION_LV_NAND, 686 INSTRUCTION_LV_NOR, 687 INSTRUCTION_LV_OR, 688 INSTRUCTION_LV_PACK_B, 689 INSTRUCTION_LV_PACK_H, 690 INSTRUCTION_LV_PACKS_B, 691 INSTRUCTION_LV_PACKS_H, 692 INSTRUCTION_LV_PACKUS_B, 693 INSTRUCTION_LV_PACKUS_H, 694 INSTRUCTION_LV_PERM_N, 695 INSTRUCTION_LV_RL_B, 696 INSTRUCTION_LV_RL_H, 697 INSTRUCTION_LV_SLL, 698 INSTRUCTION_LV_SLL_B, 699 INSTRUCTION_LV_SLL_H, 700 INSTRUCTION_LV_SRA_B, 701 INSTRUCTION_LV_SRA_H, 702 INSTRUCTION_LV_SRL, 703 INSTRUCTION_LV_SRL_B, 704 INSTRUCTION_LV_SRL_H, 705 INSTRUCTION_LV_SUB_B, 706 INSTRUCTION_LV_SUB_H, 707 INSTRUCTION_LV_SUBS_B, 708 INSTRUCTION_LV_SUBS_H, 709 INSTRUCTION_LV_SUBU_B, 710 INSTRUCTION_LV_SUBU_H, 711 INSTRUCTION_LV_SUBUS_B, 712 INSTRUCTION_LV_SUBUS_H, 713 INSTRUCTION_LV_UNPACK_B, 714 INSTRUCTION_LV_UNPACK_H, 715 INSTRUCTION_LV_XOR 716 }; 717 718 //-----------------------------------------------[ Code Operation ]----- 719 720 # define MAX_OPCOD_0 64 // Instructions with immediat 721 # define MAX_OPCOD_1 64 // Instruction ORFPX32/64 722 # define MAX_OPCOD_2 256 // Instruction ORVDX64 723 # define MAX_OPCOD_3 256 // Instructions Register-Register 724 # define MAX_OPCOD_4 32 // Instructions "set flag" with register 725 # define MAX_OPCOD_5 32 // Instructions "set flag" with immediat 726 # define MAX_OPCOD_6 4 // Instruction Shift/Rotate with immediat 727 # define MAX_OPCOD_7 16 // Instructions multiply with HI-LO 728 # define MAX_OPCOD_8 2 // Instructions acces at HI-LO 729 # define MAX_OPCOD_9 8 // Instructions special 730 # define MAX_OPCOD_10 4 // Instructions no operation 731 # define MAX_OPCOD_11 4 // Instruction Shift/Rotate with register 732 # define MAX_OPCOD_12 4 // Instructions extend 733 # define MAX_OPCOD_13 4 // Instructions extend (64b) 734 735 // OPCOD_0 - [31:26] Instructions with immediat 736 # define OPCOD_L_J 0x00 // 000_000 737 # define OPCOD_L_JAL 0x01 // 000_001 738 # define OPCOD_L_BNF 0x03 // 000_011 739 # define OPCOD_L_BF 0x04 // 000_100 740 # define OPCOD_L_RFE 0x09 // 001_001 741 # define OPCOD_L_JR 0x11 // 010_001 742 # define OPCOD_L_JALR 0x12 // 010_010 743 # define OPCOD_L_MACI 0x13 // 010_011 744 # define OPCOD_L_CUST1 0x1c // 011_100 745 # define OPCOD_L_CUST2 0x1d // 011_101 746 # define OPCOD_L_CUST3 0x1e // 011_110 747 # define OPCOD_L_CUST4 0x1f // 011_111 748 # define OPCOD_L_CUST5 0x3c // 111_100 749 # define OPCOD_L_CUST6 0x3d // 111_101 750 # define OPCOD_L_CUST7 0x3e // 111_110 751 # define OPCOD_L_CUST8 0x3f // 111_111 752 # define OPCOD_L_LD 0x20 // 100_000 753 # define OPCOD_L_LWZ 0x21 // 100_001 754 # define OPCOD_L_LWS 0x22 // 100_010 755 # define OPCOD_L_LBZ 0x23 // 100_011 756 # define OPCOD_L_LBS 0x24 // 100_100 757 # define OPCOD_L_LHZ 0x25 // 100_101 758 # define OPCOD_L_LHS 0x26 // 100_110 759 # define OPCOD_L_ADDI 0x27 // 100_111 760 # define OPCOD_L_ADDIC 0x28 // 101_000 761 # define OPCOD_L_ANDI 0x29 // 101_001 762 # define OPCOD_L_ORI 0x2a // 101_010 763 # define OPCOD_L_XORI 0x2b // 101_011 764 # define OPCOD_L_MULI 0x2c // 101_100 765 # define OPCOD_L_MFSPR 0x2d // 101_101 766 # define OPCOD_L_MTSPR 0x30 // 110_000 767 # define OPCOD_L_SD 0x34 // 110_100 768 # define OPCOD_L_SW 0x35 // 110_101 769 # define OPCOD_L_SB 0x36 // 110_110 770 # define OPCOD_L_SH 0x37 // 110_111 771 772 # define OPCOD_1 0x33 // 110_011 // Instruction ORFPX32/64 773 # define OPCOD_2 0x0a // 001_010 // Instruction ORVDX64 774 # define OPCOD_3 0x38 // 111_000 // Instructions Register-Register 775 # define OPCOD_4 0x39 // 111_001 // Instructions "set flag" with register 776 # define OPCOD_5 0x2f // 101_111 // Instructions "set flag" with immediat 777 # define OPCOD_6 0x2e // 101_110 // Instruction Shift/Rotate with immediat 778 # define OPCOD_7 0x31 // 110_001 // Instructions multiply with HI-LO 779 # define OPCOD_8 0x06 // 000_110 // Instructions acces at HI-LO 780 # define OPCOD_9 0x08 // 001_000 // Instructions special 781 # define OPCOD_10 0x05 // 000_101 // Instructions no operation 782 783 // OPCOD_3 instructions - [9:8] [3:0] Instructions Register-Register 784 # define OPCOD_L_ADD 0x00 // 00_0000 785 # define OPCOD_L_ADDC 0x01 // 00_0001 786 # define OPCOD_L_SUB 0x02 // 00_0010 787 # define OPCOD_L_AND 0x03 // 00_0011 788 # define OPCOD_L_OR 0x04 // 00_0100 789 # define OPCOD_L_XOR 0x05 // 00_0101 790 # define OPCOD_L_CMOV 0x0e // 00_1110 791 # define OPCOD_L_FF1 0x0f // 00_1111 792 # define OPCOD_L_FL1 0x1f // 01_1111 793 # define OPCOD_L_MUL 0x36 // 11_0110 794 # define OPCOD_L_DIV 0x39 // 11_1001 795 # define OPCOD_L_DIVU 0x3a // 11_1010 796 # define OPCOD_L_MULU 0x3b // 11_1011 797 798 # define OPCOD_11 0x8 // 1000 // Instruction Shift/Rotate with register 799 # define OPCOD_12 0xc // 1100 // Instructions extend 800 # define OPCOD_13 0xd // 1101 // Instructions extend (64b) 801 802 // OPCOD_4 instructions - [25:21] Instructions "set flag" with register 803 # define OPCOD_L_SFEQ 0x00 // 00000 804 # define OPCOD_L_SFNE 0x01 // 00001 805 # define OPCOD_L_SFGTU 0x02 // 00010 806 # define OPCOD_L_SFGEU 0x03 // 00011 807 # define OPCOD_L_SFLTU 0x04 // 00100 808 # define OPCOD_L_SFLEU 0x05 // 00101 809 # define OPCOD_L_SFGTS 0x0a // 01010 810 # define OPCOD_L_SFGES 0x0b // 01011 811 # define OPCOD_L_SFLTS 0x0c // 01100 812 # define OPCOD_L_SFLES 0x0d // 01101 813 814 // OPCOD_5 instructions - [25:21] Instructions "set flag" with immediat 815 # define OPCOD_L_SFEQI 0x00 // 00000 816 # define OPCOD_L_SFNEI 0x01 // 00001 817 # define OPCOD_L_SFGTUI 0x02 // 00010 818 # define OPCOD_L_SFGEUI 0x03 // 00011 819 # define OPCOD_L_SFLTUI 0x04 // 00100 820 # define OPCOD_L_SFLEUI 0x05 // 00101 821 # define OPCOD_L_SFGTSI 0x0a // 01010 822 # define OPCOD_L_SFGESI 0x0b // 01011 823 # define OPCOD_L_SFLTSI 0x0c // 01100 824 # define OPCOD_L_SFLESI 0x0d // 01101 825 826 // OPCOD_6 instructions - [7:6] Instruction Shift/Rotate with immediat 827 # define OPCOD_L_SLLI 0x0 // 00 828 # define OPCOD_L_SRLI 0x1 // 01 829 # define OPCOD_L_SRAI 0x2 // 10 830 # define OPCOD_L_RORI 0x3 // 11 831 832 // OPCOD_7 instructions - [3:0] Instructions multiply with HI-LO 833 # define OPCOD_L_MAC 0x1 // 0001 834 # define OPCOD_L_MSB 0x2 // 0010 835 836 // OPCOD_8 instructions - [17] Instructions acces at HI-LO 837 # define OPCOD_L_MOVHI 0x0 // 0 838 # define OPCOD_L_MACRC 0x1 // 1 839 840 // OPCOD_9 instructions - [25:23] Instruction special 841 # define OPCOD_L_SYS 0x0 // 000 842 # define OPCOD_L_TRAP 0x2 // 010 843 # define OPCOD_L_MSYNC 0x4 // 100 844 # define OPCOD_L_PSYNC 0x5 // 101 845 # define OPCOD_L_CSYNC 0x6 // 110 846 847 // OPCOD_10 instructions - [25:24] Instruction no operation 848 # define OPCOD_L_NOP 0x1 // 01 849 850 // OPCOD_11 instructions - [7:6] Instruction Shift/Rotate with register 851 # define OPCOD_L_SLL 0x0 // 00 852 # define OPCOD_L_SRL 0x1 // 01 853 # define OPCOD_L_SRA 0x2 // 10 854 # define OPCOD_L_ROR 0x3 // 11 855 856 // OPCOD_12 instructions - [9:6] Instructions extend 857 # define OPCOD_L_EXTHS 0x0 // 0000 858 # define OPCOD_L_EXTHZ 0x2 // 0010 859 # define OPCOD_L_EXTBS 0x1 // 0001 860 # define OPCOD_L_EXTBZ 0x3 // 0011 861 862 // OPCOD_13 instructions - [9:6] Instructions extend (64b) 863 # define OPCOD_L_EXTWS 0x0 // 0000 864 # define OPCOD_L_EXTWZ 0x1 // 0001 865 387 866 /* 388 #define _size_instruction 32389 #define _size_instruction_log2 5390 391 //----------------------------------------------------[ Operation ]-----392 // #define _nb_operation 32393 // #define _size_operation 5394 395 #define _operation_none 0x0396 #define _operation_l_adds 0x1397 #define _operation_l_addu 0x2398 #define _operation_l_subs 0x3399 #define _operation_l_and 0x4400 #define _operation_l_or 0x5401 #define _operation_l_xor 0x6402 #define _operation_l_cmove 0x7403 #define _operation_l_read_imm 0x8404 #define _operation_l_movhi 0x9405 #define _operation_l_muls 0xa406 #define _operation_l_mulu 0xb407 #define _operation_l_divs 0xc408 #define _operation_l_divu 0xd409 #define _operation_l_exts 0xe410 #define _operation_l_extz 0xf411 #define _operation_l_ff1 0x10412 #define _operation_l_fl1 0x11413 #define _operation_l_sll 0x12414 #define _operation_l_sla 0x13415 #define _operation_l_srl 0x14416 #define _operation_l_ror 0x15417 #define _operation_l_cmp_eq 0x16418 #define _operation_l_cmp_ne 0x17419 #define _operation_l_cmp_ges 0x18420 #define _operation_l_cmp_geu 0x19421 #define _operation_l_cmp_gts 0x1a422 #define _operation_l_cmp_gtu 0x1b423 #define _operation_l_cmp_les 0x1c424 #define _operation_l_cmp_leu 0x1d425 #define _operation_l_cmp_lts 0x1e426 #define _operation_l_cmp_ltu 0x1f427 867 428 868 //--------------------------------------------------[ destination ]----- … … 466 906 #define mask_CONDITION_STACK 0x8 // Branch with pop in stack pointer 467 907 468 //-------------------------------------------------[ branch_state ]-----469 #define cst_BRANCH_STATE_NONE 0x0 // 0 0470 #define cst_BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal471 #define cst_BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0472 #define cst_BRANCH_STATE_SPEC_TAKE 0x3 // 1 1473 908 */ 474 909 … … 620 1055 621 1056 /* 622 //----------------------------------------------------623 // Code Operation (before decode)624 //----------------------------------------------------625 626 // Codop - [31:26] Instructions with immediat627 #define OPCOD_L_J 0x00 // 000_000628 #define OPCOD_L_JAL 0x01 // 000_001629 #define OPCOD_L_BNF 0x03 // 000_011630 #define OPCOD_L_BF 0x04 // 000_100631 #define OPCOD_L_RFE 0x09 // 001_001632 #define OPCOD_L_JR 0x11 // 010_001633 #define OPCOD_L_JALR 0x12 // 010_010634 #define OPCOD_L_MACI 0x13 // 010_011635 #define OPCOD_L_CUST1 0x1c // 011_100636 #define OPCOD_L_CUST2 0x1d // 011_101637 #define OPCOD_L_CUST3 0x1e // 011_110638 #define OPCOD_L_CUST4 0x1f // 011_111639 #define OPCOD_L_CUST5 0x3c // 111_100640 #define OPCOD_L_CUST6 0x3d // 111_101641 #define OPCOD_L_CUST7 0x3e // 111_110642 #define OPCOD_L_CUST8 0x3f // 111_111643 #define OPCOD_L_LD 0x20 // 100_000644 #define OPCOD_L_LWZ 0x21 // 100_001645 #define OPCOD_L_LWS 0x22 // 100_010646 #define OPCOD_L_LBZ 0x23 // 100_011647 #define OPCOD_L_LBS 0x24 // 100_100648 #define OPCOD_L_LHZ 0x25 // 100_101649 #define OPCOD_L_LHS 0x26 // 100_110650 #define OPCOD_L_ADDI 0x27 // 100_111651 #define OPCOD_L_ADDIC 0x28 // 101_000652 #define OPCOD_L_ANDI 0x29 // 101_001653 #define OPCOD_L_ORI 0x2a // 101_010654 #define OPCOD_L_XORI 0x2b // 101_011655 #define OPCOD_L_MULI 0x2c // 101_100656 #define OPCOD_L_MFSPR 0x2d // 101_101657 #define OPCOD_L_MTSPR 0x30 // 110_000658 #define OPCOD_L_SD 0x32 // 110_010659 #define OPCOD_L_SW 0x35 // 110_101660 #define OPCOD_L_SB 0x36 // 110_110661 #define OPCOD_L_SH 0x37 // 110_111662 663 #define OPCOD_INST_LV 0x0a // 001_010 // Instruction ORVDX64664 #define OPCOD_INST_LF 0x33 // 110_011 // Instruction ORFPX32/64665 666 #define OPCOD_SPECIAL 0x38 // 111_000 // Instructions Register-Register667 #define OPCOD_SPECIAL_1 0x39 // 111_001 // Instructions "set flag" with register668 #define OPCOD_SPECIAL_2 0x2f // 101_111 // Instructions "set flag" with immediat669 #define OPCOD_SPECIAL_6 0x2e // 101_110 // Instruction Shift/Rotate with immediat670 #define OPCOD_SPECIAL_7 0x31 // 110_001 // Instructions multiply with HI-LO671 #define OPCOD_SPECIAL_8 0x06 // 000_110 // Instructions acces at HI-LO672 673 // OPCOD_SPECIAL instructions - [9:8] [3:0] Instructions Register-Register674 #define OPCOD_L_ADD 0x00 // 00_0000675 #define OPCOD_L_ADDC 0x01 // 00_0001676 #define OPCOD_L_SUB 0x02 // 00_0010677 #define OPCOD_L_AND 0x03 // 00_0011678 #define OPCOD_L_OR 0x04 // 00_0100679 #define OPCOD_L_XOR 0x05 // 00_0101680 #define OPCOD_L_CMOV 0x0e // 00_1110681 #define OPCOD_L_FF1 0x0f // 00_1111682 #define OPCOD_L_FL1 0x1f // 01_1111683 #define OPCOD_L_MUL 0x36 // 11_0110684 #define OPCOD_L_DIV 0x39 // 11_1001685 #define OPCOD_L_DIVU 0x3a // 11_1010686 #define OPCOD_L_MULU 0x3b // 11_1011687 688 #define OPCOD_SPECIAL_3 0xc // 1100 // Instructions extend689 #define OPCOD_SPECIAL_4 0xd // 1101 // Instructions extend (64b)690 #define OPCOD_SPECIAL_5 0x8 // 1000 // Instruction Shift/Rotate with register691 692 // OPCOD_SPECIAL_1 instructions - [25:21] Instructions "set flag" with register693 #define OPCOD_L_SFEQ 0x00 // 00000694 #define OPCOD_L_SFNE 0x01 // 00001695 #define OPCOD_L_SFGTU 0x02 // 00010696 #define OPCOD_L_SFGEU 0x03 // 00011697 #define OPCOD_L_SFLTU 0x04 // 00100698 #define OPCOD_L_SFLEU 0x05 // 00101699 #define OPCOD_L_SFGTS 0x0a // 01010700 #define OPCOD_L_SFGES 0x0b // 01011701 #define OPCOD_L_SFLTS 0x0c // 01100702 #define OPCOD_L_SFLES 0x0d // 01101703 704 // OPCOD_SPECIAL_2 instructions - [25:21] Instructions "set flag" with immediat705 #define OPCOD_L_SFEQI 0x00 // 00000706 #define OPCOD_L_SFNEI 0x01 // 00001707 #define OPCOD_L_SFGTUI 0x02 // 00010708 #define OPCOD_L_SFGEUI 0x03 // 00011709 #define OPCOD_L_SFLTUI 0x04 // 00100710 #define OPCOD_L_SFLEUI 0x05 // 00101711 #define OPCOD_L_SFGTSI 0x0a // 01010712 #define OPCOD_L_SFGESI 0x0b // 01011713 #define OPCOD_L_SFLTSI 0x0c // 01100714 #define OPCOD_L_SFLESI 0x0d // 01101715 716 // OPCOD_SPECIAL_3 instructions - [9:6] Instructions extend717 #define OPCOD_L_EXTHS 0x0 // 0000718 #define OPCOD_L_EXTHZ 0x2 // 0010719 #define OPCOD_L_EXTBS 0x1 // 0001720 #define OPCOD_L_EXTBZ 0x3 // 0011721 722 // OPCOD_SPECIAL_4 instructions - [9:6] Instructions extend (64b)723 #define OPCOD_L_EXTWS 0x0 // 0000724 #define OPCOD_L_EXTWZ 0x1 // 0001725 726 // OPCOD_SPECIAL_5 instructions - [7:6] Instruction Shift/Rotate with register727 #define OPCOD_L_SLL 0x0 // 00728 #define OPCOD_L_SRL 0x1 // 01729 #define OPCOD_L_SRA 0x2 // 10730 #define OPCOD_L_ROR 0x3 // 11731 732 // OPCOD_SPECIAL_6 instructions - [7:6] Instruction Shift/Rotate with immediat733 #define OPCOD_L_SLLI 0x0 // 00734 #define OPCOD_L_SRLI 0x1 // 01735 #define OPCOD_L_SRAI 0x2 // 10736 #define OPCOD_L_RORI 0x3 // 11737 738 // OPCOD_SPECIAL_7 instructions - [3:0] Instructions multiply with HI-LO739 #define OPCOD_L_MAC 0x1 // 0001740 #define OPCOD_L_MSB 0x2 // 0010741 742 // OPCOD_SPECIAL_8 instructions - [17] Instructions acces at HI-LO743 #define OPCOD_L_MOVHI 0x0 // 0744 #define OPCOD_L_MACRC 0x1 // 1745 746 // Particular case Instructions systems747 #define OPCOD_L_MSYNC 0x22000000748 #define OPCOD_L_CSYNC 0x23000000749 #define OPCOD_L_PSYNC 0x22800000750 #define OPCOD_L_NOP 0x1500751 #define OPCOD_L_SYS 0x2000752 #define OPCOD_L_TRAP 0x2100753 754 //----------------------------------------------------755 // Code Operation (after decode)756 //----------------------------------------------------757 758 typedef enum759 {760 // ##### WARNING : This opcode must be the first#####761 INST_L_NO_IMPLEMENTED , // Operation is not implemented762 763 INST_L_ADD , // L.ADD , L.ADDI , L.ADDC , L.ADDIC764 INST_L_AND , // L.AND , L.ANDI765 INST_L_OR , // L.OR , L.ORI766 INST_L_XOR , // L.XOR , L.XORI767 INST_L_CMOV , // L.CMOV768 INST_L_SUB , // L.SUB769 INST_L_FF1 , // L.FF1770 INST_L_EXTBS , // L.EXTBS771 INST_L_EXTBZ , // L.EXTBZ772 INST_L_EXTHS , // L.EXTHS773 INST_L_EXTHZ , // L.EXTHZ774 INST_L_EXTWS , // L.EXTWS775 INST_L_EXTWZ , // L.EXTWZ776 INST_L_e , //777 INST_L_f , //778 INST_L_MUL , // L.MUL , L.MULI779 INST_L_MULU , // L.MULU780 INST_L_DIV , // L.DIV781 INST_L_DIVU , // L.DIVU782 INST_L_SLL , // L.SLL , L.SLLI783 INST_L_SRL , // L.SRL , L.SRLI784 INST_L_SRA , // L.SRA , L.SRAI785 INST_L_ROR , // L.ROR , L.RORI786 INST_L_SFGES , // L.SFGES , L.SFGESI787 INST_L_SFGEU , // L.SFGEU , L.SFGEUI788 INST_L_SFGTS , // L.SFGTS , L.SFGTSI789 INST_L_SFGTU , // L.SFGTU , L.SFGTUI790 INST_L_SFLES , // L.SFLES , L.SFLESI791 INST_L_SFLEU , // L.SFLEU , L.SFLEUI792 INST_L_SFLTS , // L.SFLTS , L.SFLTSI793 INST_L_SFLTU , // L.SFLTU , L.SFLTUI794 INST_L_SFEQ , // L.SFEQ , L.SFEQI795 INST_L_SFNE , // L.SFNE , L.SFNEI796 INST_L_READ , // L.BNF , L.BF , L.JR797 INST_L_MOVHI , // L.MOVI798 INST_L_CSYNC , // L.CSYNC799 INST_L_MSYNC , // L.MSYNC800 INST_L_PSYNC , // L.PSYNC801 INST_L_RFE , // L.RFE802 INST_L_MAC , // L.MAC , L.MACI803 INST_L_MSB , // L.MSB804 INST_L_MACRC , // L.MACRC805 INST_L_2b , //806 INST_L_MEMB , // L.LBS , L.LBZ , L.SB807 INST_L_MEMH , // L.LHS , L.LHZ , L.SH808 INST_L_MEMW , // L.LWS , L.LWZ , L.SW809 INST_L_MEMD , // L.LD , L.SD810 INST_L_CUST1 , // L.CUST1811 INST_L_CUST2 , // L.CUST2812 INST_L_CUST3 , // L.CUST3813 INST_L_CUST4 , // L.CUST4814 INST_L_CUST5 , // L.CUST5815 INST_L_CUST6 , // L.CUST6816 INST_L_CUST7 , // L.CUST7817 INST_L_CUST8 , // L.CUST8818 INST_L_38 , //819 INST_L_39 , //820 INST_L_3a , //821 INST_L_3b , //822 INST_L_3c , //823 INST_L_3d , //824 INST_L_3e , //825 INST_NOP // L.NOP826 } opcod_t;827 828 #define LOG2_NB_INST_L 6829 #define NB_INST_L 64 // +1 -> INST_L_NO_IMPLEMENTED830 //#define NB_INST_L (INST_L_NO_IMPLEMENTED+1)831 1057 */ 832 1058
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