Changeset 84
- Timestamp:
- May 13, 2008, 8:04:50 PM (17 years ago)
- Location:
- trunk
- Files:
-
- 13 edited
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IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg (modified) (1 diff)
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IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp (modified) (7 diffs)
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IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h (modified) (2 diffs)
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IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp (modified) (1 diff)
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IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_statistics_allocation.cpp (modified) (1 diff)
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IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp (modified) (2 diffs)
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IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_statistics_declaration.cpp (modified) (1 diff)
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IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h (modified) (1 diff)
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IPs/systemC/processor/Morpheo/Behavioural/include/Stat.h (modified) (1 diff)
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IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (modified) (1 diff)
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IPs/systemC/processor/Morpheo/Behavioural/src/Stat_create_expr.cpp (modified) (1 diff)
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IPs/systemC/processor/Morpheo/Documentation/Source/Makefile (modified) (2 diffs)
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Makefile.tools (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg
r81 r84 1 1 Address_management 2 2 1 8 *2 # nb_instruction 3 3 2 32*2 # size_address3 30 30 *2 # size_address 4 4 1 4 *4 # size_branch_update_prediction -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
r82 r84 115 115 const int32_t percent_transaction_address = 75; 116 116 const int32_t percent_transaction_predict = 75; 117 const int32_t percent_transaction_event = 10;117 const int32_t percent_transaction_event = 5; 118 118 119 119 SC_START(0); … … 136 136 TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event 137 137 138 Tcontrol_t p_val = false; 139 Tcontrol_t c_val = false; 140 Tcontrol_t n_val = false; 141 142 Tgeneral_data_t p_addr = 0x100; 143 Tgeneral_data_t c_addr = 0x100; 144 Tgeneral_data_t n_addr = 0x100; 138 uint32_t jump = 7 ;// packet 139 uint32_t nb_packet = 1; 140 141 Tcontrol_t c_val = false; 142 Tcontrol_t n_val = false; 143 Tcontrol_t nn_val = false; 144 145 Tgeneral_data_t c_addr = 0x100; 146 Tgeneral_data_t n_addr = 0x100; 147 Tgeneral_data_t nn_addr = 0x100; 148 145 149 Tcontrol_t c_enable [_param->_nb_instruction]; 146 150 Tcontrol_t n_enable [_param->_nb_instruction]; 147 151 148 Tcontrol_t c_is_ds_take = 0; 149 Tinst_ifetch_ptr_t c_ifetch_ptr = 0; 150 Tbranch_state_t c_branch_state = BRANCH_STATE_NONE; 151 Tprediction_ptr_t c_branch_ptr = 0; 152 153 Tcontrol_t n_is_ds_take = 0; 154 Tinst_ifetch_ptr_t n_ifetch_ptr = 0; 155 Tbranch_state_t n_branch_state = BRANCH_STATE_NONE; 156 Tprediction_ptr_t n_branch_ptr = 0; 152 Tcontrol_t c_is_ds_take = 0; 153 Tcontrol_t n_is_ds_take = 0; 154 Tcontrol_t nn_is_ds_take = 0; 157 155 158 156 c_enable [0] = 1; … … 164 162 { 165 163 in_EVENT_VAL ->write(1); 166 in_EVENT_ADDRESS->write( c_addr);164 in_EVENT_ADDRESS->write(n_addr); 167 165 SC_START(1); 168 166 } while (out_EVENT_ACK->read() == false); 169 167 in_EVENT_VAL ->write(0); 170 168 169 n_val = 1; 170 171 171 LABEL("Loop of Test"); 172 172 … … 175 175 LABEL("Iteration %d",iteration); 176 176 177 in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address); 177 // PREDICT 178 { 179 in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); 180 181 SC_START(0); 182 183 Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); 184 185 uint32_t begin = addr%_param->_nb_instruction; 186 uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); 187 Tcontrol_t take = (nb_packet%jump)==0; 188 189 if (take) 190 addr += 0x100; 191 else 192 addr += end-begin+1; 193 194 for (uint32_t i=0; i<_param->_nb_instruction; i++) 195 in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); 196 in_PREDICT_PC_NEXT ->write(addr); 197 in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); 198 in_PREDICT_INST_IFETCH_PTR ->write(0); 199 in_PREDICT_BRANCH_STATE ->write(0); 200 in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); 201 } 202 203 // ADDRESS 204 { 205 in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address); 206 } 207 178 208 in_EVENT_VAL ->write((rand()%100)<percent_transaction_event ); 179 in_EVENT_ADDRESS->write(rand() << 2); 180 181 uint32_t begin = rand() % _param->_nb_instruction; 182 uint32_t end = (begin + (rand() % _param->_nb_instruction)); 183 end = (end > _param->_nb_instruction)?_param->_nb_instruction:end; 184 185 in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); 186 for (uint32_t i=0; i<_param->_nb_instruction; i++) 187 in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); 188 in_PREDICT_PC_NEXT ->write(rand() << 2); 189 in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(rand()%2); 190 in_PREDICT_INST_IFETCH_PTR ->write(begin); 191 in_PREDICT_BRANCH_STATE ->write(c_addr%SIZE_BRANCH_STATE); 192 in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(c_addr%_param->_size_branch_update_prediction); 193 209 in_EVENT_ADDRESS->write(0x100); 210 211 //------------------------------------------------- 194 212 SC_START(0); 195 196 LABEL("---------------------"); 197 LABEL(" * pc-4 : %d %.8x",p_val, p_addr); 198 LABEL(" * pc : %d %.8x",c_val, c_addr); 199 LABEL(" * pc+4 : %d %.8x",n_val, n_addr); 200 LABEL("---------------------"); 213 //------------------------------------------------- 201 214 202 215 if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) … … 204 217 LABEL("PREDICT : Transaction accepted"); 205 218 206 TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),p_addr); 207 TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),c_addr); 208 TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),c_is_ds_take); 219 if (c_val) 220 TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); 221 TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); 222 TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); 223 224 nn_val = true; 225 nn_addr = in_PREDICT_PC_NEXT ->read(); 226 nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); 227 228 for (uint32_t i=0; i<_param->_nb_instruction; i++) 229 n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); 209 230 } 210 231 211 232 if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read()) 212 233 { … … 218 239 TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),c_enable[i]); 219 240 if (_param->_have_port_instruction_ptr) 220 TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(), c_ifetch_ptr);221 TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(), c_branch_state);241 TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0); 242 TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0); 222 243 if (_param->_have_port_branch_update_prediction_id) 223 TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),c_branch_ptr ); 224 225 p_val = true; 226 c_val = n_val; 227 228 p_addr = c_addr; 229 230 if (n_val) 244 TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0); 245 246 c_val = 0; 247 nb_packet ++; 248 } 249 250 251 if (not c_val) 252 { 253 if (n_val and nn_val) 231 254 { 232 c_addr = n_addr; 233 234 c_ifetch_ptr = n_ifetch_ptr ; 235 c_branch_state = n_branch_state; 236 c_branch_ptr = n_branch_ptr ; 237 c_is_ds_take = n_is_ds_take ; 255 c_val = 1; 256 c_addr = n_addr; 257 c_is_ds_take = n_is_ds_take; 238 258 239 259 for (uint32_t i=0; i<_param->_nb_instruction; i++) 240 260 c_enable [i] = n_enable [i]; 261 262 n_val = 1; 263 n_addr = nn_addr; 264 n_is_ds_take = nn_is_ds_take; 265 266 nn_val = 0; 241 267 } 242 243 n_val = false;244 245 LABEL(" * pc-4 : %d %.8x",p_val, p_addr);246 LABEL(" * pc : %d %.8x",c_val, c_addr);247 LABEL(" * pc+4 : %d %.8x",n_val, n_addr);248 }249 250 if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())251 {252 LABEL("PREDICT : Update information");253 254 if (c_val)255 {256 LABEL(" * current is valid -> new next");257 n_val = true;258 259 for (uint32_t i=0; i<_param->_nb_instruction; i++)260 n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read();261 n_addr = in_PREDICT_PC_NEXT ->read();262 n_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read();263 n_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read();264 n_branch_state = in_PREDICT_BRANCH_STATE ->read();265 n_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();266 }267 else268 {269 LABEL(" * current is not valid -> new current");270 c_val = true;271 272 for (uint32_t i=0; i<_param->_nb_instruction; i++)273 c_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read();274 c_addr = in_PREDICT_PC_NEXT ->read();275 c_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read();276 c_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read();277 c_branch_state = in_PREDICT_BRANCH_STATE ->read();278 c_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();279 }280 281 LABEL(" * pc-4 : %d %.8x",p_val, p_addr);282 LABEL(" * pc : %d %.8x",c_val, c_addr);283 LABEL(" * pc+4 : %d %.8x",n_val, n_addr);284 285 268 } 286 269 … … 289 272 LABEL("EVENT : Transaction accepted"); 290 273 291 c_val = true; 292 n_val = false; 293 294 c_addr = in_EVENT_ADDRESS->read(); 295 c_ifetch_ptr = 0; 296 c_branch_state = BRANCH_STATE_NONE; 297 c_branch_ptr = 0; 298 c_is_ds_take = 0; 299 300 c_enable [0] = 1; 274 c_val = false; 275 n_val = true; 276 nn_val = false; 277 278 n_addr = in_EVENT_ADDRESS->read(); 279 n_is_ds_take = 0; 280 281 n_enable [0] = 1; 301 282 for (uint32_t i=1; i<_param->_nb_instruction; i++) 302 c_enable [i] = 0; 303 304 LABEL(" * pc-4 : %d %.8x",p_val, p_addr); 305 LABEL(" * pc : %d %.8x",c_val, c_addr); 306 LABEL(" * pc+4 : %d %.8x",n_val, n_addr); 283 n_enable [i] = 0; 307 284 } 285 286 287 { 288 string str_c_enable = ""; 289 string str_n_enable = ""; 290 291 for (uint32_t i=0; i<_param->_nb_instruction; i++) 292 { 293 str_c_enable += " " + toString(c_enable [i]); 294 str_n_enable += " " + toString(n_enable [i]); 295 } 296 297 LABEL("-----------------------------------"); 298 LABEL(" * nb_packet : %d",nb_packet); 299 LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str()); 300 if (nn_val) 301 { 302 LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str()); 303 } 304 else 305 { 306 LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr ); 307 } 308 LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr); 309 LABEL("-----------------------------------"); 310 } 311 308 312 SC_START(1); 313 309 314 } 310 315 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h
r82 r84 50 50 #ifdef STATISTICS 51 51 public : Stat * _stat; 52 public : counter_t * _stat_nb_transaction_address; 53 public : counter_t * _stat_nb_transaction_predict; 54 public : counter_t * _stat_nb_transaction_event ; 55 public : counter_t * _stat_sum_packet_size ; 52 56 #endif 53 57 … … 91 95 92 96 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 93 private : Tcontrol_t reg_PC_PREVIOUS_VAL; 94 private : Tgeneral_address_t reg_PC_PREVIOUS; 97 private : Tcontrol_t reg_PC_CURRENT_VAL ; 98 private : Tgeneral_address_t reg_PC_CURRENT ; 99 private : Tcontrol_t reg_PC_CURRENT_IS_DS_TAKE ; 100 private : Tcontrol_t * reg_PC_CURRENT_INSTRUCTION_ENABLE ; //[nb_instruction] 101 private : Tinst_ifetch_ptr_t reg_PC_CURRENT_INST_IFETCH_PTR ; 102 private : Tbranch_state_t reg_PC_CURRENT_BRANCH_STATE ; 103 private : Tprediction_ptr_t reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID ; 95 104 96 private : Tcontrol_t reg_PC_ CURRENT_VAL;97 private : Tgeneral_address_t reg_PC_ CURRENT;98 private : Tcontrol_t reg_PC_ CURRENT_IS_DS_TAKE;99 private : Tcontrol_t * reg_PC_ CURRENT_INSTRUCTION_ENABLE; //[nb_instruction]100 private : Tinst_ifetch_ptr_t reg_PC_ CURRENT_INST_IFETCH_PTR;101 private : Tbranch_state_t reg_PC_ CURRENT_BRANCH_STATE;102 private : Tprediction_ptr_t reg_PC_ CURRENT_BRANCH_UPDATE_PREDICTION_ID;105 private : Tcontrol_t reg_PC_NEXT_VAL ; 106 private : Tgeneral_address_t reg_PC_NEXT ; 107 private : Tcontrol_t reg_PC_NEXT_IS_DS_TAKE ; 108 private : Tcontrol_t * reg_PC_NEXT_INSTRUCTION_ENABLE ; //[nb_instruction] 109 private : Tinst_ifetch_ptr_t reg_PC_NEXT_INST_IFETCH_PTR ; 110 private : Tbranch_state_t reg_PC_NEXT_BRANCH_STATE ; 111 private : Tprediction_ptr_t reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID ; 103 112 104 private : Tcontrol_t reg_PC_NEXT_ VAL;105 private : Tgeneral_address_t reg_PC_NEXT ;106 private : Tcontrol_t reg_PC_NEXT_ IS_DS_TAKE;107 private : Tcontrol_t * reg_PC_NEXT_INSTRUCTION_ENABLE ; //[nb_instruction]108 private : Tinst_ifetch_ptr_t reg_PC_NEXT_INST_IFETCH_PTR ;109 private : Tbranch_state_t reg_PC_NEXT_BRANCH_STATE ;110 private : Tprediction_ptr_t reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;113 private : Tcontrol_t reg_PC_NEXT_NEXT_VAL ; 114 private : Tgeneral_address_t reg_PC_NEXT_NEXT ; 115 private : Tcontrol_t reg_PC_NEXT_NEXT_IS_DS_TAKE ; 116 //private : Tcontrol_t * reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE ; //[nb_instruction] 117 //private : Tinst_ifetch_ptr_t reg_PC_NEXT_NEXT_INST_IFETCH_PTR ; 118 //private : Tbranch_state_t reg_PC_NEXT_NEXT_BRANCH_STATE ; 119 //private : Tprediction_ptr_t reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID; 111 120 112 121 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp
r81 r84 45 45 // ========================================= 46 46 47 internal_PREDICT_VAL = reg_PC_PREVIOUS_VAL and not reg_PC_NEXT_VAL;47 internal_PREDICT_VAL = not reg_PC_NEXT_NEXT_VAL; 48 48 49 49 PORT_WRITE(out_PREDICT_VAL ,internal_PREDICT_VAL); 50 PORT_WRITE(out_PREDICT_PC_PREVIOUS ,reg_PC_ PREVIOUS);51 PORT_WRITE(out_PREDICT_PC_CURRENT ,reg_PC_ CURRENT );52 PORT_WRITE(out_PREDICT_PC_CURRENT_IS_DS_TAKE,reg_PC_ CURRENT_IS_DS_TAKE);50 PORT_WRITE(out_PREDICT_PC_PREVIOUS ,reg_PC_CURRENT ); 51 PORT_WRITE(out_PREDICT_PC_CURRENT ,reg_PC_NEXT ); 52 PORT_WRITE(out_PREDICT_PC_CURRENT_IS_DS_TAKE,reg_PC_NEXT_IS_DS_TAKE); 53 53 54 55 56 54 log_printf(FUNC,Address_management,FUNCTION,"End"); 57 55 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_statistics_allocation.cpp
r81 r84 27 27 "Address_management", 28 28 param_statistics); 29 30 _stat_nb_transaction_address = _stat->create_variable("nb_transaction_address"); 31 _stat_nb_transaction_predict = _stat->create_variable("nb_transaction_predict"); 32 _stat_nb_transaction_event = _stat->create_variable("nb_transaction_event" ); 33 _stat_sum_packet_size = _stat->create_variable("sum_packet_size" ); 34 35 _stat->create_expr_average_by_cycle("average_transaction_address", "nb_transaction_address", "", _("Average transaction in Address interface by cycle")); 36 _stat->create_expr_average_by_cycle("average_transaction_predict", "nb_transaction_predict", "", _("Average transaction in Predict interface by cycle")); 37 _stat->create_expr_average_by_cycle("average_transaction_event" , "nb_transaction_event" , "", _("Average transaction in Event interface by cycle" )); 38 _stat->create_expr ("average_packet_size" , "/ sum_packet_size nb_transaction_address", TYPE_COUNTER, "", _("Average of Packet size per request")); 29 39 30 40 log_printf(FUNC,Address_management,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
r82 r84 26 26 if (PORT_READ(in_NRESET) == 0) 27 27 { 28 reg_PC_PREVIOUS_VAL = 0; 29 reg_PC_CURRENT_VAL = 0; 30 reg_PC_NEXT_VAL = 0; 28 // nothing is valid 29 reg_PC_CURRENT_VAL = 0; 30 reg_PC_NEXT_VAL = 0; 31 reg_PC_NEXT_NEXT_VAL = 0; 31 32 } 32 33 else 33 34 { 34 35 // ========================================= 36 // ===== PREDICT =========================== 37 // ========================================= 38 if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL) 39 { 40 for (uint32_t i=0; i<_param->_nb_instruction; i++) 41 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]); 42 if (_param->_have_port_instruction_ptr) 43 reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); 44 reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); 45 if (_param->_have_port_branch_update_prediction_id) 46 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); 47 48 reg_PC_NEXT_NEXT_VAL = 1; // address is valid 49 reg_PC_NEXT_NEXT = PORT_READ(in_PREDICT_PC_NEXT ); 50 reg_PC_NEXT_NEXT_IS_DS_TAKE = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE ); 51 52 #ifdef STATISTICS 53 (*_stat_nb_transaction_predict) ++; 54 #endif 55 } 56 57 // ========================================= 35 58 // ===== ADDRESS =========================== 36 59 // ========================================= 37 60 // transaction with icache 38 if ( internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK))61 if ( (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) or not reg_PC_CURRENT_VAL) 39 62 { 40 // current pc became previous pc 41 reg_PC_PREVIOUS_VAL = 1; 42 reg_PC_PREVIOUS = reg_PC_CURRENT ; 43 44 // next pc became next pc 45 reg_PC_CURRENT_VAL = reg_PC_NEXT_VAL; // can be not valid 63 #ifdef STATISTICS 64 if (reg_PC_CURRENT_VAL) 65 { 66 (*_stat_nb_transaction_address) ++; 67 68 for (uint32_t i=0; i<_param->_nb_instruction; i++) 69 if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true) 70 (*_stat_sum_packet_size) ++; 71 } 72 #endif 73 74 75 Tcontrol_t pc_next_val = reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL; 76 77 // next pc became current pc 78 reg_PC_CURRENT_VAL = pc_next_val; 46 79 47 80 // if pc_next is not valid : don't erase PC and PC_IS_DS_TAKE : this register is send a the predict (to compute pc_next) 48 if ( reg_PC_NEXT_VAL)81 if (pc_next_val) 49 82 { 50 reg_PC_CURRENT = reg_PC_NEXT ; 51 reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; 83 reg_PC_CURRENT = reg_PC_NEXT ; 84 reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; 85 reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ; 86 reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ; 87 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID; 88 89 for (uint32_t i=0; i<_param->_nb_instruction; i++) 90 reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i]; 91 92 reg_PC_NEXT_VAL = reg_PC_NEXT_NEXT_VAL ; 93 // if pc_next_next is not valid : don't erase PC_NEXT and PC_NEXT_IS_DS_TAKE : this register is send a the predict (to compute pc_next) 94 if (reg_PC_NEXT_NEXT_VAL) 95 { 96 reg_PC_NEXT = reg_PC_NEXT_NEXT ; 97 reg_PC_NEXT_IS_DS_TAKE = reg_PC_NEXT_NEXT_IS_DS_TAKE; 98 } 99 100 // invalid next next pc 101 reg_PC_NEXT_NEXT_VAL = 0; 52 102 } 53 103 54 reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ;55 reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ;56 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;57 58 for (uint32_t i=0; i<_param->_nb_instruction; i++)59 reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];60 61 // have not next pc62 reg_PC_NEXT_VAL = 0;63 104 } 64 105 65 // =========================================66 // ===== PREDICT ===========================67 // =========================================68 bool new_pc_current = not reg_PC_CURRENT_VAL;69 if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)70 if (new_pc_current)71 {72 reg_PC_CURRENT_VAL = 1;73 reg_PC_CURRENT = PORT_READ(in_PREDICT_PC_NEXT );74 reg_PC_CURRENT_IS_DS_TAKE = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE );75 if (_param->_have_port_instruction_ptr)76 reg_PC_CURRENT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR );77 reg_PC_CURRENT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE );78 if (_param->_have_port_branch_update_prediction_id)79 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);80 81 // #error "INSTRUCTION_ENABLE : ERROR implémentation, remplacer PC_PREVIOUS par PC_NEXT_NEXT"82 83 for (uint32_t i=0; i<_param->_nb_instruction; i++)84 reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);85 }86 else87 {88 reg_PC_NEXT_VAL = 1;89 reg_PC_NEXT = PORT_READ(in_PREDICT_PC_NEXT );90 reg_PC_NEXT_IS_DS_TAKE = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE );91 if (_param->_have_port_instruction_ptr)92 reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR );93 reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE );94 if (_param->_have_port_branch_update_prediction_id)95 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);96 97 for (uint32_t i=0; i<_param->_nb_instruction; i++)98 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);99 }100 106 101 107 // ========================================= … … 104 110 if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK) 105 111 { 106 reg_PC_CURRENT_VAL = 1; 107 reg_PC_CURRENT = PORT_READ(in_EVENT_ADDRESS); 112 log_printf(TRACE,Address_management,FUNCTION,"EVENT : Transaction"); 113 reg_PC_CURRENT_VAL = 0; 114 reg_PC_NEXT_VAL = 1; 115 reg_PC_NEXT = PORT_READ(in_EVENT_ADDRESS); 108 116 // Event is never is ds_take : 109 117 // * branch miss speculation : can't be place a branch in delay slot 110 118 // * load miss speculation : the load is execute, the event_address is the next address (also the destination of branch) 111 119 // * exception : goto the first instruction of exception handler (also is not in delay slot). 112 reg_PC_ CURRENT_IS_DS_TAKE = 0;113 reg_PC_CURRENT_INST_IFETCH_PTR = 0;114 reg_PC_CURRENT_BRANCH_STATE = BRANCH_STATE_NONE;115 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = 0;120 reg_PC_NEXT_IS_DS_TAKE = 0; 121 // reg_PC_NEXT_INST_IFETCH_PTR = 0; 122 // reg_PC_NEXT_BRANCH_STATE = BRANCH_STATE_NONE; 123 // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; 116 124 117 reg_PC_CURRENT_INSTRUCTION_ENABLE [0] = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.118 for (uint32_t i=1; i<_param->_nb_instruction; i++)119 reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = 0;125 // reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle. 126 // for (uint32_t i=1; i<_param->_nb_instruction; i++) 127 // reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; 120 128 121 reg_PC_NEXT_VAL = 0; // cancel all prediction (event is send at the predict unit) 129 reg_PC_NEXT_NEXT_VAL = 0; // cancel all prediction (event is send at the predict unit) 130 131 #ifdef STATISTICS 132 (*_stat_nb_transaction_event) ++; 133 #endif 122 134 } 123 135 } 136 137 #if DEBUG >= DEBUG_TRACE 138 log_printf(TRACE,Address_management,FUNCTION,"Address_Management : "); 139 log_printf(TRACE,Address_management,FUNCTION,"Current : %d %d 0x%x",reg_PC_CURRENT_VAL, reg_PC_CURRENT_IS_DS_TAKE, reg_PC_CURRENT); 140 log_printf(TRACE,Address_management,FUNCTION,"Next : %d %d 0x%x",reg_PC_NEXT_VAL, reg_PC_NEXT_IS_DS_TAKE, reg_PC_NEXT); 141 log_printf(TRACE,Address_management,FUNCTION,"Next_Next : %d %d 0x%x",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT); 142 #endif 124 143 125 144 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_statistics_declaration.cpp
r81 r84 24 24 _stat_nb_write = _stat->create_variable("nb_write"); 25 25 26 _stat->create_expr_average_by_cycle("average_read" , "nb_read" , "", "Average read by cycle");27 _stat->create_expr_average_by_cycle("average_write", "nb_write", "", "Average write by cycle");26 _stat->create_expr_average_by_cycle("average_read" , "nb_read" , "", _("Average read by cycle" )); 27 _stat->create_expr_average_by_cycle("average_write", "nb_write", "", _("Average write by cycle")); 28 28 29 _stat->create_expr_percent ("percent_use_read" , "average_read" , toString(_param->_nb_port_read +_param->_nb_port_read_write), "Percent read by cycle");30 _stat->create_expr_percent ("percent_use_write", "average_write", toString(_param->_nb_port_write+_param->_nb_port_read_write), "Percent write by cycle");29 _stat->create_expr_percent ("percent_use_read" , "average_read" , toString(_param->_nb_port_read +_param->_nb_port_read_write), _("Percent read by cycle" )); 30 _stat->create_expr_percent ("percent_use_write", "average_write", toString(_param->_nb_port_write+_param->_nb_port_read_write), _("Percent write by cycle")); 31 31 32 32 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h
r83 r84 41 41 # define DEBUG_Multi_Front_end false 42 42 # define DEBUG_Front_end false 43 # define DEBUG_Context_State true43 # define DEBUG_Context_State false 44 44 # define DEBUG_Decod_unit false 45 45 # define DEBUG_Decod false 46 46 # define DEBUG_Decod_queue false 47 47 # define DEBUG_Ifetch_unit false 48 # define DEBUG_Address_management false48 # define DEBUG_Address_management true 49 49 # define DEBUG_Ifetch_queue false 50 50 # define DEBUG_Ifetch_unit_Glue false -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat.h
r81 r84 81 81 std::string expr, 82 82 bool each_cycle=false); 83 84 public : void create_expr (std::string varname, 85 std::string expr, 86 counter_type_t type, 87 std::string unit, 88 std::string description, 89 bool each_cycle=false); 90 83 91 public : void create_expr_average (std::string varname, 84 92 std::string expr_sum, -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r83 r84 6 6 #define MORPHEO_MAJOR_VERSION 0 7 7 #define MORPHEO_MINOR_VERSION 2 8 #define MORPHEO_REVISION 8 38 #define MORPHEO_REVISION 84 9 9 10 10 // Identification : MORPHEO_MAJOR_VERSION.MORPHEO_MINOR_VERSION.MORPHEO_REVISION -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_create_expr.cpp
r81 r84 20 20 _list_expr->push_back(expression); 21 21 } 22 23 void Stat::create_expr (std::string varname, 24 std::string expr, 25 counter_type_t type, 26 std::string unit, 27 std::string description, 28 bool each_cycle) 29 { 30 if (type = TYPE_COUNTER) 31 create_counter (varname,unit,description); 32 else 33 create_variable(varname); 34 35 create_expr(varname, expr, each_cycle); 36 } 37 22 38 23 39 void Stat::create_expr_average (std::string varname, -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile
r81 r84 291 291 #-------------------------------------------------------------------------------- 292 292 view : doc 293 @ 293 @\ 294 294 declare SELECT_FILE; \ 295 295 declare SELECT_LANG; \ … … 372 372 $(ECHO) "Format selected : $$SELECT_FORMAT"; \ 373 373 $(ECHO) ""; \ 374 \375 \376 374 \ 377 375 $$SELECT_VIEWER "$$SELECT_FILE-$$SELECT_LANG.$$SELECT_FORMAT" & \ -
trunk/Makefile.tools
r82 r84 49 49 GNUPLOT = gnuplot 50 50 # Commands to view the document 51 VIEWDVI = xdvi52 VIEWPS = gv53 VIEWPDF = xpdf54 VIEWPDF_FS = $(VIEWPDF) - fullscreen51 VIEWDVI = evince 52 VIEWPS = evince 53 VIEWPDF = evince 54 VIEWPDF_FS = $(VIEWPDF) -s 55 55 56 56 #----------------------------------------------------------
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