Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src
- Files:
-
- 9 edited
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Load_store_unit.cpp (modified) (6 diffs)
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Load_store_unit_allocation.cpp (modified) (4 diffs)
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Load_store_unit_deallocation.cpp (modified) (3 diffs)
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Load_store_unit_end_cycle.cpp (modified) (2 diffs)
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Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp (modified) (1 diff)
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Load_store_unit_function_speculative_load_commit_genMoore.cpp (modified) (4 diffs)
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Load_store_unit_function_speculative_load_commit_transition.cpp (modified) (11 diffs)
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Parameters.cpp (modified) (2 diffs)
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Parameters_msg_error.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
r82 r88 39 39 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 40 40 41 #if DEBUG_Load_store_unit == true 42 log_printf(INFO,Load_store_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); 43 44 std::cout << *param << std::endl; 45 #endif 46 41 47 #ifdef SYSTEMC 42 48 log_printf(INFO,Load_store_unit,FUNCTION,"Allocation"); … … 46 52 47 53 #ifdef STATISTICS 48 log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics"); 49 50 statistics_declaration(param_statistics); 54 if (usage_is_set(_usage,USE_STATISTICS)) 55 { 56 log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics"); 57 58 statistics_declaration(param_statistics); 59 } 51 60 #endif 52 61 53 62 #ifdef VHDL 54 // generate the vhdl 55 log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl"); 56 57 vhdl(); 58 #endif 59 60 #ifdef SYSTEMC 63 if (usage_is_set(_usage,USE_VHDL)) 64 { 65 // generate the vhdl 66 log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl"); 67 68 vhdl(); 69 } 70 #endif 71 72 #ifdef SYSTEMC 73 if (usage_is_set(_usage,USE_SYSTEMC)) 74 { 61 75 // Function pointer 62 76 … … 84 98 85 99 internal_DCACHE_RSP_ACK = 1; 86 PORT_WRITE(out_DCACHE_RSP_ACK, 1); 100 PORT_WRITE(out_DCACHE_RSP_ACK [0], internal_DCACHE_RSP_ACK); 101 for (uint32_t i=1; i<_param->_nb_cache_port; ++i) 102 { 103 PORT_WRITE(out_DCACHE_RSP_ACK [i], 0); 104 PORT_WRITE(out_DCACHE_REQ_VAL [i], 0); 105 } 106 107 for (uint32_t i=1; i<_param->_nb_inst_memory; i++) 108 { 109 PORT_WRITE(out_MEMORY_OUT_VAL [i], 0); 110 } 87 111 88 112 log_printf(INFO,Load_store_unit,FUNCTION,"Method - transition"); … … 111 135 dont_initialize (); 112 136 sensitive_neg << *(in_CLOCK); 113 sensitive << *(in_MEMORY_IN_OPERATION); 114 115 #ifdef SYSTEMCASS_SPECIFIC 116 // List dependency information 117 (*(out_MEMORY_IN_ACK)) (*(in_MEMORY_IN_OPERATION)); 137 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 138 sensitive << (*(in_MEMORY_IN_VAL [i])) 139 << (*(in_MEMORY_IN_OPERATION [i])); 140 141 #ifdef SYSTEMCASS_SPECIFIC 142 // List dependency information 143 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 144 // for (uint32_t x=0; x<_param->_nb_inst_memory; x++) 145 { 146 (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_VAL [i])); 147 (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_OPERATION [i])); 148 } 118 149 #endif 119 150 … … 137 168 // List dependency information 138 169 #endif 139 170 } 140 171 #endif 141 172 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); … … 149 180 150 181 #ifdef STATISTICS 151 log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file"); 152 153 delete _stat; 182 if (usage_is_set(_usage,USE_STATISTICS)) 183 { 184 log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file"); 185 186 delete _stat; 187 } 154 188 #endif 155 189 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r82 r88 3 3 * $Id$ 4 4 * 5 * [ 5 * [ Description ] 6 6 * 7 7 */ 8 8 9 9 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" 10 #include "Behavioural/include/Allocation.h" 10 11 11 12 namespace morpheo { … … 37 38 _interfaces = entity->set_interfaces(); 38 39 39 // ~~~~~[ 40 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 40 41 { 41 42 Interface * interface = _interfaces->set_interface("" … … 43 44 ,IN 44 45 ,SOUTH, 45 "Generalist interface"46 _("Generalist interface") 46 47 #endif 47 48 ); … … 50 51 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 51 52 } 52 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 53 54 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 53 55 { 54 Interface_fifo * interface = _interfaces->set_interface("memory_in" 55 #ifdef POSITION 56 ,IN 57 ,WEST 58 ,"Instruction from Reservations station" 59 #endif 60 ); 56 ALLOC1_INTERFACE("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory); 61 57 62 in_MEMORY_IN_VAL = interface->set_signal_valack_in (VAL); 63 out_MEMORY_IN_ACK = interface->set_signal_valack_out (ACK); 64 65 if (_param->_have_port_context_id) 66 in_MEMORY_IN_CONTEXT_ID = interface->set_signal_in <Tcontext_t > ("context_id" ,_param->_size_context_id ); 67 if (_param->_have_port_front_end_id) 68 in_MEMORY_IN_FRONT_END_ID = interface->set_signal_in <Tcontext_t > ("front_end_id" ,_param->_size_front_end_id ); 69 if (_param->_have_port_ooo_engine_id) 70 in_MEMORY_IN_OOO_ENGINE_ID = interface->set_signal_in <Tcontext_t > ("ooo_engine_id",_param->_size_ooo_engine_id ); 71 if (_param->_have_port_packet_id) 72 in_MEMORY_IN_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 73 in_MEMORY_IN_OPERATION = interface->set_signal_in <Toperation_t > ("operation" ,_param->_size_operation ); 74 in_MEMORY_IN_TYPE = interface->set_signal_in <Ttype_t > ("type" ,_param->_size_type ); 75 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage 76 if (_param->_have_port_load_queue_ptr) 77 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("load_queue_ptr_write" ,_param->_size_address_load_queue ); 78 in_MEMORY_IN_HAS_IMMEDIAT = interface->set_signal_in <Tcontrol_t > ("has_immediat",1 ); 79 in_MEMORY_IN_IMMEDIAT = interface->set_signal_in <Tgeneral_data_t > ("immediat" ,_param->_size_general_data ); 80 in_MEMORY_IN_DATA_RA = interface->set_signal_in <Tgeneral_data_t > ("data_ra" ,_param->_size_general_data ); 81 in_MEMORY_IN_DATA_RB = interface->set_signal_in <Tgeneral_data_t > ("data_rb" ,_param->_size_general_data ); 82 in_MEMORY_IN_DATA_RC = interface->set_signal_in <Tspecial_data_t > ("data_rc" ,_param->_size_special_data ); 83 in_MEMORY_IN_WRITE_RD = interface->set_signal_in <Tcontrol_t > ("write_rd" ,1 ); 84 in_MEMORY_IN_NUM_REG_RD = interface->set_signal_in <Tgeneral_address_t> ("num_reg_rd" ,1 ); 85 in_MEMORY_IN_WRITE_RE = interface->set_signal_in <Tcontrol_t > ("write_re" ,1 ); 86 in_MEMORY_IN_NUM_REG_RE = interface->set_signal_in <Tspecial_address_t> ("num_reg_re" ,1 ); 58 ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL ,VAL); 59 ALLOC1_VALACK_OUT(out_MEMORY_IN_ACK ,ACK); 60 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 61 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 62 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); 63 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 64 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 65 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 66 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 67 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 68 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 69 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); 70 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data ); 71 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data ); 72 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); 73 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 74 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,1 ); 75 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 76 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,1 ); 87 77 } 88 78 89 // ~~~~~[ 79 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 90 80 { 91 Interface_fifo * interface = _interfaces->set_interface("memory_out" 92 #ifdef POSITION 93 ,OUT 94 ,EAST 95 ,"Instruction to write queue" 96 #endif 97 ); 81 ALLOC1_INTERFACE("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory); 98 82 99 out_MEMORY_OUT_VAL = interface->set_signal_valack_out(VAL); 100 in_MEMORY_OUT_ACK = interface->set_signal_valack_in (ACK); 101 if (_param->_have_port_context_id) 102 out_MEMORY_OUT_CONTEXT_ID = interface->set_signal_out <Tcontext_t > ("context_id" ,_param->_size_context_id ); 103 if (_param->_have_port_front_end_id) 104 out_MEMORY_OUT_FRONT_END_ID = interface->set_signal_out <Tcontext_t > ("front_end_id" ,_param->_size_front_end_id ); 105 if (_param->_have_port_ooo_engine_id) 106 out_MEMORY_OUT_OOO_ENGINE_ID = interface->set_signal_out <Tcontext_t > ("ooo_engine_id" ,_param->_size_ooo_engine_id ); 107 if (_param->_have_port_packet_id) 108 out_MEMORY_OUT_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 109 // out_MEMORY_OUT_OPERATION = interface->set_signal_out <Toperation_t > ("operation" ,_param->_size_operation ); 110 out_MEMORY_OUT_TYPE = interface->set_signal_out <Ttype_t > ("type" ,_param->_size_type ); 111 out_MEMORY_OUT_WRITE_RD = interface->set_signal_out <Tcontrol_t > ("write_rd" ,1 ); 112 out_MEMORY_OUT_NUM_REG_RD = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register ); 113 out_MEMORY_OUT_DATA_RD = interface->set_signal_out <Tgeneral_data_t > ("data_rd" ,_param->_size_general_data ); 114 out_MEMORY_OUT_WRITE_RE = interface->set_signal_out <Tcontrol_t > ("write_re" ,1 ); 115 out_MEMORY_OUT_NUM_REG_RE = interface->set_signal_out <Tspecial_address_t> ("num_reg_re" ,_param->_size_general_register ); 116 out_MEMORY_OUT_DATA_RE = interface->set_signal_out <Tspecial_data_t > ("data_re" ,_param->_size_general_data ); 117 out_MEMORY_OUT_EXCEPTION = interface->set_signal_out <Texception_t > ("exception" ,_param->_size_exception ); 118 out_MEMORY_OUT_NO_SEQUENCE = interface->set_signal_out <Tcontrol_t > ("no_sequence" ,1 ); 119 out_MEMORY_OUT_ADDRESS = interface->set_signal_out <Tgeneral_data_t > ("address" ,_param->_size_general_data ); 83 ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL ,VAL); 84 ALLOC1_VALACK_IN ( in_MEMORY_OUT_ACK ,ACK); 85 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 86 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 87 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OOO_ENGINE_ID,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); 88 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 89 // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 90 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 91 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 92 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); 93 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); 94 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 95 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_general_register ); 96 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_general_data ); 97 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 98 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 99 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); 120 100 } 121 101 122 // ~~~~~[ 102 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 123 103 { 124 Interface_fifo * interface = _interfaces->set_interface("dcache_req" 125 #ifdef POSITION 126 ,OUT 127 ,NORTH 128 ,"Request port to dcache" 129 #endif 130 ); 104 ALLOC1_INTERFACE("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port); 131 105 132 out_DCACHE_REQ_VAL = interface->set_signal_valack_out(VAL); 133 in_DCACHE_REQ_ACK = interface->set_signal_valack_in (ACK); 134 if (_param->_have_port_dcache_context_id) 135 out_DCACHE_REQ_CONTEXT_ID = interface->set_signal_out <Tcontext_t > ("context_id",_param->_size_dcache_context_id ); 136 out_DCACHE_REQ_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_dcache_packet_id ); 137 out_DCACHE_REQ_ADDRESS = interface->set_signal_out <Tdcache_address_t > ("address" ,_param->_size_general_data); 138 out_DCACHE_REQ_TYPE = interface->set_signal_out <Tdcache_type_t > ("type" ,_param->_size_dcache_type ); 139 out_DCACHE_REQ_WDATA = interface->set_signal_out <Tdcache_data_t > ("wdata" ,_param->_size_general_data); 106 ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); 107 ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,ACK); 108 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); 109 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); 110 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t,_param->_size_general_data); 111 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type ); 112 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data); 140 113 } 141 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 114 115 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 142 116 { 143 Interface_fifo * interface = _interfaces->set_interface("dcache_rsp" 144 #ifdef POSITION 145 ,IN 146 ,NORTH 147 ,"Respons port from dcache" 148 #endif 149 ); 117 ALLOC1_INTERFACE("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port); 150 118 151 in_DCACHE_RSP_VAL = interface->set_signal_valack_in (VAL); 152 out_DCACHE_RSP_ACK = interface->set_signal_valack_out(ACK); 153 if (_param->_have_port_dcache_context_id) 154 in_DCACHE_RSP_CONTEXT_ID = interface->set_signal_in <Tcontext_t > ("context_id",_param->_size_dcache_context_id ); 155 in_DCACHE_RSP_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_dcache_packet_id ); 156 in_DCACHE_RSP_RDATA = interface->set_signal_in <Tdcache_data_t > ("rdata" ,_param->_size_general_data); 157 in_DCACHE_RSP_ERROR = interface->set_signal_in <Tdcache_error_t> ("error" ,_param->_size_dcache_error); 119 ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); 120 ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,ACK); 121 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); 122 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); 123 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data); 124 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error); 158 125 } 159 // ~~~~~[ 126 // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 160 127 161 // if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS) 162 { 163 out_BYPASS_MEMORY_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_bypass_memory]; 164 if (_param->_have_port_ooo_engine_id) 165 out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t ) * [_param->_nb_bypass_memory]; 166 out_BYPASS_MEMORY_NUM_REG = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory]; 167 out_BYPASS_MEMORY_DATA = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_bypass_memory]; 168 169 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 170 { 171 Interface_fifo * interface = _interfaces->set_interface("memory_out" 172 #ifdef POSITION 173 ,OUT 174 ,NORTH 175 ,"Bypass between the load queue and the reservation station" 176 #endif 177 ); 128 { 129 ALLOC1_INTERFACE("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory); 178 130 179 out_BYPASS_MEMORY_VAL [i] = interface->set_signal_valack_out(VAL); 180 if (_param->_have_port_ooo_engine_id) 181 out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = interface->set_signal_out <Tcontext_t > ("ooo_engine_id", _param->_size_ooo_engine_id); 182 out_BYPASS_MEMORY_NUM_REG [i] = interface->set_signal_out <Tgeneral_address_t> ("num_reg" , _param->_size_general_register); 183 out_BYPASS_MEMORY_DATA [i] = interface->set_signal_out <Tgeneral_data_t > ("data" , _param->_size_general_data); 184 } 185 } 186 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 131 ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL ,VAL); 132 ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t , _param->_size_ooo_engine_id ); 133 ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t, _param->_size_general_register); 134 ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t , _param->_size_general_data ); 135 } 136 137 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 138 139 // internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port]; 140 141 // internal_MEMORY_IN_ACK = new Tcontrol_t [_param->_nb_inst_memory]; 142 // internal_MEMORY_OUT_VAL = new Tcontrol_t [_param->_nb_inst_memory]; 143 // internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory]; 144 // internal_MEMORY_OUT_PTR = new Tlsq_ptr_t [_param->_nb_inst_memory]; 145 146 // internal_DCACHE_RSP_ACK = new Tcontrol_t [_param->_nb_cache_port]; 147 // internal_DCACHE_REQ_VAL = new Tcontrol_t [_param->_nb_cache_port]; 148 // internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port]; 149 150 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 187 151 188 152 #ifdef POSITION 189 _component->generate_file(); 153 if (usage_is_set(_usage,USE_POSITION)) 154 _component->generate_file(); 190 155 #endif 191 156 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r81 r88 6 6 * $Id$ 7 7 * 8 * [ 8 * [ Description ] 9 9 * 10 10 */ 11 11 12 12 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" 13 #include "Behavioural/include/Allocation.h" 13 14 14 15 namespace morpheo { … … 28 29 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 29 30 31 if (usage_is_set(_usage,USE_SYSTEMC)) 32 { 30 33 //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) 31 34 delete in_CLOCK ; … … 33 36 delete in_NRESET; 34 37 35 delete in_MEMORY_IN_VAL ; 36 delete out_MEMORY_IN_ACK ; 37 if (_param->_have_port_context_id) 38 delete in_MEMORY_IN_CONTEXT_ID ; 39 if (_param->_have_port_front_end_id) 40 delete in_MEMORY_IN_FRONT_END_ID ; 41 if (_param->_have_port_ooo_engine_id) 42 delete in_MEMORY_IN_OOO_ENGINE_ID ; 43 if (_param->_have_port_packet_id) 44 delete in_MEMORY_IN_PACKET_ID ; 45 delete in_MEMORY_IN_OPERATION ; 46 delete in_MEMORY_IN_TYPE ; 47 delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 48 if (_param->_have_port_load_queue_ptr) 49 delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 50 delete in_MEMORY_IN_HAS_IMMEDIAT; 51 delete in_MEMORY_IN_IMMEDIAT ; 52 delete in_MEMORY_IN_DATA_RA ; 53 delete in_MEMORY_IN_DATA_RB ; 54 delete in_MEMORY_IN_DATA_RC ; 55 delete in_MEMORY_IN_WRITE_RD ; 56 delete in_MEMORY_IN_NUM_REG_RD ; 57 delete in_MEMORY_IN_WRITE_RE ; 58 delete in_MEMORY_IN_NUM_REG_RE ; 38 DELETE1_SIGNAL( in_MEMORY_IN_VAL ,_param->_nb_inst_memory,1); 39 DELETE1_SIGNAL(out_MEMORY_IN_ACK ,_param->_nb_inst_memory,1); 40 DELETE1_SIGNAL( in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory,_param->_size_context_id ); 41 DELETE1_SIGNAL( in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory,_param->_size_front_end_id ); 42 DELETE1_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory,_param->_size_ooo_engine_id ); 43 DELETE1_SIGNAL( in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory,_param->_size_rob_ptr ); 44 DELETE1_SIGNAL( in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory,_param->_size_operation ); 45 DELETE1_SIGNAL( in_MEMORY_IN_TYPE ,_param->_nb_inst_memory,_param->_size_type ); 46 DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory,_param->_size_store_queue_ptr ); 47 DELETE1_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory,_param->_size_load_queue_ptr ); 48 DELETE1_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory,1 ); 49 DELETE1_SIGNAL( in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory,_param->_size_general_data ); 50 DELETE1_SIGNAL( in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory,_param->_size_general_data ); 51 DELETE1_SIGNAL( in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory,_param->_size_general_data ); 52 DELETE1_SIGNAL( in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory,_param->_size_special_data ); 53 DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory,1 ); 54 DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory,1 ); 55 DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory,1 ); 56 DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory,1 ); 57 58 DELETE1_SIGNAL(out_MEMORY_OUT_VAL ,_param->_nb_inst_memory,1); 59 DELETE1_SIGNAL( in_MEMORY_OUT_ACK ,_param->_nb_inst_memory,1); 60 DELETE1_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory,_param->_size_context_id ); 61 DELETE1_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory,_param->_size_front_end_id ); 62 DELETE1_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory,_param->_size_ooo_engine_id ); 63 DELETE1_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory,_param->_size_rob_ptr ); 64 // DELETE1_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory,_param->_size_operation ); 65 DELETE1_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory,_param->_size_type ); 66 DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory,1 ); 67 DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory,_param->_size_general_register ); 68 DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory,_param->_size_general_data ); 69 DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory,1 ); 70 DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory,_param->_size_general_register ); 71 DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory,_param->_size_general_data ); 72 DELETE1_SIGNAL(out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory,_param->_size_exception ); 73 DELETE1_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory,1 ); 74 DELETE1_SIGNAL(out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory,_param->_size_general_data ); 75 76 DELETE1_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_cache_port,1); 77 DELETE1_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_cache_port,1); 78 DELETE1_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id ); 79 DELETE1_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port,_param->_size_dcache_packet_id ); 80 DELETE1_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port,_param->_size_general_data); 81 DELETE1_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_cache_port,_param->_size_dcache_type ); 82 DELETE1_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_cache_port,_param->_size_general_data); 83 84 DELETE1_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_cache_port,1); 85 DELETE1_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_cache_port,1); 86 DELETE1_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id ); 87 DELETE1_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port,_param->_size_dcache_packet_id ); 88 DELETE1_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_cache_port,_param->_size_general_data); 89 DELETE1_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_cache_port,_param->_size_dcache_error); 90 91 DELETE1_SIGNAL(out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory,1); 92 DELETE1_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory,_param->_size_ooo_engine_id ); 93 DELETE1_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory,_param->_size_general_register); 94 DELETE1_SIGNAL(out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory,_param->_size_general_data ); 95 96 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 97 60 delete out_MEMORY_OUT_VAL ; 61 delete in_MEMORY_OUT_ACK ; 62 if (_param->_have_port_context_id) 63 delete out_MEMORY_OUT_CONTEXT_ID; 64 if (_param->_have_port_front_end_id) 65 delete out_MEMORY_OUT_FRONT_END_ID; 66 if (_param->_have_port_ooo_engine_id) 67 delete out_MEMORY_OUT_OOO_ENGINE_ID; 68 if (_param->_have_port_packet_id) 69 delete out_MEMORY_OUT_PACKET_ID ; 70 // delete out_MEMORY_OUT_OPERATION ; 71 delete out_MEMORY_OUT_TYPE ; 72 delete out_MEMORY_OUT_WRITE_RD ; 73 delete out_MEMORY_OUT_NUM_REG_RD; 74 delete out_MEMORY_OUT_DATA_RD ; 75 delete out_MEMORY_OUT_WRITE_RE ; 76 delete out_MEMORY_OUT_NUM_REG_RE; 77 delete out_MEMORY_OUT_DATA_RE ; 78 delete out_MEMORY_OUT_EXCEPTION ; 79 delete out_MEMORY_OUT_NO_SEQUENCE; 80 delete out_MEMORY_OUT_ADDRESS ; 98 // delete [] internal_MEMORY_IN_ACK ; 99 // delete [] internal_MEMORY_OUT_VAL ; 100 // delete [] internal_MEMORY_OUT_SELECT_QUEUE; 101 // delete [] internal_MEMORY_OUT_PTR ; 81 102 82 delete out_DCACHE_REQ_VAL ; 83 delete in_DCACHE_REQ_ACK ; 84 if (_param->_have_port_dcache_context_id) 85 delete out_DCACHE_REQ_CONTEXT_ID; 86 delete out_DCACHE_REQ_PACKET_ID ; 87 delete out_DCACHE_REQ_ADDRESS ; 88 delete out_DCACHE_REQ_TYPE ; 89 delete out_DCACHE_REQ_WDATA ; 90 91 delete in_DCACHE_RSP_VAL ; 92 delete out_DCACHE_RSP_ACK ; 93 if (_param->_have_port_dcache_context_id) 94 delete in_DCACHE_RSP_CONTEXT_ID; 95 delete in_DCACHE_RSP_PACKET_ID ; 96 delete in_DCACHE_RSP_RDATA ; 97 delete in_DCACHE_RSP_ERROR ; 98 99 delete [] out_BYPASS_MEMORY_VAL ; 100 if (_param->_have_port_ooo_engine_id) 101 delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; 102 delete [] out_BYPASS_MEMORY_NUM_REG ; 103 delete [] out_BYPASS_MEMORY_DATA ; 104 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 103 // delete [] internal_DCACHE_RSP_ACK ; 104 // delete [] internal_DCACHE_REQ_VAL ; 105 // delete [] internal_DCACHE_REQ_SELECT_QUEUE; 106 107 // delete [] internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ; 108 } 109 110 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 105 111 106 112 delete _component; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp
r81 r88 26 26 27 27 #ifdef STATISTICS 28 _stat->end_cycle(); 28 if (usage_is_set(_usage,USE_STATISTICS)) 29 _stat->end_cycle(); 29 30 #endif 30 31 … … 32 33 // Evaluation before read the ouput signal 33 34 // sc_start(0); 34 _interfaces->testbench(); 35 if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) 36 _interfaces->testbench(); 35 37 #endif 36 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
r81 r88 27 27 28 28 // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 30 // Initialisation 31 internal_MEMORY_IN_PORT = 0; 32 Tcontrol_t ack [_param->_nb_inst_memory]; 33 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 34 ack [i] = 0; 29 35 36 // find first valid entry 30 37 // store queue is never full (pointer is manage by rename stage) 31 internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION)) or not _speculative_access_queue_control->full(); 38 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 39 if (PORT_READ(in_MEMORY_IN_VAL [i])) 40 { 41 internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION [i])) or not _speculative_access_queue_control->full(); 32 42 33 PORT_WRITE(out_MEMORY_IN_ACK, internal_MEMORY_IN_ACK); 43 if (internal_MEMORY_IN_ACK) 44 { 45 ack [i] = 1; 46 internal_MEMORY_IN_PORT = i; 47 break; // end 48 } 49 } 50 51 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 52 PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]); 34 53 35 54 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r81 r88 4 4 * $Id$ 5 5 * 6 * [ 6 * [ Description ] 7 7 * 8 8 */ … … 26 26 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 27 27 28 // ~~~~~[ 28 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 29 30 30 Tcontext_t memory_out_context_id = 0; … … 110 110 } 111 111 // write output 112 PORT_WRITE(out_MEMORY_OUT_VAL , internal_MEMORY_OUT_VAL);112 PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL); 113 113 114 114 if (_param->_have_port_context_id) 115 PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID , memory_out_context_id );115 PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID [0], memory_out_context_id ); 116 116 if (_param->_have_port_front_end_id) 117 PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID , memory_out_front_end_id );117 PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id ); 118 118 if (_param->_have_port_ooo_engine_id) 119 PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID, memory_out_ooo_engine_id); 120 if (_param->_have_port_packet_id) 121 PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id ); 122 // PORT_WRITE(out_MEMORY_OUT_OPERATION , memory_out_operation ); 123 PORT_WRITE(out_MEMORY_OUT_TYPE , TYPE_MEMORY ); 124 PORT_WRITE(out_MEMORY_OUT_WRITE_RD , memory_out_write_rd ); 125 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD , memory_out_num_reg_rd ); 126 PORT_WRITE(out_MEMORY_OUT_DATA_RD , memory_out_data_rd ); 127 // PORT_WRITE(out_MEMORY_OUT_WRITE_RE , memory_out_write_re ); 128 // PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE , memory_out_num_reg_re ); 129 // PORT_WRITE(out_MEMORY_OUT_DATA_RE , memory_out_data_re ); 130 PORT_WRITE(out_MEMORY_OUT_WRITE_RE , 0); 131 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE , 0); 132 PORT_WRITE(out_MEMORY_OUT_DATA_RE , 0); 133 PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception ); 134 PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE , 0); 135 PORT_WRITE(out_MEMORY_OUT_ADDRESS , 0); 136 // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 119 PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id); 120 if (_param->_have_port_rob_ptr) 121 PORT_WRITE(out_MEMORY_OUT_PACKET_ID [0], memory_out_packet_id ); 122 // PORT_WRITE(out_MEMORY_OUT_OPERATION [0], memory_out_operation ); 123 PORT_WRITE(out_MEMORY_OUT_TYPE [0], TYPE_MEMORY ); 124 PORT_WRITE(out_MEMORY_OUT_WRITE_RD [0], memory_out_write_rd ); 125 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD [0], memory_out_num_reg_rd ); 126 PORT_WRITE(out_MEMORY_OUT_DATA_RD [0], memory_out_data_rd ); 127 // PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], memory_out_write_re ); 128 // PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], memory_out_num_reg_re ); 129 // PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], memory_out_data_re ); 130 PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], 0); 131 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], 0); 132 PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], 0); 133 PORT_WRITE(out_MEMORY_OUT_EXCEPTION [0], memory_out_exception ); 134 PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE [0], 0); 135 PORT_WRITE(out_MEMORY_OUT_ADDRESS [0], 0); 136 137 // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 137 138 138 139 Tcontext_t dcache_req_context_id; … … 201 202 } 202 203 203 PORT_WRITE(out_DCACHE_REQ_VAL , internal_DCACHE_REQ_VAL);204 PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL); 204 205 if (_param->_have_port_dcache_context_id) 205 PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID , dcache_req_context_id);206 PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id );207 PORT_WRITE(out_DCACHE_REQ_ADDRESS , dcache_req_address );208 PORT_WRITE(out_DCACHE_REQ_TYPE , dcache_req_type );209 PORT_WRITE(out_DCACHE_REQ_WDATA , dcache_req_wdata );206 PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id); 207 PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id ); 208 PORT_WRITE(out_DCACHE_REQ_ADDRESS [0], dcache_req_address ); 209 PORT_WRITE(out_DCACHE_REQ_TYPE [0], dcache_req_type ); 210 PORT_WRITE(out_DCACHE_REQ_WDATA [0], dcache_req_wdata ); 210 211 211 212 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r81 r88 255 255 // Interface "MEMORY_IN" 256 256 //================================================================ 257 258 if ((PORT_READ(in_MEMORY_IN_VAL ) == 1) and257 258 if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and 259 259 ( internal_MEMORY_IN_ACK == 1)) 260 260 { … … 266 266 267 267 #ifdef DEBUG_TEST 268 if (PORT_READ(in_MEMORY_IN_TYPE ) != TYPE_MEMORY)268 if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY) 269 269 throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'"); 270 270 #endif 271 Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION );272 Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT ) +273 PORT_READ(in_MEMORY_IN_DATA_RA ));271 Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]); 272 Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) + 273 PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT])); 274 274 bool exception_alignement = (mask_memory_access(operation) & address) != 0; 275 275 … … 287 287 288 288 // Write pointer is define in rename stage : 289 Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE );289 Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 290 290 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); 291 291 … … 375 375 log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); 376 376 377 _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID );378 _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID );379 _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID );380 _store_queue [index]._packet_id = (not _param->_have_port_ packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID);377 _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); 378 _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); 379 _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); 380 _store_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); 381 381 _store_queue [index]._operation = operation; 382 _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE );382 _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 383 383 _store_queue [index]._address = address; 384 384 385 385 // reordering data 386 _store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB ), memory_size(operation), 0);387 // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD );386 _store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); 387 // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); 388 388 } 389 389 } … … 413 413 // NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits) 414 414 _speculative_access_queue [index]._state = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE; 415 _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID );416 _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID );417 _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID );418 _speculative_access_queue [index]._packet_id = (not _param->_have_port_ packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID);415 _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); 416 _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); 417 _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); 418 _speculative_access_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); 419 419 420 420 _speculative_access_queue [index]._operation = operation; 421 _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE );422 _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE );421 _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 422 _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 423 423 _speculative_access_queue [index]._address = address; 424 424 // NOTE : is operation is a load, then they are a result and must write in the register file 425 425 _speculative_access_queue [index]._write_rd = is_operation_memory_load(operation); 426 _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD );426 _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); 427 427 428 428 _speculative_access_queue [index]._exception = exception; … … 437 437 438 438 if (( internal_MEMORY_OUT_VAL == 1) and 439 (PORT_READ(in_MEMORY_OUT_ACK ) == 1))439 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) 440 440 { 441 441 log_printf(TRACE,Load_store_unit,FUNCTION,"MEMORY_OUT transaction"); … … 495 495 496 496 if (( internal_DCACHE_REQ_VAL == 1) and 497 (PORT_READ(in_DCACHE_REQ_ACK ) == 1))497 (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) 498 498 { 499 499 log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_REQ"); … … 598 598 // Interface "DCACHE_RSP" 599 599 //================================================================ 600 if ((PORT_READ(in_DCACHE_RSP_VAL )== 1) and600 if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and 601 601 ( internal_DCACHE_RSP_ACK == 1)) 602 602 { … … 604 604 605 605 // don't use context_id : because there are one queue for all thread 606 //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID );607 Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID );608 Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA );609 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR );606 //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); 607 Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]); 608 Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA [0]); 609 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); 610 610 611 611 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); … … 662 662 663 663 664 #if DEBUG>=DEBUG_TRACE664 #if defined(DEBUG) and (DEBUG>=DEBUG_TRACE) 665 665 // ***** dump store queue 666 666 std::cout << "Dump STORE_QUEUE :" << std::endl … … 694 694 << _load_queue[j] << std::endl; 695 695 } 696 697 696 #endif 698 697 699 698 #ifdef STATISTICS 700 for (uint32_t i=0; i<_param->_size_store_queue; i++) 701 if (_store_queue[i]._state != STORE_QUEUE_EMPTY) 702 (*_stat_use_store_queue) ++; 703 for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) 704 if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) 705 (*_stat_use_speculative_access_queue) ++; 706 for (uint32_t i=0; i<_param->_size_load_queue; i++) 707 if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) 708 (*_stat_use_load_queue) ++; 699 if (usage_is_set(_usage,USE_STATISTICS)) 700 { 701 for (uint32_t i=0; i<_param->_size_store_queue; i++) 702 if (_store_queue[i]._state != STORE_QUEUE_EMPTY) 703 (*_stat_use_store_queue) ++; 704 for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) 705 if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) 706 (*_stat_use_speculative_access_queue) ++; 707 for (uint32_t i=0; i<_param->_size_load_queue; i++) 708 if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) 709 (*_stat_use_load_queue) ++; 710 } 709 711 #endif 710 712 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
r81 r88 26 26 Tspeculative_load_t speculative_load , 27 27 uint32_t nb_bypass_memory , 28 uint32_t nb_cache_port , 29 uint32_t nb_inst_memory , 28 30 uint32_t nb_context , 29 31 uint32_t nb_front_end , … … 33 35 uint32_t size_special_data , 34 36 uint32_t nb_general_register , 35 uint32_t nb_special_register ): 36 _size_store_queue (size_store_queue ), 37 _size_load_queue (size_load_queue ), 38 _size_speculative_access_queue (size_speculative_access_queue), 39 _nb_port_check (nb_port_check ), 40 _speculative_load (speculative_load ), 41 _nb_bypass_memory (nb_bypass_memory ), 42 _nb_context (nb_context ), 43 _nb_front_end (nb_front_end ), 44 _nb_ooo_engine (nb_ooo_engine ), 45 _nb_packet (nb_packet ), 46 _size_general_data (size_general_data ), 47 _size_special_data (size_special_data ), 48 _nb_general_register (nb_general_register ), 49 _nb_special_register (nb_special_register ), 50 51 _size_address_store_queue (log2(size_store_queue )), 52 _size_address_load_queue (log2(size_load_queue )), 53 _size_address_speculative_access_queue (log2(size_speculative_access_queue)), 54 55 _size_context_id (log2(nb_context )), 56 _size_front_end_id (log2(nb_front_end )), 57 _size_ooo_engine_id (log2(nb_ooo_engine )), 58 _size_packet_id (log2(nb_packet )), 59 _size_general_register (log2(nb_general_register)), 60 _size_special_register (log2(nb_special_register)), 61 _size_dcache_context_id (_size_context_id + _size_front_end_id + _size_ooo_engine_id), 62 _size_dcache_packet_id ((log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1), 63 64 _have_port_context_id (_size_context_id >0), 65 _have_port_front_end_id (_size_front_end_id >0), 66 _have_port_ooo_engine_id (_size_ooo_engine_id>0), 67 _have_port_packet_id (_size_packet_id >0), 68 _have_port_dcache_context_id (_size_dcache_context_id>0), 69 _have_port_load_queue_ptr (_size_load_queue>1), 70 71 _mask_address_lsb (gen_mask<Tdcache_address_t>(log2(size_general_data/8))), 72 _mask_address_msb (gen_mask<Tdcache_address_t>(size_general_data) << log2(size_general_data/8)) 37 uint32_t nb_special_register , 38 bool is_toplevel) 73 39 { 74 40 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 41 42 _size_store_queue = size_store_queue ; 43 _size_load_queue = size_load_queue ; 44 _size_speculative_access_queue = size_speculative_access_queue; 45 _nb_port_check = nb_port_check ; 46 _speculative_load = speculative_load ; 47 _nb_bypass_memory = nb_bypass_memory ; 48 _nb_cache_port = nb_cache_port ; 49 _nb_inst_memory = nb_inst_memory ; 50 _nb_context = nb_context ; 51 _nb_front_end = nb_front_end ; 52 _nb_ooo_engine = nb_ooo_engine ; 53 _nb_packet = nb_packet ; 54 _nb_general_register = nb_general_register ; 55 _nb_special_register = nb_special_register ; 56 57 _size_speculative_access_queue_ptr = log2(size_speculative_access_queue); 58 59 _size_dcache_context_id = log2(nb_context) + log2(nb_front_end) + log2(nb_ooo_engine); 60 _size_dcache_packet_id = (log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1; 61 62 _have_port_dcache_context_id = _size_dcache_context_id>0; 63 64 _mask_address_lsb = gen_mask<Tdcache_address_t>(log2(size_general_data/8)); 65 _mask_address_msb = gen_mask<Tdcache_address_t>(size_general_data) << log2(size_general_data/8); 66 75 67 test(); 68 69 if (is_toplevel) 70 { 71 _size_context_id = log2(nb_context ); 72 _size_front_end_id = log2(nb_front_end ); 73 _size_ooo_engine_id = log2(nb_ooo_engine ); 74 _size_rob_ptr = log2(nb_packet ); 75 _size_general_register = log2(nb_general_register); 76 _size_special_register = log2(nb_special_register); 77 _size_store_queue_ptr = log2(size_store_queue ); 78 _size_load_queue_ptr = log2(size_load_queue ); 79 _size_general_data = size_general_data ; 80 _size_special_data = size_special_data ; 81 82 _have_port_context_id = _size_context_id >0; 83 _have_port_front_end_id = _size_front_end_id >0; 84 _have_port_ooo_engine_id = _size_ooo_engine_id >0; 85 _have_port_rob_ptr = _size_rob_ptr >0; 86 _have_port_load_queue_ptr = _size_load_queue_ptr>0; 87 88 copy(); 89 } 90 76 91 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 77 92 }; 78 93 94 // #undef FUNCTION 95 // #define FUNCTION "Load_store_unit::Parameters (copy)" 96 // Parameters::Parameters (Parameters & param): 97 // _size_store_queue (param._size_store_queue ), 98 // _size_load_queue (param._size_load_queue ), 99 // _size_speculative_access_queue (param._size_speculative_access_queue), 100 // _nb_port_check (param._nb_port_check ), 101 // _speculative_load (param._speculative_load ), 102 // _nb_bypass_memory (param._nb_bypass_memory ), 103 // _nb_cache_port (param._nb_cache_port ), 104 // _nb_inst_memory (param._nb_inst_memory ), 105 // _nb_context (param._nb_context ), 106 // _nb_front_end (param._nb_front_end ), 107 // _nb_ooo_engine (param._nb_ooo_engine ), 108 // _nb_packet (param._nb_packet ), 109 // _size_general_data (param._size_general_data ), 110 // _size_special_data (param._size_special_data ), 111 // _nb_general_register (param._nb_general_register ), 112 // _nb_special_register (param._nb_special_register ), 113 114 // _size_address_store_queue (param._size_address_store_queue ), 115 // _size_address_load_queue (param._size_address_load_queue ), 116 // _size_address_speculative_access_queue (param._size_address_speculative_access_queue), 117 118 // _size_context_id (param._size_context_id ), 119 // _size_front_end_id (param._size_front_end_id ), 120 // _size_ooo_engine_id (param._size_ooo_engine_id ), 121 // _size_packet_id (param._size_packet_id ), 122 // _size_general_register (param._size_general_register ), 123 // _size_special_register (param._size_special_register ), 124 // _size_dcache_context_id (param._size_dcache_context_id ), 125 // _size_dcache_packet_id (param._size_dcache_packet_id ), 126 127 // _have_port_context_id (param._have_port_context_id ), 128 // _have_port_front_end_id (param._have_port_front_end_id ), 129 // _have_port_ooo_engine_id (param._have_port_ooo_engine_id), 130 // _have_port_packet_id (param._have_port_packet_id ), 131 // _have_port_dcache_context_id(param._have_port_dcache_context_id), 132 // _have_port_load_queue_ptr(param._have_port_load_queue_ptr), 133 134 // _mask_address_lsb (param._mask_address_lsb), 135 // _mask_address_msb (param._mask_address_msb) 136 // { 137 // log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 138 // test(); 139 // log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 140 // }; 141 79 142 #undef FUNCTION 80 #define FUNCTION "Load_store_unit::Parameters (copy)" 81 Parameters::Parameters (Parameters & param): 82 _size_store_queue (param._size_store_queue ), 83 _size_load_queue (param._size_load_queue ), 84 _size_speculative_access_queue (param._size_speculative_access_queue), 85 _nb_port_check (param._nb_port_check ), 86 _speculative_load (param._speculative_load ), 87 _nb_bypass_memory (param._nb_bypass_memory ), 88 _nb_context (param._nb_context ), 89 _nb_front_end (param._nb_front_end ), 90 _nb_ooo_engine (param._nb_ooo_engine ), 91 _nb_packet (param._nb_packet ), 92 _size_general_data (param._size_general_data ), 93 _size_special_data (param._size_special_data ), 94 _nb_general_register (param._nb_general_register ), 95 _nb_special_register (param._nb_special_register ), 96 97 _size_address_store_queue (param._size_address_store_queue ), 98 _size_address_load_queue (param._size_address_load_queue ), 99 _size_address_speculative_access_queue (param._size_address_speculative_access_queue), 100 101 _size_context_id (param._size_context_id ), 102 _size_front_end_id (param._size_front_end_id ), 103 _size_ooo_engine_id (param._size_ooo_engine_id ), 104 _size_packet_id (param._size_packet_id ), 105 _size_general_register (param._size_general_register ), 106 _size_special_register (param._size_special_register ), 107 _size_dcache_context_id (param._size_dcache_context_id ), 108 _size_dcache_packet_id (param._size_dcache_packet_id ), 109 110 _have_port_context_id (param._have_port_context_id ), 111 _have_port_front_end_id (param._have_port_front_end_id ), 112 _have_port_ooo_engine_id (param._have_port_ooo_engine_id), 113 _have_port_packet_id (param._have_port_packet_id ), 114 _have_port_dcache_context_id(param._have_port_dcache_context_id), 115 _have_port_load_queue_ptr(param._have_port_load_queue_ptr), 116 117 _mask_address_lsb (param._mask_address_lsb), 118 _mask_address_msb (param._mask_address_msb) 143 #define FUNCTION "Load_store_unit::~Parameters" 144 Parameters::~Parameters (void) 119 145 { 120 146 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 121 test();122 147 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 123 148 }; 124 149 125 150 #undef FUNCTION 126 #define FUNCTION "Load_store_unit:: ~Parameters"127 Parameters::~Parameters ()151 #define FUNCTION "Load_store_unit::copy" 152 void Parameters::copy (void) 128 153 { 129 154 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
r81 r88 32 32 { 33 33 if (not (_nb_bypass_memory == 0)) 34 test.error( "Bypass memory is not supported. Please wait a next revision.");34 test.error(_("Bypass memory is not supported. Please wait a next revision.\n")); 35 35 36 36 break; … … 42 42 { 43 43 if (not (_nb_bypass_memory == 0)) 44 test.error( "In the load scheme '"+toString(_speculative_load)+"', they have none bypass.");44 test.error(toString(_("In the load scheme '%s', they have none bypass.\n"),toString(_speculative_load).c_str())); 45 45 46 test.error( "Speculative load scheme '"+toString(_speculative_load)+"' is not supported. Please wait a next revision.");46 test.error(toString(_("Speculative load scheme '%s' is not supported. Please wait a next revision.\n"),toString(_speculative_load).c_str())); 47 47 break; 48 48 } … … 50 50 51 51 if (not (_size_store_queue >= 2)) 52 test.error( "Store queue must have at less two slot.");52 test.error(_("Store queue must have at less two slot.\n")); 53 53 54 54 if (not (_nb_bypass_memory <= _size_load_queue)) 55 test.error("Bypass number must be less than load_queue's size."); 55 test.error(_("Bypass number must be less than load_queue's size.\n")); 56 57 if (_nb_cache_port > 1) 58 test.warning(_("nb_cache_port > 1 is unsupported (Coming Soon).\n")); 59 60 if (_nb_inst_memory > 1) 61 test.warning(_("nb_inst_memory > 1 is unsupported (Coming Soon).\n")); 56 62 57 63 log_printf(FUNC,Load_store_unit,FUNCTION,"End");
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