Ignore:
Timestamp:
Dec 10, 2008, 7:31:39 PM (16 years ago)
Author:
rosiere
Message:

Almost complete design
with Test and test platform

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue
Files:
13 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/Makefile

    r81 r88  
    2424library_clean                   : Ifetch_queue_library_clean
    2525
     26local_clean                     :
     27
    2628include                         $(DIR_COMPONENT)/Makefile.deps
    2729include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/main.cpp

    r81 r88  
    4747         _nb_instruction                ,
    4848         _size_branch_update_prediction ,
    49          _size_general_data             );
     49         _size_general_data             ,
     50         true // is_toplevel
     51         );
    5052     
    5153      msg(_("%s"),param->print(1).c_str());

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp

    r82 r88  
    4141#endif
    4242
     43  Tusage_t _usage = USE_ALL;
     44
     45//   _usage = usage_unset(_usage,USE_SYSTEMC              );
     46//   _usage = usage_unset(_usage,USE_VHDL                 );
     47//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
     48//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
     49//   _usage = usage_unset(_usage,USE_POSITION             );
     50//   _usage = usage_unset(_usage,USE_STATISTICS           );
     51//   _usage = usage_unset(_usage,USE_INFORMATION          );
     52
    4353  Ifetch_queue * _Ifetch_queue = new Ifetch_queue
    4454    (name.c_str(),
    … …  
    4757#endif
    4858     _param,
    49      USE_ALL);
     59     _usage);
    5060 
    5161#ifdef SYSTEMC
    … …  
    93103  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_VAL                        );
    94104  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_ACK                        );
    95   if (_param->_have_port_queue_ptr)
     105  if (_param->_have_port_ifetch_queue_ptr)
    96106  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID            );
    97107  INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
    98108  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS        );
    99   if (_param->_have_port_instruction_ptr)
     109  if (_param->_have_port_inst_ifetch_ptr)
    100110  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR            );
    101111  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_STATE               );
    102   if (_param->_have_port_branch_update_prediction_id)
     112  if (_param->_have_port_depth)
    103113  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
    104114  INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL                          ,_param->_nb_instruction);
    … …  
    106116  INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION                  ,_param->_nb_instruction);
    107117  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_ADDRESS                      );
    108   if (_param->_have_port_instruction_ptr)
     118  if (_param->_have_port_inst_ifetch_ptr)
    109119  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_INST_IFETCH_PTR              );
    110120  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_STATE                 );
    111   if (_param->_have_port_branch_update_prediction_id)
     121  if (_param->_have_port_depth)
    112122  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID  );
    113123  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_EXCEPTION                    );
    114124  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_VAL                     );
    115125  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ICACHE_RSP_ACK                     );
    116   if (_param->_have_port_queue_ptr)
     126  if (_param->_have_port_ifetch_queue_ptr)
    117127  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_PACKET_ID               );
    118128  INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION             ,_param->_nb_instruction);
    … …  
    180190          for (uint32_t i=0; i<_param->_nb_instruction; i++)
    181191          in_ADDRESS_INSTRUCTION_ENABLE [i]      ->write(i<=nb_inst_enable);
    182           if (_param->_have_port_instruction_ptr)
     192          if (_param->_have_port_inst_ifetch_ptr)
    183193          in_ADDRESS_INST_IFETCH_PTR             ->write(address%_param->_nb_instruction);
    184194          in_ADDRESS_BRANCH_STATE                ->write(address%SIZE_BRANCH_STATE);
    185           if (_param->_have_port_branch_update_prediction_id)
    186           in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_branch_update_prediction);
     195          if (_param->_have_port_depth)
     196          in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_depth);
    187197
    188198          // =====
    … …  
    241251             
    242252              list_wait_decod.push_back(address);
    243 //            list_req_icache.insert(, entry_t((_param->_have_port_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
     253//            list_req_icache.insert(, entry_t((_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
    244254
    245255              uint32_t cycle = ((rand()%100)<percent_icache_hit)?1:icache_miss_penality;
    … …  
    252262
    253263              LABEL("  * list_req_icache : %d",list_req_icache.size());
    254               list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
     264              list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
    255265              LABEL("  * list_req_icache : %d",list_req_icache.size());       
    256266              address += 4*_param->_nb_instruction;
    … …  
    292302              TEST(Tgeneral_data_t   ,out_DECOD_ADDRESS                    ->read(), addr);
    293303              TEST(Tbranch_state_t   ,out_DECOD_BRANCH_STATE               ->read(),addr%SIZE_BRANCH_STATE);
    294               if (_param->_have_port_instruction_ptr)
     304              if (_param->_have_port_inst_ifetch_ptr)
    295305              TEST(Tinst_ifetch_ptr_t,out_DECOD_INST_IFETCH_PTR            ->read(),addr%_param->_nb_instruction);
    296               if (_param->_have_port_branch_update_prediction_id)
    297               TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_branch_update_prediction);
     306              if (_param->_have_port_depth)
     307              TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_depth);
    298308              if ((addr % modulo_iberr) == 0)
    299309              TEST(Texception_t      ,out_DECOD_EXCEPTION                  ->read(),EXCEPTION_IFETCH_BUS_ERROR);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Parameters.h

    r81 r88  
    2626  public : uint32_t _size_queue                           ;
    2727  public : uint32_t _nb_instruction                       ;
    28   public : uint32_t _size_branch_update_prediction        ;
    29   public : uint32_t _size_general_data                    ;
     28//public : uint32_t _size_branch_update_prediction        ;
     29//public : uint32_t _size_general_data                    ;
    3030
    31   public : uint32_t _size_queue_ptr                       ;
    32   public : uint32_t _size_instruction_ptr                 ;
     31//public : uint32_t _size_queue_ptr                       ;
     32//public : uint32_t _size_instruction_ptr                 ;
    3333
    34   public : bool     _have_port_queue_ptr                  ;
    35   public : bool     _have_port_instruction_ptr            ;
    36   public : bool     _have_port_branch_update_prediction_id;
     34//public : bool     _have_port_queue_ptr                  ;
     35//public : bool     _have_port_instruction_ptr            ;
     36//public : bool     _have_port_branch_update_prediction_id;
    3737
    3838    //-----[ methods ]-----------------------------------------------------------
    39   public : Parameters  (uint32_t _size_queue                   ,
    40                         uint32_t _nb_instruction               ,
    41                         uint32_t _size_branch_update_prediction,
    42                         uint32_t _size_general_data            );
     39  public : Parameters  (uint32_t size_queue                   ,
     40                        uint32_t nb_instruction               ,
     41                        uint32_t size_branch_update_prediction,
     42                        uint32_t size_general_data            ,
     43                        bool     is_toplevel=false);
    4344//   public : Parameters  (Parameters & param) ;
    4445  public : ~Parameters () ;
     46
     47  public :        void            copy       (void);
    4548
    4649  public :        Parameters_test msg_error  (void);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp

    r81 r88  
    3838    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
    3939
    40     log_printf(INFO,Ifetch_queue,FUNCTION,"Allocation");
     40#if DEBUG_Ifetch_queue == true
     41    log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     42
     43    std::cout << *param << std::endl;
     44#endif   
     45
     46    log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Allocation"),_name.c_str());
    4147
    4248    allocation (
    … …  
    4753
    4854#ifdef STATISTICS
    49     if (_usage & USE_STATISTICS)
     55    if (usage_is_set(_usage,USE_STATISTICS))
    5056      {
    51         log_printf(INFO,Ifetch_queue,FUNCTION,"Allocation of statistics");
     57        log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Allocation of statistics"),_name.c_str());
    5258
    5359        statistics_allocation(param_statistics);
    … …  
    5662
    5763#ifdef VHDL
    58     if (_usage & USE_VHDL)
     64    if (usage_is_set(_usage,USE_VHDL))
    5965      {
    6066        // generate the vhdl
    61         log_printf(INFO,Ifetch_queue,FUNCTION,"Generate the vhdl");
     67        log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Generate the vhdl"),_name.c_str());
    6268       
    6369        vhdl();
    … …  
    6672
    6773#ifdef SYSTEMC
    68     if (_usage & USE_SYSTEMC)
     74    if (usage_is_set(_usage,USE_SYSTEMC))
    6975      {
    7076        // constant output
    … …  
    7581        PORT_WRITE(out_EVENT_RESET_ACK, internal_EVENT_RESET_ACK);
    7682
    77         log_printf(INFO,Ifetch_queue,FUNCTION,"Method - transition");
     83        log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Method - transition"),_name.c_str());
    7884
    7985        SC_METHOD (transition);
    … …  
    8591# endif   
    8692
    87         log_printf(INFO,Ifetch_queue,FUNCTION,"Method - genMoore");
     93        log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Method - genMoore"),_name.c_str());
    8894
    8995        SC_METHOD (genMoore);
    … …  
    107113
    108114#ifdef STATISTICS
    109     if (_usage & USE_STATISTICS)
     115    if (usage_is_set(_usage,USE_STATISTICS))
    110116      {
    111117        statistics_deallocation();
    … …  
    113119#endif
    114120
    115     log_printf(INFO,Ifetch_queue,FUNCTION,"Deallocation");
     121    log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Deallocation"),_name.c_str());
    116122    deallocation ();
    117123

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp

    r81 r88  
    6262      ALLOC_VALACK_IN ( in_ADDRESS_VAL                        ,VAL);
    6363      ALLOC_VALACK_OUT(out_ADDRESS_ACK                        ,ACK);
    64       ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_general_data            );
    65       ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_instruction_ptr         );
    66       ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state            );
    67       ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_branch_update_prediction);
    68       ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_queue_ptr               );
     64      ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_instruction_address        );
     65      ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);
     66      ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state   );
     67      ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth          );
     68      ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);
    6969
    7070    }
    … …  
    8686      ALLOC_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.");
    8787     
    88       ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_general_data            );
    89       ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr        );
    90       ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state            );
    91       ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
    92       ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch        );
     88      ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
     89      ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
     90      ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
     91      ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
     92      ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
    9393    }
    9494
    … …  
    9999      ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL      ,VAL);
    100100      ALLOC_VALACK_OUT(out_ICACHE_RSP_ACK      ,ACK);
    101       ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_queue_ptr   );
     101      ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_ifetch_queue_ptr);
    102102      ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR    ,"error"    ,Ticache_error_t,_param->_size_icache_error);
    103103    }
    … …  
    117117
    118118    // ~~~~~[ Internal ] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    119     internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction];
    120 
    121     _queue = new ifetch_queue_entry_t * [_param->_size_queue];
    122     for (uint32_t i=0;i<_param->_size_queue; i++)
    123       _queue [i] = new ifetch_queue_entry_t (_param->_nb_instruction);
     119    if (usage_is_set(_usage,USE_SYSTEMC))
     120      {
     121        internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction];
     122       
     123        _queue = new ifetch_queue_entry_t * [_param->_size_queue];
     124        for (uint32_t i=0;i<_param->_size_queue; i++)
     125          _queue [i] = new ifetch_queue_entry_t (_param->_nb_instruction);
     126      }
    124127
    125128    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    126129
    127130#ifdef POSITION
    128     _component->generate_file();
     131     if (usage_is_set(_usage,USE_POSITION))
     132       _component->generate_file();
    129133#endif
    130134

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp

    r81 r88  
    2323    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
    2424
    25     if (_usage & USE_SYSTEMC)
     25    if (usage_is_set(_usage,USE_SYSTEMC))
    2626      {
    2727        delete    in_CLOCK ;
    … …  
    3030        delete     in_ADDRESS_VAL                        ;
    3131        delete    out_ADDRESS_ACK                        ;
    32         if (_param->_have_port_queue_ptr)
     32        if (_param->_have_port_ifetch_queue_ptr)
    3333        delete    out_ADDRESS_IFETCH_QUEUE_ID            ;
    3434        delete []  in_ADDRESS_INSTRUCTION_ENABLE         ;
    3535        delete     in_ADDRESS_INSTRUCTION_ADDRESS        ;
    36         if (_param->_have_port_instruction_ptr)
     36        if (_param->_have_port_inst_ifetch_ptr)
    3737        delete     in_ADDRESS_INST_IFETCH_PTR            ;
    3838        delete     in_ADDRESS_BRANCH_STATE               ;
    39         if (_param->_have_port_branch_update_prediction_id)
     39        if (_param->_have_port_depth)
    4040        delete     in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
    4141        delete [] out_DECOD_VAL                          ;
    … …  
    4343        delete [] out_DECOD_INSTRUCTION                  ;
    4444        delete    out_DECOD_ADDRESS                      ;
    45         if (_param->_have_port_instruction_ptr)
     45        if (_param->_have_port_inst_ifetch_ptr)
    4646        delete    out_DECOD_INST_IFETCH_PTR              ;
    4747        delete    out_DECOD_BRANCH_STATE                 ;
    48         if (_param->_have_port_branch_update_prediction_id)
     48        if (_param->_have_port_depth)
    4949        delete    out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ;
    5050        delete    out_DECOD_EXCEPTION                    ;
    5151        delete     in_ICACHE_RSP_VAL                     ;
    5252        delete    out_ICACHE_RSP_ACK                     ;
    53         if (_param->_have_port_queue_ptr)
     53        if (_param->_have_port_ifetch_queue_ptr)
    5454        delete     in_ICACHE_RSP_PACKET_ID               ;
    5555        delete []  in_ICACHE_RSP_INSTRUCTION             ;
    … …  
    5858        delete    out_EVENT_RESET_ACK                    ;
    5959      }
     60
     61    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
     62    if (usage_is_set(_usage,USE_SYSTEMC))
     63      {
     64        delete    internal_DECOD_VAL;
     65        delete [] _queue;
     66      }
     67
    6068    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    61 
    62     delete    internal_DECOD_VAL;
    63     delete [] _queue;
    6469    delete    _component;
    6570

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_end_cycle.cpp

    r81 r88  
    2525
    2626#ifdef STATISTICS
    27     _stat->end_cycle();
     27    if (usage_is_set(_usage,USE_STATISTICS))
     28      _stat->end_cycle();
    2829#endif   
    2930
    … …  
    3132    // Evaluation before read the ouput signal
    3233//  sc_start(0);
    33     _interfaces->testbench();
     34    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
     35      _interfaces->testbench();
    3436#endif
    3537

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp

    r81 r88  
    2929
    3030    PORT_WRITE(out_ADDRESS_ACK            , internal_ADDRESS_ACK);
    31     if (_param->_have_port_queue_ptr)
     31    if (_param->_have_port_ifetch_queue_ptr)
    3232    PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE);
    3333
    … …  
    4545
    4646    PORT_WRITE(out_DECOD_ADDRESS                    , _queue[reg_PTR_READ]->_address                    );
    47     if (_param->_have_port_instruction_ptr)
     47    if (_param->_have_port_inst_ifetch_ptr)
    4848    PORT_WRITE(out_DECOD_INST_IFETCH_PTR            , _queue[reg_PTR_READ]->_inst_ifetch_ptr            );
    4949    PORT_WRITE(out_DECOD_BRANCH_STATE               , _queue[reg_PTR_READ]->_branch_state               );
    50     if (_param->_have_port_branch_update_prediction_id)
     50    if (_param->_have_port_depth)
    5151    PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id);
    5252    PORT_WRITE(out_DECOD_EXCEPTION                  , _queue[reg_PTR_READ]->_exception                  );

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp

    r85 r88  
    2222  void Ifetch_queue::transition (void)
    2323  {
    24     log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
     24    log_begin(Ifetch_queue,FUNCTION);
    2525
    2626    if (PORT_READ(in_NRESET) == 0)
    … …  
    3434    else
    3535      {
    36         log_printf(NONE,Ifetch_queue,FUNCTION," * KANE address : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS));
    37    
    38 
    3936        // ==========================================================
    4037        // =====[ ADDRESS ]==========================================
    … …  
    4744             
    4845#ifdef STATISTICS
    49             (*_sum_transaction_address) ++;
     46            if (usage_is_set(_usage,USE_STATISTICS))
     47              (*_sum_transaction_address) ++;
    5048#endif
    5149
    … …  
    5452                Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]);
    5553#ifdef STATISTICS
    56                 (*_sum_inst_enable) += enable;
     54                if (usage_is_set(_usage,USE_STATISTICS))
     55                  (*_sum_inst_enable) += enable;
    5756#endif
    5857                _queue[reg_PTR_WRITE]->_instruction_enable [i]      = enable;
    … …  
    6059
    6160            _queue[reg_PTR_WRITE]->_address                     = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS        );
    62             _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_instruction_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
     61            _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
    6362            _queue[reg_PTR_WRITE]->_branch_state                = PORT_READ(in_ADDRESS_BRANCH_STATE               );
    64             _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_branch_update_prediction_id)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0;
     63            _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0;
    6564           
    6665            reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue;
    … …  
    9594        if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK)
    9695          {
    97             Tpacket_t ptr = (_param->_have_port_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
     96            Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
    9897           
    9998            for (uint32_t i=0; i<_param->_nb_instruction; i++)
    … …  
    137136          }
    138137
    139 #if DEBUG >= DEBUG_TRACE
    140         log_printf(TRACE,Ifetch_queue,FUNCTION,"Dump ifetch_queue");
    141         log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE);
    142         log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ  : %d",reg_PTR_READ );
     138#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
     139        log_printf(TRACE,Ifetch_queue,FUNCTION,"  * Dump ifetch_queue");
     140        log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
     141        log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_READ  : %d",reg_PTR_READ );
    143142        for (uint32_t i=0; i<_param->_size_queue; i++)
    144143          {
    145             log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception);
     144            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception);
    146145           
    147146            for (uint32_t j=0; j<_param->_nb_instruction; j++)
    148               log_printf(TRACE,Ifetch_queue,FUNCTION,"    * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
     147              log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
    149148          }
    150149#endif
    151150
    152151#ifdef STATISTICS
    153         for (uint32_t i=0; i<_param->_size_queue; i++)
    154           switch (_queue[i]->_state)
    155             {
    156             case IFETCH_QUEUE_STATE_EMPTY          : break;
    157             case IFETCH_QUEUE_STATE_WAIT_RSP       : (*_sum_use_queue_wait_rsp      ) ++; break;
    158             case IFETCH_QUEUE_STATE_HAVE_RSP       : (*_sum_use_queue_have_rsp      ) ++; break;
    159             case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break;
    160             default : break;
    161             }
     152        if (usage_is_set(_usage,USE_STATISTICS))
     153          for (uint32_t i=0; i<_param->_size_queue; i++)
     154            switch (_queue[i]->_state)
     155              {
     156              case IFETCH_QUEUE_STATE_EMPTY          : break;
     157              case IFETCH_QUEUE_STATE_WAIT_RSP       : (*_sum_use_queue_wait_rsp      ) ++; break;
     158              case IFETCH_QUEUE_STATE_HAVE_RSP       : (*_sum_use_queue_have_rsp      ) ++; break;
     159              case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break;
     160              default : break;
     161              }
    162162#endif
    163163      }
    164 
     164   
    165165#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
    166166    end_cycle ();
    167167#endif
    168168
    169     log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
     169    log_end(Ifetch_queue,FUNCTION);
    170170  };
    171171

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp

    r81 r88  
    2222                          uint32_t nb_instruction               ,
    2323                          uint32_t size_branch_update_prediction,
    24                           uint32_t size_general_data            )
     24                          uint32_t size_general_data            ,
     25                          bool     is_toplevel)
    2526  {
    2627    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
    … …  
    2829    _size_queue                            = size_queue                   ;
    2930    _nb_instruction                        = nb_instruction               ;
    30     _size_branch_update_prediction         = size_branch_update_prediction;
    31     _size_general_data                     = size_general_data            ;
     31//  _size_branch_update_prediction         = size_branch_update_prediction;
     32//  _size_general_data                     = size_general_data            ;
    3233
    33     _size_queue_ptr                        = log2(size_queue);
    34     _size_instruction_ptr                  = log2(nb_instruction);
     34    test();
    3535
    36     _have_port_queue_ptr                   = _size_queue_ptr > 0;
    37     _have_port_instruction_ptr             = _size_instruction_ptr > 0;
    38     _have_port_branch_update_prediction_id = size_branch_update_prediction > 0;
    39    
    40     test();
     36    if (is_toplevel)
     37      {
     38        _size_instruction_address   = size_general_data;
     39        _size_ifetch_queue_ptr      = log2(size_queue);
     40        _size_inst_ifetch_ptr       = log2(nb_instruction);
     41        _size_depth                 = size_branch_update_prediction;
     42
     43        _have_port_ifetch_queue_ptr = _size_ifetch_queue_ptr > 0;
     44        _have_port_inst_ifetch_ptr  = _size_inst_ifetch_ptr > 0;
     45        _have_port_depth            = _size_depth > 0;
     46
     47        copy ();
     48      }
     49
    4150    log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
    4251  };
    … …  
    5968  };
    6069
     70#undef  FUNCTION
     71#define FUNCTION "Ifetch_queue::copy"
     72  void Parameters::copy (void)
     73  {
     74    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
     75    log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
     76  };
     77
    6178}; // end namespace ifetch_queue
    6279}; // end namespace ifetch_unit

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp

    r81 r88  
    2828
    2929    if (_size_queue == 1)
    30       test.warning("To best perfomance, size_queue must be > 1.");
     30      test.warning("To best perfomance, size_queue must be > 1.\n");
    3131   
    32 //     if (not _have_port_queue_ptr)
    33 //       test.information("They have not port '..._QUEUE_PTR'.");
    34 
    35 //     if (not _have_port_instruction_ptr)
    36 //       test.information("They have not port '..._INST_IFETCH_PTR'.");
    37 
    38 //     if (not _have_port_branch_update_prediction_id)
    39 //       test.information("They have not port '..._BRANCH_UPDATE_PREDICTION_ID'.");
    40 
    4132    log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
    4233

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_print.cpp

    r81 r88  
    2929    xml.singleton_begin("size_queue                   "); xml.attribut("value",toString(_size_queue                   )); xml.singleton_end();
    3030    xml.singleton_begin("nb_instruction               "); xml.attribut("value",toString(_nb_instruction               )); xml.singleton_end();
    31     xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
    32     xml.singleton_begin("size_general_data            "); xml.attribut("value",toString(_size_general_data            )); xml.singleton_end();
     31//  xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
     32//  xml.singleton_begin("size_general_data            "); xml.attribut("value",toString(_size_general_data            )); xml.singleton_end();
    3333    xml.balise_close();
    3434
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