Changeset 94 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
- Timestamp:
- Dec 15, 2008, 12:04:03 PM (16 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r88 r94 116 116 // ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context); 117 117 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); 118 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context); 118 119 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); 119 120 … … 130 131 ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update); 131 132 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update); 133 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update); 132 134 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update); 133 135 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update); … … 201 203 // INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context); 202 204 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); 205 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context); 203 206 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 204 207 … … 217 220 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update); 218 221 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update); 222 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update); 219 223 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update); 220 224 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update); … … 247 251 const int32_t percent_transaction_branch_complete = 75; 248 252 const int32_t percent_transaction_update = 75; 249 250 253 const int32_t percent_transaction_branch_event = 75; 254 255 const bool test1 = false; 256 const bool test2 = false; 257 const bool test3 = false; 258 const bool test4 = true; 251 259 252 260 std::list<request_t> ufpt; 253 261 std::list<request_t> upt; 262 request_t event; 254 263 255 264 SC_START(0); … … 302 311 //--------------------------------------------------------------------- 303 312 //--------------------------------------------------------------------- 304 if ( 1)305 {313 if (test1) 314 { 306 315 uint32_t context = rand() % _param->_nb_context; 307 316 … … 508 517 for (uint32_t i=0; i<upt.size(); i++) 509 518 { 510 LABEL("Address_src (-1): %.8x (%d)",out_UPDATE_BTB_ADDRESS_SRC [i]->read(),upt.size());511 512 519 bool have_transaction = false; 513 520 514 521 do 515 522 { 516 LABEL("Address_src (0) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());517 518 523 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 519 524 … … 522 527 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 523 528 524 LABEL("Address_src (1) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());525 529 SC_START(0); 526 LABEL("Address_src (2) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read()); 527 530 528 531 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 529 532 … … 534 537 535 538 if (_param->_have_port_context_id) 536 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [ i]->read(),it_upt->context);537 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [ i]->read(),it_upt->miss_commit);538 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [ i]->read(),it_upt->flag);539 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [ i]->read(),update_btb(it_upt->condition));539 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 540 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 541 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 542 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 540 543 if (update_btb(it_upt->condition)) 541 544 { 542 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [ i]->read(),it_upt->address_src);543 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [ i]->read(),it_upt->address_dest);544 TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [ i]->read(),it_upt->condition);545 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); 546 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest); 547 TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 545 548 } 546 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [ i]->read(),update_dir(it_upt->condition));549 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod)); 547 550 if (update_dir(it_upt->condition)) 548 551 if (_param->_have_port_history) 549 TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [ i]->read(),it_upt->history);550 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [ i]->read(),update_ras(it_upt->condition));552 TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 553 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition)); 551 554 if (update_ras(it_upt->condition)) 552 555 { 553 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [i]->read(),push_ras (it_upt->condition)); 554 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [i]->read(),it_upt->ras_address); 555 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [i]->read(),it_upt->ras_index); 556 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [i]->read(),not it_upt->miss_ifetch); 556 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 557 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition)); 558 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 559 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 560 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 557 561 } 558 562 ++ it_upt; … … 560 564 561 565 SC_START(1); 562 LABEL("Address_src (3) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());563 564 566 } while (not have_transaction); 565 567 566 LABEL("Address_src (4) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());567 568 in_UPDATE_ACK [port]->write(0); 568 LABEL("Address_src (5) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());569 569 // if (_param->_have_port_depth) 570 570 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); … … 586 586 } 587 587 588 //--------------------------------------------------------------------- 589 //--------------------------------------------------------------------- 590 // DECOD MISS : no RAS in ifetch 591 //--------------------------------------------------------------------- 592 //--------------------------------------------------------------------- 593 if (test2) 594 { 595 uint32_t context = rand() % _param->_nb_context; 596 597 { 598 LABEL("PREDICT - fill the queue"); 599 uint32_t port = rand() % _param->_nb_inst_predict; 600 601 LABEL(" * context : %d",context); 602 LABEL(" * port : %d",port); 603 604 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 605 { 606 request_t request; 607 request.context = context; 608 request.address_src = 0xdeadbeef+i; 609 request.address_dest = 0x21071981+i; 610 request.address_good = request.address_dest; 611 request.condition = BRANCH_CONDITION_FLAG_SET; 612 request.take = 1; 613 request.take_good = 1; 614 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 615 request.is_accurate = true; 616 request.miss_ifetch = false; 617 request.miss_decod = false; 618 request.miss_commit = false; 619 request.history = i; 620 request.ras_address = 0xdeaddead+i; 621 request.ras_index = (0x12345678+i)%_param->_size_ras_index[context]; 622 request.ufpt_ptr = ufpt_top [context]; 623 // request.upt_ptr; 624 625 bool have_transaction = false; 626 do 627 { 628 in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict); 629 in_PREDICT_CONTEXT_ID [port]->write(request.context ); 630 in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src ); 631 in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest); 632 in_PREDICT_BTB_CONDITION [port]->write(request.condition ); 633 in_PREDICT_BTB_LAST_TAKE [port]->write(request.take ); 634 in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate ); 635 in_PREDICT_DIR_HISTORY [port]->write(request.history ); 636 in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address ); 637 in_PREDICT_RAS_INDEX [port]->write(request.ras_index ); 638 639 if (_param->_have_port_depth) 640 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 641 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 642 643 SC_START(0); // fct melay 644 645 LABEL("PREDICT [%d] %d - %d (accurate : %d).", 646 port, 647 in_PREDICT_VAL [port]->read(), 648 out_PREDICT_ACK [port]->read(), 649 in_PREDICT_BTB_IS_ACCURATE [port]->read()); 650 651 if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) 652 { 653 LABEL("PREDICT [%d] - Transaction accepted",port); 654 have_transaction = true; 655 656 if (_param->_have_port_depth) 657 TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]); 658 659 ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context]; 660 } 661 662 SC_START(1); // transition 663 664 } while (not have_transaction); 665 666 // ufpt.push_back(request); 667 668 in_PREDICT_VAL [port]->write(0); 669 670 if (_param->_have_port_depth) 671 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 672 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 673 } 674 } 675 676 { 677 LABEL("DECOD - Miss"); 678 uint32_t port = rand() % _param->_nb_inst_decod; 679 680 LABEL(" * context : %d",context); 681 LABEL(" * port : %d",port); 682 683 request_t request; 684 request.context = context; 685 request.address_src = 0x14011959; 686 request.address_dest = 0x25071959; // after = not take 687 request.address_good = request.address_dest; 688 request.condition = BRANCH_CONDITION_FLAG_SET; 689 request.take = 0; 690 request.take_good = 0; 691 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 692 request.is_accurate = true; 693 request.miss_ifetch = false; 694 request.miss_decod = true ; 695 request.miss_commit = false; 696 request.history = 1; 697 request.ras_address = 0xbabababa; 698 request.ras_index = (0x87654321)%_param->_size_ras_index[context]; 699 request.ufpt_ptr = ufpt_top [context]; 700 701 event = request; 702 703 // for (uint32_t i=0; i<upt.size(); i++) 704 // just one 705 { 706 bool have_transaction = false; 707 do 708 { 709 in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod); 710 in_DECOD_CONTEXT_ID [port]->write(request.context ); 711 in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src ); 712 in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest); 713 in_DECOD_BTB_CONDITION [port]->write(request.condition ); 714 in_DECOD_BTB_LAST_TAKE [port]->write(request.take ); 715 in_DECOD_RAS_ADDRESS [port]->write(request.ras_address ); 716 in_DECOD_RAS_INDEX [port]->write(request.ras_index ); 717 in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr ); 718 in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch ); 719 in_DECOD_MISS_DECOD [port]->write(request.miss_decod ); 720 in_DECOD_IS_ACCURATE [port]->write(request.is_accurate ); 721 722 SC_START(0); // fct melay 723 724 LABEL("DECOD [%d] %d - %d", 725 port, 726 in_PREDICT_VAL [port]->read(), 727 out_PREDICT_ACK [port]->read()); 728 729 if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read()) 730 { 731 LABEL("DECOD [%d] - Transaction accepted",port); 732 have_transaction = true; 733 734 request.upt_ptr = upt_top [context]; 735 upt.push_back(request); 736 // ufpt.pop_front(); 737 738 upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context]; 739 } 740 741 SC_START(1); // transition 742 743 } while (not have_transaction); 744 745 in_DECOD_VAL [port]->write(0); 746 747 if (_param->_have_port_depth) 748 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 749 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 750 } 751 } 752 753 { 754 LABEL("BRANCH_COMPLETE - hit ifetch"); 755 756 uint32_t port = rand() % _param->_nb_inst_branch_complete; 757 758 LABEL(" * port : %d",port); 759 760 std::list<request_t>::iterator it_upt = upt.begin(); 761 762 // for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 763 // for (uint32_t i=0; i<upt.size(); i++) 764 // just one 765 { 766 bool have_transaction = false; 767 768 do 769 { 770 in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete); 771 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context ); 772 in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); 773 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good); 774 in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag ); 775 776 if (_param->_have_port_depth) 777 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 778 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 779 780 SC_START(0); 781 782 LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read()); 783 784 if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read()) 785 { 786 LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); 787 have_transaction = true; 788 789 TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit ); 790 TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good ); 791 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src ); 792 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good); 793 794 it_upt ++; 795 } 796 797 SC_START(1); 798 } while (not have_transaction); 799 800 in_BRANCH_COMPLETE_VAL [port]->write(0); 801 802 if (_param->_have_port_depth) 803 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 804 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 805 } 806 } 807 808 { 809 LABEL("UPDATE - hit ifetch"); 810 811 uint32_t port = 0; 812 813 LABEL(" * port : %d",port); 814 std::list<request_t>::iterator it_upt = upt.begin(); 815 816 // for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 817 // for (uint32_t i=0; i<upt.size(); i++) 818 // just one 819 { 820 bool have_transaction = false; 821 822 do 823 { 824 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 825 826 // if (_param->_have_port_depth) 827 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 828 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 829 830 SC_START(0); 831 832 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 833 834 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 835 { 836 LABEL("UPDATE [%d] - Transaction accepted",port); 837 have_transaction = true; 838 839 if (_param->_have_port_context_id) 840 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 841 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 842 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 843 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 844 if (update_btb(it_upt->condition)) 845 { 846 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); 847 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest); 848 TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 849 } 850 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod)); 851 852 if (update_dir(it_upt->condition)) 853 if (_param->_have_port_history) 854 TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 855 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition)); 856 if (update_ras(it_upt->condition)) 857 { 858 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 859 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition)); 860 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 861 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 862 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 863 } 864 ++ it_upt; 865 } 866 867 SC_START(1); 868 } while (not have_transaction); 869 870 in_UPDATE_ACK [port]->write(0); 871 // if (_param->_have_port_depth) 872 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 873 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 874 } 875 upt.clear(); 876 } 877 878 { 879 LABEL("BRANCH_EVENT - have miss decod"); 880 881 uint32_t port = context; 882 883 { 884 bool have_transaction = false; 885 886 do 887 { 888 in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event); 889 890 SC_START(0); 891 892 LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read()); 893 894 if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read()) 895 { 896 LABEL("BRANCH_EVENT [%d] - Transaction accepted",port); 897 have_transaction = true; 898 899 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); 900 TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take); 901 if (event.take) 902 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good); 903 904 event.address_src = 0; 905 event.take = 0; 906 event.address_dest = 0; 907 } 908 909 SC_START(1); 910 } while (not have_transaction); 911 912 in_BRANCH_EVENT_ACK [port]->write(0); 913 } 914 } 915 916 917 // Wait Garbage Collector 918 { 919 upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context]; 920 // upt_top [context] = (upt_top [context]); 921 922 while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or 923 (upt_top [context] != out_DEPTH_MAX [context]->read())) 924 SC_START(1); 925 926 } 927 } 928 929 //--------------------------------------------------------------------- 930 //--------------------------------------------------------------------- 931 // DECOD MISS : with RAS in ifetch 932 //--------------------------------------------------------------------- 933 //--------------------------------------------------------------------- 934 if (test3) 935 { 936 uint32_t context = rand() % _param->_nb_context; 937 uint32_t have_ras = false; 938 { 939 LABEL("PREDICT - fill the queue"); 940 uint32_t port = rand() % _param->_nb_inst_predict; 941 942 LABEL(" * context : %d",context); 943 LABEL(" * port : %d",port); 944 945 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 946 { 947 request_t request; 948 request.context = context; 949 request.address_src = 0xdeadbeef+i; 950 request.address_dest = 0x21071981+i; 951 request.address_good = request.address_dest; 952 request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET; 953 954 have_ras |= (update_ras(request.condition)); 955 956 request.take = 1; 957 request.take_good = 1; 958 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 959 request.is_accurate = true; 960 request.miss_ifetch = false; 961 request.miss_decod = true ; 962 request.miss_commit = false; 963 request.history = i; 964 request.ras_address = 0x12344321+i; 965 request.ras_index = (043211234+i)%_param->_size_ras_index[context]; 966 request.ufpt_ptr = ufpt_top [context]; 967 // request.upt_ptr; 968 969 bool have_transaction = false; 970 do 971 { 972 in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict); 973 in_PREDICT_CONTEXT_ID [port]->write(request.context ); 974 in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src ); 975 in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest); 976 in_PREDICT_BTB_CONDITION [port]->write(request.condition ); 977 in_PREDICT_BTB_LAST_TAKE [port]->write(request.take ); 978 in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate ); 979 in_PREDICT_DIR_HISTORY [port]->write(request.history ); 980 in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address ); 981 in_PREDICT_RAS_INDEX [port]->write(request.ras_index ); 982 983 if (_param->_have_port_depth) 984 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 985 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 986 987 SC_START(0); // fct melay 988 989 LABEL("PREDICT [%d] %d - %d (accurate : %d).", 990 port, 991 in_PREDICT_VAL [port]->read(), 992 out_PREDICT_ACK [port]->read(), 993 in_PREDICT_BTB_IS_ACCURATE [port]->read()); 994 995 if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) 996 { 997 LABEL("PREDICT [%d] - Transaction accepted",port); 998 have_transaction = true; 999 1000 if (_param->_have_port_depth) 1001 TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]); 1002 1003 ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context]; 1004 } 1005 1006 SC_START(1); // transition 1007 1008 } while (not have_transaction); 1009 1010 ufpt.push_back(request); // to update 1011 1012 in_PREDICT_VAL [port]->write(0); 1013 1014 if (_param->_have_port_depth) 1015 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1016 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1017 } 1018 } 1019 1020 { 1021 LABEL("DECOD - Miss"); 1022 uint32_t port = rand() % _param->_nb_inst_decod; 1023 1024 LABEL(" * context : %d",context); 1025 LABEL(" * port : %d",port); 1026 1027 request_t request; 1028 request.context = context; 1029 request.address_src = 0x14011959; 1030 request.address_dest = 0x25071959; // after = not take 1031 request.address_good = request.address_dest; 1032 request.condition = BRANCH_CONDITION_FLAG_SET; 1033 request.take = 0; 1034 request.take_good = 0; 1035 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 1036 request.is_accurate = true; 1037 request.miss_ifetch = false; 1038 request.miss_decod = true ; 1039 request.miss_commit = false; 1040 request.history = 1; 1041 request.ras_address = 0xbabababa; 1042 request.ras_index = (0x87654321)%_param->_size_ras_index[context]; 1043 request.ufpt_ptr = ufpt_top [context]; 1044 1045 event = request; 1046 1047 // for (uint32_t i=0; i<upt.size(); i++) 1048 // just one 1049 { 1050 bool have_transaction = false; 1051 do 1052 { 1053 in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod); 1054 in_DECOD_CONTEXT_ID [port]->write(request.context ); 1055 in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src ); 1056 in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest); 1057 in_DECOD_BTB_CONDITION [port]->write(request.condition ); 1058 in_DECOD_BTB_LAST_TAKE [port]->write(request.take ); 1059 in_DECOD_RAS_ADDRESS [port]->write(request.ras_address ); 1060 in_DECOD_RAS_INDEX [port]->write(request.ras_index ); 1061 in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr ); 1062 in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch ); 1063 in_DECOD_MISS_DECOD [port]->write(request.miss_decod ); 1064 in_DECOD_IS_ACCURATE [port]->write(request.is_accurate ); 1065 1066 SC_START(0); // fct melay 1067 1068 LABEL("DECOD [%d] %d - %d", 1069 port, 1070 in_PREDICT_VAL [port]->read(), 1071 out_PREDICT_ACK [port]->read()); 1072 1073 if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read()) 1074 { 1075 LABEL("DECOD [%d] - Transaction accepted",port); 1076 have_transaction = true; 1077 1078 request.upt_ptr = upt_top [context]; 1079 upt.push_back(request); 1080 // ufpt.pop_front(); 1081 1082 upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context]; 1083 } 1084 1085 SC_START(1); // transition 1086 1087 } while (not have_transaction); 1088 1089 in_DECOD_VAL [port]->write(0); 1090 1091 if (_param->_have_port_depth) 1092 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1093 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1094 } 1095 } 1096 1097 { 1098 LABEL("BRANCH_COMPLETE - hit ifetch"); 1099 1100 uint32_t port = rand() % _param->_nb_inst_branch_complete; 1101 1102 LABEL(" * port : %d",port); 1103 1104 std::list<request_t>::iterator it_upt = upt.begin(); 1105 1106 // for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 1107 // for (uint32_t i=0; i<upt.size(); i++) 1108 // just one 1109 { 1110 bool have_transaction = false; 1111 1112 do 1113 { 1114 in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete); 1115 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context ); 1116 in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); 1117 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good); 1118 in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag ); 1119 1120 if (_param->_have_port_depth) 1121 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1122 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1123 1124 SC_START(0); 1125 1126 LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read()); 1127 1128 if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read()) 1129 { 1130 LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); 1131 have_transaction = true; 1132 1133 TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit ); 1134 TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good ); 1135 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src ); 1136 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good); 1137 1138 it_upt ++; 1139 } 1140 1141 SC_START(1); 1142 } while (not have_transaction); 1143 1144 in_BRANCH_COMPLETE_VAL [port]->write(0); 1145 1146 if (_param->_have_port_depth) 1147 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1148 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1149 } 1150 } 1151 1152 if (have_ras) 1153 { 1154 LABEL("UPDATE - Update UPFT"); 1155 1156 uint32_t port = 0; 1157 1158 LABEL(" * port : %d",port); 1159 std::list<request_t>::iterator it_ufpt = ufpt.end(); 1160 -- it_ufpt; 1161 1162 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 1163 { 1164 bool have_transaction = false; 1165 1166 do 1167 { 1168 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 1169 1170 // if (_param->_have_port_depth) 1171 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]); 1172 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]); 1173 1174 SC_START(0); 1175 1176 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 1177 1178 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 1179 { 1180 LABEL("UPDATE [%d] - Transaction accepted",port); 1181 have_transaction = true; 1182 1183 if (_param->_have_port_context_id) 1184 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context); 1185 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or 1186 it_ufpt->miss_decod or 1187 it_ufpt->miss_commit )); 1188 // if (update_btb(it_ufpt->condition) or 1189 // update_dir(it_ufpt->condition)) 1190 // TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good); 1191 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0); 1192 // if (update_btb(it_ufpt->condition)) 1193 // { 1194 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src); 1195 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest); 1196 // TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition); 1197 // } 1198 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0); 1199 1200 // if (update_dir(it_ufpt->condition)) 1201 // if (_param->_have_port_history) 1202 // TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history); 1203 // TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition)); 1204 if (update_ras(it_ufpt->condition)) 1205 { 1206 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 1207 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition)); 1208 LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read()); 1209 LABEL("KANE : it_ufpt->ras_address : %.8x",it_ufpt->ras_address); 1210 1211 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 1212 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 1213 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 1214 } 1215 } 1216 1217 SC_START(1); 1218 } while (not have_transaction); 1219 1220 -- it_ufpt; 1221 1222 1223 in_UPDATE_ACK [port]->write(0); 1224 // if (_param->_have_port_depth) 1225 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]); 1226 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]); 1227 } 1228 } 1229 ufpt.clear(); 1230 1231 { 1232 LABEL("UPDATE - hit ifetch"); 1233 1234 uint32_t port = 0; 1235 1236 LABEL(" * port : %d",port); 1237 std::list<request_t>::iterator it_upt = upt.begin(); 1238 1239 // for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 1240 // for (uint32_t i=0; i<upt.size(); i++) 1241 // just one 1242 { 1243 bool have_transaction = false; 1244 1245 do 1246 { 1247 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 1248 1249 // if (_param->_have_port_depth) 1250 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1251 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1252 1253 SC_START(0); 1254 1255 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 1256 1257 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 1258 { 1259 LABEL("UPDATE [%d] - Transaction accepted",port); 1260 have_transaction = true; 1261 1262 if (_param->_have_port_context_id) 1263 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 1264 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 1265 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 1266 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 1267 if (update_btb(it_upt->condition)) 1268 { 1269 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); 1270 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest); 1271 TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 1272 } 1273 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod)); 1274 1275 if (update_dir(it_upt->condition)) 1276 if (_param->_have_port_history) 1277 TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 1278 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition)); 1279 if (update_ras(it_upt->condition)) 1280 { 1281 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 1282 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition)); 1283 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 1284 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 1285 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 1286 } 1287 ++ it_upt; 1288 } 1289 1290 SC_START(1); 1291 } while (not have_transaction); 1292 1293 in_UPDATE_ACK [port]->write(0); 1294 // if (_param->_have_port_depth) 1295 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1296 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1297 } 1298 } 1299 upt.clear(); 1300 1301 { 1302 LABEL("BRANCH_EVENT - have miss decod"); 1303 1304 uint32_t port = context; 1305 1306 { 1307 bool have_transaction = false; 1308 1309 do 1310 { 1311 in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event); 1312 1313 SC_START(0); 1314 1315 LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read()); 1316 1317 if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read()) 1318 { 1319 LABEL("BRANCH_EVENT [%d] - Transaction accepted",port); 1320 have_transaction = true; 1321 1322 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); 1323 TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take); 1324 if (event.take) 1325 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good); 1326 1327 event.address_src = 0; 1328 event.take = 0; 1329 event.address_dest = 0; 1330 } 1331 1332 SC_START(1); 1333 } while (not have_transaction); 1334 1335 in_BRANCH_EVENT_ACK [port]->write(0); 1336 } 1337 } 1338 1339 // Wait Garbage Collector 1340 { 1341 upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context]; 1342 // upt_top [context] = (upt_top [context]); 1343 1344 while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or 1345 (upt_top [context] != out_DEPTH_MAX [context]->read())) 1346 SC_START(1); 1347 1348 } 1349 } 1350 1351 //--------------------------------------------------------------------- 1352 //--------------------------------------------------------------------- 1353 // COMMIT MISS : with RAS in UPFT and UPT 1354 //--------------------------------------------------------------------- 1355 //--------------------------------------------------------------------- 1356 if (test4) 1357 { 1358 uint32_t context = rand() % _param->_nb_context; 1359 uint32_t have_ufpt_ras = false; 1360 uint32_t have_upt_ras = false; 1361 { 1362 LABEL("PREDICT - fill the queue"); 1363 uint32_t port = rand() % _param->_nb_inst_predict; 1364 1365 LABEL(" * context : %d",context); 1366 LABEL(" * port : %d",port); 1367 1368 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 1369 { 1370 request_t request; 1371 request.context = context; 1372 request.address_src = rand(); 1373 request.address_dest = rand(); 1374 1375 request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET; 1376 1377 request.take = 1; 1378 request.take_good = 1; 1379 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 1380 request.is_accurate = false; 1381 request.miss_ifetch = false; 1382 request.miss_decod = false; 1383 request.miss_commit = false; 1384 request.history = i; 1385 request.ras_address = rand(); 1386 request.ras_index = rand()%_param->_size_ras_index[context]; 1387 request.ufpt_ptr = ufpt_top [context]; 1388 // request.upt_ptr; 1389 1390 bool have_transaction = false; 1391 do 1392 { 1393 in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict); 1394 in_PREDICT_CONTEXT_ID [port]->write(request.context ); 1395 in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src ); 1396 in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest); 1397 in_PREDICT_BTB_CONDITION [port]->write(request.condition ); 1398 in_PREDICT_BTB_LAST_TAKE [port]->write(request.take ); 1399 in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate ); 1400 in_PREDICT_DIR_HISTORY [port]->write(request.history ); 1401 in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address ); 1402 in_PREDICT_RAS_INDEX [port]->write(request.ras_index ); 1403 1404 if (_param->_have_port_depth) 1405 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1406 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1407 1408 SC_START(0); // fct melay 1409 1410 LABEL("PREDICT [%d] %d - %d (accurate : %d).", 1411 port, 1412 in_PREDICT_VAL [port]->read(), 1413 out_PREDICT_ACK [port]->read(), 1414 in_PREDICT_BTB_IS_ACCURATE [port]->read()); 1415 1416 if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) 1417 { 1418 LABEL("PREDICT [%d] - Transaction accepted",port); 1419 have_transaction = true; 1420 1421 if (_param->_have_port_depth) 1422 TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]); 1423 1424 ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context]; 1425 } 1426 1427 SC_START(1); // transition 1428 1429 } while (not have_transaction); 1430 1431 ufpt.push_back(request); // to update 1432 1433 in_PREDICT_VAL [port]->write(0); 1434 1435 if (_param->_have_port_depth) 1436 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1437 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1438 } 1439 } 1440 1441 { 1442 LABEL("DECOD"); 1443 uint32_t port = rand() % _param->_nb_inst_decod; 1444 1445 LABEL(" * context : %d",context); 1446 LABEL(" * port : %d",port); 1447 1448 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 1449 { 1450 request_t request = ufpt.front(); 1451 1452 bool have_transaction = false; 1453 do 1454 { 1455 in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod); 1456 in_DECOD_CONTEXT_ID [port]->write(request.context ); 1457 in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src ); 1458 in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest); 1459 in_DECOD_BTB_CONDITION [port]->write(request.condition ); 1460 in_DECOD_BTB_LAST_TAKE [port]->write(request.take ); 1461 in_DECOD_RAS_ADDRESS [port]->write(request.ras_address ); 1462 in_DECOD_RAS_INDEX [port]->write(request.ras_index ); 1463 in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr ); 1464 in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch ); 1465 in_DECOD_MISS_DECOD [port]->write(request.miss_decod ); 1466 in_DECOD_IS_ACCURATE [port]->write(request.is_accurate ); 1467 1468 have_upt_ras |= (update_ras(request.condition)); 1469 1470 SC_START(0); // fct melay 1471 1472 LABEL("DECOD [%d] %d - %d", 1473 port, 1474 in_PREDICT_VAL [port]->read(), 1475 out_PREDICT_ACK [port]->read()); 1476 1477 if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read()) 1478 { 1479 LABEL("DECOD [%d] - Transaction accepted",port); 1480 have_transaction = true; 1481 1482 request.upt_ptr = upt_top [context]; 1483 upt.push_back(request); 1484 ufpt.pop_front(); 1485 1486 upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context]; 1487 } 1488 1489 SC_START(1); // transition 1490 1491 } while (not have_transaction); 1492 1493 in_DECOD_VAL [port]->write(0); 1494 1495 if (_param->_have_port_depth) 1496 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1497 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1498 } 1499 } 1500 1501 { 1502 LABEL("PREDICT - fill the queue"); 1503 uint32_t port = rand() % _param->_nb_inst_predict; 1504 1505 LABEL(" * context : %d",context); 1506 LABEL(" * port : %d",port); 1507 1508 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 1509 { 1510 request_t request; 1511 request.context = context; 1512 request.address_src = rand(); 1513 request.address_dest = rand(); 1514 request.address_good = request.address_dest; 1515 request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET; 1516 1517 have_ufpt_ras |= (update_ras(request.condition)); 1518 1519 request.take = 1; 1520 request.take_good = 1; 1521 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 1522 request.is_accurate = false; 1523 request.miss_ifetch = false; 1524 request.miss_decod = false; 1525 request.miss_commit = true; 1526 request.history = i; 1527 request.ras_address = rand(); 1528 request.ras_index = rand()%_param->_size_ras_index[context]; 1529 request.ufpt_ptr = ufpt_top [context]; 1530 // request.upt_ptr; 1531 1532 bool have_transaction = false; 1533 do 1534 { 1535 in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict); 1536 in_PREDICT_CONTEXT_ID [port]->write(request.context ); 1537 in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src ); 1538 in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest); 1539 in_PREDICT_BTB_CONDITION [port]->write(request.condition ); 1540 in_PREDICT_BTB_LAST_TAKE [port]->write(request.take ); 1541 in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate ); 1542 in_PREDICT_DIR_HISTORY [port]->write(request.history ); 1543 in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address ); 1544 in_PREDICT_RAS_INDEX [port]->write(request.ras_index ); 1545 1546 if (_param->_have_port_depth) 1547 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1548 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1549 1550 SC_START(0); // fct melay 1551 1552 LABEL("PREDICT [%d] %d - %d (accurate : %d).", 1553 port, 1554 in_PREDICT_VAL [port]->read(), 1555 out_PREDICT_ACK [port]->read(), 1556 in_PREDICT_BTB_IS_ACCURATE [port]->read()); 1557 1558 if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) 1559 { 1560 LABEL("PREDICT [%d] - Transaction accepted",port); 1561 have_transaction = true; 1562 1563 if (_param->_have_port_depth) 1564 TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]); 1565 1566 ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context]; 1567 } 1568 1569 SC_START(1); // transition 1570 1571 } while (not have_transaction); 1572 1573 ufpt.push_back(request); // to update 1574 1575 in_PREDICT_VAL [port]->write(0); 1576 1577 if (_param->_have_port_depth) 1578 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1579 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1580 } 1581 } 1582 1583 std::list<request_t>::iterator it_event; 1584 { 1585 LABEL("BRANCH_COMPLETE - hit ifetch"); 1586 1587 uint32_t port = rand() % _param->_nb_inst_branch_complete; 1588 1589 LABEL(" * port : %d",port); 1590 1591 // middle 1592 it_event = upt.begin(); 1593 for (uint32_t i=0; i < (upt.size()>>1); ++i) 1594 it_event ++; 1595 1596 for (std::list<request_t>::iterator it_upt = it_event; 1597 it_upt != upt.end(); 1598 ++it_upt) 1599 it_upt->miss_commit = true; 1600 1601 if (update_ras(it_event->condition)) 1602 it_event->address_good = ~(it_event->address_dest); 1603 else 1604 { 1605 it_event->address_good = it_event->address_dest; 1606 it_event->flag = not it_event->flag; 1607 it_event->take_good = not it_event->take_good; 1608 } 1609 1610 event = *it_event; 1611 1612 1613 // for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 1614 // for (uint32_t i=0; i<upt.size(); i++) 1615 // just one 1616 { 1617 bool have_transaction = false; 1618 1619 do 1620 { 1621 in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete); 1622 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context ); 1623 in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr ); 1624 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good); 1625 in_BRANCH_COMPLETE_FLAG [port]->write(it_event->flag ); 1626 1627 if (_param->_have_port_depth) 1628 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1629 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1630 1631 SC_START(0); 1632 1633 LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read()); 1634 1635 if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read()) 1636 { 1637 LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); 1638 LABEL(" * CONTEXT_ID %d" ,it_event->context ); 1639 LABEL(" * DEPTH %d" ,it_event->upt_ptr ); 1640 LABEL(" * CONDITION %d" ,it_event->condition ); 1641 LABEL(" * ADDRESS %.8x",it_event->address_good); 1642 LABEL(" * FLAG %d" ,it_event->flag ); 1643 1644 have_transaction = true; 1645 1646 TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit ); 1647 TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good ); 1648 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src ); 1649 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good); 1650 1651 upt_top [it_event->context] = it_event->upt_ptr; 1652 } 1653 1654 SC_START(1); 1655 } while (not have_transaction); 1656 1657 in_BRANCH_COMPLETE_VAL [port]->write(0); 1658 1659 if (_param->_have_port_depth) 1660 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1661 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1662 } 1663 } 1664 1665 if (have_ufpt_ras) 1666 { 1667 LABEL("UPDATE - Update UPFT"); 1668 1669 uint32_t port = 0; 1670 1671 LABEL(" * port : %d",port); 1672 std::list<request_t>::iterator it_ufpt = ufpt.end(); 1673 -- it_ufpt; 1674 1675 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 1676 { 1677 bool have_transaction = false; 1678 1679 do 1680 { 1681 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 1682 1683 // if (_param->_have_port_depth) 1684 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]); 1685 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]); 1686 1687 SC_START(0); 1688 1689 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 1690 1691 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 1692 { 1693 LABEL("UPDATE [%d] - Transaction accepted",port); 1694 have_transaction = true; 1695 1696 if (_param->_have_port_context_id) 1697 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context); 1698 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or 1699 it_ufpt->miss_decod or 1700 it_ufpt->miss_commit )); 1701 // if (update_btb(it_ufpt->condition) or 1702 // update_dir(it_ufpt->condition)) 1703 // TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good); 1704 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0); 1705 // if (update_btb(it_ufpt->condition)) 1706 // { 1707 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src); 1708 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest); 1709 // TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition); 1710 // } 1711 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0); 1712 1713 // if (update_dir(it_ufpt->condition)) 1714 // if (_param->_have_port_history) 1715 // TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history); 1716 // TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition)); 1717 if (update_ras(it_ufpt->condition)) 1718 { 1719 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 1720 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition)); 1721 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 1722 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 1723 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 1724 } 1725 } 1726 1727 SC_START(1); 1728 } while (not have_transaction); 1729 1730 -- it_ufpt; 1731 1732 1733 in_UPDATE_ACK [port]->write(0); 1734 // if (_param->_have_port_depth) 1735 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]); 1736 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]); 1737 } 1738 } 1739 ufpt.clear(); 1740 1741 { 1742 LABEL("UPDATE - upt"); 1743 1744 uint32_t port = 0; 1745 1746 LABEL(" * port : %d",port); 1747 std::list<request_t>::iterator it_upt = upt.end(); 1748 --it_upt; 1749 1750 // for (uint32_t i=0; i<upt.size(); i++) 1751 while (it_upt != it_event) 1752 { 1753 bool have_transaction = false; 1754 1755 do 1756 { 1757 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 1758 1759 // if (_param->_have_port_depth) 1760 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1761 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1762 1763 SC_START(0); 1764 1765 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 1766 1767 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 1768 { 1769 LABEL("UPDATE [%d] - Transaction accepted",port); 1770 have_transaction = true; 1771 1772 if (_param->_have_port_context_id) 1773 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 1774 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 1775 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 1776 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 1777 if (update_btb(it_upt->condition)) 1778 { 1779 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); 1780 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest); 1781 TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 1782 } 1783 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod)); 1784 1785 if (update_dir(it_upt->condition)) 1786 if (_param->_have_port_history) 1787 TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 1788 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition)); 1789 if (update_ras(it_upt->condition)) 1790 { 1791 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 1792 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition)); 1793 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 1794 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 1795 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 1796 } 1797 1798 -- it_upt; 1799 } 1800 1801 SC_START(1); 1802 } while (not have_transaction); 1803 1804 upt.pop_back(); 1805 in_UPDATE_ACK [port]->write(0); 1806 // if (_param->_have_port_depth) 1807 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1808 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1809 } 1810 } 1811 // upt.clear(); // Not yet 1812 1813 { 1814 LABEL("BRANCH_EVENT - have miss decod"); 1815 1816 uint32_t port = context; 1817 1818 { 1819 bool have_transaction = false; 1820 1821 do 1822 { 1823 in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event); 1824 1825 SC_START(0); 1826 1827 LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read()); 1828 1829 if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read()) 1830 { 1831 LABEL("BRANCH_EVENT [%d] - Transaction accepted",port); 1832 have_transaction = true; 1833 1834 LABEL(" * event.address_src : %.8x,",event.address_src ); 1835 LABEL(" * event.address_good : %.8x,",event.address_good); 1836 LABEL(" * event.take : %.8x,",event.take ); 1837 1838 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); 1839 TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good); 1840 if (event.take_good) 1841 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good); 1842 1843 event.address_src = 0; 1844 event.take = 0; 1845 event.address_dest = 0; 1846 } 1847 1848 SC_START(1); 1849 } while (not have_transaction); 1850 1851 in_BRANCH_EVENT_ACK [port]->write(0); 1852 } 1853 } 1854 1855 { 1856 LABEL("UPDATE - upt"); 1857 1858 uint32_t port = 0; 1859 1860 LABEL(" * port : %d",port); 1861 std::list<request_t>::iterator it_upt = upt.begin(); 1862 1863 for (uint32_t i=0; i<upt.size(); i++) 1864 { 1865 bool have_transaction = false; 1866 1867 do 1868 { 1869 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 1870 1871 // if (_param->_have_port_depth) 1872 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1873 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1874 1875 SC_START(0); 1876 1877 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 1878 1879 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 1880 { 1881 LABEL("UPDATE [%d] - Transaction accepted",port); 1882 have_transaction = true; 1883 1884 if (_param->_have_port_context_id) 1885 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 1886 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 1887 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 1888 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 1889 if (update_btb(it_upt->condition)) 1890 { 1891 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); 1892 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest); 1893 TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 1894 } 1895 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod)); 1896 1897 if (update_dir(it_upt->condition)) 1898 if (_param->_have_port_history) 1899 TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 1900 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition)); 1901 if (update_ras(it_upt->condition)) 1902 { 1903 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 1904 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition)); 1905 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 1906 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 1907 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 1908 } 1909 1910 -- it_upt; 1911 } 1912 1913 SC_START(1); 1914 } while (not have_transaction); 1915 1916 in_UPDATE_ACK [port]->write(0); 1917 // if (_param->_have_port_depth) 1918 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1919 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1920 } 1921 } 1922 upt.clear(); // Not yet 1923 1924 // Wait Garbage Collector 1925 { 1926 upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context]; 1927 // upt_top [context] = (upt_top [context]); 1928 1929 while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or 1930 (upt_top [context] != out_DEPTH_MAX [context]->read())) 1931 SC_START(1); 1932 1933 } 1934 } 1935 588 1936 }// ITERATION 589 1937 … … 649 1997 // delete [] out_BRANCH_EVENT_MISS_PREDICTION; 650 1998 delete [] out_BRANCH_EVENT_ADDRESS_SRC ; 1999 delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL; 651 2000 delete [] out_BRANCH_EVENT_ADDRESS_DEST ; 652 2001 … … 664 2013 delete [] out_UPDATE_DIR_HISTORY ; 665 2014 delete [] out_UPDATE_RAS_VAL ; 2015 delete [] out_UPDATE_RAS_FLUSH ; 666 2016 delete [] out_UPDATE_RAS_PUSH ; 667 2017 delete [] out_UPDATE_RAS_ADDRESS ;
Note: See TracChangeset
for help on using the changeset viewer.
