Changeset 97 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue
- Timestamp:
- Dec 19, 2008, 4:34:00 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue
- Files:
-
- 7 edited
-
SelfTest/src/test.cpp (modified) (11 diffs)
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include/Types.h (modified) (3 diffs)
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include/Write_queue.h (modified) (3 diffs)
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src/Parameters.cpp (modified) (1 diff)
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src/Write_queue_allocation.cpp (modified) (3 diffs)
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src/Write_queue_deallocation.cpp (modified) (1 diff)
-
src/Write_queue_transition.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp
r88 r97 22 22 public : Tpacket_t _packet_id ; 23 23 //public : Toperation_t _operation ; 24 24 //public : Ttype_t _type ; 25 25 public : Tcontrol_t _write_rd ; 26 26 public : Tgeneral_address_t _num_reg_rd ; … … 37 37 Tcontext_t ooo_engine_id, 38 38 Tpacket_t packet_id , 39 //Toperation_t operation ,40 Ttype_t type ,39 // Toperation_t operation , 40 // Ttype_t type , 41 41 Tcontrol_t write_rd , 42 42 Tgeneral_address_t num_reg_rd , … … 54 54 _packet_id = packet_id ; 55 55 //_operation = operation ; 56 56 //_type = type ; 57 57 _write_rd = write_rd ; 58 58 _num_reg_rd = num_reg_rd ; … … 74 74 << " * _packet_id : " << toString(x._packet_id ) << std::endl 75 75 //<< " * _operation : " << toString(x._operation ) << std::endl 76 76 //<< " * _type : " << toString(x._type ) << std::endl 77 77 << " * _write_rd : " << toString(x._write_rd ) << std::endl 78 78 << " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl … … 132 132 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t ); 133 133 //ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t ); 134 134 //ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t ); 135 135 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t ); 136 136 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t); … … 141 141 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t ); 142 142 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); 143 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , T general_data_t);143 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Taddress_t ); 144 144 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t ); 145 145 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t ); … … 154 154 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); 155 155 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); 156 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , T general_data_t);156 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Taddress_t ); 157 157 ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); 158 158 ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); … … 193 193 INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID ); 194 194 //INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OPERATION ); 195 195 //INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_TYPE ); 196 196 INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RD ); 197 197 INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RD ); … … 307 307 i, 308 308 //range<Toperation_t >(rand(),_param->_size_operation ), 309 309 //range<Ttype_t >(rand(),_param->_size_type ), 310 310 range<Tcontrol_t >(rand(),1 ), 311 311 range<Tgeneral_address_t>(rand(),_param->_size_general_register), … … 314 314 range<Tspecial_address_t>(rand(),_param->_size_special_register), 315 315 range<Tspecial_data_t >(rand(),_param->_size_special_data ), 316 range<Texception_t >(rand(), _param->_size_exception),316 range<Texception_t >(rand(),0 ), 317 317 range<Tcontrol_t >(rand(),1 ), 318 318 range<Tgeneral_data_t >(rand(),_param->_size_general_data )); … … 339 339 in_WRITE_QUEUE_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id ); 340 340 //in_WRITE_QUEUE_IN_OPERATION ->write(request [nb_request_in]->_operation ); 341 341 //in_WRITE_QUEUE_IN_TYPE ->write(request [nb_request_in]->_type ); 342 342 in_WRITE_QUEUE_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd ); 343 343 in_WRITE_QUEUE_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Types.h
r82 r97 27 27 public : Tpacket_t _packet_id ; 28 28 //public : Toperation_t _operation ; 29 29 //public : Ttype_t _type ; 30 30 public : Tcontrol_t _write_rd ; 31 31 public : Tgeneral_address_t _num_reg_rd ; … … 42 42 Tcontext_t ooo_engine_id, 43 43 Tpacket_t packet_id , 44 //Toperation_t operation ,45 Ttype_t type ,44 // Toperation_t operation , 45 // Ttype_t type , 46 46 Tcontrol_t write_rd , 47 47 Tgeneral_address_t num_reg_rd , … … 59 59 _packet_id = packet_id ; 60 60 //_operation = operation ; 61 61 //_type = type ; 62 62 _write_rd = write_rd ; 63 63 _num_reg_rd = num_reg_rd ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h
r88 r97 76 76 public : SC_IN (Tpacket_t ) * in_WRITE_QUEUE_IN_PACKET_ID ; 77 77 //public : SC_IN (Toperation_t ) * in_WRITE_QUEUE_IN_OPERATION ; 78 78 //public : SC_IN (Ttype_t ) * in_WRITE_QUEUE_IN_TYPE ; 79 79 public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_WRITE_RD ; 80 80 public : SC_IN (Tgeneral_address_t) * in_WRITE_QUEUE_IN_NUM_REG_RD ; … … 85 85 public : SC_IN (Texception_t ) * in_WRITE_QUEUE_IN_EXCEPTION ; 86 86 public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_NO_SEQUENCE ; 87 public : SC_IN (T general_data_t) * in_WRITE_QUEUE_IN_ADDRESS ;87 public : SC_IN (Taddress_t ) * in_WRITE_QUEUE_IN_ADDRESS ; 88 88 89 89 // -----[ Interface "Write_queue_out" ]------------------------------- … … 99 99 public : SC_OUT(Texception_t ) * out_WRITE_QUEUE_OUT_EXCEPTION ; 100 100 public : SC_OUT(Tcontrol_t ) * out_WRITE_QUEUE_OUT_NO_SEQUENCE ; 101 public : SC_OUT(T general_data_t) * out_WRITE_QUEUE_OUT_ADDRESS ;101 public : SC_OUT(Taddress_t ) * out_WRITE_QUEUE_OUT_ADDRESS ; 102 102 public : SC_OUT(Tgeneral_data_t ) * out_WRITE_QUEUE_OUT_DATA ; 103 103 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp
r88 r97 50 50 if (is_toplevel) 51 51 { 52 _size_instruction_address= size_general_data-2; 52 53 _size_context_id = log2(_nb_context ); 53 54 _size_front_end_id = log2(_nb_front_end ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp
r88 r97 60 60 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 61 61 // ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 62 62 // ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 63 63 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 64 64 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); … … 69 69 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 70 70 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 71 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);71 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 72 72 } 73 73 … … 87 87 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 88 88 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 89 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,T general_data_t,_param->_size_general_data);89 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 90 90 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); 91 91 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp
r88 r97 41 41 delete in_WRITE_QUEUE_IN_PACKET_ID ; 42 42 // delete in_WRITE_QUEUE_IN_OPERATION ; 43 delete in_WRITE_QUEUE_IN_TYPE ;43 // delete in_WRITE_QUEUE_IN_TYPE ; 44 44 delete in_WRITE_QUEUE_IN_WRITE_RD ; 45 45 delete in_WRITE_QUEUE_IN_NUM_REG_RD ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp
r88 r97 53 53 (_param->_have_port_rob_ptr )?PORT_READ(in_WRITE_QUEUE_IN_PACKET_ID ):0, 54 54 //PORT_READ(in_WRITE_QUEUE_IN_OPERATION ), 55 55 //PORT_READ(in_WRITE_QUEUE_IN_TYPE ), 56 56 PORT_READ(in_WRITE_QUEUE_IN_WRITE_RD ), 57 57 PORT_READ(in_WRITE_QUEUE_IN_NUM_REG_RD ), … … 72 72 if ( (internal_WRITE_QUEUE_OUT_VAL and PORT_READ(in_WRITE_QUEUE_OUT_ACK)) or 73 73 ((_queue->empty() == false) and 74 (_queue->front()->_type == TYPE_MEMORY) and75 (_queue->front()->_exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE) and 74 // (_queue->front()->_type == TYPE_MEMORY) and 75 (_queue->front()->_exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE) and // this exception code must be uniq 76 76 (_queue->front()->_write_rd == 0) and 77 77 (_queue->front()->_write_re == 0)))
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