Changeset 97 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src

Timestamp:

Dec 19, 2008, 4:34:00 PM (16 years ago)

Author:

rosiere

Message:

1) Update Prediction Table : statistics
2) Size instruction address on 30 bits
3) Change Log File
4) Add debug_level in simulation configuration file

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src

Files:

• Context_State_allocation.cpp (modified) (2 diffs)
• Context_State_deallocation.cpp (modified) (1 diff)
• Context_State_genMoore.cpp (modified) (3 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp

@@ -97 +97 @@
       ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EPCR          ,"address_epcr"    ,Taddress_t         ,_param->_size_instruction_address);
       ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL      ,"address_eear_val",Tcontrol_t         ,1);
-      ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EEAR          ,"address_eear"    ,Taddress_t         ,_param->_size_instruction_address);
+      ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EEAR          ,"address_eear"    ,Tgeneral_data_t    ,_param->_size_general_data);
     }
 
@@ -133 +133 @@
       ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS_NEXT_VAL             ,"address_next_val",Tcontrol_t        ,1);
       ALLOC1_SIGNAL_OUT(out_EVENT_IS_DS_TAKE                   ,"is_ds_take"      ,Tcontrol_t        ,1);
+      ALLOC1_SIGNAL_OUT(out_EVENT_TYPE                         ,"type"            ,Tevent_type_t     ,_param->_size_event_type);
+      ALLOC1_SIGNAL_OUT(out_EVENT_DEPTH                        ,"depth"           ,Tdepth_t          ,_param->_size_depth);
+
     }
 

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp

@@ -76 +76 @@
         DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL             ,_param->_nb_context,1);
         DELETE1_SIGNAL(out_EVENT_IS_DS_TAKE                   ,_param->_nb_context,1);
-        
+        DELETE1_SIGNAL(out_EVENT_TYPE                         ,_param->_nb_context,_param->_size_event_type);
+        DELETE1_SIGNAL(out_EVENT_DEPTH                        ,_param->_nb_context,_param->_size_depth);
+
         DELETE1_SIGNAL(out_SPR_EVENT_VAL                      ,_param->_nb_context,1);
         DELETE1_SIGNAL( in_SPR_EVENT_ACK                      ,_param->_nb_context,1);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp

@@ -38 +38 @@
         // SR can't change in this cycle
         // Exception Prefix High
-        Taddress_t address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
-        Taddress_t address_next     = reg_EVENT_ADDRESS_EPCR [i];
-        Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
-        Tcontrol_t is_ds_take       = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
+        Taddress_t    address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
+        Taddress_t    address_next     = reg_EVENT_ADDRESS_EPCR [i];
+        Tcontrol_t    address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
+        Tcontrol_t    is_ds_take       = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
         // excep : address exception
         // miss  : address delay_slot, and address dest
         // psync : address next
         // csync : address next
+        Tevent_type_t type                         ;//[nb_context]
+        Tdepth_t      depth            = reg_EVENT_DEPTH [i];
+
+        switch (state)
+          {
+          case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION         ); break;
+          case CONTEXT_STATE_KO_MISS_ADDR  : (type = EVENT_TYPE_MISS_SPECULATION  ); break;
+          case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC             ); break; 
+          case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC             ); break;
+          default                          : (type = EVENT_TYPE_NONE              ); break;
+          }
+//      (type = EVENT_TYPE_SPR_ACCESS        );
+//      (type = EVENT_TYPE_MSYNC             );
+//      (type = EVENT_TYPE_BRANCH_NO_ACCURATE);
+
         internal_EVENT_VAL [i] = val;
         PORT_WRITE(out_EVENT_VAL              [i], val);
@@ -52 +67 @@
         PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val);
         PORT_WRITE(out_EVENT_IS_DS_TAKE       [i], is_ds_take);
+        PORT_WRITE(out_EVENT_TYPE             [i], type);
+        if (_param->_have_port_depth)
+        PORT_WRITE(out_EVENT_DEPTH            [i], depth);
 
         log_printf(TRACE,Context_State,FUNCTION,"  * EVENT Context      : %d", i);
@@ -59 +77 @@
         log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS_NEXT_VAL : %d", address_next_val);
         log_printf(TRACE,Context_State,FUNCTION,"    * IS_DS_TAKE       : %d", is_ds_take);
+        log_printf(TRACE,Context_State,FUNCTION,"    * TYPE             : %d", type);
+        log_printf(TRACE,Context_State,FUNCTION,"    * DEPTH            : %d", depth);
       }