Changeset 98 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src
- Timestamp:
- Dec 31, 2008, 11:18:08 AM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
r97 r98 63 63 ALLOC1_VALACK_OUT(out_BRANCH_EVENT_ACK ,ACK); 64 64 // ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 65 //ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth);65 ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 66 66 // ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); 67 67 ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
r97 r98 31 31 DELETE1_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context,1); 32 32 // DELETE1_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); 33 //DELETE1_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth);33 DELETE1_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); 34 34 // DELETE1_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); 35 35 DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r95 r98 40 40 if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) 41 41 { 42 log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); 43 42 44 // throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); 43 45 44 46 context_state_t state = reg_STATE [i]; 45 47 46 Tdepth_t depth = // (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]): 47 0; 48 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; 48 49 Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; 49 50 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; … … 61 62 // is_valid = can modify local information 62 63 // if context_state_ok : yes 63 // if context_state_ko : test the depth, and the priority of e nvent64 // if context_state_ko : test the depth, and the priority of event 64 65 65 66 bool is_valid = ((state == CONTEXT_STATE_OK) or 66 67 (depth1< depth0) or 67 ((depth1==depth0) and (priority1> priority0)));68 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth 68 69 69 70 if (is_valid) … … 76 77 //reg_EVENT_ADDRESS_EEAR [i] = 0; 77 78 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; 78 reg_EVENT_IS_DELAY_SLOT [i] = dest_val;79 reg_EVENT_IS_DELAY_SLOT [i] = 1; 79 80 reg_EVENT_IS_DS_TAKE [i] = dest_val; 80 81 reg_EVENT_DEPTH [i] = depth; … … 89 90 if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) 90 91 { 92 log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); 93 91 94 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; 92 95 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; … … 190 193 if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) 191 194 { 195 log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); 196 192 197 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; 193 198 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; … … 252 257 // ------------------------------------------------------------------- 253 258 254 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 255 if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) 256 { 257 if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) 258 { 259 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 260 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 261 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 262 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 263 Tdepth_t depth_max = _param->_array_size_depth [context]; 259 // for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 260 // if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) 261 // { 262 // log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); 263 // if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) 264 // { 265 // Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 266 // Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 267 // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 268 // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 269 // Tdepth_t depth_max = _param->_array_size_depth [context]; 264 270 265 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));266 // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));267 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));268 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));271 // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 272 // // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 273 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 274 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 269 275 270 context_state_t state = reg_STATE [context];276 // context_state_t state = reg_STATE [context]; 271 277 272 // miss > excep > spr/sync273 uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);274 uint8_t priority1 = 2; // miss278 // // miss > excep > spr/sync 279 // uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 280 // uint8_t priority1 = 2; // miss 275 281 276 // is_valid = can modify local information277 // if context_state_ok : yes278 // if context_state_ko : test the depth, and the priority of envent282 // // is_valid = can modify local information 283 // // if context_state_ok : yes 284 // // if context_state_ko : test the depth, and the priority of envent 279 285 280 bool is_valid = ((state == CONTEXT_STATE_OK) or281 (depth1< depth0) or282 ((depth1==depth0) and (priority1>priority0)));286 // bool is_valid = ((state == CONTEXT_STATE_OK) or 287 // (depth1< depth0) or 288 // ((depth1==depth0) and (priority1>priority0))); 283 289 284 if (is_valid)285 {286 // commit287 Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]);288 reg_STATE [context] = CONTEXT_STATE_KO_MISS;289 reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT290 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]);291 reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence292 //reg_EVENT_ADDRESS_EEAR [context];293 reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;294 reg_EVENT_IS_DELAY_SLOT [context] = take;295 reg_EVENT_IS_DS_TAKE [context] = take;296 reg_EVENT_DEPTH [context] = depth;297 }298 }299 }290 // if (is_valid) 291 // { 292 // // commit 293 // Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); 294 // reg_STATE [context] = CONTEXT_STATE_KO_MISS; 295 // reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT 296 // reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); 297 // reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence 298 // //reg_EVENT_ADDRESS_EEAR [context]; 299 // reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; 300 // reg_EVENT_IS_DELAY_SLOT [context] = take; 301 // reg_EVENT_IS_DS_TAKE [context] = take; 302 // reg_EVENT_DEPTH [context] = depth; 303 // } 304 // } 305 // } 300 306 301 307 // ------------------------------------------------------------------- … … 305 311 if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) 306 312 { 313 log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); 307 314 // Write pc 308 315 context_state_t state = reg_STATE [i]; … … 338 345 if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) 339 346 { 347 log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); 348 340 349 // Write spr 341 350 #ifdef DEBUG_TEST -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp
r88 r98 23 23 uint32_t nb_inst_branch_complete, 24 24 uint32_t * size_depth, 25 uint32_t size_ address,25 uint32_t size_general_data, 26 26 uint32_t * size_nb_inst_decod, 27 27 uint32_t size_nb_inst_commit, … … 35 35 _nb_inst_branch_complete = nb_inst_branch_complete ; 36 36 _array_size_depth = size_depth ; 37 // _size_ address = size_address;37 // _size_general_data = size_general_data ; 38 38 // _size_nb_inst_decod = size_nb_inst_decod ; 39 39 // _size_nb_inst_commit = size_nb_inst_commit ; … … 46 46 _size_context_id = log2(_nb_context); 47 47 _size_depth = log2(max<uint32_t>(size_depth,_nb_context)); 48 _size_instruction_address = size_address; 48 _size_general_data = size_general_data; 49 _size_instruction_address = size_general_data-2; 49 50 _size_nb_inst_decod = max<uint32_t>(size_nb_inst_decod,_nb_decod_unit); 50 51 _size_nb_inst_commit = size_nb_inst_commit;
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