[15] | 1 | <?xml version='1.0' encoding='UTF-8'?> |
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| 2 | <report-views version="2.0" > |
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| 3 | <header> |
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[70] | 4 | <DateModified>2013-12-10T20:37:28</DateModified> |
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| 5 | <ModuleName>SWITCH_GEN</ModuleName> |
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| 6 | <SummaryTimeStamp>2013-11-29T16:49:35</SummaryTimeStamp> |
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[15] | 7 | <SavedFilePath>C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport</SavedFilePath> |
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| 8 | <ImplementationReportsDirectory>C:/Core MPI/CORE_MPI\</ImplementationReportsDirectory> |
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[70] | 9 | <DateInitialized>2013-06-15T13:06:16</DateInitialized> |
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[15] | 10 | <EnableMessageFiltering>false</EnableMessageFiltering> |
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| 11 | </header> |
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| 12 | <body> |
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| 13 | <viewgroup label="Design Overview" > |
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[70] | 14 | <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="true" type="FPGASummary" file="SWITCH_GEN_summary.html" label="Summary" ExpandClockNets="true" ExpandWarnings="true" > |
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[15] | 15 | <toc-item title="Design Overview" target="Design Overview" /> |
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| 16 | <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> |
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| 17 | <toc-item title="Performance Summary" target="Performance Summary" /> |
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| 18 | <toc-item title="Failing Constraints" target="Failing Constraints" /> |
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| 19 | <toc-item title="Detailed Reports" target="Detailed Reports" /> |
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[41] | 20 | <table-item tableState="CollapsedTable" tableKey="CurrentWarnings" /> |
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| 21 | <table-item tableState="CollapsedTable" tableKey="CurrentWarnings" /> |
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| 22 | <table-item tableState="ExpandedTable" tableKey="DeviceUtilizationSummary" /> |
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| 23 | <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" /> |
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[64] | 24 | <table-item tableState="CollapsedTable" tableKey="SecondaryReports" /> |
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| 25 | <table-item tableState="CollapsedTable" tableKey="DetailedReports" /> |
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[15] | 26 | </view> |
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[70] | 27 | <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="SWITCH_GEN_envsettings.html" label="System Settings" /> |
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| 28 | <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SWITCH_GEN_map.xrpt" showConstraints="0" label="IOB Properties" /> |
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| 29 | <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SWITCH_GEN_map.xrpt" label="Control Set Information" /> |
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| 30 | <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SWITCH_GEN_map.xrpt" label="Module Level Utilization" /> |
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| 31 | <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SWITCH_GEN.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> |
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| 32 | <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Pinout Report" /> |
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| 33 | <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Clock Report" /> |
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| 34 | <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SWITCH_GEN.twx" label="Static Timing" /> |
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| 35 | <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/fit/report.htm" label="CPLD Fitter Report" /> |
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| 36 | <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/tim/report.htm" label="CPLD Timing Report" /> |
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[15] | 37 | </viewgroup> |
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| 38 | <viewgroup label="XPS Errors and Warnings" > |
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| 39 | <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> |
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| 40 | <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" /> |
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| 41 | <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> |
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| 42 | <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> |
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| 43 | </viewgroup> |
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| 44 | <viewgroup label="XPS Reports" > |
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| 45 | <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> |
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| 46 | <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" /> |
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| 47 | <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> |
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| 48 | <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> |
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[70] | 49 | <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="SWITCH_GEN.log" label="System Log File" /> |
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[15] | 50 | </viewgroup> |
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| 51 | <viewgroup label="Errors and Warnings" > |
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| 52 | <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> |
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| 53 | <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" collate="1" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> |
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| 54 | <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> |
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| 55 | <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> |
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| 56 | <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> |
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| 57 | <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> |
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| 58 | <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> |
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| 59 | <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> |
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| 60 | <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> |
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| 61 | <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> |
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| 62 | <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> |
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| 63 | </viewgroup> |
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| 64 | <viewgroup label="Detailed Reports" > |
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[70] | 65 | <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="SWITCH_GEN.syr" label="Synthesis Report" > |
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[15] | 66 | <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> |
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| 67 | <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> |
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| 68 | <toc-item title="HDL Compilation" target=" HDL Compilation " /> |
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| 69 | <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> |
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| 70 | <toc-item title="HDL Analysis" target=" HDL Analysis " /> |
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| 71 | <toc-item title="HDL Parsing" target=" HDL Parsing " /> |
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| 72 | <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> |
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| 73 | <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> |
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| 74 | <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> |
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| 75 | <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> |
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| 76 | <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> |
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| 77 | <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> |
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| 78 | <toc-item title="Partition Report" target=" Partition Report " /> |
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| 79 | <toc-item title="Final Report" target=" Final Report " /> |
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| 80 | <toc-item title="Design Summary" target=" Design Summary " /> |
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| 81 | <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> |
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| 82 | <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> |
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| 83 | <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> |
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| 84 | <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> |
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| 85 | <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> |
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| 86 | <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> |
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| 87 | <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> |
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| 88 | <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> |
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| 89 | <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> |
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| 90 | </view> |
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[70] | 91 | <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.srr" label="Synplify Report" /> |
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| 92 | <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.prec_log" label="Precision Report" /> |
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| 93 | <view inputState="Synthesized" program="ngdbuild" type="Report" file="SWITCH_GEN.bld" label="Translation Report" > |
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[15] | 94 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 95 | <toc-item title="Command Line" target="Command Line:" /> |
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| 96 | <toc-item title="Partition Status" target="Partition Implementation Status" /> |
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| 97 | <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> |
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| 98 | </view> |
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[70] | 99 | <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN_map.mrp" label="Map Report" > |
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[15] | 100 | <toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
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| 101 | <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> |
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| 102 | <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> |
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| 103 | <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> |
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| 104 | <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> |
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| 105 | <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> |
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| 106 | <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> |
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| 107 | <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> |
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| 108 | <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> |
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| 109 | <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> |
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| 110 | <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> |
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| 111 | <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> |
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| 112 | <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> |
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| 113 | <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> |
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| 114 | </view> |
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[70] | 115 | <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.par" label="Place and Route Report" > |
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[15] | 116 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 117 | <toc-item title="Device Utilization" target="Device Utilization Summary:" /> |
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| 118 | <toc-item title="Router Information" target="Starting Router" /> |
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| 119 | <toc-item title="Partition Status" target="Partition Implementation Status" /> |
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| 120 | <toc-item title="Clock Report" target="Generating Clock Report" /> |
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| 121 | <toc-item title="Timing Results" target="Timing Score:" /> |
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| 122 | <toc-item title="Final Summary" target="Peak Memory Usage:" /> |
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| 123 | </view> |
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[70] | 124 | <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.twr" label="Post-PAR Static Timing Report" > |
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[15] | 125 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 126 | <toc-item title="Timing Report Description" target="Device,package,speed:" /> |
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| 127 | <toc-item title="Informational Messages" target="INFO:" /> |
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| 128 | <toc-item title="Warning Messages" target="WARNING:" /> |
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| 129 | <toc-item title="Timing Constraints" target="Timing constraint:" /> |
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| 130 | <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
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| 131 | <toc-item title="Data Sheet Report" target="Data Sheet report:" /> |
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| 132 | <toc-item title="Timing Summary" target="Timing summary:" /> |
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| 133 | <toc-item title="Trace Settings" target="Trace Settings:" /> |
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| 134 | </view> |
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[70] | 135 | <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" > |
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[15] | 136 | <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> |
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| 137 | <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> |
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| 138 | <toc-item title="Pin Resources" target="** Pin Resources **" /> |
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| 139 | <toc-item title="Global Resources" target="** Global Control Resources **" /> |
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| 140 | </view> |
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[70] | 141 | <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.tim" label="CPLD Timing Report (Text)" > |
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[15] | 142 | <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> |
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| 143 | <toc-item title="Performance Summary" target="Performance Summary:" /> |
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| 144 | </view> |
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[70] | 145 | <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SWITCH_GEN.pwr" label="Power Report" > |
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[15] | 146 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 147 | <toc-item title="Power summary" target="Power summary" /> |
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| 148 | <toc-item title="Thermal summary" target="Thermal summary" /> |
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| 149 | </view> |
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[70] | 150 | <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.bgn" label="Bitgen Report" > |
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[15] | 151 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 152 | <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> |
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| 153 | <toc-item title="Final Summary" target="DRC detected" /> |
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| 154 | </view> |
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| 155 | </viewgroup> |
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| 156 | <viewgroup label="Secondary Reports" > |
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| 157 | <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> |
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[70] | 158 | <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > |
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[15] | 159 | <toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
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| 160 | </view> |
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[70] | 161 | <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" > |
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[15] | 162 | <toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
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| 163 | </view> |
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[70] | 164 | <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> |
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| 165 | <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN_map.map" label="Map Log File" > |
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[15] | 166 | <toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
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| 167 | <toc-item title="Design Information" target="Design Information" /> |
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| 168 | <toc-item title="Design Summary" target="Design Summary" /> |
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| 169 | </view> |
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| 170 | <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> |
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[70] | 171 | <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" > |
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[15] | 172 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 173 | <toc-item title="Timing Report Description" target="Device,package,speed:" /> |
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| 174 | <toc-item title="Informational Messages" target="INFO:" /> |
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| 175 | <toc-item title="Warning Messages" target="WARNING:" /> |
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| 176 | <toc-item title="Timing Constraints" target="Timing constraint:" /> |
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| 177 | <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
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| 178 | <toc-item title="Data Sheet Report" target="Data Sheet report:" /> |
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| 179 | <toc-item title="Timing Summary" target="Timing summary:" /> |
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| 180 | <toc-item title="Trace Settings" target="Trace Settings:" /> |
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| 181 | </view> |
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[70] | 182 | <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" /> |
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| 183 | <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" > |
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[15] | 184 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 185 | </view> |
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[70] | 186 | <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" > |
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[15] | 187 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 188 | </view> |
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[70] | 189 | <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" > |
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[15] | 190 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 191 | </view> |
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[70] | 192 | <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.tsi" label="Post-Map Constraints Interaction Report" > |
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[15] | 193 | <toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
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| 194 | </view> |
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[70] | 195 | <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" /> |
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| 196 | <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" /> |
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| 197 | <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" /> |
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| 198 | <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.tsi" label="Post-Place and Route Constraints Interaction Report" > |
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[15] | 199 | <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
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| 200 | </view> |
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[70] | 201 | <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> |
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| 202 | <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> |
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| 203 | <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" > |
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[15] | 204 | <toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
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| 205 | </view> |
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[70] | 206 | <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" > |
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[15] | 207 | <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> |
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| 208 | <toc-item title="Component" target="Component " /> |
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| 209 | </view> |
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[70] | 210 | <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" > |
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[15] | 211 | <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> |
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| 212 | <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> |
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| 213 | </view> |
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[70] | 214 | <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" > |
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[15] | 215 | <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> |
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| 216 | <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> |
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| 217 | </view> |
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[70] | 218 | <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" /> |
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[15] | 219 | <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> |
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| 220 | <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> |
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| 221 | </viewgroup> |
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| 222 | </body> |
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| 223 | </report-views> |
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