[15] | 1 | -------------------------------------------------------------------------------- |
---|
| 2 | Release 12.3 Trace (nt64) |
---|
| 3 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
---|
| 4 | |
---|
| 5 | d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3 |
---|
| 6 | -n 3 -fastpaths -xml MultiMPITest.twx MultiMPITest.ncd -o MultiMPITest.twr |
---|
| 7 | MultiMPITest.pcf |
---|
| 8 | |
---|
| 9 | Design file: MultiMPITest.ncd |
---|
| 10 | Physical constraint file: MultiMPITest.pcf |
---|
| 11 | Device,package,speed: xc6slx100,fgg484,C,-3 (PRODUCTION 1.12c 2010-09-15) |
---|
| 12 | Report level: verbose report |
---|
| 13 | |
---|
| 14 | Environment Variable Effect |
---|
| 15 | -------------------- ------ |
---|
| 16 | NONE No environment variables were set |
---|
| 17 | -------------------------------------------------------------------------------- |
---|
| 18 | |
---|
| 19 | INFO:Timing:2698 - No timing constraints found, doing default enumeration. |
---|
| 20 | INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths |
---|
| 21 | option. All paths that are not constrained will be reported in the |
---|
| 22 | unconstrained paths section(s) of the report. |
---|
| 23 | INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on |
---|
| 24 | a 50 Ohm transmission line loading model. For the details of this model, |
---|
| 25 | and for more information on accounting for different loading conditions, |
---|
| 26 | please see the device datasheet. |
---|
| 27 | |
---|
| 28 | |
---|
| 29 | |
---|
| 30 | Data Sheet report: |
---|
| 31 | ----------------- |
---|
| 32 | All values displayed in nanoseconds (ns) |
---|
| 33 | |
---|
| 34 | Setup/Hold to clock clkm |
---|
| 35 | ------------+------------+------------+------------+------------+------------------+--------+ |
---|
| 36 | |Max Setup to| Process |Max Hold to | Process | | Clock | |
---|
| 37 | Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | |
---|
| 38 | ------------+------------+------------+------------+------------+------------------+--------+ |
---|
| 39 | reset | 16.672(R)| SLOW | 0.529(R)| SLOW |clkm_BUFGP | 0.000| |
---|
| 40 | ------------+------------+------------+------------+------------+------------------+--------+ |
---|
| 41 | |
---|
| 42 | Clock clkm to Pad |
---|
| 43 | ------------+-----------------+------------+-----------------+------------+------------------+--------+ |
---|
| 44 | |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | |
---|
| 45 | Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | |
---|
| 46 | ------------+-----------------+------------+-----------------+------------+------------------+--------+ |
---|
| 47 | result<0> | 8.688(R)| SLOW | 4.230(R)| FAST |clkm_BUFGP | 0.000| |
---|
| 48 | result<1> | 9.023(R)| SLOW | 4.224(R)| FAST |clkm_BUFGP | 0.000| |
---|
| 49 | result<4> | 8.935(R)| SLOW | 4.334(R)| FAST |clkm_BUFGP | 0.000| |
---|
| 50 | result<5> | 12.060(R)| SLOW | 5.801(R)| FAST |clkm_BUFGP | 0.000| |
---|
| 51 | ------------+-----------------+------------+-----------------+------------+------------------+--------+ |
---|
| 52 | |
---|
| 53 | Clock to Setup on destination clock clkm |
---|
| 54 | ---------------+---------+---------+---------+---------+ |
---|
| 55 | | Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
---|
| 56 | Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
---|
| 57 | ---------------+---------+---------+---------+---------+ |
---|
| 58 | clkm | 9.399| | | | |
---|
| 59 | ---------------+---------+---------+---------+---------+ |
---|
| 60 | |
---|
| 61 | |
---|
| 62 | Analysis completed Tue Aug 14 16:12:09 2012 |
---|
| 63 | -------------------------------------------------------------------------------- |
---|
| 64 | |
---|
| 65 | Trace Settings: |
---|
| 66 | ------------------------- |
---|
| 67 | Trace Settings |
---|
| 68 | |
---|
| 69 | Peak Memory Usage: 420 MB |
---|
| 70 | |
---|
| 71 | |
---|
| 72 | |
---|