[71] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 18:01:21 10/23/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: proto_send - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | USE ieee.numeric_std.ALL; |
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| 23 | use work.CoreTypes.all; |
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| 24 | -- Uncomment the following library declaration if using |
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| 25 | -- arithmetic functions with Signed or Unsigned values |
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| 26 | --use IEEE.NUMERIC_STD.ALL; |
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| 27 | |
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| 28 | -- Uncomment the following library declaration if instantiating |
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| 29 | -- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity proto_send is |
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| 34 | generic (sizemem : natural := 64); |
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| 35 | port ( |
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| 36 | clk,reset : in std_logic; |
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| 37 | fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée |
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| 38 | fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie |
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| 39 | fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie |
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| 40 | fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée |
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| 41 | fifo_in_data_out : in std_logic_vector(Word-1 downto 0); |
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| 42 | fifo_out_data_in : out std_logic_vector(Word-1 downto 0); |
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| 43 | packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet |
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| 44 | copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo |
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| 45 | snd_start : in std_logic; --début de la réception |
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| 46 | snd_ack :in std_logic; -- acquittement de la réception |
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| 47 | snd_comp : out std_logic; -- fin de la réception |
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| 48 | mem :in memory(0 to sizemem-1)); --données à copier vers le fifo |
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| 49 | |
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| 50 | end proto_send; |
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| 51 | |
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| 52 | architecture Behavioral of proto_send is |
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| 53 | type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end); |
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| 54 | signal etsnd : typ_send; |
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| 55 | signal snd_state,next_snd_state:natural range 0 to 7:=0; |
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| 56 | signal p_len,p_len_i : natural range 0 to 255; |
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| 57 | signal n,n_i:natural range 0 to 7; |
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| 58 | signal wr_ok,rd_ok:std_logic:='0'; |
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| 59 | signal sfifo_in,Data_to_send : std_logic_vector(Word-1 downto 0); |
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| 60 | signal spush : std_logic:='0'; |
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| 61 | signal err : std_logic_vector(Word-1 downto 0):=(others =>'0'); |
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| 62 | begin |
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| 63 | |
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| 64 | Fifo_copy_sync:process(clk) |
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| 65 | |
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| 66 | begin |
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| 67 | if rising_edge(clk) then |
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| 68 | |
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| 69 | if reset='1' then |
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| 70 | n<=0; |
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| 71 | Snd_state<=0; |
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| 72 | P_len<=0; |
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| 73 | else |
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| 74 | Snd_state<=Next_Snd_state; |
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| 75 | n<=n_i; |
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| 76 | p_len<=P_len_i; |
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| 77 | end if; |
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| 78 | end if; |
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| 79 | end process fifo_copy_sync; |
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| 80 | -- affectation concurentes |
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| 81 | Fifo_copy_val:process (Snd_state,Etsnd,copy_mode,data_to_send,rd_ok,wr_ok,spush) |
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| 82 | begin |
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| 83 | if copy_mode='0' then |
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| 84 | fifo_out_wr_en<=wr_ok; |
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| 85 | fifo_out_data_in<=data_to_send; |
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| 86 | fifo_in_rd_en<='0'; |
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| 87 | else |
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| 88 | if (Snd_state=1) or (snd_state=2) then |
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| 89 | fifo_out_wr_en<=wr_ok; |
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| 90 | fifo_in_rd_en<=rd_ok; |
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| 91 | fifo_out_data_in<=data_to_send; |
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| 92 | end if; |
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| 93 | end if; |
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| 94 | end process fifo_copy_val; |
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| 95 | -- process qui envoie des données en provenance d'un Fifo vers un Fifo |
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| 96 | FIfo_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack,fifo_in_empty, |
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| 97 | fifo_out_full,Fifo_in_data_out,p_len) |
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| 98 | variable onepop:std_logic:='0'; |
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| 99 | begin |
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| 100 | Next_snd_state<=snd_state; --valeur par defaut |
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| 101 | case snd_state is |
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| 102 | |
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| 103 | when 0 => if snd_start='1' then |
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| 104 | P_len_i<=to_integer(unsigned(packet_len)); |
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| 105 | next_snd_state<=1; |
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| 106 | n_i<=0; |
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| 107 | end if; |
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| 108 | wr_ok<='0';rd_ok<='0';onepop:='0'; |
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| 109 | snd_comp<='0'; |
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| 110 | when 1=> if P_len>0 then |
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| 111 | if copy_mode='1' then |
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| 112 | if fifo_in_empty='0' and onepop='0' then |
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| 113 | data_to_send <=fifo_in_data_out ; |
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| 114 | rd_Ok<='1'; |
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| 115 | onepop:=not onepop; --une donnée lue il faut arrêter de dépiler |
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| 116 | |
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| 117 | else |
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| 118 | rd_Ok<='0'; |
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| 119 | end if; |
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| 120 | else |
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| 121 | onepop:='1'; |
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| 122 | data_to_send<=mem(n); |
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| 123 | end if; |
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| 124 | |
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| 125 | if (fifo_out_full = '0') and onepop='1' then wr_ok<='1'; |
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| 126 | onepop:=not onepop; |
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| 127 | wr_ok<='1'; |
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| 128 | p_len_i<=p_len-1; |
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| 129 | n_i<=n+1; |
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| 130 | |
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| 131 | else |
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| 132 | wr_Ok<='0'; |
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| 133 | |
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| 134 | end if; |
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| 135 | else |
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| 136 | rd_ok<='0';wr_ok<='0'; |
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| 137 | next_snd_state<=2; |
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| 138 | snd_comp<='1'; |
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| 139 | end if; |
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| 140 | when 2 => --fin de la copie |
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| 141 | if snd_ack='1' then |
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| 142 | |
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| 143 | next_snd_state<=3; |
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| 144 | end if; |
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| 145 | wr_ok<='0';rd_ok<='0'; |
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| 146 | snd_comp<='1'; |
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| 147 | data_to_send <=(others=>'-'); |
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| 148 | when 3 =>next_snd_state<=0; |
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| 149 | snd_comp<='0'; |
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| 150 | |
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| 151 | when others => next_snd_state<=0; |
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| 152 | snd_comp<='0'; |
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| 153 | rd_ok<='0'; |
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| 154 | wr_ok<='0'; |
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| 155 | data_to_send <=(others=>'-'); |
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| 156 | end case; |
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| 157 | end process FIfo_to_fifo; |
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| 158 | |
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| 159 | end Behavioral; |
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| 160 | |
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