Changeset 136 for PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/Test_Timer.xise
- Timestamp:
- Apr 8, 2014, 5:47:05 PM (10 years ago)
- File:
-
- 1 edited
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PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/Test_Timer.xise
r128 r136 17 17 <files> 18 18 <file xil_pn:name="../NoC/Arbiter.vhd" xil_pn:type="FILE_VHDL"> 19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> 20 <association xil_pn:name="Implementation" xil_pn:seqID="3"/> 21 <library xil_pn:name="NoCLib"/> 22 </file> 23 <file xil_pn:name="../NoC/conv.vhd" xil_pn:type="FILE_VHDL"> 24 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 25 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 26 <library xil_pn:name="NoCLib"/> 27 </file> 28 <file xil_pn:name="../NoC/CoreTypes.vhd" xil_pn:type="FILE_VHDL"> 19 29 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> 20 30 <association xil_pn:name="Implementation" xil_pn:seqID="2"/> 21 31 <library xil_pn:name="NoCLib"/> 22 32 </file> 23 <file xil_pn:name="../NoC/conv.vhd" xil_pn:type="FILE_VHDL"> 24 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 25 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 26 <library xil_pn:name="NoCLib"/> 27 </file> 28 <file xil_pn:name="../NoC/CoreTypes.vhd" xil_pn:type="FILE_VHDL"> 33 <file xil_pn:name="../NoC/Crossbar.vhd" xil_pn:type="FILE_VHDL"> 34 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/> 35 <association xil_pn:name="Implementation" xil_pn:seqID="24"/> 36 <library xil_pn:name="NoCLib"/> 37 </file> 38 <file xil_pn:name="../NoC/Crossbit.vhd" xil_pn:type="FILE_VHDL"> 39 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> 40 <association xil_pn:name="Implementation" xil_pn:seqID="20"/> 41 <library xil_pn:name="NoCLib"/> 42 </file> 43 <file xil_pn:name="../NoC/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL"> 44 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> 45 <association xil_pn:name="Implementation" xil_pn:seqID="19"/> 46 <library xil_pn:name="NoCLib"/> 47 </file> 48 <file xil_pn:name="../NoC/FIFO_DP.vhd" xil_pn:type="FILE_VHDL"> 49 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 50 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 51 <library xil_pn:name="NoCLib"/> 52 </file> 53 <file xil_pn:name="../NoC/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL"> 54 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> 55 <association xil_pn:name="Implementation" xil_pn:seqID="23"/> 56 <library xil_pn:name="NoCLib"/> 57 </file> 58 <file xil_pn:name="../NoC/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL"> 59 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/> 60 <association xil_pn:name="Implementation" xil_pn:seqID="22"/> 61 <library xil_pn:name="NoCLib"/> 62 </file> 63 <file xil_pn:name="../NoC/PortRam.vhd" xil_pn:type="FILE_VHDL"> 64 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 65 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 66 <library xil_pn:name="NoCLib"/> 67 </file> 68 <file xil_pn:name="../NoC/Proto_receiv.vhd" xil_pn:type="FILE_VHDL"> 69 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> 70 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 71 <library xil_pn:name="NoCLib"/> 72 </file> 73 <file xil_pn:name="../NoC/proto_send.vhd" xil_pn:type="FILE_VHDL"> 74 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> 75 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 76 <library xil_pn:name="NoCLib"/> 77 </file> 78 <file xil_pn:name="../NoC/RAM_256.vhd" xil_pn:type="FILE_VHDL"> 79 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 80 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 81 <library xil_pn:name="NoCLib"/> 82 </file> 83 <file xil_pn:name="../NoC/Scheduler.vhd" xil_pn:type="FILE_VHDL"> 84 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/> 85 <association xil_pn:name="Implementation" xil_pn:seqID="21"/> 86 <library xil_pn:name="NoCLib"/> 87 </file> 88 <file xil_pn:name="../NoC/SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL"> 89 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> 90 <association xil_pn:name="Implementation" xil_pn:seqID="18"/> 91 <library xil_pn:name="NoCLib"/> 92 </file> 93 <file xil_pn:name="../NoC/SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL"> 94 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> 95 <association xil_pn:name="Implementation" xil_pn:seqID="17"/> 96 <library xil_pn:name="NoCLib"/> 97 </file> 98 <file xil_pn:name="../NoC/SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL"> 99 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> 100 <association xil_pn:name="Implementation" xil_pn:seqID="16"/> 101 <library xil_pn:name="NoCLib"/> 102 </file> 103 <file xil_pn:name="../NoC/SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL"> 104 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> 105 <association xil_pn:name="Implementation" xil_pn:seqID="15"/> 106 <library xil_pn:name="NoCLib"/> 107 </file> 108 <file xil_pn:name="../NoC/SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL"> 109 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> 110 <association xil_pn:name="Implementation" xil_pn:seqID="14"/> 111 <library xil_pn:name="NoCLib"/> 112 </file> 113 <file xil_pn:name="../NoC/SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL"> 114 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> 115 <association xil_pn:name="Implementation" xil_pn:seqID="13"/> 116 <library xil_pn:name="NoCLib"/> 117 </file> 118 <file xil_pn:name="../NoC/SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL"> 119 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> 120 <association xil_pn:name="Implementation" xil_pn:seqID="12"/> 121 <library xil_pn:name="NoCLib"/> 122 </file> 123 <file xil_pn:name="../NoC/SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL"> 124 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> 125 <association xil_pn:name="Implementation" xil_pn:seqID="11"/> 126 <library xil_pn:name="NoCLib"/> 127 </file> 128 <file xil_pn:name="../NoC/SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL"> 129 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> 130 <association xil_pn:name="Implementation" xil_pn:seqID="10"/> 131 <library xil_pn:name="NoCLib"/> 132 </file> 133 <file xil_pn:name="../NoC/SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL"> 134 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> 135 <association xil_pn:name="Implementation" xil_pn:seqID="9"/> 136 <library xil_pn:name="NoCLib"/> 137 </file> 138 <file xil_pn:name="../NoC/SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL"> 139 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> 140 <association xil_pn:name="Implementation" xil_pn:seqID="8"/> 141 <library xil_pn:name="NoCLib"/> 142 </file> 143 <file xil_pn:name="../NoC/SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL"> 144 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> 145 <association xil_pn:name="Implementation" xil_pn:seqID="7"/> 146 <library xil_pn:name="NoCLib"/> 147 </file> 148 <file xil_pn:name="../NoC/SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL"> 149 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> 150 <association xil_pn:name="Implementation" xil_pn:seqID="6"/> 151 <library xil_pn:name="NoCLib"/> 152 </file> 153 <file xil_pn:name="../NoC/SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL"> 154 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> 155 <association xil_pn:name="Implementation" xil_pn:seqID="5"/> 156 <library xil_pn:name="NoCLib"/> 157 </file> 158 <file xil_pn:name="../NoC/SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL"> 159 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> 160 <association xil_pn:name="Implementation" xil_pn:seqID="4"/> 161 <library xil_pn:name="NoCLib"/> 162 </file> 163 <file xil_pn:name="../NoC/stimuli1.vhd" xil_pn:type="FILE_VHDL"> 164 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 165 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 166 <library xil_pn:name="NoCLib"/> 167 </file> 168 <file xil_pn:name="../NoC/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL"> 169 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/> 170 <association xil_pn:name="Implementation" xil_pn:seqID="25"/> 171 <library xil_pn:name="NoCLib"/> 172 </file> 173 <file xil_pn:name="../NoC/SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL"> 174 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 175 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 176 <library xil_pn:name="NoCLib"/> 177 </file> 178 <file xil_pn:name="../NoC/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL"> 179 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 180 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 181 <library xil_pn:name="NoCLib"/> 182 </file> 183 <file xil_pn:name="../Core_MPI/CORE_MPI.vhd" xil_pn:type="FILE_VHDL"> 184 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/> 185 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 186 <library xil_pn:name="MPI_HCL"/> 187 </file> 188 <file xil_pn:name="../Core_MPI/DEMUX1.vhd" xil_pn:type="FILE_VHDL"> 189 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> 190 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 191 <library xil_pn:name="MPI_HCL"/> 192 </file> 193 <file xil_pn:name="../Core_MPI/DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL"> 194 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/> 195 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 196 <library xil_pn:name="MPI_HCL"/> 197 </file> 198 <file xil_pn:name="../Core_MPI/Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL"> 199 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/> 200 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 201 <library xil_pn:name="MPI_HCL"/> 202 </file> 203 <file xil_pn:name="../Core_MPI/EX1_FSM.vhd" xil_pn:type="FILE_VHDL"> 204 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/> 205 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 206 <library xil_pn:name="MPI_HCL"/> 207 </file> 208 <file xil_pn:name="../Core_MPI/EX2_FSM.vhd" xil_pn:type="FILE_VHDL"> 209 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/> 210 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 211 <library xil_pn:name="MPI_HCL"/> 212 </file> 213 <file xil_pn:name="../Core_MPI/EX3_FSM.vhd" xil_pn:type="FILE_VHDL"> 214 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/> 215 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 216 <library xil_pn:name="MPI_HCL"/> 217 </file> 218 <file xil_pn:name="../Core_MPI/EX4_FSM.vhd" xil_pn:type="FILE_VHDL"> 219 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/> 220 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 221 <library xil_pn:name="MPI_HCL"/> 222 </file> 223 <file xil_pn:name="../Core_MPI/Ex5_FSM.vhd" xil_pn:type="FILE_VHDL"> 224 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 225 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 226 <library xil_pn:name="MPI_HCL"/> 227 </file> 228 <file xil_pn:name="../Core_MPI/FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL"> 229 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/> 230 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 231 <library xil_pn:name="MPI_HCL"/> 232 </file> 233 <file xil_pn:name="../Core_MPI/FIfo_mem.vhd" xil_pn:type="FILE_VHDL"> 234 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 235 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 236 <library xil_pn:name="MPI_HCL"/> 237 </file> 238 <file xil_pn:name="../Core_MPI/FIfo_proc.vhd" xil_pn:type="FILE_VHDL"> 239 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 240 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 241 <library xil_pn:name="MPI_HCL"/> 242 </file> 243 <file xil_pn:name="../Core_MPI/image_pkg.vhd" xil_pn:type="FILE_VHDL"> 244 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 245 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 246 <library xil_pn:name="MPI_HCL"/> 247 </file> 248 <file xil_pn:name="../Core_MPI/load_instr.vhd" xil_pn:type="FILE_VHDL"> 249 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/> 250 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 251 <library xil_pn:name="MPI_HCL"/> 252 </file> 253 <file xil_pn:name="../Core_MPI/MPICORETEST.vhd" xil_pn:type="FILE_VHDL"> 254 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 255 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 256 <library xil_pn:name="MPI_HCL"/> 257 </file> 258 <file xil_pn:name="../Core_MPI/MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL"> 259 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/> 260 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 261 <library xil_pn:name="MPI_HCL"/> 262 </file> 263 <file xil_pn:name="../Core_MPI/MPI_NOC.vhd" xil_pn:type="FILE_VHDL"> 264 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/> 265 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 266 <library xil_pn:name="MPI_HCL"/> 267 </file> 268 <file xil_pn:name="../Core_MPI/MPI_PKG.vhd" xil_pn:type="FILE_VHDL"> 269 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 270 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 271 <library xil_pn:name="MPI_HCL"/> 272 </file> 273 <file xil_pn:name="../Core_MPI/MPI_RMA.vhd" xil_pn:type="FILE_VHDL"> 274 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/> 275 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 276 <library xil_pn:name="MPI_HCL"/> 277 </file> 278 <file xil_pn:name="../Core_MPI/MultiMPITest.vhd" xil_pn:type="FILE_VHDL"> 279 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/> 280 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 281 </file> 282 <file xil_pn:name="../Core_MPI/MUX1.vhd" xil_pn:type="FILE_VHDL"> 283 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> 284 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 285 <library xil_pn:name="MPI_HCL"/> 286 </file> 287 <file xil_pn:name="../Core_MPI/MUX8.vhd" xil_pn:type="FILE_VHDL"> 288 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> 289 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 290 <library xil_pn:name="MPI_HCL"/> 291 </file> 292 <file xil_pn:name="../Core_MPI/Packet_type.vhd" xil_pn:type="FILE_VHDL"> 293 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> 294 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 295 <library xil_pn:name="MPI_HCL"/> 296 </file> 297 <file xil_pn:name="../Core_MPI/RAM_32_32.vhd" xil_pn:type="FILE_VHDL"> 298 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 299 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 300 <library xil_pn:name="MPI_HCL"/> 301 </file> 302 <file xil_pn:name="../Core_MPI/RAM_64.vhd" xil_pn:type="FILE_VHDL"> 303 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 304 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 305 <library xil_pn:name="MPI_HCL"/> 306 </file> 307 <file xil_pn:name="../Core_MPI/RAM_MUX.vhd" xil_pn:type="FILE_VHDL"> 308 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 309 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 310 <library xil_pn:name="MPI_HCL"/> 311 </file> 312 <file xil_pn:name="../Core_MPI/round_robbin_machine.vhd" xil_pn:type="FILE_VHDL"> 313 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> 314 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 315 <library xil_pn:name="MPI_HCL"/> 316 </file> 317 <file xil_pn:name="../Core_MPI/SetBit.vhd" xil_pn:type="FILE_VHDL"> 318 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> 319 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 320 <library xil_pn:name="MPI_HCL"/> 321 </file> 322 <file xil_pn:name="../Core_MPI/test_DMA.vhd" xil_pn:type="FILE_VHDL"> 323 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 324 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 325 <library xil_pn:name="MPI_HCL"/> 326 </file> 327 <file xil_pn:name="../HCL_Arch_conf.vhd" xil_pn:type="FILE_VHDL"> 328 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/> 329 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 330 </file> 331 <file xil_pn:name="../Hold_FSM.vhd" xil_pn:type="FILE_VHDL"> 332 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/> 333 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 334 </file> 335 <file xil_pn:name="../HT_process.vhd" xil_pn:type="FILE_VHDL"> 336 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/> 337 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 338 </file> 339 <file xil_pn:name="../IP_Timer.vhd" xil_pn:type="FILE_VHDL"> 340 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> 341 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 342 </file> 343 <file xil_pn:name="../PE.vhd" xil_pn:type="FILE_VHDL"> 344 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/> 345 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 346 </file> 347 <file xil_pn:name="../mpi_test.vhd" xil_pn:type="FILE_VHDL"> 348 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/> 349 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 350 </file> 351 <file xil_pn:name="ipcore_dir/mem_4k8.xco" xil_pn:type="FILE_COREGEN"> 352 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> 353 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 354 </file> 355 <file xil_pn:name="ipcore_dir/mem8k8.xco" xil_pn:type="FILE_COREGEN"> 356 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/> 357 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 358 </file> 359 <file xil_pn:name="../NOC/Def_Request.vhd" xil_pn:type="FILE_VHDL"> 29 360 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> 30 361 <association xil_pn:name="Implementation" xil_pn:seqID="1"/> 31 362 <library xil_pn:name="NoCLib"/> 32 </file>33 <file xil_pn:name="../NoC/Crossbar.vhd" xil_pn:type="FILE_VHDL">34 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>35 <association xil_pn:name="Implementation" xil_pn:seqID="31"/>36 <library xil_pn:name="NoCLib"/>37 </file>38 <file xil_pn:name="../NoC/Crossbit.vhd" xil_pn:type="FILE_VHDL">39 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>40 <association xil_pn:name="Implementation" xil_pn:seqID="21"/>41 <library xil_pn:name="NoCLib"/>42 </file>43 <file xil_pn:name="../NoC/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">44 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>45 <association xil_pn:name="Implementation" xil_pn:seqID="20"/>46 <library xil_pn:name="NoCLib"/>47 </file>48 <file xil_pn:name="../NoC/FIFO_DP.vhd" xil_pn:type="FILE_VHDL">49 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>50 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>51 <library xil_pn:name="NoCLib"/>52 </file>53 <file xil_pn:name="../NoC/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">54 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>55 <association xil_pn:name="Implementation" xil_pn:seqID="30"/>56 <library xil_pn:name="NoCLib"/>57 </file>58 <file xil_pn:name="../NoC/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">59 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>60 <association xil_pn:name="Implementation" xil_pn:seqID="29"/>61 <library xil_pn:name="NoCLib"/>62 </file>63 <file xil_pn:name="../NoC/PortRam.vhd" xil_pn:type="FILE_VHDL">64 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>65 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>66 <library xil_pn:name="NoCLib"/>67 </file>68 <file xil_pn:name="../NoC/Proto_receiv.vhd" xil_pn:type="FILE_VHDL">69 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>70 <association xil_pn:name="Implementation" xil_pn:seqID="19"/>71 <library xil_pn:name="NoCLib"/>72 </file>73 <file xil_pn:name="../NoC/proto_send.vhd" xil_pn:type="FILE_VHDL">74 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>75 <association xil_pn:name="Implementation" xil_pn:seqID="18"/>76 <library xil_pn:name="NoCLib"/>77 </file>78 <file xil_pn:name="../NoC/RAM_256.vhd" xil_pn:type="FILE_VHDL">79 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>80 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>81 <library xil_pn:name="NoCLib"/>82 </file>83 <file xil_pn:name="../NoC/Scheduler.vhd" xil_pn:type="FILE_VHDL">84 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>85 <association xil_pn:name="Implementation" xil_pn:seqID="28"/>86 <library xil_pn:name="NoCLib"/>87 </file>88 <file xil_pn:name="../NoC/SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL">89 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>90 <association xil_pn:name="Implementation" xil_pn:seqID="17"/>91 <library xil_pn:name="NoCLib"/>92 </file>93 <file xil_pn:name="../NoC/SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL">94 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>95 <association xil_pn:name="Implementation" xil_pn:seqID="16"/>96 <library xil_pn:name="NoCLib"/>97 </file>98 <file xil_pn:name="../NoC/SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL">99 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>100 <association xil_pn:name="Implementation" xil_pn:seqID="15"/>101 <library xil_pn:name="NoCLib"/>102 </file>103 <file xil_pn:name="../NoC/SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL">104 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>105 <association xil_pn:name="Implementation" xil_pn:seqID="14"/>106 <library xil_pn:name="NoCLib"/>107 </file>108 <file xil_pn:name="../NoC/SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL">109 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>110 <association xil_pn:name="Implementation" xil_pn:seqID="13"/>111 <library xil_pn:name="NoCLib"/>112 </file>113 <file xil_pn:name="../NoC/SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL">114 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>115 <association xil_pn:name="Implementation" xil_pn:seqID="12"/>116 <library xil_pn:name="NoCLib"/>117 </file>118 <file xil_pn:name="../NoC/SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL">119 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>120 <association xil_pn:name="Implementation" xil_pn:seqID="11"/>121 <library xil_pn:name="NoCLib"/>122 </file>123 <file xil_pn:name="../NoC/SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL">124 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>125 <association xil_pn:name="Implementation" xil_pn:seqID="10"/>126 <library xil_pn:name="NoCLib"/>127 </file>128 <file xil_pn:name="../NoC/SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL">129 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>130 <association xil_pn:name="Implementation" xil_pn:seqID="9"/>131 <library xil_pn:name="NoCLib"/>132 </file>133 <file xil_pn:name="../NoC/SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL">134 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>135 <association xil_pn:name="Implementation" xil_pn:seqID="8"/>136 <library xil_pn:name="NoCLib"/>137 </file>138 <file xil_pn:name="../NoC/SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL">139 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>140 <association xil_pn:name="Implementation" xil_pn:seqID="7"/>141 <library xil_pn:name="NoCLib"/>142 </file>143 <file xil_pn:name="../NoC/SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL">144 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>145 <association xil_pn:name="Implementation" xil_pn:seqID="6"/>146 <library xil_pn:name="NoCLib"/>147 </file>148 <file xil_pn:name="../NoC/SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL">149 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>150 <association xil_pn:name="Implementation" xil_pn:seqID="5"/>151 <library xil_pn:name="NoCLib"/>152 </file>153 <file xil_pn:name="../NoC/SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL">154 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>155 <association xil_pn:name="Implementation" xil_pn:seqID="4"/>156 <library xil_pn:name="NoCLib"/>157 </file>158 <file xil_pn:name="../NoC/SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL">159 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>160 <association xil_pn:name="Implementation" xil_pn:seqID="3"/>161 <library xil_pn:name="NoCLib"/>162 </file>163 <file xil_pn:name="../NoC/stimuli1.vhd" xil_pn:type="FILE_VHDL">164 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>165 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>166 <library xil_pn:name="NoCLib"/>167 </file>168 <file xil_pn:name="../NoC/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">169 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>170 <association xil_pn:name="Implementation" xil_pn:seqID="44"/>171 <library xil_pn:name="NoCLib"/>172 </file>173 <file xil_pn:name="../NoC/SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL">174 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>175 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>176 <library xil_pn:name="NoCLib"/>177 </file>178 <file xil_pn:name="../NoC/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">179 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>180 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>181 <library xil_pn:name="NoCLib"/>182 </file>183 <file xil_pn:name="../Core_MPI/CORE_MPI.vhd" xil_pn:type="FILE_VHDL">184 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>185 <association xil_pn:name="Implementation" xil_pn:seqID="47"/>186 <library xil_pn:name="MPI_HCL"/>187 </file>188 <file xil_pn:name="../Core_MPI/DEMUX1.vhd" xil_pn:type="FILE_VHDL">189 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>190 <association xil_pn:name="Implementation" xil_pn:seqID="27"/>191 <library xil_pn:name="MPI_HCL"/>192 </file>193 <file xil_pn:name="../Core_MPI/DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL">194 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>195 <association xil_pn:name="Implementation" xil_pn:seqID="42"/>196 <library xil_pn:name="MPI_HCL"/>197 </file>198 <file xil_pn:name="../Core_MPI/Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL">199 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>200 <association xil_pn:name="Implementation" xil_pn:seqID="41"/>201 <library xil_pn:name="MPI_HCL"/>202 </file>203 <file xil_pn:name="../Core_MPI/EX1_FSM.vhd" xil_pn:type="FILE_VHDL">204 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>205 <association xil_pn:name="Implementation" xil_pn:seqID="40"/>206 <library xil_pn:name="MPI_HCL"/>207 </file>208 <file xil_pn:name="../Core_MPI/EX2_FSM.vhd" xil_pn:type="FILE_VHDL">209 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>210 <association xil_pn:name="Implementation" xil_pn:seqID="39"/>211 <library xil_pn:name="MPI_HCL"/>212 </file>213 <file xil_pn:name="../Core_MPI/EX3_FSM.vhd" xil_pn:type="FILE_VHDL">214 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>215 <association xil_pn:name="Implementation" xil_pn:seqID="38"/>216 <library xil_pn:name="MPI_HCL"/>217 </file>218 <file xil_pn:name="../Core_MPI/EX4_FSM.vhd" xil_pn:type="FILE_VHDL">219 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>220 <association xil_pn:name="Implementation" xil_pn:seqID="37"/>221 <library xil_pn:name="MPI_HCL"/>222 </file>223 <file xil_pn:name="../Core_MPI/Ex5_FSM.vhd" xil_pn:type="FILE_VHDL">224 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>225 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>226 <library xil_pn:name="MPI_HCL"/>227 </file>228 <file xil_pn:name="../Core_MPI/FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL">229 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>230 <association xil_pn:name="Implementation" xil_pn:seqID="36"/>231 <library xil_pn:name="MPI_HCL"/>232 </file>233 <file xil_pn:name="../Core_MPI/FIfo_mem.vhd" xil_pn:type="FILE_VHDL">234 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>235 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>236 <library xil_pn:name="MPI_HCL"/>237 </file>238 <file xil_pn:name="../Core_MPI/FIfo_proc.vhd" xil_pn:type="FILE_VHDL">239 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>240 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>241 <library xil_pn:name="MPI_HCL"/>242 </file>243 <file xil_pn:name="../Core_MPI/image_pkg.vhd" xil_pn:type="FILE_VHDL">244 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>245 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>246 <library xil_pn:name="MPI_HCL"/>247 </file>248 <file xil_pn:name="../Core_MPI/load_instr.vhd" xil_pn:type="FILE_VHDL">249 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>250 <association xil_pn:name="Implementation" xil_pn:seqID="35"/>251 <library xil_pn:name="MPI_HCL"/>252 </file>253 <file xil_pn:name="../Core_MPI/MPICORETEST.vhd" xil_pn:type="FILE_VHDL">254 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>255 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>256 <library xil_pn:name="MPI_HCL"/>257 </file>258 <file xil_pn:name="../Core_MPI/MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL">259 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>260 <association xil_pn:name="Implementation" xil_pn:seqID="34"/>261 <library xil_pn:name="MPI_HCL"/>262 </file>263 <file xil_pn:name="../Core_MPI/MPI_NOC.vhd" xil_pn:type="FILE_VHDL">264 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>265 <association xil_pn:name="Implementation" xil_pn:seqID="50"/>266 <library xil_pn:name="MPI_HCL"/>267 </file>268 <file xil_pn:name="../Core_MPI/MPI_PKG.vhd" xil_pn:type="FILE_VHDL">269 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>270 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>271 <library xil_pn:name="MPI_HCL"/>272 </file>273 <file xil_pn:name="../Core_MPI/MPI_RMA.vhd" xil_pn:type="FILE_VHDL">274 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>275 <association xil_pn:name="Implementation" xil_pn:seqID="33"/>276 <library xil_pn:name="MPI_HCL"/>277 </file>278 <file xil_pn:name="../Core_MPI/MultiMPITest.vhd" xil_pn:type="FILE_VHDL">279 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>280 <association xil_pn:name="Implementation" xil_pn:seqID="51"/>281 </file>282 <file xil_pn:name="../Core_MPI/MUX1.vhd" xil_pn:type="FILE_VHDL">283 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>284 <association xil_pn:name="Implementation" xil_pn:seqID="26"/>285 <library xil_pn:name="MPI_HCL"/>286 </file>287 <file xil_pn:name="../Core_MPI/MUX8.vhd" xil_pn:type="FILE_VHDL">288 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>289 <association xil_pn:name="Implementation" xil_pn:seqID="25"/>290 <library xil_pn:name="MPI_HCL"/>291 </file>292 <file xil_pn:name="../Core_MPI/Packet_type.vhd" xil_pn:type="FILE_VHDL">293 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>294 <association xil_pn:name="Implementation" xil_pn:seqID="24"/>295 <library xil_pn:name="MPI_HCL"/>296 </file>297 <file xil_pn:name="../Core_MPI/RAM_32_32.vhd" xil_pn:type="FILE_VHDL">298 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>299 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>300 <library xil_pn:name="MPI_HCL"/>301 </file>302 <file xil_pn:name="../Core_MPI/RAM_64.vhd" xil_pn:type="FILE_VHDL">303 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>304 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>305 <library xil_pn:name="MPI_HCL"/>306 </file>307 <file xil_pn:name="../Core_MPI/RAM_MUX.vhd" xil_pn:type="FILE_VHDL">308 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>309 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>310 <library xil_pn:name="MPI_HCL"/>311 </file>312 <file xil_pn:name="../Core_MPI/round_robbin_machine.vhd" xil_pn:type="FILE_VHDL">313 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>314 <association xil_pn:name="Implementation" xil_pn:seqID="23"/>315 <library xil_pn:name="MPI_HCL"/>316 </file>317 <file xil_pn:name="../Core_MPI/SetBit.vhd" xil_pn:type="FILE_VHDL">318 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>319 <association xil_pn:name="Implementation" xil_pn:seqID="22"/>320 <library xil_pn:name="MPI_HCL"/>321 </file>322 <file xil_pn:name="../Core_MPI/test_DMA.vhd" xil_pn:type="FILE_VHDL">323 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>324 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>325 <library xil_pn:name="MPI_HCL"/>326 </file>327 <file xil_pn:name="../HCL_Arch_conf.vhd" xil_pn:type="FILE_VHDL">328 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>329 <association xil_pn:name="Implementation" xil_pn:seqID="49"/>330 </file>331 <file xil_pn:name="../Hold_FSM.vhd" xil_pn:type="FILE_VHDL">332 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>333 <association xil_pn:name="Implementation" xil_pn:seqID="46"/>334 </file>335 <file xil_pn:name="../HT_process.vhd" xil_pn:type="FILE_VHDL">336 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>337 <association xil_pn:name="Implementation" xil_pn:seqID="45"/>338 </file>339 <file xil_pn:name="../IP_Timer.vhd" xil_pn:type="FILE_VHDL">340 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>341 <association xil_pn:name="Implementation" xil_pn:seqID="32"/>342 </file>343 <file xil_pn:name="../PE.vhd" xil_pn:type="FILE_VHDL">344 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>345 <association xil_pn:name="Implementation" xil_pn:seqID="48"/>346 </file>347 <file xil_pn:name="../mpi_test.vhd" xil_pn:type="FILE_VHDL">348 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>349 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>350 </file>351 <file xil_pn:name="ipcore_dir/mem_4k8.xco" xil_pn:type="FILE_COREGEN">352 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>353 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>354 </file>355 <file xil_pn:name="ipcore_dir/mem8k8.xco" xil_pn:type="FILE_COREGEN">356 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>357 <association xil_pn:name="Implementation" xil_pn:seqID="43"/>358 363 </file> 359 364 <file xil_pn:name="ipcore_dir/mem_4k8.xise" xil_pn:type="FILE_COREGENISE"> … … 484 489 <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> 485 490 <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> 486 <property xil_pn:name="Implementation Top" xil_pn:value="Architecture| MultiMPITest|behavior" xil_pn:valueState="non-default"/>487 <property xil_pn:name="Implementation Top File" xil_pn:value="../ Core_MPI/MultiMPITest.vhd" xil_pn:valueState="non-default"/>488 <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mpi_test /uut" xil_pn:valueState="non-default"/>491 <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mpi_test|behavior" xil_pn:valueState="non-default"/> 492 <property xil_pn:name="Implementation Top File" xil_pn:value="../mpi_test.vhd" xil_pn:valueState="non-default"/> 493 <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mpi_test" xil_pn:valueState="non-default"/> 489 494 <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> 490 495 <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> … … 561 566 <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> 562 567 <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> 563 <property xil_pn:name="Output File Name" xil_pn:value=" MultiMPITest" xil_pn:valueState="default"/>568 <property xil_pn:name="Output File Name" xil_pn:value="mpi_test" xil_pn:valueState="default"/> 564 569 <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> 570 <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/> 565 571 <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> 566 572 <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> … … 575 581 <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> 576 582 <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> 577 <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value=" MultiMPITest_map.vhd" xil_pn:valueState="default"/>578 <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value=" MultiMPITest_timesim.vhd" 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