Ignore:
Timestamp:
Apr 9, 2014, 11:19:58 PM (10 years ago)
Author:
rolagamo
Message:
 
File:
1 edited

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  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/Test_Timer.xise

    r136 r137  
    3333    <file xil_pn:name="../NoC/Crossbar.vhd" xil_pn:type="FILE_VHDL">
    3434      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
    35       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     35      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
    3636      <library xil_pn:name="NoCLib"/>
    3737    </file>
    3838    <file xil_pn:name="../NoC/Crossbit.vhd" xil_pn:type="FILE_VHDL">
    3939      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
    40       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     40      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
    4141      <library xil_pn:name="NoCLib"/>
    4242    </file>
    4343    <file xil_pn:name="../NoC/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">
    4444      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
    45       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     45      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
    4646      <library xil_pn:name="NoCLib"/>
    4747    </file>
    … …  
    5353    <file xil_pn:name="../NoC/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    5454      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
    55       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     55      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
    5656      <library xil_pn:name="NoCLib"/>
    5757    </file>
    5858    <file xil_pn:name="../NoC/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    5959      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
    60       <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     60      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
    6161      <library xil_pn:name="NoCLib"/>
    6262    </file>
    … …  
    6868    <file xil_pn:name="../NoC/Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
    6969      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
    70       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     70      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
    7171      <library xil_pn:name="NoCLib"/>
    7272    </file>
    7373    <file xil_pn:name="../NoC/proto_send.vhd" xil_pn:type="FILE_VHDL">
    7474      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
    75       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     75      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
    7676      <library xil_pn:name="NoCLib"/>
    7777    </file>
    … …  
    8383    <file xil_pn:name="../NoC/Scheduler.vhd" xil_pn:type="FILE_VHDL">
    8484      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
    85       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     85      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
    8686      <library xil_pn:name="NoCLib"/>
    8787    </file>
    … …  
    168168    <file xil_pn:name="../NoC/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
    169169      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
    170       <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     170      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
    171171      <library xil_pn:name="NoCLib"/>
    172172    </file>
    … …  
    183183    <file xil_pn:name="../Core_MPI/CORE_MPI.vhd" xil_pn:type="FILE_VHDL">
    184184      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
    185       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     185      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
    186186      <library xil_pn:name="MPI_HCL"/>
    187187    </file>
    188188    <file xil_pn:name="../Core_MPI/DEMUX1.vhd" xil_pn:type="FILE_VHDL">
    189189      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
    190       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     190      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
    191191      <library xil_pn:name="MPI_HCL"/>
    192192    </file>
    193193    <file xil_pn:name="../Core_MPI/DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL">
    194194      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
    195       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     195      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
    196196      <library xil_pn:name="MPI_HCL"/>
    197197    </file>
    198198    <file xil_pn:name="../Core_MPI/Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL">
    199199      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
    200       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     200      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
    201201      <library xil_pn:name="MPI_HCL"/>
    202202    </file>
    203203    <file xil_pn:name="../Core_MPI/EX1_FSM.vhd" xil_pn:type="FILE_VHDL">
    204204      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
    205       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     205      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
    206206      <library xil_pn:name="MPI_HCL"/>
    207207    </file>
    208208    <file xil_pn:name="../Core_MPI/EX2_FSM.vhd" xil_pn:type="FILE_VHDL">
    209209      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
    210       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     210      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
    211211      <library xil_pn:name="MPI_HCL"/>
    212212    </file>
    213213    <file xil_pn:name="../Core_MPI/EX3_FSM.vhd" xil_pn:type="FILE_VHDL">
    214214      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
    215       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     215      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
    216216      <library xil_pn:name="MPI_HCL"/>
    217217    </file>
    218218    <file xil_pn:name="../Core_MPI/EX4_FSM.vhd" xil_pn:type="FILE_VHDL">
    219219      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
    220       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     220      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
    221221      <library xil_pn:name="MPI_HCL"/>
    222222    </file>
    … …  
    228228    <file xil_pn:name="../Core_MPI/FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL">
    229229      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
    230       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     230      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
    231231      <library xil_pn:name="MPI_HCL"/>
    232232    </file>
    … …  
    248248    <file xil_pn:name="../Core_MPI/load_instr.vhd" xil_pn:type="FILE_VHDL">
    249249      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
    250       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     250      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
    251251      <library xil_pn:name="MPI_HCL"/>
    252252    </file>
    … …  
    258258    <file xil_pn:name="../Core_MPI/MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL">
    259259      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
    260       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     260      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
    261261      <library xil_pn:name="MPI_HCL"/>
    262262    </file>
    263263    <file xil_pn:name="../Core_MPI/MPI_NOC.vhd" xil_pn:type="FILE_VHDL">
    264264      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
    265       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     265      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
    266266      <library xil_pn:name="MPI_HCL"/>
    267267    </file>
    … …  
    273273    <file xil_pn:name="../Core_MPI/MPI_RMA.vhd" xil_pn:type="FILE_VHDL">
    274274      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
    275       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     275      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
    276276      <library xil_pn:name="MPI_HCL"/>
    277277    </file>
    278278    <file xil_pn:name="../Core_MPI/MultiMPITest.vhd" xil_pn:type="FILE_VHDL">
    279279      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
    280       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     280      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    281281    </file>
    282282    <file xil_pn:name="../Core_MPI/MUX1.vhd" xil_pn:type="FILE_VHDL">
    283283      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
    284       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     284      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    285285      <library xil_pn:name="MPI_HCL"/>
    286286    </file>
    287287    <file xil_pn:name="../Core_MPI/MUX8.vhd" xil_pn:type="FILE_VHDL">
    288288      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
    289       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     289      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
    290290      <library xil_pn:name="MPI_HCL"/>
    291291    </file>
    292292    <file xil_pn:name="../Core_MPI/Packet_type.vhd" xil_pn:type="FILE_VHDL">
    293293      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
    294       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     294      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
    295295      <library xil_pn:name="MPI_HCL"/>
    296296    </file>
    … …  
    312312    <file xil_pn:name="../Core_MPI/round_robbin_machine.vhd" xil_pn:type="FILE_VHDL">
    313313      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
    314       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     314      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
    315315      <library xil_pn:name="MPI_HCL"/>
    316316    </file>
    317317    <file xil_pn:name="../Core_MPI/SetBit.vhd" xil_pn:type="FILE_VHDL">
    318318      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
    319       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     319      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
    320320      <library xil_pn:name="MPI_HCL"/>
    321321    </file>
    … …  
    327327    <file xil_pn:name="../HCL_Arch_conf.vhd" xil_pn:type="FILE_VHDL">
    328328      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
    329       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     329      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
    330330    </file>
    331331    <file xil_pn:name="../Hold_FSM.vhd" xil_pn:type="FILE_VHDL">
    332332      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
    333       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     333      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
    334334    </file>
    335335    <file xil_pn:name="../HT_process.vhd" xil_pn:type="FILE_VHDL">
    336336      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
    337       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     337      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
    338338    </file>
    339339    <file xil_pn:name="../IP_Timer.vhd" xil_pn:type="FILE_VHDL">
    340340      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
    341       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     341      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
    342342    </file>
    343343    <file xil_pn:name="../PE.vhd" xil_pn:type="FILE_VHDL">
    344344      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
    345       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     345      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
    346346    </file>
    347347    <file xil_pn:name="../mpi_test.vhd" xil_pn:type="FILE_VHDL">
    … …  
    355355    <file xil_pn:name="ipcore_dir/mem8k8.xco" xil_pn:type="FILE_COREGEN">
    356356      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
    357       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     357      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
    358358    </file>
    359359    <file xil_pn:name="../NOC/Def_Request.vhd" xil_pn:type="FILE_VHDL">
    … …  
    371371
    372372  <properties>
    373     <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    374     <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
     373    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
     374    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
    375375    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
    376376    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    386386    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
    387387    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
     388    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
     389    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
    388390    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    389391    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    392394    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
    393395    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
    394     <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
    395     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
     396    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
     397    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
    396398    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
    397399    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    401403    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
    402404    <property xil_pn:name="Compiled Library Directory" xil_pn:value="modelsim10.1c" xil_pn:valueState="non-default"/>
     405    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    403406    <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
    404407    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     408    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     409    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     410    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     411    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    405412    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    406     <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
     413    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
    407414    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
    408415    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    410417    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
    411418    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
    412     <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     419    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    413420    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
    414421    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    416423    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    417424    <property xil_pn:name="Custom Do File Behavioral" xil_pn:value="wave.do" xil_pn:valueState="non-default"/>
     425    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
     426    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
    418427    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    419428    <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
    420429    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    421430    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    422     <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
    423     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    424     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
     431    <property xil_pn:name="Device" xil_pn:value="xc7vx485t" xil_pn:valueState="non-default"/>
     432    <property xil_pn:name="Device Family" xil_pn:value="Virtex7" xil_pn:valueState="non-default"/>
     433    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
    425434    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
     435    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
    426436    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    427437    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
    428     <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    429438    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
    430439    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    431     <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
     440    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
    432441    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
    433     <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     442    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
    434443    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    435     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
     444    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
    436445    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    437     <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    438446    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
    439     <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     447    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
    440448    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    441     <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    442     <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    443     <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    444     <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
     449    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
     450    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    445451    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
    446452    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    448454    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    449455    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    450     <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
     456    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
    451457    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
    452458    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
    453459    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
    454460    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
     461    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
    455462    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    456463    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    458465    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    459466    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    460     <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    461     <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
    462467    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
    463468    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    480485    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
    481486    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
    482     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     487    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
    483488    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
    484489    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
    485490    <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     491    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
    486492    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
     493    <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
    487494    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    488495    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
    489496    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    490497    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
    491     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mpi_test|behavior" xil_pn:valueState="non-default"/>
    492     <property xil_pn:name="Implementation Top File" xil_pn:value="../mpi_test.vhd" xil_pn:valueState="non-default"/>
    493     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mpi_test" xil_pn:valueState="non-default"/>
     498    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MultiMPITest|behavior" xil_pn:valueState="non-default"/>
     499    <property xil_pn:name="Implementation Top File" xil_pn:value="../Core_MPI/MultiMPITest.vhd" xil_pn:valueState="non-default"/>
     500    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mpi_test/uut" xil_pn:valueState="non-default"/>
    494501    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    495502    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    503510    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    504511    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     512    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
    505513    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
    506514    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    … …  
    521529    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
    522530    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
    523     <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
    524531    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
    525532    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    531538    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    532539    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    533     <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
    534     <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    535     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    536     <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    537     <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
    538540    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
    539541    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
    540542    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
    541     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
     543    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="non-default"/>
    542544    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
    543545    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    544546    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
    545     <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
     547    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
    546548    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
    547549    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
    548     <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
     550    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    549551    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
    550552    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
    … …  
    566568    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    567569    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
    568     <property xil_pn:name="Output File Name" xil_pn:value="mpi_test" xil_pn:valueState="default"/>
     570    <property xil_pn:name="Output File Name" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
    569571    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    570572    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
    571573    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    572574    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    573     <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
     575    <property xil_pn:name="Package" xil_pn:value="ffg1761" xil_pn:valueState="non-default"/>
    574576    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    575577    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    576578    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
    577579    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
    578     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
    579     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     580    <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
    580581    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    581582    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    582583    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
    583     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="mpi_test_map.vhd" xil_pn:valueState="default"/>
    584     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="mpi_test_timesim.vhd" xil_pn:valueState="default"/>
    585     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="mpi_test_synthesis.vhd" xil_pn:valueState="default"/>
    586     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="mpi_test_translate.vhd" xil_pn:valueState="default"/>
    587     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     584    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MultiMPITest_map.vhd" xil_pn:valueState="default"/>
     585    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MultiMPITest_timesim.vhd" xil_pn:valueState="default"/>
     586    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MultiMPITest_synthesis.vhd" xil_pn:valueState="default"/>
     587    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MultiMPITest_translate.vhd" xil_pn:valueState="default"/>
     588    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
     589    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
    588590    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    589591    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    603605    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    604606    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    605     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
     607    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
    606608    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    607609    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    608610    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    609     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="mpi_test" xil_pn:valueState="default"/>
     611    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
    610612    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    611613    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    620622    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
    621623    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
    622     <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     624    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
     625    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
    623626    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
    624627    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    626629    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
    627630    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     631    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
    628632    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    629633    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
    … …  
    634638    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    635639    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
    636     <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    637     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     640    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
    638641    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    639     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
     642    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
    640643    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
    641644    <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    656659    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    657660    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    658     <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
    659     <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     661    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
     662    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
     663    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
    660664    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
    661665    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    … …  
    688692    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    689693    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    690     <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
     694    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
    691695    <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
    692696    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
    693697    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
     698    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
    694699    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
    695700    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    696701    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    697702    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
     703    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
    698704    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
    699705    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    700     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
    701706    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
    702707    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
    … …  
    705710    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    706711    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
    707     <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
    708     <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
    709     <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
     712    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
     713    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
     714    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
     715    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    710716    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
    711717    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    … …  
    716722    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|mpi_test|behavior" xil_pn:valueState="non-default"/>
    717723    <property xil_pn:name="PROP_DesignName" xil_pn:value="Test_Timer" xil_pn:valueState="non-default"/>
    718     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     724    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex7" xil_pn:valueState="default"/>
    719725    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
    720726    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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