Ignore:
Timestamp:
May 21, 2014, 11:36:19 AM (10 years ago)
Author:
rolagamo
Message:

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC

Location:
PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0
Files:
2 copied

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/Test_Timer/Test_Timer.xise

    r137 r139  
    1010    <!-- implement in ISE Project Navigator.                               -->
    1111    <!--                                                                   -->
    12     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
     12    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
    1313  </header>
    1414
    15   <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
     15  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
    1616
    1717  <files>
    18     <file xil_pn:name="../NoC/Arbiter.vhd" xil_pn:type="FILE_VHDL">
     18    <file xil_pn:name="../NOC/Arbiter.vhd" xil_pn:type="FILE_VHDL">
    1919      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
    2020      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
    2121      <library xil_pn:name="NoCLib"/>
    2222    </file>
    23     <file xil_pn:name="../NoC/conv.vhd" xil_pn:type="FILE_VHDL">
    24       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    25       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    26       <library xil_pn:name="NoCLib"/>
    27     </file>
    28     <file xil_pn:name="../NoC/CoreTypes.vhd" xil_pn:type="FILE_VHDL">
     23    <file xil_pn:name="../NOC/conv.vhd" xil_pn:type="FILE_VHDL">
     24      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     25      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     26      <library xil_pn:name="NoCLib"/>
     27    </file>
     28    <file xil_pn:name="../NOC/CoreTypes.vhd" xil_pn:type="FILE_VHDL">
    2929      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
    3030      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
    3131      <library xil_pn:name="NoCLib"/>
    3232    </file>
    33     <file xil_pn:name="../NoC/Crossbar.vhd" xil_pn:type="FILE_VHDL">
    34       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
    35       <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
    36       <library xil_pn:name="NoCLib"/>
    37     </file>
    38     <file xil_pn:name="../NoC/Crossbit.vhd" xil_pn:type="FILE_VHDL">
     33    <file xil_pn:name="../NOC/Crossbar.vhd" xil_pn:type="FILE_VHDL">
     34      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
     35      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     36      <library xil_pn:name="NoCLib"/>
     37    </file>
     38    <file xil_pn:name="../NOC/Crossbit.vhd" xil_pn:type="FILE_VHDL">
     39      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
     40      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     41      <library xil_pn:name="NoCLib"/>
     42    </file>
     43    <file xil_pn:name="../NOC/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">
     44      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
     45      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     46      <library xil_pn:name="NoCLib"/>
     47    </file>
     48    <file xil_pn:name="../NOC/FIFO_DP.vhd" xil_pn:type="FILE_VHDL">
     49      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     50      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     51      <library xil_pn:name="NoCLib"/>
     52    </file>
     53    <file xil_pn:name="../NOC/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
     54      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
     55      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     56      <library xil_pn:name="NoCLib"/>
     57    </file>
     58    <file xil_pn:name="../NOC/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    3959      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
    4060      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
    4161      <library xil_pn:name="NoCLib"/>
    4262    </file>
    43     <file xil_pn:name="../NoC/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">
     63    <file xil_pn:name="../NOC/PortRam.vhd" xil_pn:type="FILE_VHDL">
     64      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     65      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     66      <library xil_pn:name="NoCLib"/>
     67    </file>
     68    <file xil_pn:name="../NOC/Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
     69      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     70      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     71      <library xil_pn:name="NoCLib"/>
     72    </file>
     73    <file xil_pn:name="../NOC/proto_send.vhd" xil_pn:type="FILE_VHDL">
     74      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     75      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     76      <library xil_pn:name="NoCLib"/>
     77    </file>
     78    <file xil_pn:name="../NOC/RAM_256.vhd" xil_pn:type="FILE_VHDL">
     79      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     80      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     81      <library xil_pn:name="NoCLib"/>
     82    </file>
     83    <file xil_pn:name="../NOC/Scheduler.vhd" xil_pn:type="FILE_VHDL">
    4484      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
    4585      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
    4686      <library xil_pn:name="NoCLib"/>
    4787    </file>
    48     <file xil_pn:name="../NoC/FIFO_DP.vhd" xil_pn:type="FILE_VHDL">
    49       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    50       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    51       <library xil_pn:name="NoCLib"/>
    52     </file>
    53     <file xil_pn:name="../NoC/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    54       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
    55       <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
    56       <library xil_pn:name="NoCLib"/>
    57     </file>
    58     <file xil_pn:name="../NoC/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    59       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
    60       <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
    61       <library xil_pn:name="NoCLib"/>
    62     </file>
    63     <file xil_pn:name="../NoC/PortRam.vhd" xil_pn:type="FILE_VHDL">
    64       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    65       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    66       <library xil_pn:name="NoCLib"/>
    67     </file>
    68     <file xil_pn:name="../NoC/Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
    69       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
    70       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
    71       <library xil_pn:name="NoCLib"/>
    72     </file>
    73     <file xil_pn:name="../NoC/proto_send.vhd" xil_pn:type="FILE_VHDL">
    74       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
    75       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
    76       <library xil_pn:name="NoCLib"/>
    77     </file>
    78     <file xil_pn:name="../NoC/RAM_256.vhd" xil_pn:type="FILE_VHDL">
    79       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    80       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    81       <library xil_pn:name="NoCLib"/>
    82     </file>
    83     <file xil_pn:name="../NoC/Scheduler.vhd" xil_pn:type="FILE_VHDL">
    84       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
    85       <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
    86       <library xil_pn:name="NoCLib"/>
    87     </file>
    88     <file xil_pn:name="../NoC/SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL">
     88    <file xil_pn:name="../NOC/SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL">
    8989      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
    9090      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
    9191      <library xil_pn:name="NoCLib"/>
    9292    </file>
    93     <file xil_pn:name="../NoC/SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL">
     93    <file xil_pn:name="../NOC/SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL">
    9494      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
    9595      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
    9696      <library xil_pn:name="NoCLib"/>
    9797    </file>
    98     <file xil_pn:name="../NoC/SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL">
     98    <file xil_pn:name="../NOC/SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL">
    9999      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
    100100      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
    101101      <library xil_pn:name="NoCLib"/>
    102102    </file>
    103     <file xil_pn:name="../NoC/SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL">
     103    <file xil_pn:name="../NOC/SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL">
    104104      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
    105105      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
    106106      <library xil_pn:name="NoCLib"/>
    107107    </file>
    108     <file xil_pn:name="../NoC/SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL">
     108    <file xil_pn:name="../NOC/SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL">
    109109      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
    110110      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
    111111      <library xil_pn:name="NoCLib"/>
    112112    </file>
    113     <file xil_pn:name="../NoC/SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL">
     113    <file xil_pn:name="../NOC/SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL">
    114114      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
    115115      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
    116116      <library xil_pn:name="NoCLib"/>
    117117    </file>
    118     <file xil_pn:name="../NoC/SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL">
     118    <file xil_pn:name="../NOC/SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL">
    119119      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
    120120      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    121121      <library xil_pn:name="NoCLib"/>
    122122    </file>
    123     <file xil_pn:name="../NoC/SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL">
     123    <file xil_pn:name="../NOC/SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL">
    124124      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
    125125      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    126126      <library xil_pn:name="NoCLib"/>
    127127    </file>
    128     <file xil_pn:name="../NoC/SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL">
     128    <file xil_pn:name="../NOC/SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL">
    129129      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
    130130      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    131131      <library xil_pn:name="NoCLib"/>
    132132    </file>
    133     <file xil_pn:name="../NoC/SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL">
     133    <file xil_pn:name="../NOC/SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL">
    134134      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
    135135      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
    136136      <library xil_pn:name="NoCLib"/>
    137137    </file>
    138     <file xil_pn:name="../NoC/SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL">
     138    <file xil_pn:name="../NOC/SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL">
    139139      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
    140140      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    141141      <library xil_pn:name="NoCLib"/>
    142142    </file>
    143     <file xil_pn:name="../NoC/SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL">
     143    <file xil_pn:name="../NOC/SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL">
    144144      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
    145145      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    146146      <library xil_pn:name="NoCLib"/>
    147147    </file>
    148     <file xil_pn:name="../NoC/SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL">
     148    <file xil_pn:name="../NOC/SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL">
    149149      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
    150150      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
    151151      <library xil_pn:name="NoCLib"/>
    152152    </file>
    153     <file xil_pn:name="../NoC/SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL">
     153    <file xil_pn:name="../NOC/SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL">
    154154      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
    155155      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
    156156      <library xil_pn:name="NoCLib"/>
    157157    </file>
    158     <file xil_pn:name="../NoC/SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL">
     158    <file xil_pn:name="../NOC/SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL">
    159159      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
    160160      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
    161161      <library xil_pn:name="NoCLib"/>
    162162    </file>
    163     <file xil_pn:name="../NoC/stimuli1.vhd" xil_pn:type="FILE_VHDL">
    164       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    165       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    166       <library xil_pn:name="NoCLib"/>
    167     </file>
    168     <file xil_pn:name="../NoC/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
    169       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
    170       <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
    171       <library xil_pn:name="NoCLib"/>
    172     </file>
    173     <file xil_pn:name="../NoC/SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL">
    174       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    175       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    176       <library xil_pn:name="NoCLib"/>
    177     </file>
    178     <file xil_pn:name="../NoC/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">
    179       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    180       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    181       <library xil_pn:name="NoCLib"/>
    182     </file>
    183     <file xil_pn:name="../Core_MPI/CORE_MPI.vhd" xil_pn:type="FILE_VHDL">
    184       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
    185       <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
    186       <library xil_pn:name="MPI_HCL"/>
    187     </file>
    188     <file xil_pn:name="../Core_MPI/DEMUX1.vhd" xil_pn:type="FILE_VHDL">
    189       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
    190       <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
    191       <library xil_pn:name="MPI_HCL"/>
    192     </file>
    193     <file xil_pn:name="../Core_MPI/DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL">
    194       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
    195       <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
    196       <library xil_pn:name="MPI_HCL"/>
    197     </file>
    198     <file xil_pn:name="../Core_MPI/Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL">
    199       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
    200       <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
    201       <library xil_pn:name="MPI_HCL"/>
    202     </file>
    203     <file xil_pn:name="../Core_MPI/EX1_FSM.vhd" xil_pn:type="FILE_VHDL">
    204       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
    205       <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
    206       <library xil_pn:name="MPI_HCL"/>
    207     </file>
    208     <file xil_pn:name="../Core_MPI/EX2_FSM.vhd" xil_pn:type="FILE_VHDL">
    209       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
    210       <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
    211       <library xil_pn:name="MPI_HCL"/>
    212     </file>
    213     <file xil_pn:name="../Core_MPI/EX3_FSM.vhd" xil_pn:type="FILE_VHDL">
    214       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
    215       <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
    216       <library xil_pn:name="MPI_HCL"/>
    217     </file>
    218     <file xil_pn:name="../Core_MPI/EX4_FSM.vhd" xil_pn:type="FILE_VHDL">
    219       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
    220       <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
    221       <library xil_pn:name="MPI_HCL"/>
    222     </file>
    223     <file xil_pn:name="../Core_MPI/Ex5_FSM.vhd" xil_pn:type="FILE_VHDL">
    224       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    225       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    226       <library xil_pn:name="MPI_HCL"/>
    227     </file>
    228     <file xil_pn:name="../Core_MPI/FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL">
    229       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
    230       <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
    231       <library xil_pn:name="MPI_HCL"/>
    232     </file>
    233     <file xil_pn:name="../Core_MPI/FIfo_mem.vhd" xil_pn:type="FILE_VHDL">
    234       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    235       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    236       <library xil_pn:name="MPI_HCL"/>
    237     </file>
    238     <file xil_pn:name="../Core_MPI/FIfo_proc.vhd" xil_pn:type="FILE_VHDL">
    239       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    240       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    241       <library xil_pn:name="MPI_HCL"/>
    242     </file>
    243     <file xil_pn:name="../Core_MPI/image_pkg.vhd" xil_pn:type="FILE_VHDL">
    244       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    245       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    246       <library xil_pn:name="MPI_HCL"/>
    247     </file>
    248     <file xil_pn:name="../Core_MPI/load_instr.vhd" xil_pn:type="FILE_VHDL">
    249       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
    250       <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
    251       <library xil_pn:name="MPI_HCL"/>
    252     </file>
    253     <file xil_pn:name="../Core_MPI/MPICORETEST.vhd" xil_pn:type="FILE_VHDL">
    254       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    255       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    256       <library xil_pn:name="MPI_HCL"/>
    257     </file>
    258     <file xil_pn:name="../Core_MPI/MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL">
    259       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
    260       <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
    261       <library xil_pn:name="MPI_HCL"/>
    262     </file>
    263     <file xil_pn:name="../Core_MPI/MPI_NOC.vhd" xil_pn:type="FILE_VHDL">
    264       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
    265       <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
    266       <library xil_pn:name="MPI_HCL"/>
    267     </file>
    268     <file xil_pn:name="../Core_MPI/MPI_PKG.vhd" xil_pn:type="FILE_VHDL">
    269       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    270       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    271       <library xil_pn:name="MPI_HCL"/>
    272     </file>
    273     <file xil_pn:name="../Core_MPI/MPI_RMA.vhd" xil_pn:type="FILE_VHDL">
    274       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
    275       <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
    276       <library xil_pn:name="MPI_HCL"/>
    277     </file>
    278     <file xil_pn:name="../Core_MPI/MultiMPITest.vhd" xil_pn:type="FILE_VHDL">
    279       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
    280       <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    281     </file>
    282     <file xil_pn:name="../Core_MPI/MUX1.vhd" xil_pn:type="FILE_VHDL">
    283       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
    284       <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    285       <library xil_pn:name="MPI_HCL"/>
    286     </file>
    287     <file xil_pn:name="../Core_MPI/MUX8.vhd" xil_pn:type="FILE_VHDL">
    288       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
    289       <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
    290       <library xil_pn:name="MPI_HCL"/>
    291     </file>
    292     <file xil_pn:name="../Core_MPI/Packet_type.vhd" xil_pn:type="FILE_VHDL">
     163    <file xil_pn:name="../NOC/stimuli1.vhd" xil_pn:type="FILE_VHDL">
     164      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     165      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     166      <library xil_pn:name="NoCLib"/>
     167    </file>
     168    <file xil_pn:name="../NOC/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
    293169      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
    294170      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
    295       <library xil_pn:name="MPI_HCL"/>
    296     </file>
    297     <file xil_pn:name="../Core_MPI/RAM_32_32.vhd" xil_pn:type="FILE_VHDL">
    298       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    299       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    300       <library xil_pn:name="MPI_HCL"/>
    301     </file>
    302     <file xil_pn:name="../Core_MPI/RAM_64.vhd" xil_pn:type="FILE_VHDL">
    303       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    304       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    305       <library xil_pn:name="MPI_HCL"/>
    306     </file>
    307     <file xil_pn:name="../Core_MPI/RAM_MUX.vhd" xil_pn:type="FILE_VHDL">
    308       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    309       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    310       <library xil_pn:name="MPI_HCL"/>
    311     </file>
    312     <file xil_pn:name="../Core_MPI/round_robbin_machine.vhd" xil_pn:type="FILE_VHDL">
    313       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
    314       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
    315       <library xil_pn:name="MPI_HCL"/>
    316     </file>
    317     <file xil_pn:name="../Core_MPI/SetBit.vhd" xil_pn:type="FILE_VHDL">
    318       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
    319       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
    320       <library xil_pn:name="MPI_HCL"/>
    321     </file>
    322     <file xil_pn:name="../Core_MPI/test_DMA.vhd" xil_pn:type="FILE_VHDL">
     171      <library xil_pn:name="NoCLib"/>
     172    </file>
     173    <file xil_pn:name="../NOC/SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL">
     174      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     175      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     176      <library xil_pn:name="NoCLib"/>
     177    </file>
     178    <file xil_pn:name="../NOC/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">
     179      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     180      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     181      <library xil_pn:name="NoCLib"/>
     182    </file>
     183    <file xil_pn:name="../CORE_MPI/CORE_MPI.vhd" xil_pn:type="FILE_VHDL">
     184      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     185      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     186      <library xil_pn:name="MPI_HCL"/>
     187    </file>
     188    <file xil_pn:name="../CORE_MPI/DEMUX1.vhd" xil_pn:type="FILE_VHDL">
     189      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     190      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     191      <library xil_pn:name="MPI_HCL"/>
     192    </file>
     193    <file xil_pn:name="../CORE_MPI/DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL">
     194      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     195      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     196      <library xil_pn:name="MPI_HCL"/>
     197    </file>
     198    <file xil_pn:name="../CORE_MPI/Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL">
     199      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     200      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     201      <library xil_pn:name="MPI_HCL"/>
     202    </file>
     203    <file xil_pn:name="../CORE_MPI/EX1_FSM.vhd" xil_pn:type="FILE_VHDL">
     204      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     205      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     206      <library xil_pn:name="MPI_HCL"/>
     207    </file>
     208    <file xil_pn:name="../CORE_MPI/EX2_FSM.vhd" xil_pn:type="FILE_VHDL">
     209      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     210      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     211      <library xil_pn:name="MPI_HCL"/>
     212    </file>
     213    <file xil_pn:name="../CORE_MPI/EX3_FSM.vhd" xil_pn:type="FILE_VHDL">
     214      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     215      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     216      <library xil_pn:name="MPI_HCL"/>
     217    </file>
     218    <file xil_pn:name="../CORE_MPI/EX4_FSM.vhd" xil_pn:type="FILE_VHDL">
     219      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     220      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     221      <library xil_pn:name="MPI_HCL"/>
     222    </file>
     223    <file xil_pn:name="../CORE_MPI/Ex5_FSM.vhd" xil_pn:type="FILE_VHDL">
     224      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     225      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     226      <library xil_pn:name="MPI_HCL"/>
     227    </file>
     228    <file xil_pn:name="../CORE_MPI/FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL">
     229      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     230      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     231      <library xil_pn:name="MPI_HCL"/>
     232    </file>
     233    <file xil_pn:name="../CORE_MPI/FIfo_mem.vhd" xil_pn:type="FILE_VHDL">
     234      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     235      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     236      <library xil_pn:name="MPI_HCL"/>
     237    </file>
     238    <file xil_pn:name="../CORE_MPI/FIfo_proc.vhd" xil_pn:type="FILE_VHDL">
     239      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     240      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     241      <library xil_pn:name="MPI_HCL"/>
     242    </file>
     243    <file xil_pn:name="../CORE_MPI/image_pkg.vhd" xil_pn:type="FILE_VHDL">
     244      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     245      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     246      <library xil_pn:name="MPI_HCL"/>
     247    </file>
     248    <file xil_pn:name="../CORE_MPI/load_instr.vhd" xil_pn:type="FILE_VHDL">
     249      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     250      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     251      <library xil_pn:name="MPI_HCL"/>
     252    </file>
     253    <file xil_pn:name="../CORE_MPI/MPICORETEST.vhd" xil_pn:type="FILE_VHDL">
     254      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     255      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     256      <library xil_pn:name="MPI_HCL"/>
     257    </file>
     258    <file xil_pn:name="../CORE_MPI/MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL">
     259      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     260      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     261      <library xil_pn:name="MPI_HCL"/>
     262    </file>
     263    <file xil_pn:name="../CORE_MPI/MPI_NOC.vhd" xil_pn:type="FILE_VHDL">
     264      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     265      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     266      <library xil_pn:name="MPI_HCL"/>
     267    </file>
     268    <file xil_pn:name="../CORE_MPI/MPI_PKG.vhd" xil_pn:type="FILE_VHDL">
     269      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     270      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     271      <library xil_pn:name="MPI_HCL"/>
     272    </file>
     273    <file xil_pn:name="../CORE_MPI/MPI_RMA.vhd" xil_pn:type="FILE_VHDL">
     274      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     275      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     276      <library xil_pn:name="MPI_HCL"/>
     277    </file>
     278    <file xil_pn:name="../CORE_MPI/MultiMPITest.vhd" xil_pn:type="FILE_VHDL">
     279      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     280      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     281    </file>
     282    <file xil_pn:name="../CORE_MPI/MUX1.vhd" xil_pn:type="FILE_VHDL">
     283      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     284      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     285      <library xil_pn:name="MPI_HCL"/>
     286    </file>
     287    <file xil_pn:name="../CORE_MPI/MUX8.vhd" xil_pn:type="FILE_VHDL">
     288      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     289      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     290      <library xil_pn:name="MPI_HCL"/>
     291    </file>
     292    <file xil_pn:name="../CORE_MPI/Packet_type.vhd" xil_pn:type="FILE_VHDL">
     293      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     294      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     295      <library xil_pn:name="MPI_HCL"/>
     296    </file>
     297    <file xil_pn:name="../CORE_MPI/RAM_32_32.vhd" xil_pn:type="FILE_VHDL">
     298      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     299      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     300      <library xil_pn:name="MPI_HCL"/>
     301    </file>
     302    <file xil_pn:name="../CORE_MPI/RAM_64.vhd" xil_pn:type="FILE_VHDL">
     303      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     304      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     305      <library xil_pn:name="MPI_HCL"/>
     306    </file>
     307    <file xil_pn:name="../CORE_MPI/RAM_MUX.vhd" xil_pn:type="FILE_VHDL">
     308      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     309      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     310      <library xil_pn:name="MPI_HCL"/>
     311    </file>
     312    <file xil_pn:name="../CORE_MPI/round_robbin_machine.vhd" xil_pn:type="FILE_VHDL">
     313      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     314      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     315      <library xil_pn:name="MPI_HCL"/>
     316    </file>
     317    <file xil_pn:name="../CORE_MPI/SetBit.vhd" xil_pn:type="FILE_VHDL">
     318      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     319      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     320      <library xil_pn:name="MPI_HCL"/>
     321    </file>
     322    <file xil_pn:name="../CORE_MPI/test_DMA.vhd" xil_pn:type="FILE_VHDL">
    323323      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    324324      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    … …  
    326326    </file>
    327327    <file xil_pn:name="../HCL_Arch_conf.vhd" xil_pn:type="FILE_VHDL">
    328       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
    329       <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
     328      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     329      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    330330    </file>
    331331    <file xil_pn:name="../Hold_FSM.vhd" xil_pn:type="FILE_VHDL">
    332       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
    333       <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
     332      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     333      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    334334    </file>
    335335    <file xil_pn:name="../HT_process.vhd" xil_pn:type="FILE_VHDL">
    336       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
    337       <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
     336      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     337      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    338338    </file>
    339339    <file xil_pn:name="../IP_Timer.vhd" xil_pn:type="FILE_VHDL">
    340       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
    341       <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
     340      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     341      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    342342    </file>
    343343    <file xil_pn:name="../PE.vhd" xil_pn:type="FILE_VHDL">
    344       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
    345       <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
     344      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     345      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    346346    </file>
    347347    <file xil_pn:name="../mpi_test.vhd" xil_pn:type="FILE_VHDL">
    348       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
     348      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    349349      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    350350    </file>
    … …  
    354354    </file>
    355355    <file xil_pn:name="ipcore_dir/mem8k8.xco" xil_pn:type="FILE_COREGEN">
    356       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
    357       <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
     356      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     357      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    358358    </file>
    359359    <file xil_pn:name="../NOC/Def_Request.vhd" xil_pn:type="FILE_VHDL">
    … …  
    362362      <library xil_pn:name="NoCLib"/>
    363363    </file>
    364     <file xil_pn:name="ipcore_dir/mem_4k8.xise" xil_pn:type="FILE_COREGENISE">
    365       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    366     </file>
    367     <file xil_pn:name="ipcore_dir/mem8k8.xise" xil_pn:type="FILE_COREGENISE">
    368       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     364    <file xil_pn:name="Nexys4_Master.ucf" xil_pn:type="FILE_UCF">
     365      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     366    </file>
     367    <file xil_pn:name="../NOC/NOC_tree.vhd" xil_pn:type="FILE_VHDL">
     368      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
     369      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     370      <library xil_pn:name="NoCLib"/>
     371    </file>
     372    <file xil_pn:name="../NOC/test_noc_tree.vhd" xil_pn:type="FILE_VHDL">
     373      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
     374      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     375    </file>
     376    <file xil_pn:name="pinloc.ucf" xil_pn:type="FILE_UCF">
     377      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     378    </file>
     379    <file xil_pn:name="simu_tree.vhd" xil_pn:type="FILE_VHDL">
     380      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
     381      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="238"/>
     382      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="238"/>
     383      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="238"/>
    369384    </file>
    370385  </files>
    … …  
    429444    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    430445    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    431     <property xil_pn:name="Device" xil_pn:value="xc7vx485t" xil_pn:valueState="non-default"/>
    432     <property xil_pn:name="Device Family" xil_pn:value="Virtex7" xil_pn:valueState="non-default"/>
     446    <property xil_pn:name="Device" xil_pn:value="xc7a100t" xil_pn:valueState="default"/>
     447    <property xil_pn:name="Device Family" xil_pn:value="Artix7" xil_pn:valueState="non-default"/>
    433448    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
    434449    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    467482    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
    468483    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
    469     <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
     484    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
    470485    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
    471486    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    491506    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
    492507    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
    493     <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
     508    <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="non-default"/>
    494509    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    495510    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
    496511    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    497512    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
    498     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MultiMPITest|behavior" xil_pn:valueState="non-default"/>
    499     <property xil_pn:name="Implementation Top File" xil_pn:value="../Core_MPI/MultiMPITest.vhd" xil_pn:valueState="non-default"/>
    500     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mpi_test/uut" xil_pn:valueState="non-default"/>
     513    <property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
     514    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|test_tree_8x8|behavior" xil_pn:valueState="non-default"/>
     515    <property xil_pn:name="Implementation Top File" xil_pn:value="../NOC/test_noc_tree.vhd" xil_pn:valueState="non-default"/>
     516    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/test_tree_8x8" xil_pn:valueState="non-default"/>
    501517    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    502518    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    538554    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    539555    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
     556    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
    540557    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
    541558    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
    … …  
    568585    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    569586    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
    570     <property xil_pn:name="Output File Name" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
     587    <property xil_pn:name="Output File Name" xil_pn:value="test_tree_8x8" xil_pn:valueState="default"/>
    571588    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    572589    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
    573590    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    574591    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    575     <property xil_pn:name="Package" xil_pn:value="ffg1761" xil_pn:valueState="non-default"/>
     592    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/>
    576593    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    577594    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    579596    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
    580597    <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
     598    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
    581599    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    582600    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    583601    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
    584     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MultiMPITest_map.vhd" xil_pn:valueState="default"/>
    585     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MultiMPITest_timesim.vhd" xil_pn:valueState="default"/>
    586     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MultiMPITest_synthesis.vhd" xil_pn:valueState="default"/>
    587     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MultiMPITest_translate.vhd" xil_pn:valueState="default"/>
     602    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="test_tree_8x8_map.vhd" xil_pn:valueState="default"/>
     603    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="test_tree_8x8_timesim.vhd" xil_pn:valueState="default"/>
     604    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="test_tree_8x8_synthesis.vhd" xil_pn:valueState="default"/>
     605    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="test_tree_8x8_translate.vhd" xil_pn:valueState="default"/>
    588606    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
    589607    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
    … …  
    609627    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    610628    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    611     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
     629    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="test_tree_8x8" xil_pn:valueState="default"/>
    612630    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    613631    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    632650    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    633651    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
    634     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mpi_test" xil_pn:valueState="non-default"/>
    635     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.mpi_test" xil_pn:valueState="non-default"/>
     652    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/simu_tree" xil_pn:valueState="non-default"/>
     653    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.simu_tree" xil_pn:valueState="non-default"/>
    636654    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    637655    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    … …  
    655673    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    656674    <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
    657     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.mpi_test" xil_pn:valueState="default"/>
     675    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.simu_tree" xil_pn:valueState="default"/>
    658676    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    659677    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    … …  
    665683    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    666684    <property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
     685    <property xil_pn:name="Target UCF File Name" xil_pn:value="pinloc.ucf" xil_pn:valueState="non-default"/>
    667686    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    668687    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    … …  
    698717    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
    699718    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
    700     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    701     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
     719    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
     720    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
    702721    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
    703722    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
    … …  
    720739    <!-- The following properties are for internal use only. These should not be modified.-->
    721740    <!--                                                                                  -->
    722     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|mpi_test|behavior" xil_pn:valueState="non-default"/>
     741    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|simu_tree|behavior" xil_pn:valueState="non-default"/>
    723742    <property xil_pn:name="PROP_DesignName" xil_pn:value="Test_Timer" xil_pn:valueState="non-default"/>
    724     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex7" xil_pn:valueState="default"/>
     743    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="artix7" xil_pn:valueState="default"/>
    725744    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
    726745    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    … …  
    736755  </properties>
    737756
    738   <bindings/>
     757  <bindings>
     758    <binding xil_pn:location="/MultiMPITest" xil_pn:name="Nexys4_Master.ucf"/>
     759    <binding xil_pn:location="/test_tree_8x8" xil_pn:name="pinloc.ucf"/>
     760  </bindings>
    739761
    740762  <libraries>
Note: See TracChangeset for help on using the changeset viewer.