Ignore:
Timestamp:
Sep 18, 2013, 1:39:39 PM (11 years ago)
Author:
rolagamo
Message:
 
File:
1 edited

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  • PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/GENERIC_16_16.gise

    r22 r69  
    2929  </files>
    3030
    31   <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
     31  <transforms xmlns="http://www.xilinx.com/XMLSchema">
     32    <transform xil_pn:end_ts="1370435746" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1370435746">
     33      <status xil_pn:value="SuccessfullyRun"/>
     34      <status xil_pn:value="ReadyToRun"/>
     35    </transform>
     36    <transform xil_pn:end_ts="1370435746" xil_pn:in_ck="9216248337673135807" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1370435746">
     37      <status xil_pn:value="SuccessfullyRun"/>
     38      <status xil_pn:value="ReadyToRun"/>
     39      <outfile xil_pn:name="../CORE_MPI/sim_fifo.vhd"/>
     40      <outfile xil_pn:name="Arbiter.vhd"/>
     41      <outfile xil_pn:name="C:/RomSwitch/testport5.vhd"/>
     42      <outfile xil_pn:name="CoreTypes.vhd"/>
     43      <outfile xil_pn:name="Crossbar.vhd"/>
     44      <outfile xil_pn:name="Crossbit.vhd"/>
     45      <outfile xil_pn:name="FIFO_256_FWFT.vhd"/>
     46      <outfile xil_pn:name="FIFO_DP.vhd"/>
     47      <outfile xil_pn:name="INPUT_PORT_MODULE.vhd"/>
     48      <outfile xil_pn:name="OUTPUT_PORT_MODULE.vhd"/>
     49      <outfile xil_pn:name="Proto_receiv.vhd"/>
     50      <outfile xil_pn:name="RAM_256.vhd"/>
     51      <outfile xil_pn:name="SCHEDULER10_10.VHD"/>
     52      <outfile xil_pn:name="SCHEDULER11_11.VHD"/>
     53      <outfile xil_pn:name="SCHEDULER12_12.VHD"/>
     54      <outfile xil_pn:name="SCHEDULER13_13.VHD"/>
     55      <outfile xil_pn:name="SCHEDULER14_14.VHD"/>
     56      <outfile xil_pn:name="SCHEDULER15_15.VHD"/>
     57      <outfile xil_pn:name="SCHEDULER16_16.VHD"/>
     58      <outfile xil_pn:name="SCHEDULER2_2.VHD"/>
     59      <outfile xil_pn:name="SCHEDULER3_3.VHD"/>
     60      <outfile xil_pn:name="SCHEDULER4_4.VHD"/>
     61      <outfile xil_pn:name="SCHEDULER5_5.VHD"/>
     62      <outfile xil_pn:name="SCHEDULER6_6.VHD"/>
     63      <outfile xil_pn:name="SCHEDULER7_7.VHD"/>
     64      <outfile xil_pn:name="SCHEDULER8_8.VHD"/>
     65      <outfile xil_pn:name="SCHEDULER9_9.VHD"/>
     66      <outfile xil_pn:name="SWITCH_GEN.vhd"/>
     67      <outfile xil_pn:name="SWITCH_GENERIQUE.vhd"/>
     68      <outfile xil_pn:name="Scheduler.vhd"/>
     69      <outfile xil_pn:name="conv.vhd"/>
     70      <outfile xil_pn:name="proto_send.vhd"/>
     71      <outfile xil_pn:name="stimuli1.vhd"/>
     72      <outfile xil_pn:name="test_xbar_8x8.vhd"/>
     73    </transform>
     74    <transform xil_pn:end_ts="1370435946" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="1086089259624485161" xil_pn:start_ts="1370435946">
     75      <status xil_pn:value="SuccessfullyRun"/>
     76      <status xil_pn:value="ReadyToRun"/>
     77    </transform>
     78    <transform xil_pn:end_ts="1370435946" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-661505819731779733" xil_pn:start_ts="1370435946">
     79      <status xil_pn:value="SuccessfullyRun"/>
     80      <status xil_pn:value="ReadyToRun"/>
     81    </transform>
     82    <transform xil_pn:end_ts="1370435746" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="1089920306747347169" xil_pn:start_ts="1370435746">
     83      <status xil_pn:value="SuccessfullyRun"/>
     84      <status xil_pn:value="ReadyToRun"/>
     85    </transform>
     86    <transform xil_pn:end_ts="1370435746" xil_pn:in_ck="9216248337673135807" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1370435746">
     87      <status xil_pn:value="SuccessfullyRun"/>
     88      <status xil_pn:value="ReadyToRun"/>
     89      <outfile xil_pn:name="../CORE_MPI/sim_fifo.vhd"/>
     90      <outfile xil_pn:name="Arbiter.vhd"/>
     91      <outfile xil_pn:name="C:/RomSwitch/testport5.vhd"/>
     92      <outfile xil_pn:name="CoreTypes.vhd"/>
     93      <outfile xil_pn:name="Crossbar.vhd"/>
     94      <outfile xil_pn:name="Crossbit.vhd"/>
     95      <outfile xil_pn:name="FIFO_256_FWFT.vhd"/>
     96      <outfile xil_pn:name="FIFO_DP.vhd"/>
     97      <outfile xil_pn:name="INPUT_PORT_MODULE.vhd"/>
     98      <outfile xil_pn:name="OUTPUT_PORT_MODULE.vhd"/>
     99      <outfile xil_pn:name="Proto_receiv.vhd"/>
     100      <outfile xil_pn:name="RAM_256.vhd"/>
     101      <outfile xil_pn:name="SCHEDULER10_10.VHD"/>
     102      <outfile xil_pn:name="SCHEDULER11_11.VHD"/>
     103      <outfile xil_pn:name="SCHEDULER12_12.VHD"/>
     104      <outfile xil_pn:name="SCHEDULER13_13.VHD"/>
     105      <outfile xil_pn:name="SCHEDULER14_14.VHD"/>
     106      <outfile xil_pn:name="SCHEDULER15_15.VHD"/>
     107      <outfile xil_pn:name="SCHEDULER16_16.VHD"/>
     108      <outfile xil_pn:name="SCHEDULER2_2.VHD"/>
     109      <outfile xil_pn:name="SCHEDULER3_3.VHD"/>
     110      <outfile xil_pn:name="SCHEDULER4_4.VHD"/>
     111      <outfile xil_pn:name="SCHEDULER5_5.VHD"/>
     112      <outfile xil_pn:name="SCHEDULER6_6.VHD"/>
     113      <outfile xil_pn:name="SCHEDULER7_7.VHD"/>
     114      <outfile xil_pn:name="SCHEDULER8_8.VHD"/>
     115      <outfile xil_pn:name="SCHEDULER9_9.VHD"/>
     116      <outfile xil_pn:name="SWITCH_GEN.vhd"/>
     117      <outfile xil_pn:name="SWITCH_GENERIQUE.vhd"/>
     118      <outfile xil_pn:name="Scheduler.vhd"/>
     119      <outfile xil_pn:name="conv.vhd"/>
     120      <outfile xil_pn:name="proto_send.vhd"/>
     121      <outfile xil_pn:name="stimuli1.vhd"/>
     122      <outfile xil_pn:name="test_xbar_8x8.vhd"/>
     123    </transform>
     124    <transform xil_pn:end_ts="1370435977" xil_pn:in_ck="9216248337673135807" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4512714324515926764" xil_pn:start_ts="1370435946">
     125      <status xil_pn:value="FailedRun"/>
     126      <status xil_pn:value="ReadyToRun"/>
     127    </transform>
     128  </transforms>
    32129
    33130</generated_project>
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