- Timestamp:
- Dec 20, 2013, 7:55:55 PM (11 years ago)
- File:
-
- 1 edited
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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise
r64 r70 86 86 <file xil_pn:fileType="FILE_NCD" xil_pn:name="EX4_FSM_guide.ncd" xil_pn:origination="imported"/> 87 87 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="FIFO_256_FWFT_isim_beh.exe"/> 88 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Hold_FSM_isim_beh.exe"/> 88 89 <file xil_pn:fileType="FILE_NCD" xil_pn:name="MPICORETEST_guide.ncd" xil_pn:origination="imported"/> 89 90 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MPI_CORE_SCHEDULER.bld"/> … … 113 114 <file xil_pn:fileType="FILE_HTML" xil_pn:name="MPI_CORE_SCHEDULER_summary.html"/> 114 115 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MPI_CORE_SCHEDULER_xst.xrpt"/> 116 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="MPI_NOC.fdo"/> 115 117 <file xil_pn:fileType="FILE_SPL" xil_pn:name="MPI_NOC.spl"/> 116 118 <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="MPI_NOC.sym" xil_pn:origination="imported"/> … … 118 120 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MultiMPITest.bld"/> 119 121 <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MultiMPITest.cmd_log"/> 122 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="MultiMPITest.fdo"/> 120 123 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MultiMPITest.lso"/> 121 124 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest.ncd" xil_pn:subbranch="Par"/> … … 160 163 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="PE.bld"/> 161 164 <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="PE.cmd_log"/> 165 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="PE.fdo"/> 162 166 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="PE.lso"/> 163 167 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="PE.ncd" xil_pn:subbranch="Par"/> … … 220 224 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_map.ncd" xil_pn:subbranch="Map"/> 221 225 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="SWITCH_GEN_map.ngm" xil_pn:subbranch="Map"/> 222 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_map.xrpt"/>223 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_ngdbuild.xrpt"/>224 226 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="SWITCH_GEN_pad.csv" xil_pn:subbranch="Par"/> 225 227 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="SWITCH_GEN_pad.txt" xil_pn:subbranch="Par"/> 226 228 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_par.xrpt"/> 227 229 <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GEN_summary.html"/> 228 <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="SWITCH_GEN_summary.xml"/>229 <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="SWITCH_GEN_usage.xml"/>230 230 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_xst.xrpt"/> 231 <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="SetBit.vhi"/> 231 232 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/> 232 233 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/> … … 266 267 <file xil_pn:fileType="FILE_HTML" xil_pn:name="load_instr_summary.html"/> 267 268 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="load_instr_xst.xrpt"/> 269 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="mpi_test.fdo"/> 268 270 <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mpi_test_beh.prj"/> 269 271 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="mpi_test_isim_beh.exe"/> … … 276 278 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/> 277 279 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_DMA_isim_beh.exe"/> 280 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="test_xbar_8x8.fdo"/> 278 281 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_xbar_8x8_isim_beh.exe"/> 279 282 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/> 280 283 <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/> 284 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/> 281 285 <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/> 282 286 <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> 287 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/> 283 288 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> 284 289 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> … … 290 295 <status xil_pn:value="FailedRun"/> 291 296 <status xil_pn:value="ReadyToRun"/> 292 </transform> 293 <transform xil_pn:end_ts="1366390106" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1366390106"> 294 <status xil_pn:value="SuccessfullyRun"/> 295 <status xil_pn:value="ReadyToRun"/> 296 </transform> 297 <transform xil_pn:end_ts="1366622930" xil_pn:in_ck="-6687518003772672403" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1366622930"> 298 <status xil_pn:value="SuccessfullyRun"/> 299 <status xil_pn:value="ReadyToRun"/> 297 <status xil_pn:value="OutOfDateForProperties"/> 298 </transform> 299 <transform xil_pn:end_ts="1367007171" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1367007171"> 300 <status xil_pn:value="SuccessfullyRun"/> 301 <status xil_pn:value="ReadyToRun"/> 302 </transform> 303 <transform xil_pn:end_ts="1387380771" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1387380771"> 304 <status xil_pn:value="SuccessfullyRun"/> 305 <status xil_pn:value="ReadyToRun"/> 306 <status xil_pn:value="OutOfDateForInputs"/> 307 <status xil_pn:value="OutOfDateForOutputs"/> 308 <status xil_pn:value="InputChanged"/> 309 <status xil_pn:value="OutputChanged"/> 300 310 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/> 301 311 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/> … … 336 346 <outfile xil_pn:name="EX4_FSM.vhd"/> 337 347 <outfile xil_pn:name="Ex0_Fsm.vhd"/> 348 <outfile xil_pn:name="Ex5_FSM.vhd"/> 338 349 <outfile xil_pn:name="FIFO_64_FWFT.vhd"/> 339 350 <outfile xil_pn:name="FIfo_mem.vhd"/> 340 351 <outfile xil_pn:name="FIfo_proc.vhd"/> 352 <outfile xil_pn:name="HT_process.vhd"/> 341 353 <outfile xil_pn:name="Hold_FSM.vhd"/> 342 354 <outfile xil_pn:name="MPICORETEST.vhd"/> … … 351 363 <outfile xil_pn:name="RAM_32_32.vhd"/> 352 364 <outfile xil_pn:name="RAM_64.vhd"/> 365 <outfile xil_pn:name="SetBit.vhd"/> 353 366 <outfile xil_pn:name="image_pkg.vhd"/> 354 367 <outfile xil_pn:name="load_instr.vhd"/> … … 358 371 <outfile xil_pn:name="test_DMA.vhd"/> 359 372 </transform> 360 <transform xil_pn:end_ts="1366610992" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1366610992"> 361 <status xil_pn:value="SuccessfullyRun"/> 362 <status xil_pn:value="ReadyToRun"/> 363 </transform> 364 <transform xil_pn:end_ts="1366610993" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1366610992"> 365 <status xil_pn:value="SuccessfullyRun"/> 366 <status xil_pn:value="ReadyToRun"/> 367 </transform> 368 <transform xil_pn:end_ts="1366390108" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1366390108"> 369 <status xil_pn:value="SuccessfullyRun"/> 370 <status xil_pn:value="ReadyToRun"/> 371 </transform> 372 <transform xil_pn:end_ts="1366622930" xil_pn:in_ck="-6687518003772672403" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1366622930"> 373 <status xil_pn:value="SuccessfullyRun"/> 374 <status xil_pn:value="ReadyToRun"/> 373 <transform xil_pn:end_ts="1384950666" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1384950666"> 374 <status xil_pn:value="SuccessfullyRun"/> 375 <status xil_pn:value="ReadyToRun"/> 376 </transform> 377 <transform xil_pn:end_ts="1384950668" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1384950666"> 378 <status xil_pn:value="SuccessfullyRun"/> 379 <status xil_pn:value="ReadyToRun"/> 380 </transform> 381 <transform xil_pn:end_ts="1375733793" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2670075927112038592" xil_pn:start_ts="1375733793"> 382 <status xil_pn:value="SuccessfullyRun"/> 383 <status xil_pn:value="ReadyToRun"/> 384 </transform> 385 <transform xil_pn:end_ts="1387380771" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1387380771"> 386 <status xil_pn:value="SuccessfullyRun"/> 387 <status xil_pn:value="ReadyToRun"/> 388 <status xil_pn:value="OutOfDateForInputs"/> 389 <status xil_pn:value="OutOfDateForPredecessor"/> 390 <status xil_pn:value="OutOfDateForOutputs"/> 391 <status xil_pn:value="InputChanged"/> 392 <status xil_pn:value="OutputChanged"/> 375 393 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/> 376 394 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/> … … 411 429 <outfile xil_pn:name="EX4_FSM.vhd"/> 412 430 <outfile xil_pn:name="Ex0_Fsm.vhd"/> 431 <outfile xil_pn:name="Ex5_FSM.vhd"/> 413 432 <outfile xil_pn:name="FIFO_64_FWFT.vhd"/> 414 433 <outfile xil_pn:name="FIfo_mem.vhd"/> 415 434 <outfile xil_pn:name="FIfo_proc.vhd"/> 435 <outfile xil_pn:name="HT_process.vhd"/> 416 436 <outfile xil_pn:name="Hold_FSM.vhd"/> 417 437 <outfile xil_pn:name="MPICORETEST.vhd"/> … … 426 446 <outfile xil_pn:name="RAM_32_32.vhd"/> 427 447 <outfile xil_pn:name="RAM_64.vhd"/> 448 <outfile xil_pn:name="SetBit.vhd"/> 428 449 <outfile xil_pn:name="image_pkg.vhd"/> 429 450 <outfile xil_pn:name="load_instr.vhd"/> … … 433 454 <outfile xil_pn:name="test_DMA.vhd"/> 434 455 </transform> 435 <transform xil_pn:end_ts="1366622969" xil_pn:in_ck="-6687518003772672403" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-471607606114857674" xil_pn:start_ts="1366622930"> 436 <status xil_pn:value="SuccessfullyRun"/> 437 <status xil_pn:value="ReadyToRun"/> 438 <status xil_pn:value="OutOfDateForOutputs"/> 439 <status xil_pn:value="OutputChanged"/> 440 <outfile xil_pn:name="fuse.log"/> 441 <outfile xil_pn:name="isim"/> 442 <outfile xil_pn:name="isim.log"/> 443 <outfile xil_pn:name="mpi_test_beh.prj"/> 444 <outfile xil_pn:name="mpi_test_isim_beh.exe"/> 445 <outfile xil_pn:name="xilinxsim.ini"/> 446 </transform> 447 <transform xil_pn:end_ts="1366622969" xil_pn:in_ck="2617743916491253678" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="810398370776000169" xil_pn:start_ts="1366622969"> 448 <status xil_pn:value="SuccessfullyRun"/> 449 <status xil_pn:value="ReadyToRun"/> 450 <status xil_pn:value="OutOfDateForOutputs"/> 451 <status xil_pn:value="OutputChanged"/> 452 <outfile xil_pn:name="isim.cmd"/> 453 <outfile xil_pn:name="isim.log"/> 454 <outfile xil_pn:name="mpi_test_isim_beh.wdb"/> 455 </transform> 456 <transform xil_pn:end_ts="1354901662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1354901662"> 457 <status xil_pn:value="SuccessfullyRun"/> 458 <status xil_pn:value="ReadyToRun"/> 459 </transform> 460 <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1582102620978348987" xil_pn:start_ts="1364403007"> 461 <status xil_pn:value="SuccessfullyRun"/> 462 <status xil_pn:value="ReadyToRun"/> 463 <status xil_pn:value="OutOfDateForInputs"/> 464 <status xil_pn:value="InputAdded"/> 465 <status xil_pn:value="InputChanged"/> 466 </transform> 467 <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1364403007"> 468 <status xil_pn:value="SuccessfullyRun"/> 469 <status xil_pn:value="ReadyToRun"/> 470 </transform> 471 <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1364403007"> 472 <status xil_pn:value="SuccessfullyRun"/> 473 <status xil_pn:value="ReadyToRun"/> 474 </transform> 475 <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1364403007"> 476 <status xil_pn:value="SuccessfullyRun"/> 477 <status xil_pn:value="ReadyToRun"/> 478 </transform> 479 <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1364403007"> 480 <status xil_pn:value="SuccessfullyRun"/> 481 <status xil_pn:value="ReadyToRun"/> 482 <status xil_pn:value="OutOfDateForPredecessor"/> 483 </transform> 484 <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4624523187203829856" xil_pn:start_ts="1364403007"> 485 <status xil_pn:value="SuccessfullyRun"/> 486 <status xil_pn:value="ReadyToRun"/> 487 <status xil_pn:value="OutOfDateForPredecessor"/> 488 </transform> 489 <transform xil_pn:end_ts="1365597033" xil_pn:in_ck="-7317970075764060686" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-1458878356683843968" xil_pn:start_ts="1365596908"> 490 <status xil_pn:value="SuccessfullyRun"/> 491 <status xil_pn:value="WarningsGenerated"/> 456 <transform xil_pn:end_ts="1387380806" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-6667380628693525942" xil_pn:start_ts="1387380771"> 457 <status xil_pn:value="SuccessfullyRun"/> 492 458 <status xil_pn:value="ReadyToRun"/> 493 459 <status xil_pn:value="OutOfDateForInputs"/> 494 460 <status xil_pn:value="OutOfDateForPredecessor"/> 495 <status xil_pn:value="InputAdded"/> 461 <status xil_pn:value="OutOfDateForOutputs"/> 462 <status xil_pn:value="InputChanged"/> 463 <status xil_pn:value="OutputChanged"/> 464 <outfile xil_pn:name="mpi_test.fdo"/> 465 <outfile xil_pn:name="vsim.wlf"/> 466 <outfile xil_pn:name="work"/> 467 </transform> 468 <transform xil_pn:end_ts="1354901662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1354901662"> 469 <status xil_pn:value="SuccessfullyRun"/> 470 <status xil_pn:value="ReadyToRun"/> 471 </transform> 472 <transform xil_pn:end_ts="1383365892" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1582102620978348987" xil_pn:start_ts="1383365882"> 473 <status xil_pn:value="SuccessfullyRun"/> 474 <status xil_pn:value="ReadyToRun"/> 475 </transform> 476 <transform xil_pn:end_ts="1375422910" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2670075927112038592" xil_pn:start_ts="1375422910"> 477 <status xil_pn:value="SuccessfullyRun"/> 478 <status xil_pn:value="ReadyToRun"/> 479 </transform> 480 <transform xil_pn:end_ts="1375399240" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1375399240"> 481 <status xil_pn:value="SuccessfullyRun"/> 482 <status xil_pn:value="ReadyToRun"/> 483 </transform> 484 <transform xil_pn:end_ts="1375399240" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1375399240"> 485 <status xil_pn:value="SuccessfullyRun"/> 486 <status xil_pn:value="ReadyToRun"/> 487 </transform> 488 <transform xil_pn:end_ts="1375422910" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="6952878091308752832" xil_pn:start_ts="1375422910"> 489 <status xil_pn:value="SuccessfullyRun"/> 490 <status xil_pn:value="ReadyToRun"/> 491 </transform> 492 <transform xil_pn:end_ts="1375422910" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8344791072052426826" xil_pn:start_ts="1375422910"> 493 <status xil_pn:value="SuccessfullyRun"/> 494 <status xil_pn:value="ReadyToRun"/> 495 </transform> 496 <transform xil_pn:end_ts="1385740019" xil_pn:in_ck="-8697612743778259046" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4800614739687910250" xil_pn:start_ts="1385739753"> 497 <status xil_pn:value="SuccessfullyRun"/> 498 <status xil_pn:value="WarningsGenerated"/> 499 <status xil_pn:value="ReadyToRun"/> 500 <status xil_pn:value="OutOfDateForInputs"/> 496 501 <status xil_pn:value="InputChanged"/> 497 502 <outfile xil_pn:name="Crossbar.ngr"/> … … 515 520 <outfile xil_pn:name="xst"/> 516 521 </transform> 517 <transform xil_pn:end_ts="1365008714" xil_pn:in_ck="6885079285025204965" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1365008714"> 518 <status xil_pn:value="SuccessfullyRun"/> 519 <status xil_pn:value="ReadyToRun"/> 520 <status xil_pn:value="OutOfDateForPredecessor"/> 521 </transform> 522 <transform xil_pn:end_ts="1365597048" xil_pn:in_ck="3099115937148329492" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-5155457213437603231" xil_pn:start_ts="1365597033"> 522 <transform xil_pn:end_ts="1383365919" xil_pn:in_ck="6885079285025204965" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1383365918"> 523 <status xil_pn:value="SuccessfullyRun"/> 524 <status xil_pn:value="ReadyToRun"/> 525 </transform> 526 <transform xil_pn:end_ts="1385740045" xil_pn:in_ck="3099115937148329492" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1241333572523989429" xil_pn:start_ts="1385740019"> 523 527 <status xil_pn:value="SuccessfullyRun"/> 524 528 <status xil_pn:value="WarningsGenerated"/> … … 531 535 <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> 532 536 </transform> 533 <transform xil_pn:end_ts="13 65597494" xil_pn:in_ck="4998795473985982555" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4079613270754646221" xil_pn:start_ts="1365597048">534 <status xil_pn:value=" SuccessfullyRun"/>537 <transform xil_pn:end_ts="1385740175" xil_pn:in_ck="4998795473985982555" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2137179975354236087" xil_pn:start_ts="1385740045"> 538 <status xil_pn:value="FailedRun"/> 535 539 <status xil_pn:value="WarningsGenerated"/> 536 540 <status xil_pn:value="ReadyToRun"/> … … 539 543 <outfile xil_pn:name="MultiMPITest_map.map"/> 540 544 <outfile xil_pn:name="MultiMPITest_map.mrp"/> 541 <outfile xil_pn:name="MultiMPITest_map.ncd"/>542 545 <outfile xil_pn:name="MultiMPITest_map.ngm"/> 543 546 <outfile xil_pn:name="MultiMPITest_map.xrpt"/> … … 546 549 <outfile xil_pn:name="_xmsgs/map.xmsgs"/> 547 550 </transform> 548 <transform xil_pn:end_ts="13 65598174" xil_pn:in_ck="-2175087184199880886" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1365597494">549 <status xil_pn:value=" SuccessfullyRun"/>550 <status xil_pn:value=" WarningsGenerated"/>551 <status xil_pn:value=" ReadyToRun"/>551 <transform xil_pn:end_ts="1375723360" xil_pn:in_ck="-2175087184199880886" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="832869163894192598" xil_pn:start_ts="1375723309"> 552 <status xil_pn:value="AbortedRun"/> 553 <status xil_pn:value="ReadyToRun"/> 554 <status xil_pn:value="OutOfDateForInputs"/> 552 555 <status xil_pn:value="OutOfDateForPredecessor"/> 553 <outfile xil_pn:name="MultiMPITest.ncd"/> 554 <outfile xil_pn:name="MultiMPITest.pad"/> 555 <outfile xil_pn:name="MultiMPITest.par"/> 556 <outfile xil_pn:name="MultiMPITest.ptwx"/> 557 <outfile xil_pn:name="MultiMPITest.unroutes"/> 558 <outfile xil_pn:name="MultiMPITest.xpi"/> 559 <outfile xil_pn:name="MultiMPITest_pad.csv"/> 560 <outfile xil_pn:name="MultiMPITest_pad.txt"/> 561 <outfile xil_pn:name="MultiMPITest_par.xrpt"/> 562 <outfile xil_pn:name="_xmsgs/par.xmsgs"/> 563 </transform> 564 <transform xil_pn:end_ts="1365598174" xil_pn:in_ck="-5951230430360050753" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1365598146"> 565 <status xil_pn:value="SuccessfullyRun"/> 566 <status xil_pn:value="ReadyToRun"/> 556 <status xil_pn:value="OutOfDateForOutputs"/> 557 <status xil_pn:value="InputChanged"/> 558 <status xil_pn:value="InputRemoved"/> 559 <status xil_pn:value="OutputChanged"/> 560 <status xil_pn:value="OutputRemoved"/> 561 </transform> 562 <transform xil_pn:end_ts="1375521689" xil_pn:in_ck="-8422061398529632623" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1375521634"> 563 <status xil_pn:value="SuccessfullyRun"/> 564 <status xil_pn:value="ReadyToRun"/> 565 <status xil_pn:value="OutOfDateForInputs"/> 567 566 <status xil_pn:value="OutOfDateForPredecessor"/> 568 <outfile xil_pn:name="MultiMPITest.twr"/> 569 <outfile xil_pn:name="MultiMPITest.twx"/> 570 <outfile xil_pn:name="_xmsgs/trce.xmsgs"/> 567 <status xil_pn:value="OutOfDateForOutputs"/> 568 <status xil_pn:value="InputChanged"/> 569 <status xil_pn:value="InputRemoved"/> 570 <status xil_pn:value="OutputChanged"/> 571 <status xil_pn:value="OutputRemoved"/> 571 572 </transform> 572 573 </transforms>
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