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Changeset 70 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/load_instr.vhd
- Timestamp:
- Dec 20, 2013, 7:55:55 PM (11 years ago)
- File:
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- 1 edited
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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/load_instr.vhd
r64 r70 9 9 -- Target Devices: 10 10 -- Tool versions: 11 -- Description: Ce m dule permet de charger une instruction dans le FIFO 111 -- Description: Ce module permet de charger une instruction dans le FIFO 1 12 12 -- 13 13 -- Dependencies: … … 56 56 --signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM 57 57 signal Base_Adr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); 58 58 signal adr_ptr : natural range 0 to 65536:=0; 59 59 signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée 60 signal fifo_din_i:std_logic_vector(WORD-1 downto 0):=(others=>'Z'); 60 signal fifo_din_i:std_logic_vector(WORD-1 downto 0):=(others=>'-'); 61 signal iLen,iLen_i : natural range 0 to 15:=0; --longueur de l'instruction à copier dans le Fifo 61 62 signal fifo_wr_i :std_logic:='0'; 62 63 signal base_adrset_i : std_logic:='0'; … … 79 80 Base_AdrSet<=Base_adrSet_i; 80 81 ram_address_rd<=ram_address_i; 82 adr_ptr<=to_integer(unsigned(ram_address_i)); 81 83 dma_rd_request<=dma_rd_request_i; 82 84 instruction_ack<=instruction_ack_i; 83 85 count<=count_i; 86 Ilen<=Ilen_i; 84 87 85 88 … … 102 105 Ram_rd_en<='0'; 103 106 Instruction_ack_i<='0'; 104 fifo_din_i<=(others=>' Z');107 fifo_din_i<=(others=>'-'); 105 108 Base_AdrSet_i<='0'; 106 109 … … 112 115 Ram_rd_en<='0'; 113 116 114 fifo_din_i<=(others=>' Z');117 fifo_din_i<=(others=>'-'); 115 118 Base_AdrSet_i<='1'; 116 119 … … 121 124 Dma_rd_request_i<='1'; 122 125 Instruction_ack_i<='0'; 123 fifo_din_i<=(others=>' Z');126 fifo_din_i<=(others=>'-'); 124 127 Base_AdrSet_i<='1'; 125 128 when readptr => … … 130 133 Dma_rd_request_i<='1'; 131 134 Instruction_ack_i<='0'; 132 fifo_din_i<=(others=>' Z');135 fifo_din_i<=(others=>'-'); 133 136 Base_AdrSet_i<='1'; 134 137 when readmem => … … 147 150 Ram_rd_en<='0'; 148 151 Instruction_ack_i<='1'; 149 fifo_din_i<=(others=>' Z');152 fifo_din_i<=(others=>'-'); 150 153 Base_AdrSet_i<='1'; 151 154 when st_timeout => … … 155 158 Ram_rd_en<='0'; 156 159 Instruction_ack_i<='0'; 157 fifo_din_i<=(others=>' Z');160 fifo_din_i<=(others=>'-'); 158 161 Base_AdrSet_i<='1'; 159 162 end case; 160 163 end process; 161 164 162 NEXT_STATE_DECODE: process (etloadinst, Base_AdrSet,Ram_data,Instruction,instruction_en, fifo_full,dma_rd_grant,count )165 NEXT_STATE_DECODE: process (etloadinst, Base_AdrSet,Ram_data,Instruction,instruction_en, fifo_full,dma_rd_grant,count,Ilen) 163 166 variable ptr : std_logic_vector(ADRLEN-1 downto 0); 164 167 variable timeout: natural range 0 to 255; … … 171 174 case (etloadinst) is 172 175 when init => if base_adrset='1' and Instruction_en='1' then 173 176 Ilen_i<=to_integer(unsigned(Instruction(3 downto 0)));--initialisation de longueur 174 177 next_loadinst<=getbus; 175 178 elsif Instruction_en='1' then … … 179 182 next_loadinst<=init; 180 183 Base_Adr<=X"0000"; 184 Ilen_i<=0; 181 185 end if; 182 186 fifo_wr_i<='0'; 183 187 count_i<=0; 188 184 189 -- 185 190 When Setadr => if Base_adrSet='0' then 186 Base_Adr<= instruction& X"00"; --récupération des bits de poids forts de l'instruction191 Base_Adr<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction 187 192 -- 188 193 end if; 189 194 next_loadinst<=init; 190 Ram_address_i<=(others=>' Z');195 Ram_address_i<=(others=>'-'); 191 196 count_i<=0; 192 197 when getbus => … … 196 201 197 202 -- prépare la prochaine lecture 198 199 203 200 204 else 201 205 202 206 end if; 203 Ram_address_i<=(others=>' Z');207 Ram_address_i<=(others=>'-'); 204 208 count_i<=0; 205 209 When readptr => … … 226 230 elsif count=5 then 227 231 ptr(15 downto 8):=Ram_data; 228 --count_i <=count+1;229 --elsif count=6 then230 --ptr(15 downto 8):=Ram_data;231 232 count_i<=0; 232 233 timeout:=0; … … 242 243 if dma_rd_grant = '1' then --s'assurer que le bus est disponible 243 244 if fifo_full='0' then 244 245 if ilen >0 then 245 246 if count=0 then 246 247 iptr:=to_integer(unsigned(ptr)); … … 253 254 elsif count=2 then 254 255 count_i <=count+1; 255 AdrTmp:= iptr+1; --incrémentation de l'adresse256 AdrTmp:=Adr_ptr+1; --incrémentation de l'adresse 256 257 fifo_wr_i<='0'; 257 258 elsif count=3 then 258 259 count_i <=count+1; 259 260 fifo_wr_i<='1'; --écriture de la donnée dans le fifo 261 Ilen_i<=Ilen-1; 260 262 elsif count=4 then 261 263 fifo_wr_i<='0'; 262 263 count_i <=count+1; 264 elsif count=5 then 265 fifo_wr_i<='1'; --lecture de la donnée 2 266 count_i <=count+1; 267 AdrTmp:=iptr+2; 268 elsif count=6 then 269 count_i <=count+1; 270 fifo_wr_i<='0'; 271 elsif count=7 then 272 count_i <=count+1; 273 fifo_wr_i<='0'; 274 elsif count=8 then 275 fifo_wr_i<='1';--lecture de la donnée 3 276 count_i <=count+1; 277 AdrTmp:=iptr+3; 278 elsif count =9 then 279 count_i <=count+1; 280 281 fifo_wr_i<='0'; 282 elsif count=10 then 283 count_i <=count+1; 284 fifo_wr_i<='0'; 285 286 elsif count=11 then 287 fifo_wr_i<='1'; --lecture de la donnée 4 288 count_i <=count+1; 289 ADRTmp:=iptr+4;--incrémente l'adresse 290 elsif count =12 then 291 count_i <=count+1; 292 293 fifo_wr_i<='0'; 294 elsif count=13 then 295 count_i <=count+1; 296 fifo_wr_i<='0'; 297 elsif count=14 then 298 fifo_wr_i<='1';--lecture de la donnée 5 299 count_i <=count+1; 300 ADRtmp:=iptr+5; 301 elsif count =15 then 302 count_i <=count+1; 303 fifo_wr_i<='0'; 304 elsif count=16 then 305 count_i <=count+1; 306 fifo_wr_i<='0'; 307 elsif count=17 then 308 fifo_wr_i<='1';--lecture de la donnée 6 309 count_i <=count+1; 310 next_loadinst <= freebus; 264 count_i<=1; 311 265 end if; 312 266 else 267 fifo_wr_i<='0'; 268 next_loadinst <= freebus; 269 end if; 270 313 271 Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16)); 314 272 end if; … … 319 277 next_loadinst<=st_timeout; 320 278 end if; 321 Ram_address_i<=(others=>' Z'); -- le bus n'est pas libre279 Ram_address_i<=(others=>'-'); -- le bus n'est pas libre 322 280 323 281 end if; … … 326 284 fifo_wr_i<='0'; 327 285 count_i<=0; 328 Ram_address_i<=(others=>' Z');286 Ram_address_i<=(others=>'-'); 329 287 if instruction_en='0' then 330 288 next_loadinst <= init; … … 332 290 when st_timeout => 333 291 fifo_wr_i<='0'; 334 Ram_address_i<=(others=>' Z');292 Ram_address_i<=(others=>'-'); 335 293 next_loadinst<=init; 336 294 count_i<=0;
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