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Changeset 71 for PROJECT_CORE_MPI
- Timestamp:
- Dec 20, 2013, 9:20:36 PM (11 years ago)
- Location:
- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03
- Files:
-
- 3 edited
-
CoreTypes.vhd (modified) (3 diffs)
-
INPUT_PORT_MODULE.vhd (modified) (2 diffs)
-
proto_send.vhd (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
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PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/CoreTypes.vhd
r69 r71 37 37 type memory is 38 38 array (natural range <>) of std_logic_vector(word-1 downto 0); 39 40 type Core_io is 39 40 type Core_i is 41 record 42 Instr_ack :std_logic;-- signal la prise en compte de l'instruction 43 Ready :std_logic;-- indique que la dernière fonction est terminée 44 InitOk :std_logic; -- l'initialisation est terminée 45 Hold_Req :std_logic;--Demande DMA 46 RamSel :std_logic;-- indique le statut de la RAM (0 ->dispo 1->occupé par Core_MPI) 47 IsMain : std_logic; -- indique si la librairie est principal 48 Rank : natural range 0 to 15; --donne le rang du processus courant 49 Spawned: std_logic; --indique que ce module a été activé par la bibliothèque 50 end record; 51 type Core_o is 52 record 53 Instr_en :std_logic; -- active une instruction MPI 54 Hold_Ack :std_logic;-- Autorisation DMA 55 MemBusy :std_logic;-- active le refus de DMA (1 -> ignoré la requête DMA de MPI HCL) 56 Instruction :std_logic_vector (word-1 downto 0); -- fonction Mpi à exécuter 57 end record; 58 type core_s is 59 record 60 IntState1 : natural range 0 to 255; --permet de stocker l'état des MAE interne dans les procédures 61 IntState2 : natural range 0 to 255; 62 WinId :natural range 0 to 255; --stocke le dernier Id utilisé par WinCreate 63 end record; 64 type core_io is 65 record 66 I:core_i; --les entrées 67 O:core_o; --les sorties 68 S:core_s; --les signaux temporaires 69 end record; 70 71 type Core_io_old is 41 72 record 42 73 Instr_en :std_logic; -- active une instruction MPI … … 53 84 WinId :natural range 0 to 255; --stocke le dernier Id utilisé par WinCreate 54 85 IsMain : std_logic; -- indique si la librairie est principal 55 Rank : natural range 0 to 1 6; --donne le rang du processus courant86 Rank : natural range 0 to 15; --donne le rang du processus courant 56 87 Spawned: std_logic; --indique que ce module a été activé par la bibliothèque 57 88 end record; 58 89 59 type typ_dpram is 60 record 61 62 63 clk_wr : STD_LOGIC; 64 clk_rd : STD_LOGIC; 90 type typ_dpram_i is 91 record 92 data_out : STD_LOGIC_VECTOR (Word-1 downto 0); 93 94 end record; 95 type typ_dpram_o is 96 record 97 clk_wr : STD_LOGIC; 98 clk_rd : STD_LOGIC; 65 99 we : STD_LOGIC; 66 100 ena : STD_LOGIC; … … 68 102 addr_wr: STD_LOGIC_VECTOR (ADRLEN-1 downto 0); 69 103 addr_rd : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); 70 data_in : STD_LOGIC_VECTOR (Word-1 downto 0); 71 data_out : STD_LOGIC_VECTOR (Word-1 downto 0); 72 73 74 end record; 104 data_in : STD_LOGIC_VECTOR (Word-1 downto 0); 105 end record; 106 type typ_dpram is 107 record 108 O : typ_dpram_o; 109 I : typ_dpram_I; 110 end record; 75 111 type Typ_MPIPort_in is 76 112 record -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/INPUT_PORT_MODULE.vhd
r65 r71 552 552 ReadOk<='0'; 553 553 pop_state<=stateErr; 554 data_counter<=(others => '0');554 --data_counter<=(others => '0'); 555 555 end if; 556 556 else … … 605 605 dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request 606 606 dat_data_out_pulse <= '0'; --transmettre le signal pour le dernier mot 607 dat_priority_rotation <= '0';607 dat_priority_rotation <= Port_granted; --dès qu'on a la priorité on la garde 608 608 dat_exec<='1'; 609 609 dat_Err<='0'; -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd
r69 r71 21 21 use IEEE.STD_LOGIC_1164.ALL; 22 22 USE ieee.numeric_std.ALL; 23 use CoreTypes.all;23 use work.CoreTypes.all; 24 24 -- Uncomment the following library declaration if using 25 25 -- arithmetic functions with Signed or Unsigned values … … 35 35 port ( 36 36 clk,reset : in std_logic; 37 fifo_empty,fifo_full : in std_logic; 38 push : out std_logic:='0'; 39 fifo_in : out std_logic_vector(Word-1 downto 0); 37 fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée 38 fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie 39 fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie 40 fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée 41 fifo_in_data_out : in std_logic_vector(Word-1 downto 0); 42 fifo_out_data_in : out std_logic_vector(Word-1 downto 0); 43 packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet 44 copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo 40 45 snd_start : in std_logic; --début de la réception 41 46 snd_ack :in std_logic; -- acquittement de la réception 42 47 snd_comp : out std_logic; -- fin de la réception 43 mem :in memory(0 to sizemem-1)); 48 mem :in memory(0 to sizemem-1)); --données à copier vers le fifo 44 49 45 50 end proto_send; … … 48 53 type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end); 49 54 signal etsnd : typ_send; 50 signal sfifo_in : std_logic_vector(Word-1 downto 0); 55 signal snd_state,next_snd_state:natural range 0 to 7:=0; 56 signal p_len,p_len_i : natural range 0 to 255; 57 signal n,n_i:natural range 0 to 7; 58 signal wr_ok,rd_ok:std_logic:='0'; 59 signal sfifo_in,Data_to_send : std_logic_vector(Word-1 downto 0); 51 60 signal spush : std_logic:='0'; 52 61 signal err : std_logic_vector(Word-1 downto 0):=(others =>'0'); 53 62 begin 54 63 55 proc_send : process (clk,reset) 56 variable dlen,i: natural range 0 to 255 :=0; 64 Fifo_copy_sync:process(clk) 65 66 begin 67 if rising_edge(clk) then 68 69 if reset='1' then 70 n<=0; 71 Snd_state<=0; 72 P_len<=0; 73 else 74 Snd_state<=Next_Snd_state; 75 n<=n_i; 76 p_len<=P_len_i; 77 end if; 78 end if; 79 end process fifo_copy_sync; 80 -- affectation concurentes 81 Fifo_copy_val:process (Snd_state,Etsnd,copy_mode,data_to_send,rd_ok,wr_ok,spush) 82 begin 83 if copy_mode='0' then 84 fifo_out_wr_en<=wr_ok; 85 fifo_out_data_in<=data_to_send; 86 fifo_in_rd_en<='0'; 87 else 88 if (Snd_state=1) or (snd_state=2) then 89 fifo_out_wr_en<=wr_ok; 90 fifo_in_rd_en<=rd_ok; 91 fifo_out_data_in<=data_to_send; 92 end if; 93 end if; 94 end process fifo_copy_val; 95 -- process qui envoie des données en provenance d'un Fifo vers un Fifo 96 FIfo_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack,fifo_in_empty, 97 fifo_out_full,Fifo_in_data_out,p_len) 98 variable onepop:std_logic:='0'; 57 99 begin 58 if reset='1' then 59 etsnd<=s_head; 60 err<=(others =>'0'); 61 else 62 if rising_edge(clk) then -- le process s'exécute sur chaque front 63 -- montant de l'horloge 64 case etsnd is 65 when s_head => 66 sfifo_in<=mem(0); 67 snd_comp<='0'; 68 i:=0; 69 70 if fifo_empty='1' and snd_start='1' then 71 spush<='1'; 72 snd_comp<='0'; 73 etsnd<=s_len; 74 end if; 75 when s_pulse => 76 spush<='1'; 77 etsnd<=s_len; 78 when s_len => 79 sfifo_in<=mem(1); --8 données 80 i:=i+1; 81 dlen:=to_integer(unsigned(mem(i))); 82 if dlen > 2 then 83 spush<='1'; 84 snd_comp<='0'; 85 etsnd<=s_data; 86 else 87 spush<='1'; 88 snd_comp<='1'; 89 etsnd<=s_end; 90 91 end if; 92 when s_len2 => 93 snd_comp<='0'; 94 etsnd<=s_data; 95 96 when s_data => 97 if (fifo_full='0') and (dlen >2) then 98 i:=i+1; 99 sfifo_in<=mem(i); 100 if i>=dlen-1 then --les indices 0 et 1 étant réservés 101 --les données sont comptés à partir de 2 102 etsnd<=s_end; 103 snd_comp<='1'; 104 spush<='1'; 105 else 106 spush<='1'; 107 end if; 108 109 else 110 spush<='0'; 111 end if; 112 113 when s_end => 114 spush<='0'; 115 etsnd<=s_head; 116 sfifo_in<=(others=>'-'); 117 if snd_ack='1' then 118 etsnd<=s_head; 119 end if; 120 when others => 121 spush<='0'; 122 etsnd<=s_head; 123 sfifo_in<=(others=>'0'); 124 end case; 125 end if; 126 end if; 127 end process; 100 Next_snd_state<=snd_state; --valeur par defaut 101 case snd_state is 102 103 when 0 => if snd_start='1' then 104 P_len_i<=to_integer(unsigned(packet_len)); 105 next_snd_state<=1; 106 n_i<=0; 107 end if; 108 wr_ok<='0';rd_ok<='0';onepop:='0'; 109 snd_comp<='0'; 110 when 1=> if P_len>0 then 111 if copy_mode='1' then 112 if fifo_in_empty='0' and onepop='0' then 113 data_to_send <=fifo_in_data_out ; 114 rd_Ok<='1'; 115 onepop:=not onepop; --une donnée lue il faut arrêter de dépiler 116 117 else 118 rd_Ok<='0'; 119 end if; 120 else 121 onepop:='1'; 122 data_to_send<=mem(n); 123 end if; 124 125 if (fifo_out_full = '0') and onepop='1' then wr_ok<='1'; 126 onepop:=not onepop; 127 wr_ok<='1'; 128 p_len_i<=p_len-1; 129 n_i<=n+1; 130 131 else 132 wr_Ok<='0'; 133 134 end if; 135 else 136 rd_ok<='0';wr_ok<='0'; 137 next_snd_state<=2; 138 snd_comp<='1'; 139 end if; 140 when 2 => --fin de la copie 141 if snd_ack='1' then 142 143 next_snd_state<=3; 144 end if; 145 wr_ok<='0';rd_ok<='0'; 146 snd_comp<='1'; 147 data_to_send <=(others=>'-'); 148 when 3 =>next_snd_state<=0; 149 snd_comp<='0'; 150 151 when others => next_snd_state<=0; 152 snd_comp<='0'; 153 rd_ok<='0'; 154 wr_ok<='0'; 155 data_to_send <=(others=>'-'); 156 end case; 157 end process FIfo_to_fifo; 128 158 129 -- affectation concurentes130 131 push<=spush;132 fifo_in<=sfifo_in;133 159 end Behavioral; 134 160
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