source: PROJECT_SMART_EEG

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Diff Rev Age Author Log Message
(edit) @89   11 years szahmed Added Headline comments for Verilog files explaining their brief …
(edit) @88   11 years lambert Updating qsys file
(edit) @87   11 years lambert Adding generation simulation support for verilog
(edit) @86   11 years szahmed correct qsys.qsys
(edit) @85   11 years szahmed Added Projects folder
(edit) @84   11 years lambert Adding hierarchical subdirectory for every component
(edit) @83   11 years szahmed Initial Commit
(edit) @82   11 years lambert Removing .ht* tests, doesn't work sadly
(edit) @81   11 years lambert * Adding Doc/README to test revision file * Testing .htaccess and …
(edit) @80   11 years lambert Adding standard layout of svn tree
(add) @79   11 years lambert Introducing PROJECT_SMART_EEG in syel svn repository
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