source: PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec_hw.tcl

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Diff Rev Age Author Log Message
(edit) @87   10 years lambert Adding generation simulation support for verilog
(copy) @84   10 years lambert Adding hierarchical subdirectory for every component
copied from PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec_hw.tcl:
(add) @83   10 years szahmed Initial Commit
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