Changeset 23
- Timestamp:
- Apr 16, 2009, 2:47:08 PM (16 years ago)
- Location:
- sources/test_regression
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
sources/test_regression/02052006/system.cpp
r1 r23 13 13 14 14 struct test : sc_module { 15 int 15 int32_t reg; 16 16 sc_signal<bool> reg_bool; 17 17 sc_signal<int> reg_int; … … 38 38 ASSERT(((unsigned int)reg) == reg_unsigned_int .read()); 39 39 ASSERT(((char) reg) == reg_char .read()); 40 #if 0 41 cout << (double)reg << " " << reg_double.read() << endl; 42 cout << sizeof (double) << " " << sizeof (reg_double.read()) << endl; 43 #endif 40 44 ASSERT(((double)reg) == reg_double.read()); 41 45 ASSERT(((long) reg) == reg_long .read()); … … 48 52 ASSERT(((signed int) reg & 0xFFFFFFFF) == (signed int) (reg_i32 .read())); 49 53 ASSERT(((signed int) reg & 0x0000FFFF) == (signed int) (reg_i16 .read())); 50 ASSERT(((signed int) reg & 0x0000003F) 54 ASSERT(((signed int) reg & 0x0000003F) == (signed int) (reg_i6 .read())); 51 55 reg = reg + 1; 52 56 reg_bool = reg & 1; … … 54 58 reg_unsigned_int = reg; 55 59 reg_char = reg; 56 reg_double = reg;60 reg_double .write(reg); 57 61 reg_long = reg; 58 62 reg_ui32 = reg; … … 80 84 81 85 SC_HAS_PROCESS(test); 82 86 test (sc_module_name n) : sc_module (n), 83 87 clk("clk") 84 88 { 85 86 89 SC_METHOD(trans); 90 sensitive << clk.pos(); 87 91 dont_initialize(); 88 92 }; 89 93 }; 90 94 91 95 int sc_main (int argc, char *argv[]) 92 96 { 93 97 sc_clock signal_clk("my_clock",1, 0.5); 94 98 sc_signal<bool> resetn("resetn"); 95 99 … … 98 102 test1.resetn (resetn); 99 103 100 101 104 // Init & run 105 sc_start (0); 102 106 103 107 resetn = false; 104 108 sc_start (4); 105 109 resetn = true; 106 110 sc_start (100); 107 111 108 112 return EXIT_SUCCESS; 109 113 } 110 114 -
sources/test_regression/19042005/system.cpp
r1 r23 128 128 sc_trace(system_trace_file, signal_clk, "clk"); 129 129 130 bool b1 = 0;131 longl1 = 0;130 bool b1 = 0; 131 uint64_t l1 = 0; 132 132 133 133 #if 0 -
sources/test_regression/19042005/system_systemcass.x-60_reference.vcd
r1 r23 7 7 $var wire 1 aaa clk $end 8 8 $var wire 1 aab b1 $end 9 $var wire 32 aac l1 [31:0] $end9 $var wire 64 aac l1 [63:0] $end 10 10 $var wire 1 aad test1.i1 $end 11 11 $var wire 8 aae test1.i2 [7:0] $end -
sources/test_regression/28102005/system.cpp
r18 r23 27 27 check_time (int i) 28 28 { 29 29 const sc_time &t = sc_time_stamp (); 30 30 CERR(i); 31 31 CERR(t.to_double()); 32 #ifdef SYSTEMCASS_SPECIFIC 33 ASSERT((int) (t.to_double ()) == i); 34 #else 32 35 ASSERT((int) (t.to_double ()) == i * 1000); 36 #endif 33 37 CERR(t.to_seconds ()); 34 38 double seconds = t.to_seconds()*1000000000; … … 37 41 char s[256]; 38 42 const char *unit; 43 #ifdef SYSTEMCASS_SPECIFIC 44 unit = "NS"; 45 #else 39 46 if (i == 0) 40 47 unit = "s"; … … 43 50 else 44 51 unit = "ns"; 52 #endif 45 53 sprintf (s, "%d %s", i,unit); 46 54 CERR(s); … … 55 63 56 64 check_time (0); 57 65 sc_start (0); 58 66 59 67 check_time (0); 60 68 sc_start (1); 61 69 check_time (1); 62 70 63 71 sc_start (15); 64 72 check_time (16); 65 73 66 74 sc_start (7); 67 75 check_time (23); 68 76 69 77 sc_start (100); 70 78 check_time (123); 71 79 72 80 sc_start (1000); 73 81 check_time (1123); 74 82 cerr << "Test OK.\n";
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