[450] | 1 | /////////////////////////////////////////////////////////////////////////////// |
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[648] | 2 | // File: top.cpp |
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| 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : august 2013 |
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| 6 | // This program is released under the GNU public license |
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[648] | 7 | // |
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| 8 | // Modified by: Cesar Fuguet |
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| 9 | // Modified on: mars 2014 |
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[450] | 10 | /////////////////////////////////////////////////////////////////////////////// |
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[648] | 11 | // This file define a generic TSAR architecture with an IO network emulating |
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[450] | 12 | // an external bus (i.e. Hypertransport) to access external peripherals: |
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| 13 | // |
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[472] | 14 | // - BROM : boot ROM |
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| 15 | // - FBUF : Frame Buffer |
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| 16 | // - MTTY : multi TTY (up to 15 channels) |
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| 17 | // - MNIC : Network controller (up to 2 channels) |
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[498] | 18 | // - CDMA : Chained Buffer DMA controller (up to 4 channels) |
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[472] | 19 | // - BDEV : Dlock Device controler (1 channel) |
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[648] | 20 | // |
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[450] | 21 | // The internal physical address space is 40 bits. |
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| 22 | // |
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[607] | 23 | // It contains a 2D mesh of XMAX*YMAX clusters, and the cluster index |
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| 24 | // is encoded on 8 bits (X_WIDTH = 4 / Y_WIDTH = 4) whatever the mesh size. |
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[450] | 25 | // |
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[607] | 26 | // It contains 3 networks: |
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| 27 | // |
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[450] | 28 | // 1) the INT network supports Read/Write transactions |
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[648] | 29 | // between processors and L2 caches or peripherals. |
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[450] | 30 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 31 | // It supports also coherence transactions between L1 & L2 caches. |
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| 32 | // 3) the RAM network is emulating the 3D network between L2 caches |
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[472] | 33 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 34 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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[450] | 35 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 36 | // 4) the IOX network connects the two IO bridge components to the |
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| 37 | // 6 external peripheral controllers. |
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| 38 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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[648] | 39 | // |
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[472] | 40 | // The external peripherals IRQs are connected to the XICU component |
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[648] | 41 | // in cluster(0,0): therefore, the number of channels for the external |
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[472] | 42 | // peripherals (MTTY, MNIC, CDMA) is limited by the number of IRQ ports... |
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[450] | 43 | // |
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[584] | 44 | // In cluster(0,0), the XICU HWI input ports are connected as follow: |
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| 45 | // - IRQ_IN[0] to IRQ_IN[7] grounded (reserved for PTI or SWI) |
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[472] | 46 | // - IRQ_IN[8] to IRQ_IN[9] are connected to 2 NIC_RX channels. |
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| 47 | // - IRQ_IN[10] to IRQ_IN[11] are connected to 2 NIC_TX channels. |
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| 48 | // - IRQ_IN[12] to IRQ_IN[15] are connected to 4 CDMA channels |
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| 49 | // - IRQ_IN[16] to IRQ_IN[30] are connected to 15 TTY channels |
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| 50 | // - IRQ_IN[31] is connected to BDEV |
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[584] | 51 | // In other clusters, the XICU HWI input ports are grounded. |
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[648] | 52 | // |
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[450] | 53 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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| 54 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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| 55 | // connected to the three networks (INT, RAM, IOX). |
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| 56 | // The number of clusters cannot be larger than 256. |
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[472] | 57 | // The number of processors per cluster cannot be larger than 4. |
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[648] | 58 | // |
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[450] | 59 | // - It uses two dspin_local_crossbar per cluster to implement the |
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[648] | 60 | // local interconnect correponding to the INT network. |
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[450] | 61 | // - It uses two dspin_local_crossbar per cluster to implement the |
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[648] | 62 | // local interconnect correponding to the coherence INT network. |
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[450] | 63 | // - It uses two virtual_dspin_router per cluster to implement |
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| 64 | // the INT network (routing both the direct and coherence trafic). |
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| 65 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 66 | // - It uses the vci_cc_vcache_wrapper. |
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| 67 | // - It uses the vci_mem_cache. |
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| 68 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 69 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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| 70 | // |
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| 71 | // The TsarIobCluster component is defined in files |
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| 72 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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| 73 | // |
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| 74 | // The main hardware parameters must be defined in the hard_config.h file : |
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| 75 | // - XMAX : number of clusters in a row (power of 2) |
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| 76 | // - YMAX : number of clusters in a column (power of 2) |
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| 77 | // - CLUSTER_SIZE : size of the segment allocated to a cluster |
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| 78 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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| 79 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) |
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| 80 | // - NB_TTY_CHANNELS : number of TTY channels in I/O network (< 16) |
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| 81 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (< 9) |
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[648] | 82 | // |
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[450] | 83 | // Some secondary hardware parameters must be defined in this top.cpp file: |
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[648] | 84 | // - XRAM_LATENCY : external ram latency |
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[450] | 85 | // - MEMC_WAYS : L2 cache number of ways |
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| 86 | // - MEMC_SETS : L2 cache number of sets |
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[648] | 87 | // - L1_IWAYS |
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| 88 | // - L1_ISETS |
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| 89 | // - L1_DWAYS |
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| 90 | // - L1_DSETS |
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[450] | 91 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 92 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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| 93 | // - BDEV_SECTOR_SIZE : block size for block drvice |
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[648] | 94 | // - BDEV_IMAGE_NAME : file pathname for block device |
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[450] | 95 | // - NIC_RX_NAME : file pathname for NIC received packets |
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| 96 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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| 97 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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| 98 | // |
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| 99 | // General policy for 40 bits physical address decoding: |
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| 100 | // All physical segments base addresses are multiple of 1 Mbytes |
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[648] | 101 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[450] | 102 | // The (x_width + y_width) MSB bits (left aligned) define |
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| 103 | // the cluster index, and the LADR bits define the local index: |
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| 104 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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| 105 | // |x_width|y_width|---| 8 | 24 | |
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| 106 | // |
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| 107 | // General policy for 14 bits SRCID decoding: |
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| 108 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 109 | // | X_ID | Y_ID |---| L_ID | |
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| 110 | // |x_width|y_width|---| 6 | |
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| 111 | ///////////////////////////////////////////////////////////////////////// |
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| 112 | |
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| 113 | #include <systemc> |
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| 114 | #include <sys/time.h> |
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| 115 | #include <iostream> |
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| 116 | #include <sstream> |
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| 117 | #include <cstdlib> |
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| 118 | #include <cstdarg> |
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| 119 | #include <stdint.h> |
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| 120 | |
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| 121 | #include "gdbserver.h" |
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| 122 | #include "mapping_table.h" |
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| 123 | |
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| 124 | #include "tsar_iob_cluster.h" |
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| 125 | #include "vci_chbuf_dma.h" |
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| 126 | #include "vci_multi_tty.h" |
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| 127 | #include "vci_multi_nic.h" |
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| 128 | #include "vci_block_device_tsar.h" |
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| 129 | #include "vci_framebuffer.h" |
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| 130 | #include "vci_iox_network.h" |
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| 131 | |
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| 132 | #include "alloc_elems.h" |
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| 133 | |
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| 134 | /////////////////////////////////////////////////// |
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| 135 | // OS |
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| 136 | /////////////////////////////////////////////////// |
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| 137 | #define USE_ALMOS 0 |
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| 138 | |
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| 139 | #define almos_bootloader_pathname "bootloader.bin" |
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| 140 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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| 141 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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| 142 | |
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| 143 | /////////////////////////////////////////////////// |
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| 144 | // Parallelisation |
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| 145 | /////////////////////////////////////////////////// |
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[648] | 146 | #define USE_OPENMP 0 |
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[450] | 147 | |
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| 148 | #if USE_OPENMP |
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| 149 | #include <omp.h> |
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| 150 | #endif |
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| 151 | |
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| 152 | /////////////////////////////////////////////////////////// |
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[648] | 153 | // DSPIN parameters |
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[450] | 154 | /////////////////////////////////////////////////////////// |
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| 155 | |
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| 156 | #define dspin_int_cmd_width 39 |
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| 157 | #define dspin_int_rsp_width 32 |
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| 158 | |
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| 159 | #define dspin_ram_cmd_width 64 |
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| 160 | #define dspin_ram_rsp_width 64 |
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| 161 | |
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| 162 | /////////////////////////////////////////////////////////// |
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[648] | 163 | // VCI fields width for the 3 VCI networks |
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[450] | 164 | /////////////////////////////////////////////////////////// |
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| 165 | |
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[648] | 166 | #define vci_cell_width_int 4 |
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| 167 | #define vci_cell_width_ext 8 |
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[450] | 168 | |
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[648] | 169 | #define vci_plen_width 8 |
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| 170 | #define vci_address_width 40 |
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| 171 | #define vci_rerror_width 1 |
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| 172 | #define vci_clen_width 1 |
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| 173 | #define vci_rflag_width 1 |
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| 174 | #define vci_srcid_width 14 |
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| 175 | #define vci_pktid_width 4 |
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| 176 | #define vci_trdid_width 4 |
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| 177 | #define vci_wrplen_width 1 |
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[450] | 178 | |
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| 179 | //////////////////////////////////////////////////////////// |
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[648] | 180 | // Main Hardware Parameters values |
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[450] | 181 | //////////////////////i///////////////////////////////////// |
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| 182 | |
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[648] | 183 | #define X_WIDTH 4 |
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| 184 | #define Y_WIDTH 4 |
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| 185 | #define X_MAX (1<<X_WIDTH) |
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| 186 | #define Y_MAX (1<<Y_WIDTH) |
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[450] | 187 | |
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| 188 | //////////////////////////////////////////////////////////// |
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[648] | 189 | // Secondary Hardware Parameters values |
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[450] | 190 | //////////////////////i///////////////////////////////////// |
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| 191 | |
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[648] | 192 | #define XRAM_LATENCY 0 |
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[450] | 193 | |
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[648] | 194 | #define MEMC_WAYS 16 |
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| 195 | #define MEMC_SETS 256 |
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[450] | 196 | |
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[648] | 197 | #define L1_IWAYS 4 |
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| 198 | #define L1_ISETS 64 |
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[450] | 199 | |
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[648] | 200 | #define L1_DWAYS 4 |
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| 201 | #define L1_DSETS 64 |
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[450] | 202 | |
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[648] | 203 | #define FBUF_X_SIZE 128 |
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| 204 | #define FBUF_Y_SIZE 128 |
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[450] | 205 | |
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[648] | 206 | #define BDEV_SECTOR_SIZE 512 |
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| 207 | #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" |
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[450] | 208 | |
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[648] | 209 | #define NIC_RX_NAME "giet_vm/nic/rx_packets.txt" |
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| 210 | #define NIC_TX_NAME "giet_vm/nic/tx_packets.txt" |
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| 211 | #define NIC_TIMEOUT 10000 |
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[450] | 212 | |
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[648] | 213 | #define cluster(x,y) ((y) + ((x)<<4)) |
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[450] | 214 | |
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| 215 | //////////////////////////////////////////////////////////// |
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[648] | 216 | // Software to be loaded in ROM & RAM |
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[450] | 217 | //////////////////////i///////////////////////////////////// |
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| 218 | |
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[648] | 219 | #define BOOT_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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[450] | 220 | |
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| 221 | //////////////////////////////////////////////////////////// |
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[648] | 222 | // DEBUG Parameters default values |
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[450] | 223 | //////////////////////i///////////////////////////////////// |
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| 224 | |
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[648] | 225 | #define MAX_FROZEN_CYCLES 10000 |
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[450] | 226 | |
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| 227 | ///////////////////////////////////////////////////////// |
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| 228 | // Physical segments definition |
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| 229 | ///////////////////////////////////////////////////////// |
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| 230 | |
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[584] | 231 | // Non replicated peripherals (must be in cluster 0) |
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[450] | 232 | |
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[648] | 233 | #define BROM_BASE 0x00BFC00000 |
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[658] | 234 | #define BROM_SIZE 0x0000010000 // 64 Kbytes |
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[450] | 235 | |
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[648] | 236 | #define IOBX_BASE 0x00BE000000 |
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[658] | 237 | #define IOBX_SIZE 0x0000001000 // 4 Kbytes |
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[450] | 238 | |
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[648] | 239 | #define BDEV_BASE 0x00B3000000 |
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[658] | 240 | #define BDEV_SIZE 0x0000008000 // 4 Kbytes |
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[450] | 241 | |
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[648] | 242 | #define MTTY_BASE 0x00B4000000 |
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| 243 | #define MTTY_SIZE (0x0000001000 * 16) // 4 Kbytes |
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[450] | 244 | |
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[648] | 245 | #define MNIC_BASE 0x00B5000000 |
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| 246 | #define MNIC_SIZE 0x0000080000 // 512 Kbytes |
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[450] | 247 | |
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[648] | 248 | #define CDMA_BASE 0x00B6000000 |
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| 249 | #define CDMA_SIZE (0x0000001000 * 2) // 4 Kbytes per channel |
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[450] | 250 | |
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[648] | 251 | #define FBUF_BASE 0x00B7000000 |
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| 252 | #define FBUF_SIZE (800 * 600 * 2) |
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[450] | 253 | |
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[648] | 254 | // Replicated peripherals : address is incremented by a cluster offset |
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| 255 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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[450] | 256 | |
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[648] | 257 | #define XRAM_BASE 0x0000000000 |
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| 258 | #define XRAM_SIZE 0x0010000000 // 256 Mbytes |
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[450] | 259 | |
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[648] | 260 | #define XICU_BASE 0x00B0000000 |
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| 261 | #define XICU_SIZE 0x0000001000 // 4 Kbytes |
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[450] | 262 | |
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[648] | 263 | #define MDMA_BASE 0x00B1000000 |
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| 264 | #define MDMA_SIZE 0x0000001000 * 4 // 4 Kbytes per channel |
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[450] | 265 | |
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[648] | 266 | // Replicated mem segments (XRAM) : address is incremented by a cluster offset |
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| 267 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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[584] | 268 | |
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[648] | 269 | #define MEMC_BASE 0x00B2000000 |
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| 270 | #define MEMC_SIZE 0x0000001000 // 4 Kbytes |
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[450] | 271 | |
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| 272 | //////////////////////////////////////////////////////////////////////// |
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| 273 | // SRCID definition |
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| 274 | //////////////////////////////////////////////////////////////////////// |
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| 275 | // All initiators are in the same indexing space (14 bits). |
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| 276 | // The SRCID is structured in two fields: |
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| 277 | // - The 10 MSB bits define the cluster index (left aligned) |
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| 278 | // - The 4 LSB bits define the local index. |
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[648] | 279 | // Two different initiators cannot have the same SRCID, but a given |
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| 280 | // initiator can have two alias SRCIDs: |
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[450] | 281 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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| 282 | // and each initiator has one single SRCID. |
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| 283 | // - External initiators (bdev, cdma) are not replicated, but can be |
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[648] | 284 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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[450] | 285 | // They have the same local index, but two different cluster indexes. |
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| 286 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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[648] | 287 | // and external initiators, they must have different local indexes. |
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[450] | 288 | // Consequence: For a local interconnect, the INI_ID port index |
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| 289 | // is NOT equal to the SRCID local index, and the local interconnect |
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| 290 | // must make a translation: SRCID => INI_ID (port index) |
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| 291 | //////////////////////////////////////////////////////////////////////// |
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| 292 | |
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[648] | 293 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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| 294 | #define MDMA_LOCAL_SRCID 0x8 |
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| 295 | #define IOBX_LOCAL_SRCID 0x9 |
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| 296 | #define MEMC_LOCAL_SRCID 0xA |
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| 297 | #define CDMA_LOCAL_SRCID 0xE // hard-coded in dspin_tsar |
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| 298 | #define BDEV_LOCAL_SRCID 0xF // hard-coded in dspin_tsar |
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[450] | 299 | |
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[550] | 300 | /////////////////////////////////////////////////////////////////////// |
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[450] | 301 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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[550] | 302 | /////////////////////////////////////////////////////////////////////// |
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[450] | 303 | |
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[648] | 304 | #define INT_MEMC_TGT_ID 0 |
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| 305 | #define INT_XICU_TGT_ID 1 |
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[658] | 306 | #define INT_BROM_TGT_ID 2 |
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| 307 | #define INT_MDMA_TGT_ID 3 |
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| 308 | #define INT_IOBX_TGT_ID 4 |
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[450] | 309 | |
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[648] | 310 | #define INT_PROC_INI_ID 0 // from 0 to 7 |
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| 311 | #define INT_MDMA_INI_ID nb_procs |
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| 312 | #define INT_IOBX_INI_ID (nb_procs + 1) |
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[450] | 313 | |
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[550] | 314 | /////////////////////////////////////////////////////////////////////// |
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[450] | 315 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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[550] | 316 | /////////////////////////////////////////////////////////////////////// |
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[450] | 317 | |
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[648] | 318 | #define RAM_XRAM_TGT_ID 0 |
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[450] | 319 | |
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[648] | 320 | #define RAM_MEMC_INI_ID 0 |
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| 321 | #define RAM_IOBX_INI_ID 1 |
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[450] | 322 | |
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[550] | 323 | /////////////////////////////////////////////////////////////////////// |
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[450] | 324 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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[550] | 325 | /////////////////////////////////////////////////////////////////////// |
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[450] | 326 | |
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[648] | 327 | #define IOX_IOB0_TGT_ID 0 // don't change this value |
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| 328 | #define IOX_IOB1_TGT_ID 1 // don't change this value |
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| 329 | #define IOX_FBUF_TGT_ID 2 |
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| 330 | #define IOX_BDEV_TGT_ID 3 |
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| 331 | #define IOX_MNIC_TGT_ID 4 |
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| 332 | #define IOX_CDMA_TGT_ID 5 |
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[658] | 333 | #define IOX_MTTY_TGT_ID 6 |
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[450] | 334 | |
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[648] | 335 | #define IOX_IOB0_INI_ID 0 // Don't change this value |
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| 336 | #define IOX_IOB1_INI_ID 1 // Don't change this value |
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| 337 | #define IOX_BDEV_INI_ID 2 |
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| 338 | #define IOX_CDMA_INI_ID 3 |
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[450] | 339 | |
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[550] | 340 | //////////////////////////////////////////////////////////////////////// |
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[450] | 341 | int _main(int argc, char *argv[]) |
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[550] | 342 | //////////////////////////////////////////////////////////////////////// |
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[450] | 343 | { |
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| 344 | using namespace sc_core; |
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| 345 | using namespace soclib::caba; |
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| 346 | using namespace soclib::common; |
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| 347 | |
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[648] | 348 | char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code |
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| 349 | size_t ncycles = 1000000000; // simulated cycles |
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| 350 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image |
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| 351 | char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file |
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| 352 | char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file |
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| 353 | ssize_t threads_nr = 1; // simulator's threads number |
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| 354 | bool debug_ok = false; // trace activated |
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| 355 | size_t debug_period = 1; // trace period |
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| 356 | size_t debug_memc_id = 0xFFFFFFFF; // idx of traced memc |
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| 357 | size_t debug_proc_id = 0xFFFFFFFF; // idx of traced proc |
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| 358 | bool debug_iob = false; // trace iobs when true |
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| 359 | uint32_t debug_from = 0; // trace start cycle |
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| 360 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen procs |
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| 361 | size_t block_size = BDEV_SECTOR_SIZE; // disk block size |
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| 362 | size_t nb_procs = 1; |
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| 363 | size_t x_size = 2; |
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| 364 | size_t y_size = 2; |
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| 365 | size_t nb_tty_channels = 1; |
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| 366 | size_t nb_nic_channels = 1; |
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[450] | 367 | |
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[648] | 368 | assert((X_WIDTH == 4) and (Y_WIDTH == 4)); |
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| 369 | |
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[450] | 370 | ////////////// command line arguments ////////////////////// |
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| 371 | if (argc > 1) |
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| 372 | { |
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| 373 | for (int n = 1; n < argc; n = n + 2) |
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| 374 | { |
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| 375 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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| 376 | { |
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| 377 | ncycles = atoi(argv[n+1]); |
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[648] | 378 | continue; |
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[450] | 379 | } |
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[648] | 380 | if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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[450] | 381 | { |
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| 382 | strcpy(soft_name, argv[n+1]); |
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[648] | 383 | continue; |
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[450] | 384 | } |
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[648] | 385 | if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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[450] | 386 | { |
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[648] | 387 | strcpy(disk_name, argv[n+1]); |
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| 388 | continue; |
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[450] | 389 | } |
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[648] | 390 | if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc)) |
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[450] | 391 | { |
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[648] | 392 | nb_procs = atoi(argv[n+1]); |
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| 393 | assert((nb_procs > 0) && (nb_procs < 5)); |
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| 394 | continue; |
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[450] | 395 | } |
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[648] | 396 | if ((strcmp(argv[n],"-XSIZE") == 0) && (n+1<argc)) |
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[450] | 397 | { |
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[648] | 398 | x_size = atoi(argv[n+1]); |
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| 399 | assert((x_size > 0) && (x_size < X_MAX)); |
---|
| 400 | continue; |
---|
| 401 | } |
---|
| 402 | if ((strcmp(argv[n],"-YSIZE") == 0) && (n+1<argc)) |
---|
| 403 | { |
---|
| 404 | y_size = atoi(argv[n+1]); |
---|
| 405 | assert((y_size > 0) && (y_size < Y_MAX)); |
---|
| 406 | continue; |
---|
| 407 | } |
---|
| 408 | if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
---|
| 409 | { |
---|
| 410 | debug_ok = true; |
---|
| 411 | debug_from = atoi(argv[n+1]); |
---|
| 412 | continue; |
---|
| 413 | } |
---|
| 414 | if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
---|
| 415 | { |
---|
[450] | 416 | debug_memc_id = atoi(argv[n+1]); |
---|
[648] | 417 | size_t x = debug_memc_id >> Y_WIDTH; |
---|
| 418 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
---|
| 419 | assert((x < x_size) && (y < y_size)); |
---|
| 420 | continue; |
---|
[450] | 421 | } |
---|
[648] | 422 | if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) ) |
---|
[450] | 423 | { |
---|
[648] | 424 | debug_iob = (atoi(argv[n+1]) != 0) ? 1 : 0; |
---|
| 425 | continue; |
---|
[450] | 426 | } |
---|
[648] | 427 | if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
---|
[450] | 428 | { |
---|
[607] | 429 | debug_proc_id = atoi(argv[n+1]); |
---|
[648] | 430 | size_t cluster_xy = debug_proc_id / nb_procs ; |
---|
| 431 | size_t x = cluster_xy >> Y_WIDTH; |
---|
| 432 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
---|
| 433 | assert((x < x_size) && (y < y_size)); |
---|
| 434 | continue; |
---|
[450] | 435 | } |
---|
[648] | 436 | if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
---|
[450] | 437 | { |
---|
| 438 | threads_nr = atoi(argv[n+1]); |
---|
[648] | 439 | assert(threads_nr > 0); |
---|
| 440 | continue; |
---|
[450] | 441 | } |
---|
[648] | 442 | if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
---|
[450] | 443 | { |
---|
| 444 | frozen_cycles = atoi(argv[n+1]); |
---|
[648] | 445 | assert(frozen_cycles > 0); |
---|
| 446 | continue; |
---|
[450] | 447 | } |
---|
[648] | 448 | if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
---|
[450] | 449 | { |
---|
| 450 | debug_period = atoi(argv[n+1]); |
---|
[648] | 451 | assert(debug_period > 0); |
---|
| 452 | continue; |
---|
[450] | 453 | } |
---|
[648] | 454 | |
---|
| 455 | std::cout << " Arguments are (key,value) couples.\n" |
---|
| 456 | << " The order is not important.\n" |
---|
| 457 | << " Accepted arguments are :\n\n" |
---|
| 458 | << " -NCYCLES number of simulated_cycles\n" |
---|
| 459 | << " -SOFT pathname for embedded soft\n" |
---|
| 460 | << " -DISK pathname for disk image\n" |
---|
| 461 | << " -NPROCS number of processors per cluster\n" |
---|
| 462 | << " -XSIZE number of clusters on X\n" |
---|
| 463 | << " -YSIZE number of clusters on Y\n" |
---|
| 464 | << " -DEBUG debug start cycle\n" |
---|
| 465 | << " -MEMCID index of memc to trace\n" |
---|
| 466 | << " -IOB debug IOBs if non_zero_value\n\n" |
---|
| 467 | << " -PROCID index of proc to trace\n" |
---|
| 468 | << " -THREADS simulator's threads number\n" |
---|
| 469 | << " -FROZEN max number of frozen cycles\n" |
---|
| 470 | << " -PERIOD number of cycles between trace\n\n"; |
---|
| 471 | exit(0); |
---|
[450] | 472 | } |
---|
| 473 | } |
---|
| 474 | |
---|
[648] | 475 | // one DMA channel per proc |
---|
| 476 | size_t nb_dma_channels = nb_procs; |
---|
[450] | 477 | |
---|
[648] | 478 | // clusters containing IOB0 and IOB1 |
---|
| 479 | size_t cluster_iob0 = cluster(0,0); |
---|
| 480 | size_t cluster_iob1 = cluster(x_size - 1, y_size - 1); |
---|
[450] | 481 | |
---|
[648] | 482 | assert( (nb_tty_channels < 16) and |
---|
[472] | 483 | "The NB_TTY_CHANNELS parameter must be smaller than 16" ); |
---|
[450] | 484 | |
---|
[648] | 485 | assert( (nb_nic_channels == 1) and |
---|
| 486 | "The NB_NIC_CHANNELS parameter must be 1" ); |
---|
[450] | 487 | |
---|
| 488 | std::cout << std::endl; |
---|
[648] | 489 | std::cout << " - X_SIZE = " << x_size << std::endl; |
---|
| 490 | std::cout << " - Y_SIZE = " << y_size << std::endl; |
---|
| 491 | std::cout << " - NB_PROCS = " << nb_procs << std::endl; |
---|
| 492 | std::cout << " - NB_DMA_CHANNELS = " << nb_dma_channels << std::endl; |
---|
| 493 | std::cout << " - NB_TTY_CHANNELS = " << nb_tty_channels << std::endl; |
---|
| 494 | std::cout << " - NB_NIC_CHANNELS = " << nb_nic_channels << std::endl; |
---|
| 495 | std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; |
---|
| 496 | std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; |
---|
| 497 | std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; |
---|
| 498 | std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; |
---|
[450] | 499 | |
---|
| 500 | std::cout << std::endl; |
---|
| 501 | |
---|
| 502 | #if USE_OPENMP |
---|
| 503 | omp_set_dynamic(false); |
---|
| 504 | omp_set_num_threads(threads_nr); |
---|
| 505 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
| 506 | #endif |
---|
| 507 | |
---|
| 508 | // Define VciParams objects |
---|
| 509 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
| 510 | vci_plen_width, |
---|
| 511 | vci_address_width, |
---|
| 512 | vci_rerror_width, |
---|
| 513 | vci_clen_width, |
---|
| 514 | vci_rflag_width, |
---|
| 515 | vci_srcid_width, |
---|
| 516 | vci_pktid_width, |
---|
| 517 | vci_trdid_width, |
---|
| 518 | vci_wrplen_width> vci_param_int; |
---|
| 519 | |
---|
| 520 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
| 521 | vci_plen_width, |
---|
| 522 | vci_address_width, |
---|
[648] | 523 | vci_rerror_width, |
---|
[450] | 524 | vci_clen_width, |
---|
| 525 | vci_rflag_width, |
---|
| 526 | vci_srcid_width, |
---|
| 527 | vci_pktid_width, |
---|
| 528 | vci_trdid_width, |
---|
| 529 | vci_wrplen_width> vci_param_ext; |
---|
| 530 | |
---|
| 531 | ///////////////////////////////////////////////////////////////////// |
---|
| 532 | // INT network mapping table |
---|
| 533 | // - two levels address decoding for commands |
---|
| 534 | // - two levels srcid decoding for responses |
---|
| 535 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
---|
| 536 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
---|
| 537 | ///////////////////////////////////////////////////////////////////// |
---|
[648] | 538 | MappingTable maptab_int( |
---|
| 539 | vci_address_width, |
---|
| 540 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
---|
| 541 | IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
| 542 | 0x00FF000000); |
---|
[450] | 543 | |
---|
[648] | 544 | for (size_t x = 0; x < x_size; x++) |
---|
[450] | 545 | { |
---|
[648] | 546 | for (size_t y = 0; y < y_size; y++) |
---|
[450] | 547 | { |
---|
[648] | 548 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
| 549 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[550] | 550 | bool config = true; |
---|
| 551 | bool cacheable = true; |
---|
[450] | 552 | |
---|
[658] | 553 | // the five following segments are defined in all clusters |
---|
[450] | 554 | |
---|
[648] | 555 | std::ostringstream smemc_conf; |
---|
[450] | 556 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
| 557 | maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE, |
---|
[648] | 558 | IntTab(cluster(x,y),INT_MEMC_TGT_ID), |
---|
| 559 | not cacheable, config )); |
---|
[450] | 560 | |
---|
[648] | 561 | std::ostringstream smemc_xram; |
---|
[450] | 562 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
| 563 | maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE, |
---|
[648] | 564 | IntTab(cluster(x,y),INT_MEMC_TGT_ID), |
---|
| 565 | cacheable)); |
---|
[450] | 566 | |
---|
[648] | 567 | std::ostringstream sxicu; |
---|
[450] | 568 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
[648] | 569 | maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE, |
---|
| 570 | IntTab(cluster(x,y),INT_XICU_TGT_ID), |
---|
| 571 | not cacheable)); |
---|
[450] | 572 | |
---|
[658] | 573 | std::ostringstream sbrom; |
---|
| 574 | sbrom << "int_seg_brom_" << x << "_" << y; |
---|
| 575 | maptab_int.add(Segment(sbrom.str(), BROM_BASE+offset, BROM_SIZE, |
---|
| 576 | IntTab(cluster(x,y),INT_BROM_TGT_ID), |
---|
| 577 | cacheable)); |
---|
| 578 | |
---|
[648] | 579 | std::ostringstream smdma; |
---|
[450] | 580 | smdma << "int_seg_mdma_" << x << "_" << y; |
---|
[648] | 581 | maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE, |
---|
| 582 | IntTab(cluster(x,y),INT_MDMA_TGT_ID), |
---|
| 583 | not cacheable)); |
---|
[450] | 584 | |
---|
[648] | 585 | // the following segments are only defined in cluster_iob0 or in |
---|
| 586 | // cluster_iob1 |
---|
| 587 | if ((cluster(x,y) == cluster_iob0) || (cluster(x,y) == cluster_iob1)) |
---|
[450] | 588 | { |
---|
[648] | 589 | std::ostringstream siobx; |
---|
[450] | 590 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
[648] | 591 | maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE, |
---|
| 592 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 593 | not cacheable, config )); |
---|
[450] | 594 | |
---|
[648] | 595 | std::ostringstream stty; |
---|
[450] | 596 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
[648] | 597 | maptab_int.add(Segment(stty.str(), MTTY_BASE+offset, MTTY_SIZE, |
---|
| 598 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 599 | not cacheable)); |
---|
[450] | 600 | |
---|
[648] | 601 | std::ostringstream sfbf; |
---|
[450] | 602 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
[648] | 603 | maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE, |
---|
| 604 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 605 | not cacheable)); |
---|
[450] | 606 | |
---|
[648] | 607 | std::ostringstream sbdv; |
---|
[450] | 608 | sbdv << "int_seg_bdev_" << x << "_" << y; |
---|
[648] | 609 | maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE, |
---|
| 610 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 611 | not cacheable)); |
---|
[450] | 612 | |
---|
[648] | 613 | std::ostringstream snic; |
---|
[450] | 614 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
[648] | 615 | maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE, |
---|
| 616 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 617 | not cacheable)); |
---|
[450] | 618 | |
---|
[648] | 619 | std::ostringstream sdma; |
---|
[450] | 620 | sdma << "int_seg_cdma_" << x << "_" << y; |
---|
[648] | 621 | maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE, |
---|
| 622 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 623 | not cacheable)); |
---|
[450] | 624 | } |
---|
| 625 | |
---|
| 626 | // This define the mapping between the SRCIDs |
---|
| 627 | // and the port index on the local interconnect. |
---|
| 628 | |
---|
[648] | 629 | maptab_int.srcid_map(IntTab(cluster(x,y), MDMA_LOCAL_SRCID), |
---|
| 630 | IntTab(cluster(x,y), INT_MDMA_INI_ID)); |
---|
| 631 | maptab_int.srcid_map(IntTab(cluster(x,y), IOBX_LOCAL_SRCID), |
---|
| 632 | IntTab(cluster(x,y), INT_IOBX_INI_ID)); |
---|
[450] | 633 | |
---|
[648] | 634 | for ( size_t p = 0 ; p < nb_procs ; p++ ) |
---|
| 635 | { |
---|
| 636 | maptab_int.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p), |
---|
| 637 | IntTab(cluster(x,y), INT_PROC_INI_ID + p)); |
---|
| 638 | } |
---|
[450] | 639 | } |
---|
| 640 | } |
---|
| 641 | std::cout << "INT network " << maptab_int << std::endl; |
---|
| 642 | |
---|
| 643 | ///////////////////////////////////////////////////////////////////////// |
---|
[648] | 644 | // RAM network mapping table |
---|
[450] | 645 | // - two levels address decoding for commands |
---|
| 646 | // - two levels srcid decoding for responses |
---|
[648] | 647 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
[450] | 648 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
| 649 | // - 1 local target (XRAM) per cluster |
---|
| 650 | //////////////////////////////////////////////////////////////////////// |
---|
[648] | 651 | MappingTable maptab_ram( |
---|
| 652 | vci_address_width, |
---|
| 653 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
---|
| 654 | IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
| 655 | 0x00FF000000); |
---|
[450] | 656 | |
---|
[648] | 657 | for (size_t x = 0; x < x_size; x++) |
---|
[450] | 658 | { |
---|
[648] | 659 | for (size_t y = 0; y < y_size ; y++) |
---|
| 660 | { |
---|
| 661 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
| 662 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[450] | 663 | |
---|
| 664 | std::ostringstream sxram; |
---|
| 665 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
[648] | 666 | maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, |
---|
| 667 | XRAM_SIZE, IntTab(cluster(x,y), 0), false)); |
---|
[450] | 668 | } |
---|
| 669 | } |
---|
| 670 | |
---|
[550] | 671 | // This define the mapping between the initiators SRCID |
---|
| 672 | // and the port index on the RAM local interconnect. |
---|
[648] | 673 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
[450] | 674 | |
---|
[648] | 675 | maptab_ram.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID), |
---|
| 676 | IntTab(cluster_iob0, RAM_IOBX_INI_ID)); |
---|
| 677 | maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID), |
---|
| 678 | IntTab(cluster_iob1, RAM_IOBX_INI_ID)); |
---|
| 679 | maptab_ram.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID), |
---|
| 680 | IntTab(cluster_iob0, RAM_IOBX_INI_ID)); |
---|
| 681 | maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID), |
---|
| 682 | IntTab(cluster_iob1, RAM_IOBX_INI_ID)); |
---|
| 683 | maptab_ram.srcid_map(IntTab(cluster_iob1, MEMC_LOCAL_SRCID), |
---|
| 684 | IntTab(cluster_iob1, RAM_MEMC_INI_ID)); |
---|
[450] | 685 | |
---|
| 686 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
| 687 | |
---|
| 688 | /////////////////////////////////////////////////////////////////////// |
---|
[648] | 689 | // IOX network mapping table |
---|
[450] | 690 | // - two levels address decoding for commands |
---|
| 691 | // - two levels srcid decoding for responses |
---|
| 692 | // - 4 initiators (IOB0, IOB1, BDEV, CDMA) |
---|
| 693 | // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC) |
---|
| 694 | /////////////////////////////////////////////////////////////////////// |
---|
[648] | 695 | MappingTable maptab_iox( |
---|
| 696 | vci_address_width, |
---|
| 697 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
---|
| 698 | IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
| 699 | 0x00FF000000); |
---|
[450] | 700 | |
---|
| 701 | // compute base addresses for cluster_iob0 and cluster_iob1 |
---|
[648] | 702 | uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
| 703 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
| 704 | uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
| 705 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[450] | 706 | |
---|
| 707 | // Each peripheral can be accessed through two segments, |
---|
| 708 | // depending on the used IOB (IOB0 or IOB1). |
---|
[648] | 709 | maptab_iox.add(Segment("iox_seg_mtty_0", MTTY_BASE + iob0_base, MTTY_SIZE, |
---|
| 710 | IntTab(cluster_iob0, IOX_MTTY_TGT_ID), false)); |
---|
| 711 | maptab_iox.add(Segment("iox_seg_mtty_1", MTTY_BASE + iob1_base, MTTY_SIZE, |
---|
| 712 | IntTab(cluster_iob1, IOX_MTTY_TGT_ID), false)); |
---|
| 713 | maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE, |
---|
| 714 | IntTab(cluster_iob0, IOX_FBUF_TGT_ID), false)); |
---|
| 715 | maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE, |
---|
| 716 | IntTab(cluster_iob1, IOX_FBUF_TGT_ID), false)); |
---|
| 717 | maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE, |
---|
| 718 | IntTab(cluster_iob0, IOX_BDEV_TGT_ID), false)); |
---|
| 719 | maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE, |
---|
| 720 | IntTab(cluster_iob1, IOX_BDEV_TGT_ID), false)); |
---|
| 721 | maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE, |
---|
| 722 | IntTab(cluster_iob0, IOX_MNIC_TGT_ID), false)); |
---|
| 723 | maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE, |
---|
| 724 | IntTab(cluster_iob1, IOX_MNIC_TGT_ID), false)); |
---|
| 725 | maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE, |
---|
| 726 | IntTab(cluster_iob0, IOX_CDMA_TGT_ID), false)); |
---|
| 727 | maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE, |
---|
| 728 | IntTab(cluster_iob1, IOX_CDMA_TGT_ID), false)); |
---|
[450] | 729 | |
---|
| 730 | // Each physical RAM can be accessed through IOB0, or through IOB1. |
---|
| 731 | // if IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
| 732 | // and the choice depends on on address bit A[39]. |
---|
[648] | 733 | // if IOMMU is activated the addresses use only 32 bits (virtual |
---|
| 734 | // addresses), and the choice depends on address bit A[31]. |
---|
| 735 | for (size_t x = 0; x < x_size; x++) |
---|
[450] | 736 | { |
---|
[648] | 737 | for (size_t y = 0; y < y_size ; y++) |
---|
| 738 | { |
---|
| 739 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
| 740 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[450] | 741 | |
---|
[648] | 742 | // send command to XRAM through IOB0 |
---|
| 743 | if ( x < (x_size/2) ) |
---|
[450] | 744 | { |
---|
| 745 | std::ostringstream siob0; |
---|
| 746 | siob0 << "iox_seg_xram_" << x << "_" << y; |
---|
[648] | 747 | maptab_iox.add(Segment(siob0.str(), offset, 0x80000000, |
---|
| 748 | IntTab(cluster_iob0,IOX_IOB0_TGT_ID), |
---|
| 749 | false)); |
---|
[450] | 750 | } |
---|
[648] | 751 | // send command to XRAM through IOB1 |
---|
| 752 | else |
---|
[450] | 753 | { |
---|
| 754 | std::ostringstream siob1; |
---|
| 755 | siob1 << "iox_seg_xram_" << x << "_" << y; |
---|
[648] | 756 | maptab_iox.add(Segment(siob1.str(), offset, 0x80000000, |
---|
| 757 | IntTab(cluster_iob1,IOX_IOB1_TGT_ID), |
---|
| 758 | false)); |
---|
[450] | 759 | } |
---|
| 760 | } |
---|
| 761 | } |
---|
| 762 | // useful when IOMMU activated |
---|
[648] | 763 | maptab_iox.add(Segment("iox_seg_xram", 0xc0000000, 0x40000000, |
---|
| 764 | IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); |
---|
[450] | 765 | |
---|
| 766 | // This define the mapping between the initiators (identified by the SRCID) |
---|
| 767 | // and the port index on the IOX local interconnect. |
---|
[648] | 768 | // External initiator have two alias SRCID (iob0 / iob1 access) |
---|
[450] | 769 | |
---|
[648] | 770 | maptab_iox.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID), |
---|
| 771 | IntTab(cluster_iob0, IOX_CDMA_INI_ID)); |
---|
| 772 | maptab_iox.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID), |
---|
| 773 | IntTab(cluster_iob1, IOX_CDMA_INI_ID)); |
---|
| 774 | maptab_iox.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID), |
---|
| 775 | IntTab(cluster_iob0, IOX_BDEV_INI_ID)); |
---|
| 776 | maptab_iox.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID), |
---|
| 777 | IntTab(cluster_iob0, IOX_BDEV_INI_ID)); |
---|
[450] | 778 | |
---|
[648] | 779 | for (size_t x = 0; x < x_size; x++) |
---|
[450] | 780 | { |
---|
[648] | 781 | for (size_t y = 0; y < y_size ; y++) |
---|
| 782 | { |
---|
| 783 | size_t iob = (x < (x_size / 2)) ? IOX_IOB0_INI_ID |
---|
| 784 | : IOX_IOB1_INI_ID; |
---|
[550] | 785 | |
---|
[648] | 786 | for (size_t p = 0 ; p < nb_procs ; p++) |
---|
| 787 | { |
---|
| 788 | maptab_iox.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p), |
---|
| 789 | IntTab(cluster(x,y), iob)); |
---|
| 790 | } |
---|
| 791 | maptab_iox.srcid_map(IntTab( cluster(x,y), MDMA_LOCAL_SRCID), |
---|
| 792 | IntTab( cluster(x,y), IOX_IOB0_INI_ID)); |
---|
[450] | 793 | } |
---|
| 794 | } |
---|
| 795 | |
---|
| 796 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
| 797 | |
---|
| 798 | //////////////////// |
---|
| 799 | // Signals |
---|
[648] | 800 | //////////////////// |
---|
[450] | 801 | |
---|
[648] | 802 | sc_clock signal_clk("clk"); |
---|
| 803 | sc_signal<bool> signal_resetn("resetn"); |
---|
[450] | 804 | |
---|
[648] | 805 | sc_signal<bool> signal_irq_false; |
---|
| 806 | sc_signal<bool> signal_irq_bdev; |
---|
| 807 | sc_signal<bool> signal_irq_mnic_rx[1]; |
---|
| 808 | sc_signal<bool> signal_irq_mnic_tx[1]; |
---|
| 809 | sc_signal<bool> signal_irq_mtty[16]; |
---|
| 810 | sc_signal<bool> signal_irq_cdma[1*2]; |
---|
[450] | 811 | |
---|
[550] | 812 | // DSPIN signals for loopback in cluster_iob0 & cluster_iob1 |
---|
[648] | 813 | DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback; |
---|
| 814 | DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback; |
---|
| 815 | DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback; |
---|
| 816 | DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback; |
---|
[550] | 817 | |
---|
[450] | 818 | // VCI signals for IOX network |
---|
[648] | 819 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
| 820 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
| 821 | VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); |
---|
| 822 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
[450] | 823 | |
---|
[648] | 824 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
| 825 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
| 826 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 827 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 828 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 829 | VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); |
---|
| 830 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
[450] | 831 | |
---|
[648] | 832 | // Horizontal inter-clusters INT network DSPIN |
---|
[450] | 833 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = |
---|
[648] | 834 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 835 | "signal_dspin_int_cmd_h_inc", x_size-1, y_size, 3); |
---|
[450] | 836 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = |
---|
[648] | 837 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 838 | "signal_dspin_int_cmd_h_dec", x_size-1, y_size, 3); |
---|
[450] | 839 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = |
---|
[648] | 840 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 841 | "signal_dspin_int_rsp_h_inc", x_size-1, y_size, 2); |
---|
[450] | 842 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = |
---|
[648] | 843 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 844 | "signal_dspin_int_rsp_h_dec", x_size-1, y_size, 2); |
---|
[450] | 845 | |
---|
| 846 | // Vertical inter-clusters INT network DSPIN |
---|
| 847 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = |
---|
[648] | 848 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 849 | "signal_dspin_int_cmd_v_inc", x_size, y_size-1, 3); |
---|
[450] | 850 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = |
---|
[648] | 851 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 852 | "signal_dspin_int_cmd_v_dec", x_size, y_size-1, 3); |
---|
[450] | 853 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = |
---|
[648] | 854 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 855 | "signal_dspin_int_rsp_v_inc", x_size, y_size-1, 2); |
---|
[450] | 856 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = |
---|
[648] | 857 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 858 | "signal_dspin_int_rsp_v_dec", x_size, y_size-1, 2); |
---|
[450] | 859 | |
---|
[648] | 860 | // Mesh boundaries INT network DSPIN |
---|
[450] | 861 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = |
---|
[648] | 862 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 863 | "signal_dspin_false_int_cmd_in", x_size, y_size, 4, 3); |
---|
[450] | 864 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = |
---|
[648] | 865 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 866 | "signal_dspin_false_int_cmd_out", x_size, y_size, 4, 3); |
---|
[450] | 867 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = |
---|
[648] | 868 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 869 | "signal_dspin_false_int_rsp_in", x_size, y_size, 4, 2); |
---|
[450] | 870 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = |
---|
[648] | 871 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 872 | "signal_dspin_false_int_rsp_out", x_size, y_size, 4, 2); |
---|
[450] | 873 | |
---|
| 874 | |
---|
[648] | 875 | // Horizontal inter-clusters RAM network DSPIN |
---|
[450] | 876 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
[648] | 877 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 878 | "signal_dspin_ram_cmd_h_inc", x_size-1, y_size); |
---|
[450] | 879 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
[648] | 880 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 881 | "signal_dspin_ram_cmd_h_dec", x_size-1, y_size); |
---|
[450] | 882 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
[648] | 883 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 884 | "signal_dspin_ram_rsp_h_inc", x_size-1, y_size); |
---|
[450] | 885 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
[648] | 886 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 887 | "signal_dspin_ram_rsp_h_dec", x_size-1, y_size); |
---|
[450] | 888 | |
---|
| 889 | // Vertical inter-clusters RAM network DSPIN |
---|
| 890 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
[648] | 891 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 892 | "signal_dspin_ram_cmd_v_inc", x_size, y_size-1); |
---|
[450] | 893 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
[648] | 894 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 895 | "signal_dspin_ram_cmd_v_dec", x_size, y_size-1); |
---|
[450] | 896 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
[648] | 897 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 898 | "signal_dspin_ram_rsp_v_inc", x_size, y_size-1); |
---|
[450] | 899 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
[648] | 900 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 901 | "signal_dspin_ram_rsp_v_dec", x_size, y_size-1); |
---|
[450] | 902 | |
---|
[648] | 903 | // Mesh boundaries RAM network DSPIN |
---|
[450] | 904 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
[648] | 905 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 906 | "signal_dspin_false_ram_cmd_in", x_size, y_size, 4); |
---|
[450] | 907 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
[648] | 908 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 909 | "signal_dspin_false_ram_cmd_out", x_size, y_size, 4); |
---|
[450] | 910 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
[648] | 911 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 912 | "signal_dspin_false_ram_rsp_in", x_size, y_size, 4); |
---|
[450] | 913 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
[648] | 914 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 915 | "signal_dspin_false_ram_rsp_out", x_size, y_size, 4); |
---|
[450] | 916 | |
---|
| 917 | //////////////////////////// |
---|
[648] | 918 | // Loader |
---|
[450] | 919 | //////////////////////////// |
---|
| 920 | |
---|
| 921 | #if USE_ALMOS |
---|
| 922 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
| 923 | almos_archinfo_pathname, |
---|
| 924 | almos_kernel_pathname); |
---|
| 925 | #else |
---|
| 926 | soclib::common::Loader loader(soft_name); |
---|
| 927 | #endif |
---|
| 928 | |
---|
| 929 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 930 | proc_iss::set_loader(loader); |
---|
| 931 | |
---|
| 932 | //////////////////////////////////////// |
---|
| 933 | // Instanciated Hardware Components |
---|
| 934 | //////////////////////////////////////// |
---|
| 935 | |
---|
[648] | 936 | std::cout << std::endl << "External Bus and Peripherals" << std::endl |
---|
| 937 | << std::endl; |
---|
[450] | 938 | |
---|
| 939 | // IOX network |
---|
| 940 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
[648] | 941 | iox_network = new VciIoxNetwork<vci_param_ext>("iox_network", |
---|
| 942 | maptab_iox, |
---|
[658] | 943 | 7, // number of targets |
---|
[648] | 944 | 4 ); // number of initiators |
---|
[658] | 945 | |
---|
[450] | 946 | // Network Controller |
---|
[550] | 947 | VciMultiNic<vci_param_ext>* mnic; |
---|
[648] | 948 | mnic = new VciMultiNic<vci_param_ext>("mnic", |
---|
| 949 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
| 950 | maptab_iox, |
---|
| 951 | nb_nic_channels, |
---|
| 952 | 0, // mac_4 address |
---|
| 953 | 0, // mac_2 address |
---|
| 954 | nic_rx_name, |
---|
| 955 | nic_tx_name); |
---|
[450] | 956 | |
---|
| 957 | // Frame Buffer |
---|
[550] | 958 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
[648] | 959 | fbuf = new VciFrameBuffer<vci_param_ext>("fbuf", |
---|
| 960 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
| 961 | maptab_iox, |
---|
| 962 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
[450] | 963 | |
---|
| 964 | // Block Device |
---|
[550] | 965 | // for AHCI |
---|
| 966 | // std::vector<std::string> filenames; |
---|
[648] | 967 | // filenames.push_back(disk_name); // one single disk |
---|
[550] | 968 | VciBlockDeviceTsar<vci_param_ext>* bdev; |
---|
[648] | 969 | bdev = new VciBlockDeviceTsar<vci_param_ext>("bdev", |
---|
| 970 | maptab_iox, |
---|
| 971 | IntTab(0, BDEV_LOCAL_SRCID), |
---|
| 972 | IntTab(0, IOX_BDEV_TGT_ID), |
---|
| 973 | disk_name, |
---|
| 974 | block_size, |
---|
| 975 | 64, // burst size (bytes) |
---|
| 976 | 0 ); // disk latency |
---|
[450] | 977 | |
---|
| 978 | // Chained Buffer DMA controller |
---|
[550] | 979 | VciChbufDma<vci_param_ext>* cdma; |
---|
[648] | 980 | cdma = new VciChbufDma<vci_param_ext>("cdma", |
---|
| 981 | maptab_iox, |
---|
| 982 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
| 983 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
| 984 | 64, // burst size (bytes) |
---|
| 985 | 2 * nb_nic_channels); |
---|
[450] | 986 | // Multi-TTY controller |
---|
| 987 | std::vector<std::string> vect_names; |
---|
[648] | 988 | for( size_t tid = 0 ; tid < nb_tty_channels ; tid++ ) |
---|
[450] | 989 | { |
---|
| 990 | std::ostringstream term_name; |
---|
| 991 | term_name << "term" << tid; |
---|
| 992 | vect_names.push_back(term_name.str().c_str()); |
---|
| 993 | } |
---|
[550] | 994 | VciMultiTty<vci_param_ext>* mtty; |
---|
[648] | 995 | mtty = new VciMultiTty<vci_param_ext>("mtty_iox", |
---|
| 996 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
| 997 | maptab_iox, |
---|
| 998 | vect_names); |
---|
| 999 | // Clusters |
---|
| 1000 | typedef TsarIobCluster<vci_param_int, vci_param_ext, dspin_int_cmd_width, |
---|
| 1001 | dspin_int_rsp_width, dspin_ram_cmd_width, dspin_ram_rsp_width> |
---|
| 1002 | TsarIobClusterType; |
---|
| 1003 | |
---|
| 1004 | TsarIobClusterType* clusters[x_size][y_size]; |
---|
[450] | 1005 | |
---|
| 1006 | #if USE_OPENMP |
---|
| 1007 | #pragma omp parallel |
---|
| 1008 | { |
---|
| 1009 | #pragma omp for |
---|
| 1010 | #endif |
---|
[648] | 1011 | |
---|
| 1012 | for(size_t i = 0; i < (x_size * y_size); i++) |
---|
[450] | 1013 | { |
---|
[648] | 1014 | size_t x = i / y_size; |
---|
| 1015 | size_t y = i % y_size; |
---|
[450] | 1016 | |
---|
| 1017 | #if USE_OPENMP |
---|
| 1018 | #pragma omp critical |
---|
| 1019 | { |
---|
| 1020 | #endif |
---|
| 1021 | std::cout << std::endl; |
---|
| 1022 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
| 1023 | std::cout << std::endl; |
---|
| 1024 | |
---|
| 1025 | std::ostringstream sc; |
---|
| 1026 | sc << "cluster_" << x << "_" << y; |
---|
| 1027 | |
---|
[648] | 1028 | bool memc_debug = |
---|
| 1029 | debug_ok && (cluster(x,y) == debug_memc_id); |
---|
| 1030 | bool proc_debug = |
---|
| 1031 | debug_ok && (cluster(x,y) == (debug_proc_id / nb_procs)); |
---|
[450] | 1032 | |
---|
[648] | 1033 | TsarIobClusterType::ClusterParams params = { |
---|
| 1034 | .insname = sc.str().c_str(), |
---|
| 1035 | .nb_procs = nb_procs, |
---|
| 1036 | .nb_dmas = nb_dma_channels, |
---|
| 1037 | .x_id = x, |
---|
| 1038 | .y_id = y, |
---|
| 1039 | .x_size = x_size, |
---|
| 1040 | .y_size = y_size, |
---|
| 1041 | .mt_int = maptab_int, |
---|
| 1042 | .mt_ext = maptab_ram, |
---|
| 1043 | .mt_iox = maptab_iox, |
---|
| 1044 | .x_width = X_WIDTH, |
---|
| 1045 | .y_width = Y_WIDTH, |
---|
| 1046 | .l_width = vci_srcid_width - X_WIDTH - Y_WIDTH, |
---|
| 1047 | .int_memc_tgtid = INT_MEMC_TGT_ID, |
---|
| 1048 | .int_xicu_tgtid = INT_XICU_TGT_ID, |
---|
| 1049 | .int_mdma_tgtid = INT_MDMA_TGT_ID, |
---|
| 1050 | .int_iobx_tgtid = INT_IOBX_TGT_ID, |
---|
[658] | 1051 | .int_brom_tgtid = INT_BROM_TGT_ID, |
---|
[648] | 1052 | .int_proc_srcid = INT_PROC_INI_ID, |
---|
| 1053 | .int_mdma_srcid = INT_MDMA_INI_ID, |
---|
| 1054 | .int_iobx_srcid = INT_IOBX_INI_ID, |
---|
| 1055 | .ext_xram_tgtid = RAM_XRAM_TGT_ID, |
---|
| 1056 | .ext_memc_srcid = RAM_MEMC_INI_ID, |
---|
| 1057 | .ext_iobx_srcid = RAM_IOBX_INI_ID, |
---|
| 1058 | .memc_ways = MEMC_WAYS, |
---|
| 1059 | .memc_sets = MEMC_SETS, |
---|
| 1060 | .l1_i_ways = L1_IWAYS, |
---|
| 1061 | .l1_i_sets = L1_ISETS, |
---|
| 1062 | .l1_d_ways = L1_DWAYS, |
---|
| 1063 | .l1_d_sets = L1_DSETS, |
---|
| 1064 | .xram_latency = XRAM_LATENCY, |
---|
| 1065 | .loader = loader, |
---|
| 1066 | .frozen_cycles = frozen_cycles, |
---|
| 1067 | .debug_start_cycle = debug_from, |
---|
| 1068 | .memc_debug_ok = memc_debug, |
---|
| 1069 | .proc_debug_ok = proc_debug, |
---|
| 1070 | .iob_debug_ok = debug_ok and debug_iob |
---|
| 1071 | }; |
---|
[450] | 1072 | |
---|
[648] | 1073 | clusters[x][y] = new TsarIobClusterType(params); |
---|
[450] | 1074 | |
---|
| 1075 | #if USE_OPENMP |
---|
| 1076 | } // end critical |
---|
| 1077 | #endif |
---|
| 1078 | } // end for |
---|
| 1079 | #if USE_OPENMP |
---|
| 1080 | } |
---|
| 1081 | #endif |
---|
| 1082 | |
---|
| 1083 | std::cout << std::endl; |
---|
| 1084 | |
---|
[648] | 1085 | /////////////////////////////////////////////////////////////////////////// |
---|
| 1086 | // Net-list |
---|
| 1087 | /////////////////////////////////////////////////////////////////////////// |
---|
[450] | 1088 | |
---|
| 1089 | // IOX network connexion |
---|
[648] | 1090 | iox_network->p_clk (signal_clk); |
---|
| 1091 | iox_network->p_resetn (signal_resetn); |
---|
| 1092 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
| 1093 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
| 1094 | iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); |
---|
| 1095 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
| 1096 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
| 1097 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
| 1098 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
| 1099 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
| 1100 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
| 1101 | iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); |
---|
| 1102 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
[450] | 1103 | |
---|
| 1104 | // BDEV connexion |
---|
[648] | 1105 | bdev->p_clk (signal_clk); |
---|
| 1106 | bdev->p_resetn (signal_resetn); |
---|
| 1107 | bdev->p_irq (signal_irq_bdev); |
---|
[584] | 1108 | |
---|
[550] | 1109 | // For AHCI |
---|
[648] | 1110 | // bdev->p_channel_irq[0] (signal_irq_bdev); |
---|
[584] | 1111 | |
---|
[648] | 1112 | bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
| 1113 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
[450] | 1114 | |
---|
| 1115 | std::cout << " - BDEV connected" << std::endl; |
---|
| 1116 | |
---|
| 1117 | // FBUF connexion |
---|
[648] | 1118 | fbuf->p_clk (signal_clk); |
---|
| 1119 | fbuf->p_resetn (signal_resetn); |
---|
| 1120 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
[450] | 1121 | |
---|
| 1122 | std::cout << " - FBUF connected" << std::endl; |
---|
| 1123 | |
---|
| 1124 | // MNIC connexion |
---|
[648] | 1125 | mnic->p_clk (signal_clk); |
---|
| 1126 | mnic->p_resetn (signal_resetn); |
---|
| 1127 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
| 1128 | for ( size_t i=0 ; i<nb_nic_channels ; i++ ) |
---|
[450] | 1129 | { |
---|
[648] | 1130 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 1131 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
[450] | 1132 | } |
---|
| 1133 | |
---|
| 1134 | std::cout << " - MNIC connected" << std::endl; |
---|
| 1135 | |
---|
| 1136 | // MTTY connexion |
---|
[648] | 1137 | mtty->p_clk (signal_clk); |
---|
| 1138 | mtty->p_resetn (signal_resetn); |
---|
| 1139 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
| 1140 | for ( size_t i=0 ; i<nb_tty_channels ; i++ ) |
---|
[450] | 1141 | { |
---|
[648] | 1142 | mtty->p_irq[i] (signal_irq_mtty[i]); |
---|
[450] | 1143 | } |
---|
| 1144 | |
---|
| 1145 | std::cout << " - MTTY connected" << std::endl; |
---|
| 1146 | |
---|
| 1147 | // CDMA connexion |
---|
[648] | 1148 | cdma->p_clk (signal_clk); |
---|
| 1149 | cdma->p_resetn (signal_resetn); |
---|
| 1150 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
| 1151 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
| 1152 | for ( size_t i=0 ; i<(nb_nic_channels*2) ; i++) |
---|
[450] | 1153 | { |
---|
[648] | 1154 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
[450] | 1155 | } |
---|
| 1156 | |
---|
| 1157 | std::cout << " - CDMA connected" << std::endl; |
---|
| 1158 | |
---|
[584] | 1159 | // IRQ connexions from external peripherals (cluster_iob0 only) |
---|
[498] | 1160 | // IRQ_MNIC_RX -> IRQ[08] to IRQ[09] |
---|
| 1161 | // IRQ_MNIC_TX -> IRQ[10] to IRQ[11] |
---|
| 1162 | // IRQ_CDMA -> IRQ[12] to IRQ[15] |
---|
| 1163 | // IRQ_MTTY -> IRQ[16] to IRQ[30] |
---|
| 1164 | // IRQ_BDEV -> IRQ[31] |
---|
| 1165 | |
---|
[648] | 1166 | size_t mx = 16 + nb_tty_channels; |
---|
[450] | 1167 | for ( size_t n=0 ; n<32 ; n++ ) |
---|
| 1168 | { |
---|
[648] | 1169 | if ( n < 8 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1170 | else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1171 | else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1172 | else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1173 | else if ( n < mx ) (*clusters[0][0]->p_irq[n]) (signal_irq_mtty[n-16]); |
---|
| 1174 | else if ( n < 31 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1175 | else (*clusters[0][0]->p_irq[n]) (signal_irq_bdev); |
---|
[450] | 1176 | } |
---|
| 1177 | |
---|
| 1178 | // IOB0 cluster connexion to IOX network |
---|
[648] | 1179 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
| 1180 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
[450] | 1181 | |
---|
| 1182 | // IOB1 cluster connexion to IOX network |
---|
[648] | 1183 | (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
| 1184 | (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
[450] | 1185 | |
---|
| 1186 | // All clusters Clock & RESET connexions |
---|
[648] | 1187 | for ( size_t x = 0; x < (x_size); x++ ) |
---|
[450] | 1188 | { |
---|
[648] | 1189 | for (size_t y = 0; y < y_size; y++) |
---|
[450] | 1190 | { |
---|
[648] | 1191 | clusters[x][y]->p_clk (signal_clk); |
---|
| 1192 | clusters[x][y]->p_resetn (signal_resetn); |
---|
[450] | 1193 | } |
---|
| 1194 | } |
---|
| 1195 | |
---|
[648] | 1196 | const int& NORTH = VirtualDspinRouter<dspin_int_cmd_width>::NORTH; |
---|
| 1197 | const int& SOUTH = VirtualDspinRouter<dspin_int_cmd_width>::SOUTH; |
---|
| 1198 | const int& EAST = VirtualDspinRouter<dspin_int_cmd_width>::EAST; |
---|
| 1199 | const int& WEST = VirtualDspinRouter<dspin_int_cmd_width>::WEST; |
---|
| 1200 | |
---|
[450] | 1201 | // Inter Clusters horizontal connections |
---|
[648] | 1202 | if (x_size > 1) |
---|
[450] | 1203 | { |
---|
[648] | 1204 | for (size_t x = 0; x < (x_size-1); x++) |
---|
[450] | 1205 | { |
---|
[648] | 1206 | for (size_t y = 0; y < y_size; y++) |
---|
[450] | 1207 | { |
---|
[468] | 1208 | for (size_t k = 0; k < 3; k++) |
---|
| 1209 | { |
---|
[648] | 1210 | clusters[x][y]->p_dspin_int_cmd_out[EAST][k]( |
---|
| 1211 | signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1212 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k]( |
---|
| 1213 | signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1214 | clusters[x][y]->p_dspin_int_cmd_in[EAST][k]( |
---|
| 1215 | signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1216 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k]( |
---|
| 1217 | signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
[468] | 1218 | } |
---|
| 1219 | |
---|
[450] | 1220 | for (size_t k = 0; k < 2; k++) |
---|
| 1221 | { |
---|
[648] | 1222 | clusters[x][y]->p_dspin_int_rsp_out[EAST][k]( |
---|
| 1223 | signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1224 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k]( |
---|
| 1225 | signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1226 | clusters[x][y]->p_dspin_int_rsp_in[EAST][k]( |
---|
| 1227 | signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1228 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k]( |
---|
| 1229 | signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
[450] | 1230 | } |
---|
| 1231 | |
---|
[648] | 1232 | clusters[x][y]->p_dspin_ram_cmd_out[EAST]( |
---|
| 1233 | signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1234 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST]( |
---|
| 1235 | signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1236 | clusters[x][y]->p_dspin_ram_cmd_in[EAST]( |
---|
| 1237 | signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1238 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST]( |
---|
| 1239 | signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1240 | clusters[x][y]->p_dspin_ram_rsp_out[EAST]( |
---|
| 1241 | signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1242 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST]( |
---|
| 1243 | signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1244 | clusters[x][y]->p_dspin_ram_rsp_in[EAST]( |
---|
| 1245 | signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1246 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST]( |
---|
| 1247 | signal_dspin_ram_rsp_h_dec[x][y]); |
---|
[450] | 1248 | } |
---|
| 1249 | } |
---|
| 1250 | } |
---|
| 1251 | |
---|
[648] | 1252 | std::cout << std::endl << "Horizontal connections established" |
---|
| 1253 | << std::endl; |
---|
[450] | 1254 | |
---|
| 1255 | // Inter Clusters vertical connections |
---|
[648] | 1256 | if (y_size > 1) |
---|
[450] | 1257 | { |
---|
[648] | 1258 | for (size_t y = 0; y < (y_size-1); y++) |
---|
[450] | 1259 | { |
---|
[648] | 1260 | for (size_t x = 0; x < x_size; x++) |
---|
[450] | 1261 | { |
---|
[468] | 1262 | for (size_t k = 0; k < 3; k++) |
---|
| 1263 | { |
---|
[648] | 1264 | clusters[x][y]->p_dspin_int_cmd_out[NORTH][k]( |
---|
| 1265 | signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1266 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k]( |
---|
| 1267 | signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1268 | clusters[x][y]->p_dspin_int_cmd_in[NORTH][k]( |
---|
| 1269 | signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1270 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k]( |
---|
| 1271 | signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
[468] | 1272 | } |
---|
| 1273 | |
---|
[450] | 1274 | for (size_t k = 0; k < 2; k++) |
---|
| 1275 | { |
---|
[648] | 1276 | clusters[x][y]->p_dspin_int_rsp_out[NORTH][k]( |
---|
| 1277 | signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1278 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k]( |
---|
| 1279 | signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1280 | clusters[x][y]->p_dspin_int_rsp_in[NORTH][k]( |
---|
| 1281 | signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1282 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k]( |
---|
| 1283 | signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
[450] | 1284 | } |
---|
| 1285 | |
---|
[648] | 1286 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH]( |
---|
| 1287 | signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1288 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH]( |
---|
| 1289 | signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1290 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH]( |
---|
| 1291 | signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1292 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH]( |
---|
| 1293 | signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1294 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH]( |
---|
| 1295 | signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1296 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH]( |
---|
| 1297 | signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1298 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH]( |
---|
| 1299 | signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1300 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH]( |
---|
| 1301 | signal_dspin_ram_rsp_v_dec[x][y]); |
---|
[450] | 1302 | } |
---|
| 1303 | } |
---|
| 1304 | } |
---|
| 1305 | |
---|
| 1306 | std::cout << "Vertical connections established" << std::endl; |
---|
| 1307 | |
---|
| 1308 | // East & West boundary cluster connections |
---|
[648] | 1309 | for (size_t y = 0; y < y_size; y++) |
---|
[450] | 1310 | { |
---|
[468] | 1311 | for (size_t k = 0; k < 3; k++) |
---|
| 1312 | { |
---|
[648] | 1313 | clusters[0][y]->p_dspin_int_cmd_in[WEST][k]( |
---|
| 1314 | signal_dspin_false_int_cmd_in[0][y][WEST][k]); |
---|
| 1315 | clusters[0][y]->p_dspin_int_cmd_out[WEST][k]( |
---|
| 1316 | signal_dspin_false_int_cmd_out[0][y][WEST][k]); |
---|
| 1317 | clusters[x_size-1][y]->p_dspin_int_cmd_in[EAST][k]( |
---|
| 1318 | signal_dspin_false_int_cmd_in[x_size-1][y][EAST][k]); |
---|
| 1319 | clusters[x_size-1][y]->p_dspin_int_cmd_out[EAST][k]( |
---|
| 1320 | signal_dspin_false_int_cmd_out[x_size-1][y][EAST][k]); |
---|
[468] | 1321 | } |
---|
| 1322 | |
---|
[450] | 1323 | for (size_t k = 0; k < 2; k++) |
---|
| 1324 | { |
---|
[648] | 1325 | clusters[0][y]->p_dspin_int_rsp_in[WEST][k]( |
---|
| 1326 | signal_dspin_false_int_rsp_in[0][y][WEST][k]); |
---|
| 1327 | clusters[0][y]->p_dspin_int_rsp_out[WEST][k]( |
---|
| 1328 | signal_dspin_false_int_rsp_out[0][y][WEST][k]); |
---|
| 1329 | clusters[x_size-1][y]->p_dspin_int_rsp_in[EAST][k]( |
---|
| 1330 | signal_dspin_false_int_rsp_in[x_size-1][y][EAST][k]); |
---|
| 1331 | clusters[x_size-1][y]->p_dspin_int_rsp_out[EAST][k]( |
---|
| 1332 | signal_dspin_false_int_rsp_out[x_size-1][y][EAST][k]); |
---|
[450] | 1333 | } |
---|
| 1334 | |
---|
[648] | 1335 | // handling IOB to RAM network connection in cluster_iob0 |
---|
| 1336 | if( y == 0 ) |
---|
[550] | 1337 | { |
---|
[648] | 1338 | (*clusters[0][0]->p_dspin_iob_cmd_out)( |
---|
| 1339 | signal_dspin_cmd_iob0_loopback); |
---|
| 1340 | clusters[0][0]->p_dspin_ram_cmd_in[WEST]( |
---|
| 1341 | signal_dspin_cmd_iob0_loopback); |
---|
| 1342 | clusters[0][0]->p_dspin_ram_cmd_out[WEST]( |
---|
| 1343 | signal_dspin_false_ram_cmd_out[0][0][WEST]); |
---|
| 1344 | clusters[0][0]->p_dspin_ram_rsp_in[WEST]( |
---|
| 1345 | signal_dspin_false_ram_rsp_in[0][0][WEST]); |
---|
| 1346 | clusters[0][0]->p_dspin_ram_rsp_out[WEST]( |
---|
| 1347 | signal_dspin_rsp_iob0_loopback); |
---|
| 1348 | (*clusters[0][0]->p_dspin_iob_rsp_in)( |
---|
| 1349 | signal_dspin_rsp_iob0_loopback); |
---|
[550] | 1350 | } |
---|
| 1351 | else |
---|
| 1352 | { |
---|
[648] | 1353 | clusters[0][y]->p_dspin_ram_cmd_in[WEST]( |
---|
| 1354 | signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
| 1355 | clusters[0][y]->p_dspin_ram_cmd_out[WEST]( |
---|
| 1356 | signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
| 1357 | clusters[0][y]->p_dspin_ram_rsp_in[WEST]( |
---|
| 1358 | signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
| 1359 | clusters[0][y]->p_dspin_ram_rsp_out[WEST]( |
---|
| 1360 | signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
[550] | 1361 | } |
---|
| 1362 | |
---|
[648] | 1363 | // handling IOB to RAM network connection in cluster_iob1 |
---|
| 1364 | if( y == y_size-1 ) |
---|
[550] | 1365 | { |
---|
[648] | 1366 | (*clusters[x_size-1][y_size-1]->p_dspin_iob_cmd_out)( |
---|
| 1367 | signal_dspin_cmd_iob1_loopback); |
---|
| 1368 | clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_in[EAST]( |
---|
| 1369 | signal_dspin_cmd_iob1_loopback); |
---|
[550] | 1370 | |
---|
[648] | 1371 | clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_out[EAST]( |
---|
| 1372 | signal_dspin_false_ram_cmd_out[x_size-1][y_size-1][EAST]); |
---|
| 1373 | clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_in[EAST]( |
---|
| 1374 | signal_dspin_false_ram_rsp_in[x_size-1][y_size-1][EAST]); |
---|
[550] | 1375 | |
---|
[648] | 1376 | clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_out[EAST]( |
---|
| 1377 | signal_dspin_rsp_iob1_loopback); |
---|
| 1378 | (*clusters[x_size-1][y_size-1]->p_dspin_iob_rsp_in)( |
---|
| 1379 | signal_dspin_rsp_iob1_loopback); |
---|
[550] | 1380 | } |
---|
| 1381 | else |
---|
| 1382 | { |
---|
[648] | 1383 | clusters[x_size-1][y]->p_dspin_ram_cmd_in[EAST]( |
---|
| 1384 | signal_dspin_false_ram_cmd_in[x_size-1][y][EAST]); |
---|
| 1385 | clusters[x_size-1][y]->p_dspin_ram_cmd_out[EAST]( |
---|
| 1386 | signal_dspin_false_ram_cmd_out[x_size-1][y][EAST]); |
---|
| 1387 | clusters[x_size-1][y]->p_dspin_ram_rsp_in[EAST]( |
---|
| 1388 | signal_dspin_false_ram_rsp_in[x_size-1][y][EAST]); |
---|
| 1389 | clusters[x_size-1][y]->p_dspin_ram_rsp_out[EAST]( |
---|
| 1390 | signal_dspin_false_ram_rsp_out[x_size-1][y][EAST]); |
---|
[550] | 1391 | } |
---|
[450] | 1392 | } |
---|
| 1393 | |
---|
| 1394 | std::cout << "East & West boundaries established" << std::endl; |
---|
| 1395 | |
---|
| 1396 | // North & South boundary clusters connections |
---|
[648] | 1397 | for (size_t x = 0; x < x_size; x++) |
---|
[450] | 1398 | { |
---|
[468] | 1399 | for (size_t k = 0; k < 3; k++) |
---|
| 1400 | { |
---|
[648] | 1401 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k]( |
---|
| 1402 | signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); |
---|
| 1403 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k]( |
---|
| 1404 | signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); |
---|
| 1405 | clusters[x][y_size-1]->p_dspin_int_cmd_in[NORTH][k]( |
---|
| 1406 | signal_dspin_false_int_cmd_in[x][y_size-1][NORTH][k]); |
---|
| 1407 | clusters[x][y_size-1]->p_dspin_int_cmd_out[NORTH][k]( |
---|
| 1408 | signal_dspin_false_int_cmd_out[x][y_size-1][NORTH][k]); |
---|
[468] | 1409 | } |
---|
| 1410 | |
---|
[450] | 1411 | for (size_t k = 0; k < 2; k++) |
---|
| 1412 | { |
---|
[648] | 1413 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k]( |
---|
| 1414 | signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); |
---|
| 1415 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k]( |
---|
| 1416 | signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); |
---|
| 1417 | clusters[x][y_size-1]->p_dspin_int_rsp_in[NORTH][k]( |
---|
| 1418 | signal_dspin_false_int_rsp_in[x][y_size-1][NORTH][k]); |
---|
| 1419 | clusters[x][y_size-1]->p_dspin_int_rsp_out[NORTH][k]( |
---|
| 1420 | signal_dspin_false_int_rsp_out[x][y_size-1][NORTH][k]); |
---|
[450] | 1421 | } |
---|
| 1422 | |
---|
[648] | 1423 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH]( |
---|
| 1424 | signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
| 1425 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH]( |
---|
| 1426 | signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
| 1427 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH]( |
---|
| 1428 | signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
| 1429 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH]( |
---|
| 1430 | signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
[450] | 1431 | |
---|
[648] | 1432 | clusters[x][y_size-1]->p_dspin_ram_cmd_in[NORTH]( |
---|
| 1433 | signal_dspin_false_ram_cmd_in[x][y_size-1][NORTH]); |
---|
| 1434 | clusters[x][y_size-1]->p_dspin_ram_cmd_out[NORTH]( |
---|
| 1435 | signal_dspin_false_ram_cmd_out[x][y_size-1][NORTH]); |
---|
| 1436 | clusters[x][y_size-1]->p_dspin_ram_rsp_in[NORTH]( |
---|
| 1437 | signal_dspin_false_ram_rsp_in[x][y_size-1][NORTH]); |
---|
| 1438 | clusters[x][y_size-1]->p_dspin_ram_rsp_out[NORTH]( |
---|
| 1439 | signal_dspin_false_ram_rsp_out[x][y_size-1][NORTH]); |
---|
[450] | 1440 | } |
---|
| 1441 | |
---|
[648] | 1442 | std::cout << "North & South boundaries established" << std::endl |
---|
| 1443 | << std::endl; |
---|
[450] | 1444 | |
---|
| 1445 | //////////////////////////////////////////////////////// |
---|
| 1446 | // Simulation |
---|
| 1447 | /////////////////////////////////////////////////////// |
---|
| 1448 | |
---|
| 1449 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
[584] | 1450 | |
---|
[450] | 1451 | signal_resetn = false; |
---|
| 1452 | |
---|
[584] | 1453 | signal_irq_false = false; |
---|
| 1454 | |
---|
[450] | 1455 | // network boundaries signals |
---|
[648] | 1456 | for (size_t x = 0; x < x_size ; x++) |
---|
[450] | 1457 | { |
---|
[648] | 1458 | for (size_t y = 0; y < y_size ; y++) |
---|
[450] | 1459 | { |
---|
| 1460 | for (size_t a = 0; a < 4; a++) |
---|
| 1461 | { |
---|
[468] | 1462 | for (size_t k = 0; k < 3; k++) |
---|
| 1463 | { |
---|
[648] | 1464 | signal_dspin_false_int_cmd_in[x][y][a][k].write = false; |
---|
| 1465 | signal_dspin_false_int_cmd_in[x][y][a][k].read = true; |
---|
[468] | 1466 | signal_dspin_false_int_cmd_out[x][y][a][k].write = false; |
---|
[648] | 1467 | signal_dspin_false_int_cmd_out[x][y][a][k].read = true; |
---|
[468] | 1468 | } |
---|
| 1469 | |
---|
[450] | 1470 | for (size_t k = 0; k < 2; k++) |
---|
| 1471 | { |
---|
[648] | 1472 | signal_dspin_false_int_rsp_in[x][y][a][k].write = false; |
---|
| 1473 | signal_dspin_false_int_rsp_in[x][y][a][k].read = true; |
---|
[468] | 1474 | signal_dspin_false_int_rsp_out[x][y][a][k].write = false; |
---|
[648] | 1475 | signal_dspin_false_int_rsp_out[x][y][a][k].read = true; |
---|
[450] | 1476 | } |
---|
| 1477 | |
---|
[648] | 1478 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
| 1479 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
[450] | 1480 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
[648] | 1481 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
[450] | 1482 | |
---|
[648] | 1483 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
| 1484 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
[450] | 1485 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
[648] | 1486 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
[450] | 1487 | } |
---|
| 1488 | } |
---|
| 1489 | } |
---|
| 1490 | |
---|
[550] | 1491 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1492 | signal_resetn = true; |
---|
[450] | 1493 | |
---|
[550] | 1494 | for (size_t n = 1; n < ncycles; n++) |
---|
| 1495 | { |
---|
[607] | 1496 | // Monitor a specific address for one L1 cache |
---|
[584] | 1497 | // clusters[1][1]->proc[0]->cache_monitor(0x50090ULL); |
---|
[450] | 1498 | |
---|
[607] | 1499 | // Monitor a specific address for one L2 cache |
---|
| 1500 | // clusters[0][0]->memc->cache_monitor( 0x170000ULL); |
---|
| 1501 | |
---|
| 1502 | // Monitor a specific address for one XRAM |
---|
[648] | 1503 | // if (n == 3000000) |
---|
| 1504 | // clusters[0][0]->xram->start_monitor( 0x170000ULL , 64); |
---|
[607] | 1505 | |
---|
[550] | 1506 | if (debug_ok and (n > debug_from) and (n % debug_period == 0)) |
---|
[450] | 1507 | { |
---|
[648] | 1508 | std::cout << " ***********************" |
---|
| 1509 | << " cycle " << std::dec << n |
---|
| 1510 | << " ***********************" |
---|
| 1511 | << std::endl; |
---|
[450] | 1512 | |
---|
[648] | 1513 | // trace proc[debug_proc_id] |
---|
[607] | 1514 | if ( debug_proc_id != 0xFFFFFFFF ) |
---|
[550] | 1515 | { |
---|
[648] | 1516 | size_t l = debug_proc_id % nb_procs ; |
---|
| 1517 | size_t cluster_xy = debug_proc_id / nb_procs ; |
---|
| 1518 | size_t x = cluster_xy >> Y_WIDTH; |
---|
| 1519 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
---|
[450] | 1520 | |
---|
[584] | 1521 | clusters[x][y]->proc[l]->print_trace(1); |
---|
[450] | 1522 | |
---|
[550] | 1523 | std::ostringstream proc_signame; |
---|
| 1524 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
[648] | 1525 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace( |
---|
| 1526 | proc_signame.str()); |
---|
[450] | 1527 | |
---|
[584] | 1528 | clusters[x][y]->xicu->print_trace(l); |
---|
| 1529 | |
---|
| 1530 | std::ostringstream xicu_signame; |
---|
| 1531 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
[648] | 1532 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace( |
---|
| 1533 | xicu_signame.str()); |
---|
[584] | 1534 | |
---|
[648] | 1535 | if( clusters[x][y]->signal_proc_it[l].read() ) |
---|
[584] | 1536 | std::cout << "### IRQ_PROC_" << std::dec |
---|
[648] | 1537 | << x << "_" << y << "_" << l |
---|
| 1538 | << " ACTIVE" << std::endl; |
---|
| 1539 | } |
---|
[450] | 1540 | |
---|
[607] | 1541 | // trace INT network |
---|
[550] | 1542 | // clusters[0][0]->int_xbar_cmd_d->print_trace(); |
---|
| 1543 | // clusters[0][0]->int_xbar_rsp_d->print_trace(); |
---|
[450] | 1544 | |
---|
[648] | 1545 | // clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace( |
---|
| 1546 | // "[SIG] INT_CMD_L2G_D_0_0"); |
---|
| 1547 | // clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace( |
---|
| 1548 | // "[SIG] INT_RSP_G2L_D_0_0"); |
---|
[607] | 1549 | |
---|
[550] | 1550 | // clusters[0][0]->int_router_cmd->print_trace(0); |
---|
| 1551 | // clusters[0][0]->int_router_rsp->print_trace(0); |
---|
[450] | 1552 | |
---|
[607] | 1553 | // trace INT_CMD_D xbar and router in cluster 0_1 |
---|
| 1554 | // clusters[0][1]->int_router_cmd->print_trace(0); |
---|
| 1555 | // clusters[0][1]->int_router_rsp->print_trace(0); |
---|
[648] | 1556 | |
---|
| 1557 | // clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace( |
---|
| 1558 | // "[SIG] INT_CMD_G2L_D_0_0"); |
---|
| 1559 | // clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace( |
---|
| 1560 | // "[SIG] INT_RSP_L2G_D_0_0"); |
---|
| 1561 | |
---|
[607] | 1562 | // clusters[0][1]->int_xbar_cmd_d->print_trace(); |
---|
| 1563 | // clusters[0][1]->int_xbar_rsp_d->print_trace(); |
---|
| 1564 | |
---|
[648] | 1565 | // trace memc[debug_memc_id] |
---|
[607] | 1566 | if ( debug_memc_id != 0xFFFFFFFF ) |
---|
[550] | 1567 | { |
---|
[648] | 1568 | size_t x = debug_memc_id >> Y_WIDTH; |
---|
| 1569 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
---|
| 1570 | |
---|
[550] | 1571 | clusters[x][y]->memc->print_trace(0); |
---|
| 1572 | std::ostringstream smemc_tgt; |
---|
| 1573 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
[648] | 1574 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace( |
---|
| 1575 | smemc_tgt.str()); |
---|
[550] | 1576 | std::ostringstream smemc_ini; |
---|
| 1577 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
[648] | 1578 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace( |
---|
| 1579 | smemc_ini.str()); |
---|
[550] | 1580 | clusters[x][y]->xram->print_trace(); |
---|
| 1581 | std::ostringstream sxram_tgt; |
---|
| 1582 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
[648] | 1583 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace( |
---|
| 1584 | sxram_tgt.str()); |
---|
[550] | 1585 | } |
---|
[450] | 1586 | |
---|
[584] | 1587 | // trace RAM network routers |
---|
| 1588 | // for( size_t cluster = 0 ; cluster < XMAX*YMAX ; cluster++ ) |
---|
| 1589 | // { |
---|
| 1590 | // size_t x = cluster / YMAX; |
---|
| 1591 | // size_t y = cluster % YMAX; |
---|
| 1592 | // clusters[x][y]->ram_router_cmd->print_trace(); |
---|
| 1593 | // clusters[x][y]->ram_router_rsp->print_trace(); |
---|
| 1594 | // } |
---|
[648] | 1595 | |
---|
| 1596 | // trace iob, iox and external peripherals |
---|
[550] | 1597 | if ( debug_iob ) |
---|
| 1598 | { |
---|
| 1599 | clusters[0][0]->iob->print_trace(); |
---|
[648] | 1600 | clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( |
---|
| 1601 | "[SIG]IOB0_INT_TGT"); |
---|
| 1602 | clusters[0][0]->signal_int_vci_ini_iobx.print_trace( |
---|
| 1603 | "[SIG]IOB0_INT_INI"); |
---|
| 1604 | clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( |
---|
| 1605 | "[SIG]IOB0_RAM_INI"); |
---|
[450] | 1606 | |
---|
[550] | 1607 | signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
| 1608 | signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
[450] | 1609 | |
---|
[648] | 1610 | // signal_dspin_cmd_iob0_loopback.print_trace( |
---|
| 1611 | // "[SIG]IOB0_CMD_LOOPBACK"); |
---|
| 1612 | // signal_dspin_rsp_iob0_loopback.print_trace( |
---|
| 1613 | // "[SIG]IOB0_RSP_LOOPBACK"); |
---|
[450] | 1614 | |
---|
[607] | 1615 | cdma->print_trace(); |
---|
| 1616 | signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); |
---|
| 1617 | signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); |
---|
[450] | 1618 | |
---|
[550] | 1619 | // mtty->print_trace(); |
---|
| 1620 | // signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT"); |
---|
[450] | 1621 | |
---|
[607] | 1622 | // bdev->print_trace(); |
---|
| 1623 | // signal_vci_tgt_bdev.print_trace("[SIG]IOX_BDEV_TGT"); |
---|
| 1624 | // signal_vci_ini_bdev.print_trace("[SIG]IOX_BDEV_INI"); |
---|
[450] | 1625 | |
---|
[550] | 1626 | // fbuf->print_trace(); |
---|
| 1627 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); |
---|
[498] | 1628 | |
---|
[550] | 1629 | iox_network->print_trace(); |
---|
[450] | 1630 | |
---|
[550] | 1631 | // interrupts |
---|
[648] | 1632 | if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED" |
---|
| 1633 | << std::endl; |
---|
[550] | 1634 | } |
---|
| 1635 | } |
---|
[450] | 1636 | |
---|
[550] | 1637 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1638 | } |
---|
[648] | 1639 | |
---|
| 1640 | delete iox_network; |
---|
| 1641 | delete mnic; |
---|
| 1642 | delete fbuf; |
---|
| 1643 | delete bdev; |
---|
| 1644 | delete cdma; |
---|
| 1645 | delete mtty; |
---|
| 1646 | |
---|
| 1647 | for(size_t x = 0; x < x_size; x++) |
---|
| 1648 | { |
---|
| 1649 | for(size_t y = 0; y < y_size; y++) |
---|
| 1650 | { |
---|
| 1651 | delete clusters[x][y]; |
---|
| 1652 | } |
---|
| 1653 | } |
---|
| 1654 | |
---|
| 1655 | return EXIT_SUCCESS; |
---|
[450] | 1656 | } |
---|
| 1657 | |
---|
| 1658 | int sc_main (int argc, char *argv[]) |
---|
| 1659 | { |
---|
| 1660 | try { |
---|
| 1661 | return _main(argc, argv); |
---|
| 1662 | } catch (std::exception &e) { |
---|
| 1663 | std::cout << e.what() << std::endl; |
---|
| 1664 | } catch (...) { |
---|
| 1665 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1666 | throw; |
---|
| 1667 | } |
---|
| 1668 | return 1; |
---|
| 1669 | } |
---|
| 1670 | |
---|
| 1671 | |
---|
| 1672 | // Local Variables: |
---|
| 1673 | // tab-width: 3 |
---|
| 1674 | // c-basic-offset: 3 |
---|
| 1675 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1676 | // indent-tabs-mode: nil |
---|
| 1677 | // End: |
---|
| 1678 | |
---|
| 1679 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
| 1680 | |
---|