Ignore:
Timestamp:
Jul 24, 2013, 8:47:40 AM (11 years ago)
Author:
cfuguet
Message:


Merging vci_mem_cache from branches/v5 to trunk [441-467]

=-----------------------------------------------------------------------
r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port

=-----------------------------------------------------------------------
r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

  • Adding missing "strings" for print_trace() function
  • Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

=-----------------------------------------------------------------------
r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface


Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

=-----------------------------------------------------------------------
r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

  • Renaming FROM_MC DSPIN flits fields in M2P
  • Renaming FROM_L1 DSPIN flits fields in P2M
  • Renaming CLEANUP_ACK DSPIN flits fields in CLACK

=-----------------------------------------------------------------------
r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

  • Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.
  • Adding third port for the clack coherence network.
  • Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

=-----------------------------------------------------------------------
r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

=-----------------------------------------------------------------------
r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

  • In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

=-----------------------------------------------------------------------
r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

=-----------------------------------------------------------------------
r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.


Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

=-----------------------------------------------------------------------
r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

  • This platform contains a third local crossbar interconnect for the CLACK network.
  • It works only in a monocluster topology

=-----------------------------------------------------------------------
r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

  • Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

=-----------------------------------------------------------------------
r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

  • Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

=-----------------------------------------------------------------------
r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

  • Adding preprocessor conditional statements for ALMOS support


Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/platforms/tsar_generic_iob/top.cpp

    r450 r468  
    802802   // Horizontal inter-clusters INT network DSPIN
    803803   DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc =
    804       alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 2);
     804      alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 3);
    805805   DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec =
    806       alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 2);
     806      alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 3);
    807807   DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc =
    808808      alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2);
    … …  
    812812   // Vertical inter-clusters INT network DSPIN
    813813   DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc =
    814       alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 2);
     814      alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 3);
    815815   DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec =
    816       alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 2);
     816      alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 3);
    817817   DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc =
    818818      alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2);
    … …  
    822822   // Mesh boundaries INT network DSPIN
    823823   DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in =
    824       alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 2, 4);
     824      alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4, 3);
    825825   DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out =
    826       alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 2, 4);
     826      alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4, 3);
    827827   DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in =
    828       alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 2, 4);
     828      alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4, 2);
    829829   DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out =
    830       alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 2, 4);
     830      alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4, 2);
    831831
    832832
    … …  
    11521152         for (size_t y = 0; y < YMAX; y++)
    11531153         {
     1154            for (size_t k = 0; k < 3; k++)
     1155            {
     1156               clusters[x][y]->p_dspin_int_cmd_out[EAST][k]      (signal_dspin_int_cmd_h_inc[x][y][k]);
     1157               clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k]     (signal_dspin_int_cmd_h_inc[x][y][k]);
     1158               clusters[x][y]->p_dspin_int_cmd_in[EAST][k]       (signal_dspin_int_cmd_h_dec[x][y][k]);
     1159               clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k]    (signal_dspin_int_cmd_h_dec[x][y][k]);
     1160            }
     1161
    11541162            for (size_t k = 0; k < 2; k++)
    11551163            {
    1156                clusters[x][y]->p_dspin_int_cmd_out[k][EAST]      (signal_dspin_int_cmd_h_inc[x][y][k]);
    1157                clusters[x+1][y]->p_dspin_int_cmd_in[k][WEST]     (signal_dspin_int_cmd_h_inc[x][y][k]);
    1158                clusters[x][y]->p_dspin_int_cmd_in[k][EAST]       (signal_dspin_int_cmd_h_dec[x][y][k]);
    1159                clusters[x+1][y]->p_dspin_int_cmd_out[k][WEST]    (signal_dspin_int_cmd_h_dec[x][y][k]);
    1160                clusters[x][y]->p_dspin_int_rsp_out[k][EAST]      (signal_dspin_int_rsp_h_inc[x][y][k]);
    1161                clusters[x+1][y]->p_dspin_int_rsp_in[k][WEST]     (signal_dspin_int_rsp_h_inc[x][y][k]);
    1162                clusters[x][y]->p_dspin_int_rsp_in[k][EAST]       (signal_dspin_int_rsp_h_dec[x][y][k]);
    1163                clusters[x+1][y]->p_dspin_int_rsp_out[k][WEST]    (signal_dspin_int_rsp_h_dec[x][y][k]);
     1164               clusters[x][y]->p_dspin_int_rsp_out[EAST][k]      (signal_dspin_int_rsp_h_inc[x][y][k]);
     1165               clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k]     (signal_dspin_int_rsp_h_inc[x][y][k]);
     1166               clusters[x][y]->p_dspin_int_rsp_in[EAST][k]       (signal_dspin_int_rsp_h_dec[x][y][k]);
     1167               clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k]    (signal_dspin_int_rsp_h_dec[x][y][k]);
    11641168            }
    11651169
    … …  
    11851189         for (size_t x = 0; x < XMAX; x++)
    11861190         {
     1191            for (size_t k = 0; k < 3; k++)
     1192            {
     1193               clusters[x][y]->p_dspin_int_cmd_out[NORTH][k]     (signal_dspin_int_cmd_v_inc[x][y][k]);
     1194               clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k]    (signal_dspin_int_cmd_v_inc[x][y][k]);
     1195               clusters[x][y]->p_dspin_int_cmd_in[NORTH][k]      (signal_dspin_int_cmd_v_dec[x][y][k]);
     1196               clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k]   (signal_dspin_int_cmd_v_dec[x][y][k]);
     1197            }
     1198
    11871199            for (size_t k = 0; k < 2; k++)
    11881200            {
    1189                clusters[x][y]->p_dspin_int_cmd_out[k][NORTH]     (signal_dspin_int_cmd_v_inc[x][y][k]);
    1190                clusters[x][y+1]->p_dspin_int_cmd_in[k][SOUTH]    (signal_dspin_int_cmd_v_inc[x][y][k]);
    1191                clusters[x][y]->p_dspin_int_cmd_in[k][NORTH]      (signal_dspin_int_cmd_v_dec[x][y][k]);
    1192                clusters[x][y+1]->p_dspin_int_cmd_out[k][SOUTH]   (signal_dspin_int_cmd_v_dec[x][y][k]);
    1193                clusters[x][y]->p_dspin_int_rsp_out[k][NORTH]     (signal_dspin_int_rsp_v_inc[x][y][k]);
    1194                clusters[x][y+1]->p_dspin_int_rsp_in[k][SOUTH]    (signal_dspin_int_rsp_v_inc[x][y][k]);
    1195                clusters[x][y]->p_dspin_int_rsp_in[k][NORTH]      (signal_dspin_int_rsp_v_dec[x][y][k]);
    1196                clusters[x][y+1]->p_dspin_int_rsp_out[k][SOUTH]   (signal_dspin_int_rsp_v_dec[x][y][k]);
     1201               clusters[x][y]->p_dspin_int_rsp_out[NORTH][k]     (signal_dspin_int_rsp_v_inc[x][y][k]);
     1202               clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k]    (signal_dspin_int_rsp_v_inc[x][y][k]);
     1203               clusters[x][y]->p_dspin_int_rsp_in[NORTH][k]      (signal_dspin_int_rsp_v_dec[x][y][k]);
     1204               clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k]   (signal_dspin_int_rsp_v_dec[x][y][k]);
    11971205            }
    11981206
    … …  
    12141222   for (size_t y = 0; y < YMAX; y++)
    12151223   {
     1224      for (size_t k = 0; k < 3; k++)
     1225      {
     1226         clusters[0][y]->p_dspin_int_cmd_in[WEST][k]          (signal_dspin_false_int_cmd_in[0][y][WEST][k]);
     1227         clusters[0][y]->p_dspin_int_cmd_out[WEST][k]         (signal_dspin_false_int_cmd_out[0][y][WEST][k]);
     1228         clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST][k]     (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]);
     1229         clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST][k]    (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]);
     1230      }
     1231
    12161232      for (size_t k = 0; k < 2; k++)
    12171233      {
    1218          clusters[0][y]->p_dspin_int_cmd_in[k][WEST]          (signal_dspin_false_int_cmd_in[0][y][k][WEST]);
    1219          clusters[0][y]->p_dspin_int_cmd_out[k][WEST]         (signal_dspin_false_int_cmd_out[0][y][k][WEST]);
    1220          clusters[0][y]->p_dspin_int_rsp_in[k][WEST]          (signal_dspin_false_int_rsp_in[0][y][k][WEST]);
    1221          clusters[0][y]->p_dspin_int_rsp_out[k][WEST]         (signal_dspin_false_int_rsp_out[0][y][k][WEST]);
    1222 
    1223          clusters[XMAX-1][y]->p_dspin_int_cmd_in[k][EAST]     (signal_dspin_false_int_cmd_in[XMAX-1][y][k][EAST]);
    1224          clusters[XMAX-1][y]->p_dspin_int_cmd_out[k][EAST]    (signal_dspin_false_int_cmd_out[XMAX-1][y][k][EAST]);
    1225          clusters[XMAX-1][y]->p_dspin_int_rsp_in[k][EAST]     (signal_dspin_false_int_rsp_in[XMAX-1][y][k][EAST]);
    1226          clusters[XMAX-1][y]->p_dspin_int_rsp_out[k][EAST]    (signal_dspin_false_int_rsp_out[XMAX-1][y][k][EAST]);
     1234         clusters[0][y]->p_dspin_int_rsp_in[WEST][k]          (signal_dspin_false_int_rsp_in[0][y][WEST][k]);
     1235         clusters[0][y]->p_dspin_int_rsp_out[WEST][k]         (signal_dspin_false_int_rsp_out[0][y][WEST][k]);
     1236         clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST][k]     (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]);
     1237         clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST][k]    (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]);
    12271238      }
    12281239
    … …  
    12431254   for (size_t x = 0; x < XMAX; x++)
    12441255   {
     1256      for (size_t k = 0; k < 3; k++)
     1257      {
     1258         clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k]         (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]);
     1259         clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k]        (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]);
     1260         clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH][k]    (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]);
     1261         clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH][k]   (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]);
     1262      }
     1263
    12451264      for (size_t k = 0; k < 2; k++)
    12461265      {
    1247          clusters[x][0]->p_dspin_int_cmd_in[k][SOUTH]         (signal_dspin_false_int_cmd_in[x][0][k][SOUTH]);
    1248          clusters[x][0]->p_dspin_int_cmd_out[k][SOUTH]        (signal_dspin_false_int_cmd_out[x][0][k][SOUTH]);
    1249          clusters[x][0]->p_dspin_int_rsp_in[k][SOUTH]         (signal_dspin_false_int_rsp_in[x][0][k][SOUTH]);
    1250          clusters[x][0]->p_dspin_int_rsp_out[k][SOUTH]        (signal_dspin_false_int_rsp_out[x][0][k][SOUTH]);
    1251 
    1252          clusters[x][YMAX-1]->p_dspin_int_cmd_in[k][NORTH]    (signal_dspin_false_int_cmd_in[x][YMAX-1][k][NORTH]);
    1253          clusters[x][YMAX-1]->p_dspin_int_cmd_out[k][NORTH]   (signal_dspin_false_int_cmd_out[x][YMAX-1][k][NORTH]);
    1254          clusters[x][YMAX-1]->p_dspin_int_rsp_in[k][NORTH]    (signal_dspin_false_int_rsp_in[x][YMAX-1][k][NORTH]);
    1255          clusters[x][YMAX-1]->p_dspin_int_rsp_out[k][NORTH]   (signal_dspin_false_int_rsp_out[x][YMAX-1][k][NORTH]);
     1266         clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k]         (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]);
     1267         clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k]        (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]);
     1268         clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH][k]    (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]);
     1269         clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH][k]   (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]);
    12561270      }
    12571271
    … …  
    12831297         for (size_t a = 0; a < 4; a++)
    12841298         {
     1299            for (size_t k = 0; k < 3; k++)
     1300            {
     1301               signal_dspin_false_int_cmd_in[x][y][a][k].write = false;
     1302               signal_dspin_false_int_cmd_in[x][y][a][k].read = true;
     1303               signal_dspin_false_int_cmd_out[x][y][a][k].write = false;
     1304               signal_dspin_false_int_cmd_out[x][y][a][k].read = true;
     1305            }
     1306
    12851307            for (size_t k = 0; k < 2; k++)
    12861308            {
    1287                signal_dspin_false_int_cmd_in[x][y][k][a].write = false;
    1288                signal_dspin_false_int_cmd_in[x][y][k][a].read = true;
    1289                signal_dspin_false_int_cmd_out[x][y][k][a].write = false;
    1290                signal_dspin_false_int_cmd_out[x][y][k][a].read = true;
    1291 
    1292                signal_dspin_false_int_rsp_in[x][y][k][a].write = false;
    1293                signal_dspin_false_int_rsp_in[x][y][k][a].read = true;
    1294                signal_dspin_false_int_rsp_out[x][y][k][a].write = false;
    1295                signal_dspin_false_int_rsp_out[x][y][k][a].read = true;
     1309               signal_dspin_false_int_rsp_in[x][y][a][k].write = false;
     1310               signal_dspin_false_int_rsp_in[x][y][a][k].read = true;
     1311               signal_dspin_false_int_rsp_out[x][y][a][k].write = false;
     1312               signal_dspin_false_int_rsp_out[x][y][a][k].read = true;
    12961313            }
    12971314
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