[450] | 1 | /////////////////////////////////////////////////////////////////////////////// |
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[648] | 2 | // File: top.cpp |
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| 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : august 2013 |
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| 6 | // This program is released under the GNU public license |
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[648] | 7 | // |
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| 8 | // Modified by: Cesar Fuguet |
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| 9 | // Modified on: mars 2014 |
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[450] | 10 | /////////////////////////////////////////////////////////////////////////////// |
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[648] | 11 | // This file define a generic TSAR architecture with an IO network emulating |
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[450] | 12 | // an external bus (i.e. Hypertransport) to access external peripherals: |
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| 13 | // |
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[472] | 14 | // - BROM : boot ROM |
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| 15 | // - FBUF : Frame Buffer |
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| 16 | // - MTTY : multi TTY (up to 15 channels) |
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| 17 | // - MNIC : Network controller (up to 2 channels) |
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[498] | 18 | // - CDMA : Chained Buffer DMA controller (up to 4 channels) |
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[472] | 19 | // - BDEV : Dlock Device controler (1 channel) |
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[648] | 20 | // |
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[450] | 21 | // The internal physical address space is 40 bits. |
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| 22 | // |
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[607] | 23 | // It contains a 2D mesh of XMAX*YMAX clusters, and the cluster index |
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| 24 | // is encoded on 8 bits (X_WIDTH = 4 / Y_WIDTH = 4) whatever the mesh size. |
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[450] | 25 | // |
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[607] | 26 | // It contains 3 networks: |
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| 27 | // |
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[450] | 28 | // 1) the INT network supports Read/Write transactions |
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[648] | 29 | // between processors and L2 caches or peripherals. |
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[450] | 30 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 31 | // It supports also coherence transactions between L1 & L2 caches. |
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| 32 | // 3) the RAM network is emulating the 3D network between L2 caches |
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[472] | 33 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 34 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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[450] | 35 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 36 | // 4) the IOX network connects the two IO bridge components to the |
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| 37 | // 6 external peripheral controllers. |
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| 38 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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[648] | 39 | // |
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[472] | 40 | // The external peripherals IRQs are connected to the XICU component |
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[648] | 41 | // in cluster(0,0): therefore, the number of channels for the external |
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[472] | 42 | // peripherals (MTTY, MNIC, CDMA) is limited by the number of IRQ ports... |
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[450] | 43 | // |
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[584] | 44 | // In cluster(0,0), the XICU HWI input ports are connected as follow: |
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| 45 | // - IRQ_IN[0] to IRQ_IN[7] grounded (reserved for PTI or SWI) |
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[472] | 46 | // - IRQ_IN[8] to IRQ_IN[9] are connected to 2 NIC_RX channels. |
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| 47 | // - IRQ_IN[10] to IRQ_IN[11] are connected to 2 NIC_TX channels. |
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| 48 | // - IRQ_IN[12] to IRQ_IN[15] are connected to 4 CDMA channels |
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| 49 | // - IRQ_IN[16] to IRQ_IN[30] are connected to 15 TTY channels |
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| 50 | // - IRQ_IN[31] is connected to BDEV |
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[584] | 51 | // In other clusters, the XICU HWI input ports are grounded. |
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[648] | 52 | // |
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[450] | 53 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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| 54 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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| 55 | // connected to the three networks (INT, RAM, IOX). |
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| 56 | // The number of clusters cannot be larger than 256. |
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[472] | 57 | // The number of processors per cluster cannot be larger than 4. |
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[648] | 58 | // |
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[450] | 59 | // - It uses two dspin_local_crossbar per cluster to implement the |
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[648] | 60 | // local interconnect correponding to the INT network. |
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[450] | 61 | // - It uses two dspin_local_crossbar per cluster to implement the |
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[648] | 62 | // local interconnect correponding to the coherence INT network. |
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[450] | 63 | // - It uses two virtual_dspin_router per cluster to implement |
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| 64 | // the INT network (routing both the direct and coherence trafic). |
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| 65 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 66 | // - It uses the vci_cc_vcache_wrapper. |
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| 67 | // - It uses the vci_mem_cache. |
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| 68 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 69 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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| 70 | // |
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| 71 | // The TsarIobCluster component is defined in files |
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| 72 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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| 73 | // |
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| 74 | // The main hardware parameters must be defined in the hard_config.h file : |
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| 75 | // - XMAX : number of clusters in a row (power of 2) |
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| 76 | // - YMAX : number of clusters in a column (power of 2) |
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| 77 | // - CLUSTER_SIZE : size of the segment allocated to a cluster |
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| 78 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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| 79 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) |
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| 80 | // - NB_TTY_CHANNELS : number of TTY channels in I/O network (< 16) |
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| 81 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (< 9) |
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[648] | 82 | // |
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[450] | 83 | // Some secondary hardware parameters must be defined in this top.cpp file: |
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[648] | 84 | // - XRAM_LATENCY : external ram latency |
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[450] | 85 | // - MEMC_WAYS : L2 cache number of ways |
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| 86 | // - MEMC_SETS : L2 cache number of sets |
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[648] | 87 | // - L1_IWAYS |
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| 88 | // - L1_ISETS |
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| 89 | // - L1_DWAYS |
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| 90 | // - L1_DSETS |
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[450] | 91 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 92 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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| 93 | // - BDEV_SECTOR_SIZE : block size for block drvice |
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[648] | 94 | // - BDEV_IMAGE_NAME : file pathname for block device |
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[450] | 95 | // - NIC_RX_NAME : file pathname for NIC received packets |
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| 96 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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| 97 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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| 98 | // |
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| 99 | // General policy for 40 bits physical address decoding: |
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| 100 | // All physical segments base addresses are multiple of 1 Mbytes |
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[648] | 101 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[450] | 102 | // The (x_width + y_width) MSB bits (left aligned) define |
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| 103 | // the cluster index, and the LADR bits define the local index: |
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| 104 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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| 105 | // |x_width|y_width|---| 8 | 24 | |
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| 106 | // |
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| 107 | // General policy for 14 bits SRCID decoding: |
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| 108 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 109 | // | X_ID | Y_ID |---| L_ID | |
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| 110 | // |x_width|y_width|---| 6 | |
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| 111 | ///////////////////////////////////////////////////////////////////////// |
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| 112 | |
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| 113 | #include <systemc> |
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| 114 | #include <sys/time.h> |
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| 115 | #include <iostream> |
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| 116 | #include <sstream> |
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| 117 | #include <cstdlib> |
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| 118 | #include <cstdarg> |
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| 119 | #include <stdint.h> |
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[695] | 120 | #include <string> |
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[450] | 121 | |
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| 122 | #include "gdbserver.h" |
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| 123 | #include "mapping_table.h" |
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| 124 | |
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| 125 | #include "tsar_iob_cluster.h" |
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| 126 | #include "vci_chbuf_dma.h" |
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| 127 | #include "vci_multi_tty.h" |
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| 128 | #include "vci_multi_nic.h" |
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| 129 | #include "vci_block_device_tsar.h" |
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| 130 | #include "vci_framebuffer.h" |
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| 131 | #include "vci_iox_network.h" |
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| 132 | |
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| 133 | #include "alloc_elems.h" |
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[695] | 134 | #include "hard_config.h" |
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[450] | 135 | |
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[695] | 136 | //////////////////////////////////////////////////////////////////////// |
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| 137 | // Parallelization |
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| 138 | //////////////////////////////////////////////////////////////////////// |
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[450] | 139 | |
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[648] | 140 | #define USE_OPENMP 0 |
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[450] | 141 | |
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| 142 | #if USE_OPENMP |
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| 143 | #include <omp.h> |
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| 144 | #endif |
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| 145 | |
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[695] | 146 | //////////////////////////////////////////////////////////////////////// |
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[648] | 147 | // DSPIN parameters |
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[695] | 148 | //////////////////////////////////////////////////////////////////////// |
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[450] | 149 | |
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[695] | 150 | #define dspin_int_cmd_width 39 |
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| 151 | #define dspin_int_rsp_width 32 |
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[450] | 152 | |
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[695] | 153 | #define dspin_ram_cmd_width 64 |
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| 154 | #define dspin_ram_rsp_width 64 |
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[450] | 155 | |
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[695] | 156 | //////////////////////////////////////////////////////////////////////// |
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[648] | 157 | // VCI fields width for the 3 VCI networks |
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[695] | 158 | //////////////////////////////////////////////////////////////////////// |
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[450] | 159 | |
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[648] | 160 | #define vci_cell_width_int 4 |
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| 161 | #define vci_cell_width_ext 8 |
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[450] | 162 | |
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[648] | 163 | #define vci_plen_width 8 |
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| 164 | #define vci_address_width 40 |
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| 165 | #define vci_rerror_width 1 |
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| 166 | #define vci_clen_width 1 |
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| 167 | #define vci_rflag_width 1 |
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| 168 | #define vci_srcid_width 14 |
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| 169 | #define vci_pktid_width 4 |
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| 170 | #define vci_trdid_width 4 |
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| 171 | #define vci_wrplen_width 1 |
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[450] | 172 | |
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[695] | 173 | //////////////////////////////////////////////////////////////////////// |
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[648] | 174 | // Secondary Hardware Parameters values |
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[695] | 175 | //////////////////////////////////////////////////////////////////////// |
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[450] | 176 | |
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[695] | 177 | #define XRAM_LATENCY 0 |
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[450] | 178 | |
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[695] | 179 | #define MEMC_WAYS 16 |
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| 180 | #define MEMC_SETS 256 |
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[450] | 181 | |
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[695] | 182 | #define L1_IWAYS 4 |
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| 183 | #define L1_ISETS 64 |
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[450] | 184 | |
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[695] | 185 | #define L1_DWAYS 4 |
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| 186 | #define L1_DSETS 64 |
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[450] | 187 | |
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[695] | 188 | #define FBUF_X_SIZE 128 |
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| 189 | #define FBUF_Y_SIZE 128 |
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[450] | 190 | |
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[695] | 191 | #define BDEV_SECTOR_SIZE 512 |
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| 192 | #define BDEV_IMAGE_NAME "/dev/null" |
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[450] | 193 | |
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[695] | 194 | #define NIC_RX_NAME "/dev/null" |
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| 195 | #define NIC_TX_NAME "/dev/null" |
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| 196 | #define NIC_TIMEOUT 10000 |
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[450] | 197 | |
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[695] | 198 | #define cluster(x,y) TsarIobClusterType::clusterId((x),(y)) |
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[450] | 199 | |
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[695] | 200 | //////////////////////////////////////////////////////////////////////// |
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[648] | 201 | // Software to be loaded in ROM & RAM |
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[695] | 202 | //////////////////////////////////////////////////////////////////////// |
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[450] | 203 | |
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[695] | 204 | #define BOOT_SOFT_NAME "/dev/null" |
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[450] | 205 | |
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[695] | 206 | //////////////////////////////////////////////////////////////////////// |
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[648] | 207 | // DEBUG Parameters default values |
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[695] | 208 | //////////////////////////////////////////////////////////////////////// |
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[450] | 209 | |
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[695] | 210 | #define MAX_FROZEN_CYCLES 10000 |
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[450] | 211 | |
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| 212 | //////////////////////////////////////////////////////////////////////// |
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| 213 | // SRCID definition |
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| 214 | //////////////////////////////////////////////////////////////////////// |
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| 215 | // All initiators are in the same indexing space (14 bits). |
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| 216 | // The SRCID is structured in two fields: |
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| 217 | // - The 10 MSB bits define the cluster index (left aligned) |
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| 218 | // - The 4 LSB bits define the local index. |
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[648] | 219 | // Two different initiators cannot have the same SRCID, but a given |
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| 220 | // initiator can have two alias SRCIDs: |
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[450] | 221 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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| 222 | // and each initiator has one single SRCID. |
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| 223 | // - External initiators (bdev, cdma) are not replicated, but can be |
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[648] | 224 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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[450] | 225 | // They have the same local index, but two different cluster indexes. |
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| 226 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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[648] | 227 | // and external initiators, they must have different local indexes. |
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[450] | 228 | // Consequence: For a local interconnect, the INI_ID port index |
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| 229 | // is NOT equal to the SRCID local index, and the local interconnect |
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| 230 | // must make a translation: SRCID => INI_ID (port index) |
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| 231 | //////////////////////////////////////////////////////////////////////// |
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| 232 | |
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[695] | 233 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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| 234 | #define MDMA_LOCAL_SRCID 0x8 |
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| 235 | #define IOBX_LOCAL_SRCID 0x9 |
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| 236 | #define MEMC_LOCAL_SRCID 0xA |
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| 237 | #define CDMA_LOCAL_SRCID 0xE // hard-coded in dspin_tsar |
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| 238 | #define BDEV_LOCAL_SRCID 0xF // hard-coded in dspin_tsar |
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[450] | 239 | |
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[550] | 240 | /////////////////////////////////////////////////////////////////////// |
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[450] | 241 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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[550] | 242 | /////////////////////////////////////////////////////////////////////// |
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[450] | 243 | |
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[648] | 244 | #define IOX_IOB0_TGT_ID 0 // don't change this value |
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| 245 | #define IOX_IOB1_TGT_ID 1 // don't change this value |
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| 246 | #define IOX_FBUF_TGT_ID 2 |
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| 247 | #define IOX_BDEV_TGT_ID 3 |
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| 248 | #define IOX_MNIC_TGT_ID 4 |
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| 249 | #define IOX_CDMA_TGT_ID 5 |
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[658] | 250 | #define IOX_MTTY_TGT_ID 6 |
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[450] | 251 | |
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[648] | 252 | #define IOX_IOB0_INI_ID 0 // Don't change this value |
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| 253 | #define IOX_IOB1_INI_ID 1 // Don't change this value |
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| 254 | #define IOX_BDEV_INI_ID 2 |
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| 255 | #define IOX_CDMA_INI_ID 3 |
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[450] | 256 | |
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[550] | 257 | //////////////////////////////////////////////////////////////////////// |
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[695] | 258 | int _main(int argc, char *argv[]) { |
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[450] | 259 | using namespace sc_core; |
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| 260 | using namespace soclib::caba; |
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| 261 | using namespace soclib::common; |
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| 262 | |
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[695] | 263 | char soft_name[256] = BOOT_SOFT_NAME; // path: binary code |
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| 264 | uint64_t ncycles = 1000000000; // simulated cycles |
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| 265 | char disk_name[256] = BDEV_IMAGE_NAME; // path: disk image |
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| 266 | char nic_rx_name[256] = NIC_RX_NAME; // path: rx packets file |
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| 267 | char nic_tx_name[256] = NIC_TX_NAME; // path: tx packets file |
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| 268 | ssize_t threads_nr = 1; // simulator's threads |
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[648] | 269 | bool debug_ok = false; // trace activated |
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| 270 | size_t debug_period = 1; // trace period |
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| 271 | size_t debug_memc_id = 0xFFFFFFFF; // idx of traced memc |
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| 272 | size_t debug_proc_id = 0xFFFFFFFF; // idx of traced proc |
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| 273 | bool debug_iob = false; // trace iobs when true |
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| 274 | uint32_t debug_from = 0; // trace start cycle |
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| 275 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen procs |
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[695] | 276 | const size_t block_size = BDEV_SECTOR_SIZE; // disk block size |
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| 277 | const size_t x_size = X_SIZE; |
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| 278 | const size_t y_size = Y_SIZE; |
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[450] | 279 | |
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[648] | 280 | assert((X_WIDTH == 4) and (Y_WIDTH == 4)); |
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[695] | 281 | |
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[450] | 282 | ////////////// command line arguments ////////////////////// |
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[695] | 283 | if (argc > 1) { |
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| 284 | for (int n = 1; n < argc; n = n + 2) { |
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| 285 | if ((strcmp(argv[n],"-NCYCLES") == 0) && ((n+1) < argc)) { |
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| 286 | ncycles = strtoll(argv[n+1], NULL, 0); |
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[648] | 287 | continue; |
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[450] | 288 | } |
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[695] | 289 | if ((strcmp(argv[n],"-SOFT") == 0) && ((n+1) < argc) ) { |
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[450] | 290 | strcpy(soft_name, argv[n+1]); |
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[648] | 291 | continue; |
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[450] | 292 | } |
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[695] | 293 | if ((strcmp(argv[n],"-DISK") == 0) && ((n+1) < argc) ) { |
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[648] | 294 | strcpy(disk_name, argv[n+1]); |
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| 295 | continue; |
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[450] | 296 | } |
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[695] | 297 | if ((strcmp(argv[n],"-DEBUG") == 0) && ((n+1) < argc) ) { |
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[648] | 298 | debug_ok = true; |
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[695] | 299 | debug_from = strtol(argv[n+1], NULL, 0); |
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[648] | 300 | continue; |
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| 301 | } |
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[695] | 302 | if ((strcmp(argv[n],"-MEMCID") == 0) && ((n+1) < argc) ) { |
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| 303 | debug_memc_id = strtol(argv[n+1], NULL, 0); |
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[648] | 304 | size_t x = debug_memc_id >> Y_WIDTH; |
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| 305 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
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| 306 | assert((x < x_size) && (y < y_size)); |
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| 307 | continue; |
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[450] | 308 | } |
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[695] | 309 | if ((strcmp(argv[n],"-IOB") == 0) && ((n+1) < argc) ) { |
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| 310 | debug_iob = (strtol(argv[n+1], NULL, 0) != 0) ? 1 : 0; |
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[648] | 311 | continue; |
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[450] | 312 | } |
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[695] | 313 | if ((strcmp(argv[n],"-PROCID") == 0) && ((n+1) < argc) ) { |
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| 314 | debug_proc_id = strtol(argv[n+1], NULL, 0); |
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| 315 | size_t cluster_xy = debug_proc_id / NB_PROCS ; |
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[648] | 316 | size_t x = cluster_xy >> Y_WIDTH; |
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| 317 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
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| 318 | assert((x < x_size) && (y < y_size)); |
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| 319 | continue; |
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[450] | 320 | } |
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[695] | 321 | if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) { |
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| 322 | threads_nr = strtol(argv[n+1], NULL, 0); |
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[648] | 323 | assert(threads_nr > 0); |
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| 324 | continue; |
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[450] | 325 | } |
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[695] | 326 | if ((strcmp(argv[n], "-FROZEN") == 0) && ((n+1) < argc)) { |
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| 327 | frozen_cycles = strtol(argv[n+1], NULL, 0); |
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[648] | 328 | assert(frozen_cycles > 0); |
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| 329 | continue; |
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[450] | 330 | } |
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[695] | 331 | if ((strcmp(argv[n], "-PERIOD") == 0) && ((n+1) < argc)) { |
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| 332 | debug_period = strtol(argv[n+1], NULL, 0); |
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[648] | 333 | assert(debug_period > 0); |
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| 334 | continue; |
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[450] | 335 | } |
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[648] | 336 | |
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| 337 | std::cout << " Arguments are (key,value) couples.\n" |
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[695] | 338 | << " The order is not important.\n" |
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| 339 | << " Accepted arguments are :\n\n" |
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| 340 | << " -NCYCLES number of simulated_cycles\n" |
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| 341 | << " -SOFT pathname for embedded soft\n" |
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| 342 | << " -DISK pathname for disk image\n" |
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| 343 | << " -DEBUG debug start cycle\n" |
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| 344 | << " -MEMCID index of memc to trace\n" |
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| 345 | << " -IOB debug IOBs if non_zero_value\n\n" |
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| 346 | << " -PROCID index of proc to trace\n" |
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| 347 | << " -THREADS simulator's threads number\n" |
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| 348 | << " -FROZEN max number of frozen cycles\n" |
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| 349 | << " -PERIOD number of cycles between trace\n\n"; |
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[648] | 350 | exit(0); |
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[450] | 351 | } |
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| 352 | } |
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| 353 | |
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[695] | 354 | assert( (NB_TTY_CHANNELS < 16) and |
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| 355 | "The NB_TTY_CHANNELS parameter must be smaller than 16" ); |
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[450] | 356 | |
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[695] | 357 | assert( (NB_NIC_CHANNELS == 1) and |
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| 358 | "The NB_NIC_CHANNELS parameter must be 1" ); |
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[450] | 359 | |
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| 360 | std::cout << std::endl; |
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[648] | 361 | std::cout << " - X_SIZE = " << x_size << std::endl; |
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| 362 | std::cout << " - Y_SIZE = " << y_size << std::endl; |
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[695] | 363 | std::cout << " - NB_PROCS = " << NB_PROCS << std::endl; |
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| 364 | std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; |
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| 365 | std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; |
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| 366 | std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; |
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[648] | 367 | std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; |
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| 368 | std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; |
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| 369 | std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; |
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| 370 | std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; |
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[450] | 371 | |
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| 372 | std::cout << std::endl; |
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| 373 | |
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| 374 | #if USE_OPENMP |
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| 375 | omp_set_dynamic(false); |
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| 376 | omp_set_num_threads(threads_nr); |
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| 377 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
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| 378 | #endif |
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| 379 | |
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| 380 | // Define VciParams objects |
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| 381 | typedef soclib::caba::VciParams<vci_cell_width_int, |
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[695] | 382 | vci_plen_width, |
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| 383 | vci_address_width, |
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| 384 | vci_rerror_width, |
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| 385 | vci_clen_width, |
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| 386 | vci_rflag_width, |
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| 387 | vci_srcid_width, |
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| 388 | vci_pktid_width, |
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| 389 | vci_trdid_width, |
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| 390 | vci_wrplen_width> vci_param_int; |
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[450] | 391 | |
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| 392 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
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[695] | 393 | vci_plen_width, |
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| 394 | vci_address_width, |
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| 395 | vci_rerror_width, |
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| 396 | vci_clen_width, |
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| 397 | vci_rflag_width, |
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| 398 | vci_srcid_width, |
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| 399 | vci_pktid_width, |
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| 400 | vci_trdid_width, |
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| 401 | vci_wrplen_width> vci_param_ext; |
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[450] | 402 | |
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[695] | 403 | // Clusters |
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| 404 | typedef TsarIobCluster<vci_param_int, vci_param_ext, dspin_int_cmd_width, |
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| 405 | dspin_int_rsp_width, dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 406 | TsarIobClusterType; |
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| 407 | |
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| 408 | // clusters containing IOB0 and IOB1 |
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| 409 | size_t cluster_iob0 = cluster(0, 0); |
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| 410 | size_t cluster_iob1 = cluster(x_size - 1, y_size - 1); |
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| 411 | |
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[450] | 412 | ///////////////////////////////////////////////////////////////////// |
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| 413 | // INT network mapping table |
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| 414 | // - two levels address decoding for commands |
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| 415 | // - two levels srcid decoding for responses |
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| 416 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
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| 417 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
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| 418 | ///////////////////////////////////////////////////////////////////// |
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[648] | 419 | MappingTable maptab_int( |
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| 420 | vci_address_width, |
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| 421 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
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[695] | 422 | IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH), |
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[648] | 423 | 0x00FF000000); |
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[450] | 424 | |
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[695] | 425 | for (size_t x = 0; x < x_size; x++) { |
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| 426 | for (size_t y = 0; y < y_size; y++) { |
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[648] | 427 | uint64_t offset = ((uint64_t)cluster(x,y)) |
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| 428 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
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[695] | 429 | const bool config = true; |
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| 430 | const bool cacheable = true; |
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[450] | 431 | |
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[658] | 432 | // the five following segments are defined in all clusters |
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[450] | 433 | |
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[648] | 434 | std::ostringstream smemc_conf; |
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[450] | 435 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
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| 436 | maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE, |
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[695] | 437 | IntTab(cluster(x,y),INT_MEMC_TGT_ID), |
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| 438 | not cacheable, config )); |
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[450] | 439 | |
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[648] | 440 | std::ostringstream smemc_xram; |
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[450] | 441 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
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| 442 | maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE, |
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[695] | 443 | IntTab(cluster(x,y),INT_MEMC_TGT_ID), |
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| 444 | cacheable)); |
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[450] | 445 | |
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[648] | 446 | std::ostringstream sxicu; |
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[450] | 447 | sxicu << "int_seg_xicu_" << x << "_" << y; |
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[648] | 448 | maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE, |
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[695] | 449 | IntTab(cluster(x,y),INT_XICU_TGT_ID), |
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| 450 | not cacheable)); |
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[450] | 451 | |
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[658] | 452 | std::ostringstream sbrom; |
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| 453 | sbrom << "int_seg_brom_" << x << "_" << y; |
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| 454 | maptab_int.add(Segment(sbrom.str(), BROM_BASE+offset, BROM_SIZE, |
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[695] | 455 | IntTab(cluster(x,y),INT_BROM_TGT_ID), |
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| 456 | cacheable)); |
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[658] | 457 | |
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[695] | 458 | std::ostringstream smtty; |
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| 459 | smtty << "int_seg_mtty_" << x << "_" << y; |
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| 460 | maptab_int.add(Segment(smtty.str(), MTTY_BASE+offset, MTTY_SIZE, |
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| 461 | IntTab(cluster(x,y),INT_MTTY_TGT_ID), |
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| 462 | not cacheable)); |
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| 463 | |
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[648] | 464 | std::ostringstream smdma; |
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[450] | 465 | smdma << "int_seg_mdma_" << x << "_" << y; |
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[648] | 466 | maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE, |
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[695] | 467 | IntTab(cluster(x,y),INT_MDMA_TGT_ID), |
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| 468 | not cacheable)); |
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[450] | 469 | |
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[648] | 470 | // the following segments are only defined in cluster_iob0 or in |
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| 471 | // cluster_iob1 |
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[695] | 472 | if ((cluster(x,y) == cluster_iob0) || |
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| 473 | (cluster(x,y) == cluster_iob1)) { |
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[648] | 474 | std::ostringstream siobx; |
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[450] | 475 | siobx << "int_seg_iobx_" << x << "_" << y; |
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[648] | 476 | maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE, |
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[695] | 477 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
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| 478 | not cacheable, config )); |
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[450] | 479 | |
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[648] | 480 | std::ostringstream stty; |
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[450] | 481 | stty << "int_seg_mtty_" << x << "_" << y; |
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[695] | 482 | maptab_int.add(Segment(stty.str(), XTTY_BASE+offset, XTTY_SIZE, |
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| 483 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
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| 484 | not cacheable)); |
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[450] | 485 | |
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[648] | 486 | std::ostringstream sfbf; |
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[450] | 487 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
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[648] | 488 | maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE, |
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[695] | 489 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
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| 490 | not cacheable)); |
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[450] | 491 | |
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[648] | 492 | std::ostringstream sbdv; |
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[450] | 493 | sbdv << "int_seg_bdev_" << x << "_" << y; |
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[648] | 494 | maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE, |
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[695] | 495 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
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| 496 | not cacheable)); |
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[450] | 497 | |
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[648] | 498 | std::ostringstream snic; |
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[450] | 499 | snic << "int_seg_mnic_" << x << "_" << y; |
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[648] | 500 | maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE, |
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[695] | 501 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
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| 502 | not cacheable)); |
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[450] | 503 | |
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[648] | 504 | std::ostringstream sdma; |
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[450] | 505 | sdma << "int_seg_cdma_" << x << "_" << y; |
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[648] | 506 | maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE, |
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[695] | 507 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
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| 508 | not cacheable)); |
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[450] | 509 | } |
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| 510 | |
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| 511 | // This define the mapping between the SRCIDs |
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| 512 | // and the port index on the local interconnect. |
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| 513 | |
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[648] | 514 | maptab_int.srcid_map(IntTab(cluster(x,y), MDMA_LOCAL_SRCID), |
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[695] | 515 | IntTab(cluster(x,y), INT_MDMA_INI_ID)); |
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[648] | 516 | maptab_int.srcid_map(IntTab(cluster(x,y), IOBX_LOCAL_SRCID), |
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[695] | 517 | IntTab(cluster(x,y), INT_IOBX_INI_ID)); |
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[450] | 518 | |
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[695] | 519 | for ( size_t p = 0 ; p < NB_PROCS ; p++ ) { |
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[648] | 520 | maptab_int.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p), |
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[695] | 521 | IntTab(cluster(x,y), INT_PROC_INI_ID + p)); |
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[648] | 522 | } |
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[450] | 523 | } |
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| 524 | } |
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| 525 | std::cout << "INT network " << maptab_int << std::endl; |
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| 526 | |
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[695] | 527 | ///////////////////////////////////////////////////////////////////////// |
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| 528 | // RAM network mapping table |
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| 529 | // - two levels address decoding for commands |
---|
| 530 | // - two levels srcid decoding for responses |
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| 531 | // - 2 local initiators (MEMC, IOBX) per cluster |
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| 532 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
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| 533 | // - 1 local target (XRAM) per cluster |
---|
| 534 | //////////////////////////////////////////////////////////////////////// |
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| 535 | MappingTable maptab_ram( |
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| 536 | vci_address_width, |
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| 537 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
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| 538 | IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH), |
---|
| 539 | 0x00FF000000); |
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[450] | 540 | |
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[695] | 541 | for (size_t x = 0; x < x_size; x++) { |
---|
| 542 | for (size_t y = 0; y < y_size ; y++) { |
---|
| 543 | uint64_t offset = ((uint64_t)cluster(x,y)) |
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| 544 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[450] | 545 | |
---|
[695] | 546 | std::ostringstream sxram; |
---|
| 547 | sxram << "ext_seg_xram_" << x << "_" << y; |
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| 548 | maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, XRAM_SIZE, |
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| 549 | IntTab(cluster(x,y), 0), false)); |
---|
| 550 | } |
---|
| 551 | } |
---|
[450] | 552 | |
---|
[695] | 553 | // This define the mapping between the initiators SRCID |
---|
| 554 | // and the port index on the RAM local interconnect. |
---|
| 555 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
[450] | 556 | |
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[695] | 557 | maptab_ram.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID), |
---|
| 558 | IntTab(cluster_iob0, RAM_IOBX_INI_ID)); |
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| 559 | maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID), |
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| 560 | IntTab(cluster_iob1, RAM_IOBX_INI_ID)); |
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| 561 | maptab_ram.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID), |
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| 562 | IntTab(cluster_iob0, RAM_IOBX_INI_ID)); |
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| 563 | maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID), |
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| 564 | IntTab(cluster_iob1, RAM_IOBX_INI_ID)); |
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| 565 | maptab_ram.srcid_map(IntTab(cluster_iob1, MEMC_LOCAL_SRCID), |
---|
| 566 | IntTab(cluster_iob1, RAM_MEMC_INI_ID)); |
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[450] | 567 | |
---|
[695] | 568 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
[450] | 569 | |
---|
[695] | 570 | /////////////////////////////////////////////////////////////////////// |
---|
| 571 | // IOX network mapping table |
---|
| 572 | // - two levels address decoding for commands |
---|
| 573 | // - two levels srcid decoding for responses |
---|
| 574 | // - 4 initiators (IOB0, IOB1, BDEV, CDMA) |
---|
| 575 | // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC) |
---|
| 576 | /////////////////////////////////////////////////////////////////////// |
---|
| 577 | MappingTable maptab_iox( |
---|
| 578 | vci_address_width, |
---|
| 579 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
---|
| 580 | IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
| 581 | 0x00FF000000); |
---|
[450] | 582 | |
---|
[695] | 583 | // compute base addresses for cluster_iob0 and cluster_iob1 |
---|
| 584 | uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
| 585 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
| 586 | uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
| 587 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[450] | 588 | |
---|
[695] | 589 | // Each peripheral can be accessed through two segments, |
---|
| 590 | // depending on the used IOB (IOB0 or IOB1). |
---|
| 591 | maptab_iox.add(Segment("iox_seg_mtty_0", XTTY_BASE + iob0_base, XTTY_SIZE, |
---|
| 592 | IntTab(cluster_iob0, IOX_MTTY_TGT_ID), false)); |
---|
| 593 | maptab_iox.add(Segment("iox_seg_mtty_1", XTTY_BASE + iob1_base, XTTY_SIZE, |
---|
| 594 | IntTab(cluster_iob1, IOX_MTTY_TGT_ID), false)); |
---|
| 595 | maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE, |
---|
| 596 | IntTab(cluster_iob0, IOX_FBUF_TGT_ID), false)); |
---|
| 597 | maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE, |
---|
| 598 | IntTab(cluster_iob1, IOX_FBUF_TGT_ID), false)); |
---|
| 599 | maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE, |
---|
| 600 | IntTab(cluster_iob0, IOX_BDEV_TGT_ID), false)); |
---|
| 601 | maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE, |
---|
| 602 | IntTab(cluster_iob1, IOX_BDEV_TGT_ID), false)); |
---|
| 603 | maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE, |
---|
| 604 | IntTab(cluster_iob0, IOX_MNIC_TGT_ID), false)); |
---|
| 605 | maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE, |
---|
| 606 | IntTab(cluster_iob1, IOX_MNIC_TGT_ID), false)); |
---|
| 607 | maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE, |
---|
| 608 | IntTab(cluster_iob0, IOX_CDMA_TGT_ID), false)); |
---|
| 609 | maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE, |
---|
| 610 | IntTab(cluster_iob1, IOX_CDMA_TGT_ID), false)); |
---|
[450] | 611 | |
---|
[695] | 612 | // Each physical RAM can be accessed through IOB0, or through IOB1. |
---|
| 613 | // if IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
| 614 | // and the choice depends on on address bit A[39]. |
---|
| 615 | // if IOMMU is activated the addresses use only 32 bits (virtual |
---|
| 616 | // addresses), and the choice depends on address bit A[31]. |
---|
| 617 | for (size_t x = 0; x < x_size; x++) { |
---|
| 618 | for (size_t y = 0; y < y_size ; y++) { |
---|
| 619 | uint64_t offset = static_cast<uint64_t>(cluster(x,y)) |
---|
| 620 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[450] | 621 | |
---|
[695] | 622 | // send command to XRAM through IOB0 |
---|
| 623 | if ( x < (x_size/2) ) { |
---|
| 624 | std::ostringstream siob0; |
---|
| 625 | siob0 << "iox_seg_xram_" << x << "_" << y; |
---|
| 626 | maptab_iox.add(Segment(siob0.str(), |
---|
| 627 | XRAM_BASE + offset, XRAM_SIZE, |
---|
| 628 | IntTab(cluster_iob0,IOX_IOB0_TGT_ID), |
---|
| 629 | false)); |
---|
| 630 | } |
---|
| 631 | // send command to XRAM through IOB1 |
---|
| 632 | else { |
---|
| 633 | std::ostringstream siob1; |
---|
| 634 | siob1 << "iox_seg_xram_" << x << "_" << y; |
---|
| 635 | maptab_iox.add(Segment(siob1.str(), |
---|
| 636 | XRAM_BASE + offset, XRAM_SIZE, |
---|
| 637 | IntTab(cluster_iob1,IOX_IOB1_TGT_ID), |
---|
| 638 | false)); |
---|
| 639 | } |
---|
| 640 | } |
---|
| 641 | } |
---|
| 642 | // useful when IOMMU activated |
---|
| 643 | //maptab_iox.add(Segment("iox_seg_xram", 0xc0000000, 0x40000000, |
---|
| 644 | // IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); |
---|
[450] | 645 | |
---|
[695] | 646 | // This define the mapping between the initiators (identified by the SRCID) |
---|
| 647 | // and the port index on the IOX local interconnect. |
---|
| 648 | // External initiator have two alias SRCID (iob0 / iob1 access) |
---|
[450] | 649 | |
---|
[695] | 650 | maptab_iox.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID), |
---|
| 651 | IntTab(cluster_iob0, IOX_CDMA_INI_ID)); |
---|
| 652 | maptab_iox.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID), |
---|
| 653 | IntTab(cluster_iob1, IOX_CDMA_INI_ID)); |
---|
| 654 | maptab_iox.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID), |
---|
| 655 | IntTab(cluster_iob0, IOX_BDEV_INI_ID)); |
---|
| 656 | maptab_iox.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID), |
---|
| 657 | IntTab(cluster_iob0, IOX_BDEV_INI_ID)); |
---|
[450] | 658 | |
---|
[695] | 659 | for (size_t x = 0; x < x_size; x++) { |
---|
| 660 | for (size_t y = 0; y < y_size ; y++) { |
---|
| 661 | size_t iob = (x < (x_size / 2)) ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID; |
---|
[550] | 662 | |
---|
[695] | 663 | for (size_t p = 0 ; p < NB_PROCS ; p++) { |
---|
| 664 | maptab_iox.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p), |
---|
| 665 | IntTab(cluster(x,y), iob)); |
---|
| 666 | } |
---|
| 667 | maptab_iox.srcid_map(IntTab( cluster(x,y), MDMA_LOCAL_SRCID), |
---|
| 668 | IntTab( cluster(x,y), IOX_IOB0_INI_ID)); |
---|
| 669 | } |
---|
| 670 | } |
---|
[450] | 671 | |
---|
[695] | 672 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
[450] | 673 | |
---|
[695] | 674 | //////////////////// |
---|
| 675 | // Signals |
---|
| 676 | //////////////////// |
---|
[450] | 677 | |
---|
[695] | 678 | sc_clock signal_clk("clk"); |
---|
| 679 | sc_signal<bool> signal_resetn("resetn"); |
---|
[450] | 680 | |
---|
[695] | 681 | sc_signal<bool> signal_irq_false; |
---|
| 682 | sc_signal<bool> signal_irq_bdev; |
---|
| 683 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
| 684 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
| 685 | sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS]; |
---|
| 686 | sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2]; |
---|
[450] | 687 | |
---|
[695] | 688 | // DSPIN signals for loopback in cluster_iob0 & cluster_iob1 |
---|
| 689 | DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback; |
---|
| 690 | DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback; |
---|
| 691 | DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback; |
---|
| 692 | DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback; |
---|
[550] | 693 | |
---|
[695] | 694 | // VCI signals for IOX network |
---|
| 695 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
| 696 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
| 697 | VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); |
---|
| 698 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
[450] | 699 | |
---|
[695] | 700 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
| 701 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
| 702 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 703 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 704 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 705 | VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); |
---|
| 706 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
[450] | 707 | |
---|
[648] | 708 | // Horizontal inter-clusters INT network DSPIN |
---|
[450] | 709 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = |
---|
[648] | 710 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 711 | "signal_dspin_int_cmd_h_inc", x_size-1, y_size, 3); |
---|
[450] | 712 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = |
---|
[648] | 713 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 714 | "signal_dspin_int_cmd_h_dec", x_size-1, y_size, 3); |
---|
[450] | 715 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = |
---|
[648] | 716 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 717 | "signal_dspin_int_rsp_h_inc", x_size-1, y_size, 2); |
---|
[450] | 718 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = |
---|
[648] | 719 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 720 | "signal_dspin_int_rsp_h_dec", x_size-1, y_size, 2); |
---|
[450] | 721 | |
---|
| 722 | // Vertical inter-clusters INT network DSPIN |
---|
| 723 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = |
---|
[648] | 724 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 725 | "signal_dspin_int_cmd_v_inc", x_size, y_size-1, 3); |
---|
[450] | 726 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = |
---|
[648] | 727 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 728 | "signal_dspin_int_cmd_v_dec", x_size, y_size-1, 3); |
---|
[450] | 729 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = |
---|
[648] | 730 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 731 | "signal_dspin_int_rsp_v_inc", x_size, y_size-1, 2); |
---|
[450] | 732 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = |
---|
[648] | 733 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 734 | "signal_dspin_int_rsp_v_dec", x_size, y_size-1, 2); |
---|
[450] | 735 | |
---|
[648] | 736 | // Mesh boundaries INT network DSPIN |
---|
[450] | 737 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = |
---|
[648] | 738 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 739 | "signal_dspin_false_int_cmd_in", x_size, y_size, 4, 3); |
---|
[450] | 740 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = |
---|
[648] | 741 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 742 | "signal_dspin_false_int_cmd_out", x_size, y_size, 4, 3); |
---|
[450] | 743 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = |
---|
[648] | 744 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 745 | "signal_dspin_false_int_rsp_in", x_size, y_size, 4, 2); |
---|
[450] | 746 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = |
---|
[648] | 747 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 748 | "signal_dspin_false_int_rsp_out", x_size, y_size, 4, 2); |
---|
[450] | 749 | |
---|
| 750 | |
---|
[648] | 751 | // Horizontal inter-clusters RAM network DSPIN |
---|
[450] | 752 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
[648] | 753 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 754 | "signal_dspin_ram_cmd_h_inc", x_size-1, y_size); |
---|
[450] | 755 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
[648] | 756 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 757 | "signal_dspin_ram_cmd_h_dec", x_size-1, y_size); |
---|
[450] | 758 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
[648] | 759 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 760 | "signal_dspin_ram_rsp_h_inc", x_size-1, y_size); |
---|
[450] | 761 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
[648] | 762 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 763 | "signal_dspin_ram_rsp_h_dec", x_size-1, y_size); |
---|
[450] | 764 | |
---|
| 765 | // Vertical inter-clusters RAM network DSPIN |
---|
| 766 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
[648] | 767 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 768 | "signal_dspin_ram_cmd_v_inc", x_size, y_size-1); |
---|
[450] | 769 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
[648] | 770 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 771 | "signal_dspin_ram_cmd_v_dec", x_size, y_size-1); |
---|
[450] | 772 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
[648] | 773 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 774 | "signal_dspin_ram_rsp_v_inc", x_size, y_size-1); |
---|
[450] | 775 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
[648] | 776 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 777 | "signal_dspin_ram_rsp_v_dec", x_size, y_size-1); |
---|
[450] | 778 | |
---|
[648] | 779 | // Mesh boundaries RAM network DSPIN |
---|
[450] | 780 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
[648] | 781 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 782 | "signal_dspin_false_ram_cmd_in", x_size, y_size, 4); |
---|
[450] | 783 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
[648] | 784 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 785 | "signal_dspin_false_ram_cmd_out", x_size, y_size, 4); |
---|
[450] | 786 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
[648] | 787 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 788 | "signal_dspin_false_ram_rsp_in", x_size, y_size, 4); |
---|
[450] | 789 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
[648] | 790 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 791 | "signal_dspin_false_ram_rsp_out", x_size, y_size, 4); |
---|
[450] | 792 | |
---|
| 793 | //////////////////////////// |
---|
[648] | 794 | // Loader |
---|
[450] | 795 | //////////////////////////// |
---|
| 796 | |
---|
| 797 | soclib::common::Loader loader(soft_name); |
---|
| 798 | |
---|
| 799 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 800 | proc_iss::set_loader(loader); |
---|
| 801 | |
---|
| 802 | //////////////////////////////////////// |
---|
| 803 | // Instanciated Hardware Components |
---|
| 804 | //////////////////////////////////////// |
---|
| 805 | |
---|
[648] | 806 | std::cout << std::endl << "External Bus and Peripherals" << std::endl |
---|
[695] | 807 | << std::endl; |
---|
[450] | 808 | |
---|
| 809 | // IOX network |
---|
| 810 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
[648] | 811 | iox_network = new VciIoxNetwork<vci_param_ext>("iox_network", |
---|
[695] | 812 | maptab_iox, |
---|
| 813 | 7, // number of targets |
---|
| 814 | 4 ); // number of initiators |
---|
[658] | 815 | |
---|
[450] | 816 | // Network Controller |
---|
[550] | 817 | VciMultiNic<vci_param_ext>* mnic; |
---|
[648] | 818 | mnic = new VciMultiNic<vci_param_ext>("mnic", |
---|
[695] | 819 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
| 820 | maptab_iox, |
---|
| 821 | NB_NIC_CHANNELS, |
---|
| 822 | 0, // mac_4 address |
---|
| 823 | 0, // mac_2 address |
---|
| 824 | nic_rx_name, |
---|
| 825 | nic_tx_name); |
---|
[450] | 826 | |
---|
| 827 | // Frame Buffer |
---|
[550] | 828 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
[648] | 829 | fbuf = new VciFrameBuffer<vci_param_ext>("fbuf", |
---|
[695] | 830 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
| 831 | maptab_iox, |
---|
| 832 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
[450] | 833 | |
---|
| 834 | // Block Device |
---|
[550] | 835 | // for AHCI |
---|
| 836 | // std::vector<std::string> filenames; |
---|
[648] | 837 | // filenames.push_back(disk_name); // one single disk |
---|
[550] | 838 | VciBlockDeviceTsar<vci_param_ext>* bdev; |
---|
[648] | 839 | bdev = new VciBlockDeviceTsar<vci_param_ext>("bdev", |
---|
[695] | 840 | maptab_iox, |
---|
| 841 | IntTab(0, BDEV_LOCAL_SRCID), |
---|
| 842 | IntTab(0, IOX_BDEV_TGT_ID), |
---|
| 843 | disk_name, |
---|
| 844 | block_size, |
---|
| 845 | 64, // burst size (bytes) |
---|
| 846 | 0 ); // disk latency |
---|
[450] | 847 | |
---|
| 848 | // Chained Buffer DMA controller |
---|
[550] | 849 | VciChbufDma<vci_param_ext>* cdma; |
---|
[648] | 850 | cdma = new VciChbufDma<vci_param_ext>("cdma", |
---|
[695] | 851 | maptab_iox, |
---|
| 852 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
| 853 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
| 854 | 64, // burst size (bytes) |
---|
| 855 | 2 * NB_NIC_CHANNELS); |
---|
[450] | 856 | // Multi-TTY controller |
---|
| 857 | std::vector<std::string> vect_names; |
---|
[695] | 858 | for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) |
---|
[450] | 859 | { |
---|
| 860 | std::ostringstream term_name; |
---|
[695] | 861 | term_name << "mtty_iox_" << tid; |
---|
[450] | 862 | vect_names.push_back(term_name.str().c_str()); |
---|
| 863 | } |
---|
[550] | 864 | VciMultiTty<vci_param_ext>* mtty; |
---|
[648] | 865 | mtty = new VciMultiTty<vci_param_ext>("mtty_iox", |
---|
[695] | 866 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
| 867 | maptab_iox, |
---|
| 868 | vect_names); |
---|
| 869 | |
---|
[648] | 870 | TsarIobClusterType* clusters[x_size][y_size]; |
---|
[450] | 871 | |
---|
| 872 | #if USE_OPENMP |
---|
| 873 | #pragma omp parallel |
---|
[695] | 874 | { |
---|
[450] | 875 | #pragma omp for |
---|
| 876 | #endif |
---|
[648] | 877 | |
---|
[695] | 878 | for(size_t i = 0; i < (x_size * y_size); i++) { |
---|
| 879 | size_t x = i / y_size; |
---|
| 880 | size_t y = i % y_size; |
---|
[450] | 881 | |
---|
| 882 | #if USE_OPENMP |
---|
| 883 | #pragma omp critical |
---|
[695] | 884 | { |
---|
[450] | 885 | #endif |
---|
| 886 | std::cout << std::endl; |
---|
| 887 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
| 888 | std::cout << std::endl; |
---|
| 889 | |
---|
| 890 | std::ostringstream sc; |
---|
| 891 | sc << "cluster_" << x << "_" << y; |
---|
| 892 | |
---|
[648] | 893 | bool memc_debug = |
---|
| 894 | debug_ok && (cluster(x,y) == debug_memc_id); |
---|
| 895 | bool proc_debug = |
---|
[695] | 896 | debug_ok && (cluster(x,y) == (debug_proc_id / NB_PROCS)); |
---|
[450] | 897 | |
---|
[648] | 898 | TsarIobClusterType::ClusterParams params = { |
---|
| 899 | .insname = sc.str().c_str(), |
---|
[695] | 900 | |
---|
[648] | 901 | .x_id = x, |
---|
| 902 | .y_id = y, |
---|
[695] | 903 | |
---|
[648] | 904 | .mt_int = maptab_int, |
---|
| 905 | .mt_ext = maptab_ram, |
---|
| 906 | .mt_iox = maptab_iox, |
---|
[695] | 907 | |
---|
[648] | 908 | .memc_ways = MEMC_WAYS, |
---|
| 909 | .memc_sets = MEMC_SETS, |
---|
| 910 | .l1_i_ways = L1_IWAYS, |
---|
| 911 | .l1_i_sets = L1_ISETS, |
---|
| 912 | .l1_d_ways = L1_DWAYS, |
---|
| 913 | .l1_d_sets = L1_DSETS, |
---|
| 914 | .xram_latency = XRAM_LATENCY, |
---|
[695] | 915 | |
---|
[648] | 916 | .loader = loader, |
---|
[695] | 917 | |
---|
[648] | 918 | .frozen_cycles = frozen_cycles, |
---|
| 919 | .debug_start_cycle = debug_from, |
---|
| 920 | .memc_debug_ok = memc_debug, |
---|
| 921 | .proc_debug_ok = proc_debug, |
---|
| 922 | .iob_debug_ok = debug_ok and debug_iob |
---|
| 923 | }; |
---|
[450] | 924 | |
---|
[648] | 925 | clusters[x][y] = new TsarIobClusterType(params); |
---|
[450] | 926 | |
---|
| 927 | #if USE_OPENMP |
---|
[695] | 928 | } // end critical |
---|
[450] | 929 | #endif |
---|
[695] | 930 | } // end for |
---|
[450] | 931 | #if USE_OPENMP |
---|
[695] | 932 | } |
---|
[450] | 933 | #endif |
---|
| 934 | |
---|
[695] | 935 | std::cout << std::endl; |
---|
[450] | 936 | |
---|
[695] | 937 | /////////////////////////////////////////////////////////////////////////// |
---|
| 938 | // Net-list |
---|
| 939 | /////////////////////////////////////////////////////////////////////////// |
---|
[450] | 940 | |
---|
[695] | 941 | // IOX network connexion |
---|
| 942 | iox_network->p_clk (signal_clk); |
---|
| 943 | iox_network->p_resetn (signal_resetn); |
---|
| 944 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
| 945 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
| 946 | iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); |
---|
| 947 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
| 948 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
| 949 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
| 950 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
| 951 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
| 952 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
| 953 | iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); |
---|
| 954 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
[450] | 955 | |
---|
[695] | 956 | // BDEV connexion |
---|
| 957 | bdev->p_clk (signal_clk); |
---|
| 958 | bdev->p_resetn (signal_resetn); |
---|
| 959 | bdev->p_irq (signal_irq_bdev); |
---|
[584] | 960 | |
---|
[695] | 961 | // For AHCI |
---|
| 962 | // bdev->p_channel_irq[0] (signal_irq_bdev); |
---|
[584] | 963 | |
---|
[695] | 964 | bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
| 965 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
[450] | 966 | |
---|
[695] | 967 | std::cout << " - BDEV connected" << std::endl; |
---|
[450] | 968 | |
---|
[695] | 969 | // FBUF connexion |
---|
| 970 | fbuf->p_clk (signal_clk); |
---|
| 971 | fbuf->p_resetn (signal_resetn); |
---|
| 972 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
[450] | 973 | |
---|
[695] | 974 | std::cout << " - FBUF connected" << std::endl; |
---|
[450] | 975 | |
---|
[695] | 976 | // MNIC connexion |
---|
| 977 | mnic->p_clk (signal_clk); |
---|
| 978 | mnic->p_resetn (signal_resetn); |
---|
| 979 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
| 980 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
| 981 | { |
---|
| 982 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 983 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
| 984 | } |
---|
[450] | 985 | |
---|
[695] | 986 | std::cout << " - MNIC connected" << std::endl; |
---|
[450] | 987 | |
---|
[695] | 988 | // MTTY connexion |
---|
| 989 | mtty->p_clk (signal_clk); |
---|
| 990 | mtty->p_resetn (signal_resetn); |
---|
| 991 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
| 992 | for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) { |
---|
| 993 | mtty->p_irq[i] (signal_irq_mtty[i]); |
---|
| 994 | } |
---|
[450] | 995 | |
---|
[695] | 996 | std::cout << " - MTTY connected" << std::endl; |
---|
[450] | 997 | |
---|
[695] | 998 | // CDMA connexion |
---|
| 999 | cdma->p_clk (signal_clk); |
---|
| 1000 | cdma->p_resetn (signal_resetn); |
---|
| 1001 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
| 1002 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
| 1003 | for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) { |
---|
| 1004 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
| 1005 | } |
---|
[450] | 1006 | |
---|
[695] | 1007 | std::cout << " - CDMA connected" << std::endl; |
---|
[450] | 1008 | |
---|
[695] | 1009 | // IRQ connexions from external peripherals (cluster_iob0 only) |
---|
| 1010 | // IRQ_MNIC_RX -> IRQ[08] to IRQ[09] |
---|
| 1011 | // IRQ_MNIC_TX -> IRQ[10] to IRQ[11] |
---|
| 1012 | // IRQ_CDMA -> IRQ[12] to IRQ[15] |
---|
| 1013 | // IRQ_MTTY -> IRQ[16] to IRQ[30] |
---|
| 1014 | // IRQ_BDEV -> IRQ[31] |
---|
[498] | 1015 | |
---|
[695] | 1016 | size_t mx = 16 + NB_TTY_CHANNELS; |
---|
| 1017 | for ( size_t n=0 ; n<32 ; n++ ) { |
---|
| 1018 | if ( n < 8 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1019 | else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1020 | else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1021 | else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1022 | else if ( n < mx ) (*clusters[0][0]->p_irq[n]) (signal_irq_mtty[n-16]); |
---|
| 1023 | else if ( n < 31 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); |
---|
| 1024 | else (*clusters[0][0]->p_irq[n]) (signal_irq_bdev); |
---|
| 1025 | } |
---|
[450] | 1026 | |
---|
[695] | 1027 | // IOB0 cluster connexion to IOX network |
---|
| 1028 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
| 1029 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
[450] | 1030 | |
---|
[695] | 1031 | // IOB1 cluster connexion to IOX network |
---|
| 1032 | (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
| 1033 | (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
[450] | 1034 | |
---|
[695] | 1035 | // All clusters Clock & RESET connexions |
---|
| 1036 | for ( size_t x = 0; x < (x_size); x++ ) { |
---|
| 1037 | for (size_t y = 0; y < y_size; y++) { |
---|
| 1038 | clusters[x][y]->p_clk (signal_clk); |
---|
| 1039 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 1040 | } |
---|
| 1041 | } |
---|
[450] | 1042 | |
---|
[648] | 1043 | const int& NORTH = VirtualDspinRouter<dspin_int_cmd_width>::NORTH; |
---|
| 1044 | const int& SOUTH = VirtualDspinRouter<dspin_int_cmd_width>::SOUTH; |
---|
| 1045 | const int& EAST = VirtualDspinRouter<dspin_int_cmd_width>::EAST; |
---|
| 1046 | const int& WEST = VirtualDspinRouter<dspin_int_cmd_width>::WEST; |
---|
| 1047 | |
---|
[450] | 1048 | // Inter Clusters horizontal connections |
---|
[695] | 1049 | if (x_size > 1) { |
---|
| 1050 | for (size_t x = 0; x < (x_size-1); x++) { |
---|
| 1051 | for (size_t y = 0; y < y_size; y++) { |
---|
| 1052 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1053 | clusters[x][y]->p_dspin_int_cmd_out[EAST][k]( |
---|
| 1054 | signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1055 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k]( |
---|
| 1056 | signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1057 | clusters[x][y]->p_dspin_int_cmd_in[EAST][k]( |
---|
| 1058 | signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1059 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k]( |
---|
| 1060 | signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
[468] | 1061 | } |
---|
| 1062 | |
---|
[695] | 1063 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1064 | clusters[x][y]->p_dspin_int_rsp_out[EAST][k]( |
---|
| 1065 | signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1066 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k]( |
---|
| 1067 | signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1068 | clusters[x][y]->p_dspin_int_rsp_in[EAST][k]( |
---|
| 1069 | signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1070 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k]( |
---|
| 1071 | signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
[450] | 1072 | } |
---|
| 1073 | |
---|
[648] | 1074 | clusters[x][y]->p_dspin_ram_cmd_out[EAST]( |
---|
| 1075 | signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1076 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST]( |
---|
| 1077 | signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1078 | clusters[x][y]->p_dspin_ram_cmd_in[EAST]( |
---|
| 1079 | signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1080 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST]( |
---|
| 1081 | signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1082 | clusters[x][y]->p_dspin_ram_rsp_out[EAST]( |
---|
| 1083 | signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1084 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST]( |
---|
| 1085 | signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1086 | clusters[x][y]->p_dspin_ram_rsp_in[EAST]( |
---|
| 1087 | signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1088 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST]( |
---|
| 1089 | signal_dspin_ram_rsp_h_dec[x][y]); |
---|
[450] | 1090 | } |
---|
| 1091 | } |
---|
| 1092 | } |
---|
| 1093 | |
---|
[648] | 1094 | std::cout << std::endl << "Horizontal connections established" |
---|
[695] | 1095 | << std::endl; |
---|
[450] | 1096 | |
---|
| 1097 | // Inter Clusters vertical connections |
---|
[695] | 1098 | if (y_size > 1) { |
---|
| 1099 | for (size_t y = 0; y < (y_size-1); y++) { |
---|
| 1100 | for (size_t x = 0; x < x_size; x++) { |
---|
| 1101 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1102 | clusters[x][y]->p_dspin_int_cmd_out[NORTH][k]( |
---|
| 1103 | signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1104 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k]( |
---|
| 1105 | signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1106 | clusters[x][y]->p_dspin_int_cmd_in[NORTH][k]( |
---|
| 1107 | signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1108 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k]( |
---|
| 1109 | signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
[468] | 1110 | } |
---|
| 1111 | |
---|
[695] | 1112 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1113 | clusters[x][y]->p_dspin_int_rsp_out[NORTH][k]( |
---|
| 1114 | signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1115 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k]( |
---|
| 1116 | signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1117 | clusters[x][y]->p_dspin_int_rsp_in[NORTH][k]( |
---|
| 1118 | signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1119 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k]( |
---|
| 1120 | signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
[450] | 1121 | } |
---|
| 1122 | |
---|
[648] | 1123 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH]( |
---|
| 1124 | signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1125 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH]( |
---|
| 1126 | signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1127 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH]( |
---|
| 1128 | signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1129 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH]( |
---|
| 1130 | signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1131 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH]( |
---|
| 1132 | signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1133 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH]( |
---|
| 1134 | signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1135 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH]( |
---|
| 1136 | signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1137 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH]( |
---|
| 1138 | signal_dspin_ram_rsp_v_dec[x][y]); |
---|
[450] | 1139 | } |
---|
| 1140 | } |
---|
| 1141 | } |
---|
| 1142 | |
---|
| 1143 | std::cout << "Vertical connections established" << std::endl; |
---|
| 1144 | |
---|
| 1145 | // East & West boundary cluster connections |
---|
[695] | 1146 | for (size_t y = 0; y < y_size; y++) { |
---|
| 1147 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1148 | clusters[0][y]->p_dspin_int_cmd_in[WEST][k]( |
---|
| 1149 | signal_dspin_false_int_cmd_in[0][y][WEST][k]); |
---|
| 1150 | clusters[0][y]->p_dspin_int_cmd_out[WEST][k]( |
---|
| 1151 | signal_dspin_false_int_cmd_out[0][y][WEST][k]); |
---|
| 1152 | clusters[x_size-1][y]->p_dspin_int_cmd_in[EAST][k]( |
---|
| 1153 | signal_dspin_false_int_cmd_in[x_size-1][y][EAST][k]); |
---|
| 1154 | clusters[x_size-1][y]->p_dspin_int_cmd_out[EAST][k]( |
---|
| 1155 | signal_dspin_false_int_cmd_out[x_size-1][y][EAST][k]); |
---|
[468] | 1156 | } |
---|
| 1157 | |
---|
[695] | 1158 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1159 | clusters[0][y]->p_dspin_int_rsp_in[WEST][k]( |
---|
| 1160 | signal_dspin_false_int_rsp_in[0][y][WEST][k]); |
---|
| 1161 | clusters[0][y]->p_dspin_int_rsp_out[WEST][k]( |
---|
| 1162 | signal_dspin_false_int_rsp_out[0][y][WEST][k]); |
---|
| 1163 | clusters[x_size-1][y]->p_dspin_int_rsp_in[EAST][k]( |
---|
| 1164 | signal_dspin_false_int_rsp_in[x_size-1][y][EAST][k]); |
---|
| 1165 | clusters[x_size-1][y]->p_dspin_int_rsp_out[EAST][k]( |
---|
| 1166 | signal_dspin_false_int_rsp_out[x_size-1][y][EAST][k]); |
---|
[450] | 1167 | } |
---|
| 1168 | |
---|
[648] | 1169 | // handling IOB to RAM network connection in cluster_iob0 |
---|
[695] | 1170 | if( y == 0 ) { |
---|
[648] | 1171 | (*clusters[0][0]->p_dspin_iob_cmd_out)( |
---|
| 1172 | signal_dspin_cmd_iob0_loopback); |
---|
| 1173 | clusters[0][0]->p_dspin_ram_cmd_in[WEST]( |
---|
| 1174 | signal_dspin_cmd_iob0_loopback); |
---|
| 1175 | clusters[0][0]->p_dspin_ram_cmd_out[WEST]( |
---|
| 1176 | signal_dspin_false_ram_cmd_out[0][0][WEST]); |
---|
| 1177 | clusters[0][0]->p_dspin_ram_rsp_in[WEST]( |
---|
| 1178 | signal_dspin_false_ram_rsp_in[0][0][WEST]); |
---|
| 1179 | clusters[0][0]->p_dspin_ram_rsp_out[WEST]( |
---|
| 1180 | signal_dspin_rsp_iob0_loopback); |
---|
| 1181 | (*clusters[0][0]->p_dspin_iob_rsp_in)( |
---|
| 1182 | signal_dspin_rsp_iob0_loopback); |
---|
[550] | 1183 | } |
---|
[695] | 1184 | else { |
---|
[648] | 1185 | clusters[0][y]->p_dspin_ram_cmd_in[WEST]( |
---|
| 1186 | signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
| 1187 | clusters[0][y]->p_dspin_ram_cmd_out[WEST]( |
---|
| 1188 | signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
| 1189 | clusters[0][y]->p_dspin_ram_rsp_in[WEST]( |
---|
| 1190 | signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
| 1191 | clusters[0][y]->p_dspin_ram_rsp_out[WEST]( |
---|
| 1192 | signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
[550] | 1193 | } |
---|
| 1194 | |
---|
[648] | 1195 | // handling IOB to RAM network connection in cluster_iob1 |
---|
[695] | 1196 | if( y == y_size-1 ) { |
---|
[648] | 1197 | (*clusters[x_size-1][y_size-1]->p_dspin_iob_cmd_out)( |
---|
| 1198 | signal_dspin_cmd_iob1_loopback); |
---|
| 1199 | clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_in[EAST]( |
---|
| 1200 | signal_dspin_cmd_iob1_loopback); |
---|
[550] | 1201 | |
---|
[648] | 1202 | clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_out[EAST]( |
---|
| 1203 | signal_dspin_false_ram_cmd_out[x_size-1][y_size-1][EAST]); |
---|
| 1204 | clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_in[EAST]( |
---|
| 1205 | signal_dspin_false_ram_rsp_in[x_size-1][y_size-1][EAST]); |
---|
[550] | 1206 | |
---|
[648] | 1207 | clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_out[EAST]( |
---|
| 1208 | signal_dspin_rsp_iob1_loopback); |
---|
| 1209 | (*clusters[x_size-1][y_size-1]->p_dspin_iob_rsp_in)( |
---|
| 1210 | signal_dspin_rsp_iob1_loopback); |
---|
[550] | 1211 | } |
---|
[695] | 1212 | else { |
---|
[648] | 1213 | clusters[x_size-1][y]->p_dspin_ram_cmd_in[EAST]( |
---|
| 1214 | signal_dspin_false_ram_cmd_in[x_size-1][y][EAST]); |
---|
| 1215 | clusters[x_size-1][y]->p_dspin_ram_cmd_out[EAST]( |
---|
| 1216 | signal_dspin_false_ram_cmd_out[x_size-1][y][EAST]); |
---|
| 1217 | clusters[x_size-1][y]->p_dspin_ram_rsp_in[EAST]( |
---|
| 1218 | signal_dspin_false_ram_rsp_in[x_size-1][y][EAST]); |
---|
| 1219 | clusters[x_size-1][y]->p_dspin_ram_rsp_out[EAST]( |
---|
| 1220 | signal_dspin_false_ram_rsp_out[x_size-1][y][EAST]); |
---|
[550] | 1221 | } |
---|
[450] | 1222 | } |
---|
| 1223 | |
---|
| 1224 | std::cout << "East & West boundaries established" << std::endl; |
---|
| 1225 | |
---|
| 1226 | // North & South boundary clusters connections |
---|
[695] | 1227 | for (size_t x = 0; x < x_size; x++) { |
---|
| 1228 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1229 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k]( |
---|
| 1230 | signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); |
---|
| 1231 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k]( |
---|
| 1232 | signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); |
---|
| 1233 | clusters[x][y_size-1]->p_dspin_int_cmd_in[NORTH][k]( |
---|
| 1234 | signal_dspin_false_int_cmd_in[x][y_size-1][NORTH][k]); |
---|
| 1235 | clusters[x][y_size-1]->p_dspin_int_cmd_out[NORTH][k]( |
---|
| 1236 | signal_dspin_false_int_cmd_out[x][y_size-1][NORTH][k]); |
---|
[468] | 1237 | } |
---|
| 1238 | |
---|
[695] | 1239 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1240 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k]( |
---|
| 1241 | signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); |
---|
| 1242 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k]( |
---|
| 1243 | signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); |
---|
| 1244 | clusters[x][y_size-1]->p_dspin_int_rsp_in[NORTH][k]( |
---|
| 1245 | signal_dspin_false_int_rsp_in[x][y_size-1][NORTH][k]); |
---|
| 1246 | clusters[x][y_size-1]->p_dspin_int_rsp_out[NORTH][k]( |
---|
| 1247 | signal_dspin_false_int_rsp_out[x][y_size-1][NORTH][k]); |
---|
[450] | 1248 | } |
---|
| 1249 | |
---|
[648] | 1250 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH]( |
---|
| 1251 | signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
| 1252 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH]( |
---|
| 1253 | signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
| 1254 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH]( |
---|
| 1255 | signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
| 1256 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH]( |
---|
| 1257 | signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
[450] | 1258 | |
---|
[648] | 1259 | clusters[x][y_size-1]->p_dspin_ram_cmd_in[NORTH]( |
---|
| 1260 | signal_dspin_false_ram_cmd_in[x][y_size-1][NORTH]); |
---|
| 1261 | clusters[x][y_size-1]->p_dspin_ram_cmd_out[NORTH]( |
---|
| 1262 | signal_dspin_false_ram_cmd_out[x][y_size-1][NORTH]); |
---|
| 1263 | clusters[x][y_size-1]->p_dspin_ram_rsp_in[NORTH]( |
---|
| 1264 | signal_dspin_false_ram_rsp_in[x][y_size-1][NORTH]); |
---|
| 1265 | clusters[x][y_size-1]->p_dspin_ram_rsp_out[NORTH]( |
---|
| 1266 | signal_dspin_false_ram_rsp_out[x][y_size-1][NORTH]); |
---|
[450] | 1267 | } |
---|
| 1268 | |
---|
[648] | 1269 | std::cout << "North & South boundaries established" << std::endl |
---|
[695] | 1270 | << std::endl; |
---|
[450] | 1271 | |
---|
| 1272 | //////////////////////////////////////////////////////// |
---|
| 1273 | // Simulation |
---|
| 1274 | /////////////////////////////////////////////////////// |
---|
| 1275 | |
---|
| 1276 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
[584] | 1277 | |
---|
[450] | 1278 | signal_resetn = false; |
---|
| 1279 | |
---|
[584] | 1280 | signal_irq_false = false; |
---|
| 1281 | |
---|
[450] | 1282 | // network boundaries signals |
---|
[695] | 1283 | for (size_t x = 0; x < x_size ; x++) { |
---|
| 1284 | for (size_t y = 0; y < y_size ; y++) { |
---|
| 1285 | for (size_t a = 0; a < 4; a++) { |
---|
| 1286 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1287 | signal_dspin_false_int_cmd_in[x][y][a][k].write = false; |
---|
| 1288 | signal_dspin_false_int_cmd_in[x][y][a][k].read = true; |
---|
[468] | 1289 | signal_dspin_false_int_cmd_out[x][y][a][k].write = false; |
---|
[648] | 1290 | signal_dspin_false_int_cmd_out[x][y][a][k].read = true; |
---|
[468] | 1291 | } |
---|
| 1292 | |
---|
[695] | 1293 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1294 | signal_dspin_false_int_rsp_in[x][y][a][k].write = false; |
---|
| 1295 | signal_dspin_false_int_rsp_in[x][y][a][k].read = true; |
---|
[468] | 1296 | signal_dspin_false_int_rsp_out[x][y][a][k].write = false; |
---|
[648] | 1297 | signal_dspin_false_int_rsp_out[x][y][a][k].read = true; |
---|
[450] | 1298 | } |
---|
| 1299 | |
---|
[648] | 1300 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
| 1301 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
[450] | 1302 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
[648] | 1303 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
[450] | 1304 | |
---|
[648] | 1305 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
| 1306 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
[450] | 1307 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
[648] | 1308 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
[450] | 1309 | } |
---|
| 1310 | } |
---|
| 1311 | } |
---|
| 1312 | |
---|
[695] | 1313 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1314 | signal_resetn = true; |
---|
[450] | 1315 | |
---|
[695] | 1316 | struct timeval t1, t2; |
---|
| 1317 | const uint64_t stats_period = 100000; |
---|
| 1318 | gettimeofday(&t1, NULL); |
---|
| 1319 | for (uint64_t n = 1; n < ncycles; n++) { |
---|
| 1320 | // stats display |
---|
| 1321 | if((n % stats_period) == 0) { |
---|
| 1322 | gettimeofday(&t2, NULL); |
---|
[450] | 1323 | |
---|
[695] | 1324 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000 + |
---|
| 1325 | (uint64_t) t1.tv_usec / 1000; |
---|
| 1326 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000 + |
---|
| 1327 | (uint64_t) t2.tv_usec / 1000; |
---|
| 1328 | double freq = (double) stats_period / (ms2 - ms1); |
---|
[607] | 1329 | |
---|
[695] | 1330 | std::cerr << "Platform Clock Frequency: " << freq << " Khz" |
---|
| 1331 | << std::endl; |
---|
[607] | 1332 | |
---|
[695] | 1333 | gettimeofday(&t1, NULL); |
---|
| 1334 | } |
---|
[450] | 1335 | |
---|
[695] | 1336 | if (debug_ok and (n > debug_from) and ((n % debug_period) == 0)) { |
---|
| 1337 | std::cout << " ***********************" |
---|
| 1338 | << " cycle " << std::dec << n |
---|
| 1339 | << " ***********************" |
---|
| 1340 | << std::endl; |
---|
[450] | 1341 | |
---|
[695] | 1342 | // trace proc[debug_proc_id] |
---|
| 1343 | if ( debug_proc_id != 0xFFFFFFFF ) { |
---|
| 1344 | size_t l = debug_proc_id % NB_PROCS ; |
---|
| 1345 | size_t cluster_xy = debug_proc_id / NB_PROCS ; |
---|
| 1346 | size_t x = cluster_xy >> Y_WIDTH; |
---|
| 1347 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
---|
[450] | 1348 | |
---|
[695] | 1349 | clusters[x][y]->proc[l]->print_trace(1); |
---|
[450] | 1350 | |
---|
[695] | 1351 | std::ostringstream proc_signame; |
---|
| 1352 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
| 1353 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace( |
---|
| 1354 | proc_signame.str()); |
---|
[584] | 1355 | |
---|
[695] | 1356 | clusters[x][y]->xicu->print_trace(l); |
---|
[584] | 1357 | |
---|
[695] | 1358 | std::ostringstream xicu_signame; |
---|
| 1359 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
| 1360 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace( |
---|
| 1361 | xicu_signame.str()); |
---|
| 1362 | |
---|
| 1363 | if( clusters[x][y]->signal_proc_it[l].read() ) { |
---|
| 1364 | std::cout << "### IRQ_PROC_" << std::dec |
---|
| 1365 | << x << "_" << y << "_" << l |
---|
| 1366 | << " ACTIVE" << std::endl; |
---|
[648] | 1367 | } |
---|
[695] | 1368 | } |
---|
[450] | 1369 | |
---|
[695] | 1370 | // trace INT network |
---|
| 1371 | // clusters[0][0]->int_xbar_d->print_trace(); |
---|
[450] | 1372 | |
---|
[695] | 1373 | // clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace( |
---|
| 1374 | // "[SIG] INT_CMD_L2G_D_0_0"); |
---|
| 1375 | // clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace( |
---|
| 1376 | // "[SIG] INT_RSP_G2L_D_0_0"); |
---|
[607] | 1377 | |
---|
[695] | 1378 | // clusters[0][0]->int_router_cmd->print_trace(0); |
---|
| 1379 | // clusters[0][0]->int_router_rsp->print_trace(0); |
---|
[450] | 1380 | |
---|
[695] | 1381 | // trace INT_CMD_D xbar and router in cluster 0_1 |
---|
| 1382 | // clusters[0][1]->int_router_cmd->print_trace(0); |
---|
| 1383 | // clusters[0][1]->int_router_rsp->print_trace(0); |
---|
[648] | 1384 | |
---|
[695] | 1385 | // clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace( |
---|
| 1386 | // "[SIG] INT_CMD_G2L_D_0_0"); |
---|
| 1387 | // clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace( |
---|
| 1388 | // "[SIG] INT_RSP_L2G_D_0_0"); |
---|
[648] | 1389 | |
---|
[695] | 1390 | // clusters[0][1]->int_xbar_cmd_d->print_trace(); |
---|
[607] | 1391 | |
---|
[695] | 1392 | // trace memc[debug_memc_id] |
---|
| 1393 | if ( debug_memc_id != 0xFFFFFFFF ) { |
---|
| 1394 | size_t x = debug_memc_id >> Y_WIDTH; |
---|
| 1395 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
---|
[648] | 1396 | |
---|
[695] | 1397 | clusters[x][y]->memc->print_trace(0); |
---|
| 1398 | std::ostringstream smemc_tgt; |
---|
| 1399 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
| 1400 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace( |
---|
| 1401 | smemc_tgt.str()); |
---|
| 1402 | std::ostringstream smemc_ini; |
---|
| 1403 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
| 1404 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace( |
---|
| 1405 | smemc_ini.str()); |
---|
| 1406 | clusters[x][y]->xram->print_trace(); |
---|
| 1407 | std::ostringstream sxram_tgt; |
---|
| 1408 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1409 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace( |
---|
| 1410 | sxram_tgt.str()); |
---|
| 1411 | } |
---|
[450] | 1412 | |
---|
[695] | 1413 | // trace iob, iox and external peripherals |
---|
| 1414 | if ( debug_iob ) { |
---|
| 1415 | clusters[0][0]->iob->print_trace(); |
---|
| 1416 | clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( |
---|
| 1417 | "[SIG]IOB0_INT_TGT"); |
---|
| 1418 | clusters[0][0]->signal_int_vci_ini_iobx.print_trace( |
---|
| 1419 | "[SIG]IOB0_INT_INI"); |
---|
| 1420 | clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( |
---|
| 1421 | "[SIG]IOB0_RAM_INI"); |
---|
[648] | 1422 | |
---|
[695] | 1423 | signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
| 1424 | signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
[450] | 1425 | |
---|
[695] | 1426 | cdma->print_trace(); |
---|
| 1427 | signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); |
---|
| 1428 | signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); |
---|
[450] | 1429 | |
---|
[695] | 1430 | iox_network->print_trace(); |
---|
[450] | 1431 | |
---|
[695] | 1432 | // interrupts |
---|
| 1433 | if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED" |
---|
| 1434 | << std::endl; |
---|
| 1435 | } |
---|
| 1436 | } |
---|
| 1437 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1438 | } |
---|
[450] | 1439 | |
---|
[648] | 1440 | delete iox_network; |
---|
| 1441 | delete mnic; |
---|
| 1442 | delete fbuf; |
---|
| 1443 | delete bdev; |
---|
| 1444 | delete cdma; |
---|
| 1445 | delete mtty; |
---|
| 1446 | |
---|
[695] | 1447 | for(size_t x = 0; x < x_size; x++) { |
---|
| 1448 | for(size_t y = 0; y < y_size; y++) { |
---|
[648] | 1449 | delete clusters[x][y]; |
---|
| 1450 | } |
---|
| 1451 | } |
---|
| 1452 | return EXIT_SUCCESS; |
---|
[450] | 1453 | } |
---|
| 1454 | |
---|
[695] | 1455 | int sc_main (int argc, char *argv[]) { |
---|
[450] | 1456 | try { |
---|
| 1457 | return _main(argc, argv); |
---|
| 1458 | } catch (std::exception &e) { |
---|
| 1459 | std::cout << e.what() << std::endl; |
---|
| 1460 | } catch (...) { |
---|
| 1461 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1462 | throw; |
---|
| 1463 | } |
---|
| 1464 | return 1; |
---|
| 1465 | } |
---|
| 1466 | |
---|
| 1467 | |
---|
| 1468 | // Local Variables: |
---|
| 1469 | // tab-width: 3 |
---|
| 1470 | // c-basic-offset: 3 |
---|
| 1471 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1472 | // indent-tabs-mode: nil |
---|
| 1473 | // End: |
---|
| 1474 | |
---|
| 1475 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
| 1476 | |
---|