[450] | 1 | /////////////////////////////////////////////////////////////////////////////// |
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[648] | 2 | // File: top.cpp |
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| 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : august 2013 |
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| 6 | // This program is released under the GNU public license |
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[648] | 7 | // |
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| 8 | // Modified by: Cesar Fuguet |
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| 9 | // Modified on: mars 2014 |
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[450] | 10 | /////////////////////////////////////////////////////////////////////////////// |
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[648] | 11 | // This file define a generic TSAR architecture with an IO network emulating |
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[450] | 12 | // an external bus (i.e. Hypertransport) to access external peripherals: |
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| 13 | // |
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[472] | 14 | // - BROM : boot ROM |
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| 15 | // - FBUF : Frame Buffer |
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| 16 | // - MTTY : multi TTY (up to 15 channels) |
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| 17 | // - MNIC : Network controller (up to 2 channels) |
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[498] | 18 | // - CDMA : Chained Buffer DMA controller (up to 4 channels) |
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[472] | 19 | // - BDEV : Dlock Device controler (1 channel) |
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[648] | 20 | // |
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[450] | 21 | // The internal physical address space is 40 bits. |
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| 22 | // |
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[607] | 23 | // It contains a 2D mesh of XMAX*YMAX clusters, and the cluster index |
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| 24 | // is encoded on 8 bits (X_WIDTH = 4 / Y_WIDTH = 4) whatever the mesh size. |
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[450] | 25 | // |
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[607] | 26 | // It contains 3 networks: |
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| 27 | // |
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[450] | 28 | // 1) the INT network supports Read/Write transactions |
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[648] | 29 | // between processors and L2 caches or peripherals. |
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[450] | 30 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 31 | // It supports also coherence transactions between L1 & L2 caches. |
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| 32 | // 3) the RAM network is emulating the 3D network between L2 caches |
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[472] | 33 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 34 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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[450] | 35 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 36 | // 4) the IOX network connects the two IO bridge components to the |
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| 37 | // 6 external peripheral controllers. |
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| 38 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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[648] | 39 | // |
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[717] | 40 | // The external peripherals IRQs are connected to the XPIC component |
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| 41 | // in IOX interconnect. |
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[450] | 42 | // |
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| 43 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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| 44 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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| 45 | // connected to the three networks (INT, RAM, IOX). |
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| 46 | // The number of clusters cannot be larger than 256. |
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[472] | 47 | // The number of processors per cluster cannot be larger than 4. |
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[648] | 48 | // |
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[450] | 49 | // - It uses two dspin_local_crossbar per cluster to implement the |
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[648] | 50 | // local interconnect correponding to the INT network. |
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[717] | 51 | // - It uses three dspin_local_crossbar per cluster to implement the |
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[648] | 52 | // local interconnect correponding to the coherence INT network. |
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[450] | 53 | // - It uses two virtual_dspin_router per cluster to implement |
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| 54 | // the INT network (routing both the direct and coherence trafic). |
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| 55 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 56 | // - It uses the vci_cc_vcache_wrapper. |
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| 57 | // - It uses the vci_mem_cache. |
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| 58 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 59 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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[717] | 60 | // - It contains one vci_simple_rom per cluster which can be used for a |
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| 61 | // distributed boot. |
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| 62 | // - It contains one vci_multi_tty per cluster for debug purposes (number |
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| 63 | // of channels can be 0). This TTY is mostly useful when using distributed |
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| 64 | // boot. |
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[450] | 65 | // |
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| 66 | // General policy for 40 bits physical address decoding: |
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| 67 | // All physical segments base addresses are multiple of 1 Mbytes |
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[648] | 68 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[717] | 69 | // The (x_width + y_width) MSB bits define the cluster index, and the |
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| 70 | // LADR bits define the local index: |
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[450] | 71 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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| 72 | // |x_width|y_width|---| 8 | 24 | |
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| 73 | // |
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| 74 | // General policy for 14 bits SRCID decoding: |
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| 75 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 76 | // | X_ID | Y_ID |---| L_ID | |
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| 77 | // |x_width|y_width|---| 6 | |
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| 78 | ///////////////////////////////////////////////////////////////////////// |
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| 79 | |
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| 80 | #include <systemc> |
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| 81 | #include <sys/time.h> |
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| 82 | #include <iostream> |
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| 83 | #include <sstream> |
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| 84 | #include <cstdlib> |
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| 85 | #include <cstdarg> |
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| 86 | #include <stdint.h> |
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[695] | 87 | #include <string> |
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[450] | 88 | |
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| 89 | #include "gdbserver.h" |
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| 90 | #include "mapping_table.h" |
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| 91 | |
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| 92 | #include "tsar_iob_cluster.h" |
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| 93 | #include "vci_chbuf_dma.h" |
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| 94 | #include "vci_multi_tty.h" |
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| 95 | #include "vci_multi_nic.h" |
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| 96 | #include "vci_block_device_tsar.h" |
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| 97 | #include "vci_framebuffer.h" |
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[717] | 98 | #include "vci_iopic.h" |
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[450] | 99 | #include "vci_iox_network.h" |
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| 100 | |
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| 101 | #include "alloc_elems.h" |
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[695] | 102 | #include "hard_config.h" |
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[450] | 103 | |
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[695] | 104 | //////////////////////////////////////////////////////////////////////// |
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| 105 | // Parallelization |
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| 106 | //////////////////////////////////////////////////////////////////////// |
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[450] | 107 | |
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[648] | 108 | #define USE_OPENMP 0 |
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[450] | 109 | |
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| 110 | #if USE_OPENMP |
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| 111 | #include <omp.h> |
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| 112 | #endif |
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| 113 | |
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[695] | 114 | //////////////////////////////////////////////////////////////////////// |
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[648] | 115 | // DSPIN parameters |
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[695] | 116 | //////////////////////////////////////////////////////////////////////// |
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[450] | 117 | |
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[695] | 118 | #define dspin_int_cmd_width 39 |
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| 119 | #define dspin_int_rsp_width 32 |
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[450] | 120 | |
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[695] | 121 | #define dspin_ram_cmd_width 64 |
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| 122 | #define dspin_ram_rsp_width 64 |
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[450] | 123 | |
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[695] | 124 | //////////////////////////////////////////////////////////////////////// |
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[648] | 125 | // VCI fields width for the 3 VCI networks |
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[695] | 126 | //////////////////////////////////////////////////////////////////////// |
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[450] | 127 | |
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[648] | 128 | #define vci_cell_width_int 4 |
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| 129 | #define vci_cell_width_ext 8 |
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[450] | 130 | |
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[648] | 131 | #define vci_plen_width 8 |
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| 132 | #define vci_address_width 40 |
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| 133 | #define vci_rerror_width 1 |
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| 134 | #define vci_clen_width 1 |
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| 135 | #define vci_rflag_width 1 |
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| 136 | #define vci_srcid_width 14 |
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| 137 | #define vci_pktid_width 4 |
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| 138 | #define vci_trdid_width 4 |
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| 139 | #define vci_wrplen_width 1 |
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[450] | 140 | |
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[695] | 141 | //////////////////////////////////////////////////////////////////////// |
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[648] | 142 | // Secondary Hardware Parameters values |
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[695] | 143 | //////////////////////////////////////////////////////////////////////// |
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[450] | 144 | |
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[695] | 145 | #define XRAM_LATENCY 0 |
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[450] | 146 | |
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[695] | 147 | #define MEMC_WAYS 16 |
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| 148 | #define MEMC_SETS 256 |
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[450] | 149 | |
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[695] | 150 | #define L1_IWAYS 4 |
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| 151 | #define L1_ISETS 64 |
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[450] | 152 | |
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[695] | 153 | #define L1_DWAYS 4 |
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| 154 | #define L1_DSETS 64 |
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[450] | 155 | |
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[695] | 156 | #define FBUF_X_SIZE 128 |
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| 157 | #define FBUF_Y_SIZE 128 |
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[450] | 158 | |
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[695] | 159 | #define BDEV_SECTOR_SIZE 512 |
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| 160 | #define BDEV_IMAGE_NAME "/dev/null" |
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[450] | 161 | |
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[695] | 162 | #define NIC_RX_NAME "/dev/null" |
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| 163 | #define NIC_TX_NAME "/dev/null" |
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| 164 | #define NIC_TIMEOUT 10000 |
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[450] | 165 | |
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[695] | 166 | #define cluster(x,y) TsarIobClusterType::clusterId((x),(y)) |
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[450] | 167 | |
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[695] | 168 | //////////////////////////////////////////////////////////////////////// |
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[648] | 169 | // Software to be loaded in ROM & RAM |
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[695] | 170 | //////////////////////////////////////////////////////////////////////// |
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[450] | 171 | |
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[695] | 172 | #define BOOT_SOFT_NAME "/dev/null" |
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[450] | 173 | |
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[695] | 174 | //////////////////////////////////////////////////////////////////////// |
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[648] | 175 | // DEBUG Parameters default values |
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[695] | 176 | //////////////////////////////////////////////////////////////////////// |
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[450] | 177 | |
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[695] | 178 | #define MAX_FROZEN_CYCLES 10000 |
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[450] | 179 | |
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| 180 | //////////////////////////////////////////////////////////////////////// |
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| 181 | // SRCID definition |
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| 182 | //////////////////////////////////////////////////////////////////////// |
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| 183 | // All initiators are in the same indexing space (14 bits). |
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| 184 | // The SRCID is structured in two fields: |
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[717] | 185 | // - The 10 MSB bits define the cluster index |
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[450] | 186 | // - The 4 LSB bits define the local index. |
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[648] | 187 | // Two different initiators cannot have the same SRCID, but a given |
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| 188 | // initiator can have two alias SRCIDs: |
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[450] | 189 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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| 190 | // and each initiator has one single SRCID. |
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| 191 | // - External initiators (bdev, cdma) are not replicated, but can be |
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[648] | 192 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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[450] | 193 | // They have the same local index, but two different cluster indexes. |
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| 194 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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[648] | 195 | // and external initiators, they must have different local indexes. |
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[450] | 196 | // Consequence: For a local interconnect, the INI_ID port index |
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| 197 | // is NOT equal to the SRCID local index, and the local interconnect |
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| 198 | // must make a translation: SRCID => INI_ID (port index) |
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| 199 | //////////////////////////////////////////////////////////////////////// |
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| 200 | |
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[695] | 201 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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| 202 | #define MDMA_LOCAL_SRCID 0x8 |
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| 203 | #define IOBX_LOCAL_SRCID 0x9 |
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[717] | 204 | #define CDMA_LOCAL_SRCID 0xA |
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| 205 | #define BDEV_LOCAL_SRCID 0xB |
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| 206 | #define XPIC_LOCAL_SRCID 0xC |
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[450] | 207 | |
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[550] | 208 | /////////////////////////////////////////////////////////////////////// |
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[717] | 209 | // TGT_ID and INI_ID port indexing for IOX local interconnect |
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[550] | 210 | /////////////////////////////////////////////////////////////////////// |
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[450] | 211 | |
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[717] | 212 | #define IOX_FBUF_TGT_ID 0 |
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| 213 | #define IOX_BDEV_TGT_ID 1 |
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| 214 | #define IOX_MNIC_TGT_ID 2 |
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| 215 | #define IOX_CDMA_TGT_ID 3 |
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| 216 | #define IOX_MTTY_TGT_ID 4 |
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| 217 | #define IOX_XPIC_TGT_ID 5 |
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| 218 | #define IOX_IOB0_TGT_ID 6 |
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| 219 | #define IOX_IOB1_TGT_ID 7 |
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[450] | 220 | |
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[717] | 221 | #define IOX_BDEV_INI_ID 0 |
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| 222 | #define IOX_CDMA_INI_ID 1 |
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| 223 | #define IOX_XPIC_INI_ID 2 |
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| 224 | #define IOX_IOB0_INI_ID 3 |
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| 225 | #define IOX_IOB1_INI_ID 4 |
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[450] | 226 | |
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[550] | 227 | //////////////////////////////////////////////////////////////////////// |
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[695] | 228 | int _main(int argc, char *argv[]) { |
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[450] | 229 | using namespace sc_core; |
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| 230 | using namespace soclib::caba; |
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| 231 | using namespace soclib::common; |
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| 232 | |
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[695] | 233 | char soft_name[256] = BOOT_SOFT_NAME; // path: binary code |
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| 234 | uint64_t ncycles = 1000000000; // simulated cycles |
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| 235 | char disk_name[256] = BDEV_IMAGE_NAME; // path: disk image |
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| 236 | char nic_rx_name[256] = NIC_RX_NAME; // path: rx packets file |
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| 237 | char nic_tx_name[256] = NIC_TX_NAME; // path: tx packets file |
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| 238 | ssize_t threads_nr = 1; // simulator's threads |
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[717] | 239 | bool debug_ok = false; |
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[648] | 240 | size_t debug_period = 1; // trace period |
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| 241 | size_t debug_memc_id = 0xFFFFFFFF; // idx of traced memc |
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| 242 | size_t debug_proc_id = 0xFFFFFFFF; // idx of traced proc |
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| 243 | bool debug_iob = false; // trace iobs when true |
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| 244 | uint32_t debug_from = 0; // trace start cycle |
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| 245 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen procs |
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[717] | 246 | bool distboot = false; // distributed boot |
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[695] | 247 | const size_t block_size = BDEV_SECTOR_SIZE; // disk block size |
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| 248 | const size_t x_size = X_SIZE; |
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| 249 | const size_t y_size = Y_SIZE; |
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[450] | 250 | |
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[648] | 251 | assert((X_WIDTH == 4) and (Y_WIDTH == 4)); |
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[695] | 252 | |
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[450] | 253 | ////////////// command line arguments ////////////////////// |
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[695] | 254 | if (argc > 1) { |
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| 255 | for (int n = 1; n < argc; n = n + 2) { |
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| 256 | if ((strcmp(argv[n],"-NCYCLES") == 0) && ((n+1) < argc)) { |
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| 257 | ncycles = strtoll(argv[n+1], NULL, 0); |
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[648] | 258 | continue; |
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[450] | 259 | } |
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[695] | 260 | if ((strcmp(argv[n],"-SOFT") == 0) && ((n+1) < argc) ) { |
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[450] | 261 | strcpy(soft_name, argv[n+1]); |
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[648] | 262 | continue; |
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[450] | 263 | } |
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[695] | 264 | if ((strcmp(argv[n],"-DISK") == 0) && ((n+1) < argc) ) { |
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[648] | 265 | strcpy(disk_name, argv[n+1]); |
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| 266 | continue; |
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[450] | 267 | } |
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[695] | 268 | if ((strcmp(argv[n],"-DEBUG") == 0) && ((n+1) < argc) ) { |
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[717] | 269 | debug_ok = true; |
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[695] | 270 | debug_from = strtol(argv[n+1], NULL, 0); |
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[648] | 271 | continue; |
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| 272 | } |
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[695] | 273 | if ((strcmp(argv[n],"-MEMCID") == 0) && ((n+1) < argc) ) { |
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| 274 | debug_memc_id = strtol(argv[n+1], NULL, 0); |
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[648] | 275 | size_t x = debug_memc_id >> Y_WIDTH; |
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| 276 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
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| 277 | assert((x < x_size) && (y < y_size)); |
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| 278 | continue; |
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[450] | 279 | } |
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[695] | 280 | if ((strcmp(argv[n],"-IOB") == 0) && ((n+1) < argc) ) { |
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| 281 | debug_iob = (strtol(argv[n+1], NULL, 0) != 0) ? 1 : 0; |
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[648] | 282 | continue; |
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[450] | 283 | } |
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[695] | 284 | if ((strcmp(argv[n],"-PROCID") == 0) && ((n+1) < argc) ) { |
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| 285 | debug_proc_id = strtol(argv[n+1], NULL, 0); |
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| 286 | size_t cluster_xy = debug_proc_id / NB_PROCS ; |
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[648] | 287 | size_t x = cluster_xy >> Y_WIDTH; |
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| 288 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
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| 289 | assert((x < x_size) && (y < y_size)); |
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| 290 | continue; |
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[450] | 291 | } |
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[695] | 292 | if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) { |
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| 293 | threads_nr = strtol(argv[n+1], NULL, 0); |
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[648] | 294 | assert(threads_nr > 0); |
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| 295 | continue; |
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[450] | 296 | } |
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[695] | 297 | if ((strcmp(argv[n], "-FROZEN") == 0) && ((n+1) < argc)) { |
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| 298 | frozen_cycles = strtol(argv[n+1], NULL, 0); |
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[648] | 299 | assert(frozen_cycles > 0); |
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| 300 | continue; |
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[450] | 301 | } |
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[695] | 302 | if ((strcmp(argv[n], "-PERIOD") == 0) && ((n+1) < argc)) { |
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| 303 | debug_period = strtol(argv[n+1], NULL, 0); |
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[648] | 304 | assert(debug_period > 0); |
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| 305 | continue; |
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[450] | 306 | } |
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[717] | 307 | if ((strcmp(argv[n], "-DISTBOOT") == 0)) { |
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| 308 | distboot = true; |
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| 309 | continue; |
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| 310 | } |
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[648] | 311 | |
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[717] | 312 | std::cout |
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| 313 | << "\nArguments are (key,value) couples." |
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| 314 | << "\nThe order is not important." |
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| 315 | << "\nAccepted arguments are :\n" |
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| 316 | << "\n -NCYCLES number of simulated_cycles" |
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| 317 | << "\n -SOFT pathname for embedded soft" |
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| 318 | << "\n -DISK pathname for disk image" |
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| 319 | << "\n -DEBUG debug start cycle" |
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| 320 | << "\n -MEMCID index of memc to trace" |
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| 321 | << "\n -IOB debug IOBs if non_zero_value" |
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| 322 | << "\n -PROCID index of proc to trace" |
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| 323 | << "\n -THREADS simulator's threads number" |
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| 324 | << "\n -FROZEN max number of frozen cycles" |
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| 325 | << "\n -PERIOD number of cycles between trace" |
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| 326 | << "\n -DISTBOOT use distributed boot ROM" |
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| 327 | << "\n (processors physical address extention is" |
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| 328 | << "\n initialized with local cluster id)" |
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| 329 | << std::endl; |
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| 330 | |
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[648] | 331 | exit(0); |
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[450] | 332 | } |
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| 333 | } |
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| 334 | |
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[695] | 335 | assert( (NB_TTY_CHANNELS < 16) and |
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| 336 | "The NB_TTY_CHANNELS parameter must be smaller than 16" ); |
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[450] | 337 | |
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[695] | 338 | assert( (NB_NIC_CHANNELS == 1) and |
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| 339 | "The NB_NIC_CHANNELS parameter must be 1" ); |
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[450] | 340 | |
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[717] | 341 | assert( (x_size > 0) and (y_size > 0) and |
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| 342 | "Number of clusters on X and Y must be at least 1" ); |
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[450] | 343 | |
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[717] | 344 | std::cout << "\n- X_SIZE = " << x_size |
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| 345 | << "\n- Y_SIZE = " << y_size |
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| 346 | << "\n- NB_PROCS = " << NB_PROCS |
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| 347 | << "\n- NB_DMA_CHANNELS = " << NB_DMA_CHANNELS |
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| 348 | << "\n- NB_TTY_CHANNELS = " << NB_TTY_CHANNELS |
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| 349 | << "\n- NB_NIC_CHANNELS = " << NB_NIC_CHANNELS |
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| 350 | << "\n- MEMC_WAYS = " << MEMC_WAYS |
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| 351 | << "\n- MEMC_SETS = " << MEMC_SETS |
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| 352 | << "\n- RAM_LATENCY = " << XRAM_LATENCY |
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| 353 | << "\n- MAX_FROZEN = " << frozen_cycles |
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| 354 | << "\n- DISTBOOT = " << distboot |
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| 355 | << std::endl; |
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| 356 | |
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[450] | 357 | std::cout << std::endl; |
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| 358 | |
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| 359 | #if USE_OPENMP |
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| 360 | omp_set_dynamic(false); |
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| 361 | omp_set_num_threads(threads_nr); |
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| 362 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
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| 363 | #endif |
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| 364 | |
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| 365 | // Define VciParams objects |
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| 366 | typedef soclib::caba::VciParams<vci_cell_width_int, |
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[695] | 367 | vci_plen_width, |
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| 368 | vci_address_width, |
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| 369 | vci_rerror_width, |
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| 370 | vci_clen_width, |
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| 371 | vci_rflag_width, |
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| 372 | vci_srcid_width, |
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| 373 | vci_pktid_width, |
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| 374 | vci_trdid_width, |
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| 375 | vci_wrplen_width> vci_param_int; |
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[450] | 376 | |
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| 377 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
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[695] | 378 | vci_plen_width, |
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| 379 | vci_address_width, |
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| 380 | vci_rerror_width, |
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| 381 | vci_clen_width, |
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| 382 | vci_rflag_width, |
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| 383 | vci_srcid_width, |
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| 384 | vci_pktid_width, |
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| 385 | vci_trdid_width, |
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| 386 | vci_wrplen_width> vci_param_ext; |
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[450] | 387 | |
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[695] | 388 | // Clusters |
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| 389 | typedef TsarIobCluster<vci_param_int, vci_param_ext, dspin_int_cmd_width, |
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| 390 | dspin_int_rsp_width, dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 391 | TsarIobClusterType; |
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| 392 | |
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| 393 | // clusters containing IOB0 and IOB1 |
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| 394 | size_t cluster_iob0 = cluster(0, 0); |
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| 395 | size_t cluster_iob1 = cluster(x_size - 1, y_size - 1); |
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| 396 | |
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[717] | 397 | // using mono cluster configuration (only one IO bridge) ? |
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| 398 | bool is_mono_cluster = ((x_size == 1) && (y_size == 1)); |
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| 399 | |
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[450] | 400 | ///////////////////////////////////////////////////////////////////// |
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| 401 | // INT network mapping table |
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| 402 | // - two levels address decoding for commands |
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| 403 | // - two levels srcid decoding for responses |
---|
| 404 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
---|
| 405 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
---|
| 406 | ///////////////////////////////////////////////////////////////////// |
---|
[648] | 407 | MappingTable maptab_int( |
---|
| 408 | vci_address_width, |
---|
| 409 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
---|
[695] | 410 | IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH), |
---|
[648] | 411 | 0x00FF000000); |
---|
[450] | 412 | |
---|
[695] | 413 | for (size_t x = 0; x < x_size; x++) { |
---|
| 414 | for (size_t y = 0; y < y_size; y++) { |
---|
[648] | 415 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
| 416 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[695] | 417 | const bool config = true; |
---|
| 418 | const bool cacheable = true; |
---|
[450] | 419 | |
---|
[658] | 420 | // the five following segments are defined in all clusters |
---|
[450] | 421 | |
---|
[648] | 422 | std::ostringstream smemc_conf; |
---|
[450] | 423 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
| 424 | maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE, |
---|
[695] | 425 | IntTab(cluster(x,y),INT_MEMC_TGT_ID), |
---|
| 426 | not cacheable, config )); |
---|
[450] | 427 | |
---|
[648] | 428 | std::ostringstream smemc_xram; |
---|
[450] | 429 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
| 430 | maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE, |
---|
[695] | 431 | IntTab(cluster(x,y),INT_MEMC_TGT_ID), |
---|
| 432 | cacheable)); |
---|
[450] | 433 | |
---|
[648] | 434 | std::ostringstream sxicu; |
---|
[450] | 435 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
[648] | 436 | maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE, |
---|
[695] | 437 | IntTab(cluster(x,y),INT_XICU_TGT_ID), |
---|
| 438 | not cacheable)); |
---|
[450] | 439 | |
---|
[658] | 440 | std::ostringstream sbrom; |
---|
| 441 | sbrom << "int_seg_brom_" << x << "_" << y; |
---|
| 442 | maptab_int.add(Segment(sbrom.str(), BROM_BASE+offset, BROM_SIZE, |
---|
[695] | 443 | IntTab(cluster(x,y),INT_BROM_TGT_ID), |
---|
| 444 | cacheable)); |
---|
[658] | 445 | |
---|
[695] | 446 | std::ostringstream smtty; |
---|
| 447 | smtty << "int_seg_mtty_" << x << "_" << y; |
---|
| 448 | maptab_int.add(Segment(smtty.str(), MTTY_BASE+offset, MTTY_SIZE, |
---|
| 449 | IntTab(cluster(x,y),INT_MTTY_TGT_ID), |
---|
| 450 | not cacheable)); |
---|
| 451 | |
---|
[648] | 452 | std::ostringstream smdma; |
---|
[450] | 453 | smdma << "int_seg_mdma_" << x << "_" << y; |
---|
[648] | 454 | maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE, |
---|
[695] | 455 | IntTab(cluster(x,y),INT_MDMA_TGT_ID), |
---|
| 456 | not cacheable)); |
---|
[450] | 457 | |
---|
[648] | 458 | // the following segments are only defined in cluster_iob0 or in |
---|
| 459 | // cluster_iob1 |
---|
[695] | 460 | if ((cluster(x,y) == cluster_iob0) || |
---|
| 461 | (cluster(x,y) == cluster_iob1)) { |
---|
[648] | 462 | std::ostringstream siobx; |
---|
[450] | 463 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
[648] | 464 | maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE, |
---|
[695] | 465 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 466 | not cacheable, config )); |
---|
[450] | 467 | |
---|
[648] | 468 | std::ostringstream stty; |
---|
[450] | 469 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
[695] | 470 | maptab_int.add(Segment(stty.str(), XTTY_BASE+offset, XTTY_SIZE, |
---|
| 471 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 472 | not cacheable)); |
---|
[450] | 473 | |
---|
[648] | 474 | std::ostringstream sfbf; |
---|
[450] | 475 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
[648] | 476 | maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE, |
---|
[695] | 477 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 478 | not cacheable)); |
---|
[450] | 479 | |
---|
[648] | 480 | std::ostringstream sbdv; |
---|
[450] | 481 | sbdv << "int_seg_bdev_" << x << "_" << y; |
---|
[648] | 482 | maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE, |
---|
[695] | 483 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 484 | not cacheable)); |
---|
[450] | 485 | |
---|
[648] | 486 | std::ostringstream snic; |
---|
[450] | 487 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
[648] | 488 | maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE, |
---|
[695] | 489 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 490 | not cacheable)); |
---|
[450] | 491 | |
---|
[648] | 492 | std::ostringstream sdma; |
---|
[450] | 493 | sdma << "int_seg_cdma_" << x << "_" << y; |
---|
[648] | 494 | maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE, |
---|
[695] | 495 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 496 | not cacheable)); |
---|
[717] | 497 | |
---|
| 498 | std::ostringstream spic; |
---|
| 499 | sdma << "int_seg_xpic_" << x << "_" << y; |
---|
| 500 | maptab_int.add(Segment(spic.str(), XPIC_BASE+offset, XPIC_SIZE, |
---|
| 501 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), |
---|
| 502 | not cacheable)); |
---|
[450] | 503 | } |
---|
| 504 | |
---|
| 505 | // This define the mapping between the SRCIDs |
---|
| 506 | // and the port index on the local interconnect. |
---|
| 507 | |
---|
[648] | 508 | maptab_int.srcid_map(IntTab(cluster(x,y), MDMA_LOCAL_SRCID), |
---|
[695] | 509 | IntTab(cluster(x,y), INT_MDMA_INI_ID)); |
---|
[648] | 510 | maptab_int.srcid_map(IntTab(cluster(x,y), IOBX_LOCAL_SRCID), |
---|
[695] | 511 | IntTab(cluster(x,y), INT_IOBX_INI_ID)); |
---|
[717] | 512 | maptab_int.srcid_map(IntTab(cluster(x,y), XPIC_LOCAL_SRCID), |
---|
| 513 | IntTab(cluster(x,y), INT_IOBX_INI_ID)); |
---|
[450] | 514 | |
---|
[695] | 515 | for ( size_t p = 0 ; p < NB_PROCS ; p++ ) { |
---|
[648] | 516 | maptab_int.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p), |
---|
[695] | 517 | IntTab(cluster(x,y), INT_PROC_INI_ID + p)); |
---|
[648] | 518 | } |
---|
[450] | 519 | } |
---|
| 520 | } |
---|
| 521 | std::cout << "INT network " << maptab_int << std::endl; |
---|
| 522 | |
---|
[695] | 523 | ///////////////////////////////////////////////////////////////////////// |
---|
| 524 | // RAM network mapping table |
---|
| 525 | // - two levels address decoding for commands |
---|
| 526 | // - two levels srcid decoding for responses |
---|
| 527 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
| 528 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
| 529 | // - 1 local target (XRAM) per cluster |
---|
| 530 | //////////////////////////////////////////////////////////////////////// |
---|
| 531 | MappingTable maptab_ram( |
---|
| 532 | vci_address_width, |
---|
[717] | 533 | IntTab(X_WIDTH + Y_WIDTH, 0), |
---|
[695] | 534 | IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH), |
---|
| 535 | 0x00FF000000); |
---|
[450] | 536 | |
---|
[695] | 537 | for (size_t x = 0; x < x_size; x++) { |
---|
| 538 | for (size_t y = 0; y < y_size ; y++) { |
---|
| 539 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
| 540 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[450] | 541 | |
---|
[695] | 542 | std::ostringstream sxram; |
---|
| 543 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
| 544 | maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, XRAM_SIZE, |
---|
[717] | 545 | IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); |
---|
[695] | 546 | } |
---|
| 547 | } |
---|
[450] | 548 | |
---|
[695] | 549 | // This define the mapping between the initiators SRCID |
---|
| 550 | // and the port index on the RAM local interconnect. |
---|
| 551 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
[450] | 552 | |
---|
[695] | 553 | maptab_ram.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID), |
---|
| 554 | IntTab(cluster_iob0, RAM_IOBX_INI_ID)); |
---|
| 555 | maptab_ram.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID), |
---|
| 556 | IntTab(cluster_iob0, RAM_IOBX_INI_ID)); |
---|
[717] | 557 | maptab_ram.srcid_map(IntTab(cluster_iob0, XPIC_LOCAL_SRCID), |
---|
| 558 | IntTab(cluster_iob0, RAM_IOBX_INI_ID)); |
---|
| 559 | maptab_ram.srcid_map(IntTab(cluster_iob0, RAM_MEMC_INI_ID), |
---|
| 560 | IntTab(cluster_iob0, RAM_MEMC_INI_ID)); |
---|
[450] | 561 | |
---|
[717] | 562 | if (not is_mono_cluster) { |
---|
| 563 | maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID), |
---|
| 564 | IntTab(cluster_iob1, RAM_IOBX_INI_ID)); |
---|
| 565 | maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID), |
---|
| 566 | IntTab(cluster_iob1, RAM_IOBX_INI_ID)); |
---|
| 567 | maptab_ram.srcid_map(IntTab(cluster_iob1, XPIC_LOCAL_SRCID), |
---|
| 568 | IntTab(cluster_iob1, RAM_IOBX_INI_ID)); |
---|
| 569 | maptab_ram.srcid_map(IntTab(cluster_iob1, RAM_MEMC_INI_ID), |
---|
| 570 | IntTab(cluster_iob1, RAM_MEMC_INI_ID)); |
---|
| 571 | } |
---|
| 572 | |
---|
[695] | 573 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
[450] | 574 | |
---|
[695] | 575 | /////////////////////////////////////////////////////////////////////// |
---|
| 576 | // IOX network mapping table |
---|
| 577 | // - two levels address decoding for commands |
---|
| 578 | // - two levels srcid decoding for responses |
---|
| 579 | // - 4 initiators (IOB0, IOB1, BDEV, CDMA) |
---|
| 580 | // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC) |
---|
| 581 | /////////////////////////////////////////////////////////////////////// |
---|
[717] | 582 | |
---|
| 583 | const size_t iox_addr_drop_bits = X_WIDTH + Y_WIDTH - 1; |
---|
| 584 | const size_t iox_addr_decd_bits = 16 - X_WIDTH - Y_WIDTH + 1; |
---|
[695] | 585 | MappingTable maptab_iox( |
---|
| 586 | vci_address_width, |
---|
[717] | 587 | IntTab(iox_addr_drop_bits, iox_addr_decd_bits), |
---|
| 588 | IntTab(X_WIDTH + Y_WIDTH , vci_param_ext::S - X_WIDTH - Y_WIDTH), |
---|
[695] | 589 | 0x00FF000000); |
---|
[450] | 590 | |
---|
[717] | 591 | |
---|
| 592 | // Each peripheral can be accessed through two segments, |
---|
| 593 | // depending on the used IOB (IOB0 or IOB1). |
---|
| 594 | |
---|
[695] | 595 | uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
| 596 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[450] | 597 | |
---|
[695] | 598 | maptab_iox.add(Segment("iox_seg_mtty_0", XTTY_BASE + iob0_base, XTTY_SIZE, |
---|
[717] | 599 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
[695] | 600 | maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE, |
---|
[717] | 601 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
[695] | 602 | maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE, |
---|
[717] | 603 | IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
[695] | 604 | maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE, |
---|
[717] | 605 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
[695] | 606 | maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE, |
---|
[717] | 607 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 608 | maptab_iox.add(Segment("iox_seg_xpic_0", XPIC_BASE + iob0_base, XPIC_SIZE, |
---|
| 609 | IntTab(0, IOX_XPIC_TGT_ID), false)); |
---|
[450] | 610 | |
---|
[717] | 611 | if (not is_mono_cluster) { |
---|
| 612 | uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
| 613 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
| 614 | |
---|
| 615 | maptab_iox.add(Segment("iox_seg_mtty_1", XTTY_BASE + iob1_base, |
---|
| 616 | XTTY_SIZE, IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 617 | maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, |
---|
| 618 | FBUF_SIZE, IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
| 619 | maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, |
---|
| 620 | BDEV_SIZE, IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
| 621 | maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, |
---|
| 622 | MNIC_SIZE, IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 623 | maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, |
---|
| 624 | CDMA_SIZE, IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 625 | maptab_iox.add(Segment("iox_seg_xpic_1", XPIC_BASE + iob1_base, |
---|
| 626 | XPIC_SIZE, IntTab(0, IOX_XPIC_TGT_ID), false)); |
---|
| 627 | } |
---|
| 628 | |
---|
| 629 | /////////////////////////////////////////////////////////////////////////// |
---|
| 630 | // - For external DMA peripherals, each physical RAM and replicated |
---|
| 631 | // XICU can be accessed through IOB0, or through IOB1 depending on address |
---|
| 632 | // bit A[32] (0 => IOB0, 1 => IOB1). |
---|
| 633 | // |
---|
| 634 | // NOTE: the special attribute in the XICU segments is used by the IOB to |
---|
| 635 | // route commands through the INT network. The commands on not special |
---|
| 636 | // segments (RAM) are routed by the IOB through the RAM network |
---|
| 637 | // |
---|
| 638 | // NOTE: The IOX interconnect is implemented as a local interconnect because |
---|
| 639 | // the global bits need to be dropped, but no locality check is |
---|
| 640 | // performed |
---|
| 641 | /////////////////////////////////////////////////////////////////////////// |
---|
| 642 | |
---|
[695] | 643 | for (size_t x = 0; x < x_size; x++) { |
---|
| 644 | for (size_t y = 0; y < y_size ; y++) { |
---|
[717] | 645 | const bool special = true; |
---|
| 646 | const bool cacheable = true; |
---|
| 647 | |
---|
| 648 | const uint64_t offset = static_cast<uint64_t>(cluster(x,y)) |
---|
[695] | 649 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[450] | 650 | |
---|
[717] | 651 | const uint64_t xicu_base = XICU_BASE + offset; |
---|
| 652 | if ( (y & 0x1) == 0 ) { |
---|
| 653 | // segments mapped to IOB0 |
---|
| 654 | std::ostringstream sxcu0; |
---|
| 655 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
---|
| 656 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, XICU_SIZE, |
---|
| 657 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, special)); |
---|
| 658 | |
---|
| 659 | std::ostringstream sram0; |
---|
| 660 | sram0 << "iox_seg_ram0_" << x << "_" << y; |
---|
| 661 | maptab_iox.add(Segment(sram0.str(), offset, XICU_BASE, |
---|
| 662 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not special)); |
---|
| 663 | } else { |
---|
| 664 | // segments mapped to IOB1 |
---|
| 665 | std::ostringstream sxcu1; |
---|
| 666 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
---|
| 667 | maptab_iox.add(Segment(sxcu1.str(), xicu_base | (1ULL<<32), XICU_SIZE, |
---|
| 668 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, special)); |
---|
| 669 | |
---|
| 670 | std::ostringstream sram1; |
---|
| 671 | sram1 << "iox_seg_ram1_" << x << "_" << y; |
---|
| 672 | maptab_iox.add(Segment(sram1.str(), offset | (1ULL<<32), XICU_BASE, |
---|
| 673 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not special)); |
---|
[695] | 674 | } |
---|
| 675 | } |
---|
| 676 | } |
---|
[450] | 677 | |
---|
[695] | 678 | // This define the mapping between the initiators (identified by the SRCID) |
---|
| 679 | // and the port index on the IOX local interconnect. |
---|
[450] | 680 | |
---|
[717] | 681 | maptab_iox.srcid_map(IntTab(0, CDMA_LOCAL_SRCID), |
---|
| 682 | IntTab(0, IOX_CDMA_INI_ID)); |
---|
| 683 | maptab_iox.srcid_map(IntTab(0, BDEV_LOCAL_SRCID), |
---|
| 684 | IntTab(0, IOX_BDEV_INI_ID)); |
---|
| 685 | maptab_iox.srcid_map(IntTab(0, XPIC_LOCAL_SRCID), |
---|
| 686 | IntTab(0, IOX_XPIC_INI_ID)); |
---|
| 687 | maptab_iox.srcid_map(IntTab(0, IOX_IOB0_INI_ID), |
---|
| 688 | IntTab(0, IOX_IOB0_INI_ID)); |
---|
[450] | 689 | |
---|
[717] | 690 | if (not is_mono_cluster) { |
---|
| 691 | maptab_iox.srcid_map(IntTab(0, IOX_IOB1_INI_ID), |
---|
| 692 | IntTab(0, IOX_IOB1_INI_ID)); |
---|
[695] | 693 | } |
---|
[450] | 694 | |
---|
[695] | 695 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
[450] | 696 | |
---|
[695] | 697 | //////////////////// |
---|
| 698 | // Signals |
---|
| 699 | //////////////////// |
---|
[450] | 700 | |
---|
[695] | 701 | sc_clock signal_clk("clk"); |
---|
| 702 | sc_signal<bool> signal_resetn("resetn"); |
---|
[450] | 703 | |
---|
[695] | 704 | sc_signal<bool> signal_irq_false; |
---|
| 705 | sc_signal<bool> signal_irq_bdev; |
---|
| 706 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
| 707 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
| 708 | sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS]; |
---|
| 709 | sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2]; |
---|
[450] | 710 | |
---|
[695] | 711 | // DSPIN signals for loopback in cluster_iob0 & cluster_iob1 |
---|
| 712 | DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback; |
---|
| 713 | DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback; |
---|
| 714 | DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback; |
---|
| 715 | DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback; |
---|
[550] | 716 | |
---|
[695] | 717 | // VCI signals for IOX network |
---|
| 718 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
| 719 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
| 720 | VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); |
---|
| 721 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
[717] | 722 | VciSignals<vci_param_ext> signal_vci_ini_xpic("signal_vci_ini_xpic"); |
---|
[450] | 723 | |
---|
[695] | 724 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
| 725 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
| 726 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 727 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 728 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 729 | VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); |
---|
| 730 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
[717] | 731 | VciSignals<vci_param_ext> signal_vci_tgt_xpic("signal_vci_tgt_xpic"); |
---|
[450] | 732 | |
---|
[648] | 733 | // Horizontal inter-clusters INT network DSPIN |
---|
[450] | 734 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = |
---|
[648] | 735 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 736 | "signal_dspin_int_cmd_h_inc", x_size-1, y_size, 3); |
---|
[450] | 737 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = |
---|
[648] | 738 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 739 | "signal_dspin_int_cmd_h_dec", x_size-1, y_size, 3); |
---|
[450] | 740 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = |
---|
[648] | 741 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 742 | "signal_dspin_int_rsp_h_inc", x_size-1, y_size, 2); |
---|
[450] | 743 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = |
---|
[648] | 744 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 745 | "signal_dspin_int_rsp_h_dec", x_size-1, y_size, 2); |
---|
[450] | 746 | |
---|
| 747 | // Vertical inter-clusters INT network DSPIN |
---|
| 748 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = |
---|
[648] | 749 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 750 | "signal_dspin_int_cmd_v_inc", x_size, y_size-1, 3); |
---|
[450] | 751 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = |
---|
[648] | 752 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 753 | "signal_dspin_int_cmd_v_dec", x_size, y_size-1, 3); |
---|
[450] | 754 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = |
---|
[648] | 755 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 756 | "signal_dspin_int_rsp_v_inc", x_size, y_size-1, 2); |
---|
[450] | 757 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = |
---|
[648] | 758 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 759 | "signal_dspin_int_rsp_v_dec", x_size, y_size-1, 2); |
---|
[450] | 760 | |
---|
[648] | 761 | // Mesh boundaries INT network DSPIN |
---|
[450] | 762 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = |
---|
[648] | 763 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 764 | "signal_dspin_false_int_cmd_in", x_size, y_size, 4, 3); |
---|
[450] | 765 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = |
---|
[648] | 766 | alloc_elems<DspinSignals<dspin_int_cmd_width> >( |
---|
| 767 | "signal_dspin_false_int_cmd_out", x_size, y_size, 4, 3); |
---|
[450] | 768 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = |
---|
[648] | 769 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 770 | "signal_dspin_false_int_rsp_in", x_size, y_size, 4, 2); |
---|
[450] | 771 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = |
---|
[648] | 772 | alloc_elems<DspinSignals<dspin_int_rsp_width> >( |
---|
| 773 | "signal_dspin_false_int_rsp_out", x_size, y_size, 4, 2); |
---|
[450] | 774 | |
---|
| 775 | |
---|
[648] | 776 | // Horizontal inter-clusters RAM network DSPIN |
---|
[450] | 777 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
[648] | 778 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 779 | "signal_dspin_ram_cmd_h_inc", x_size-1, y_size); |
---|
[450] | 780 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
[648] | 781 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 782 | "signal_dspin_ram_cmd_h_dec", x_size-1, y_size); |
---|
[450] | 783 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
[648] | 784 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 785 | "signal_dspin_ram_rsp_h_inc", x_size-1, y_size); |
---|
[450] | 786 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
[648] | 787 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 788 | "signal_dspin_ram_rsp_h_dec", x_size-1, y_size); |
---|
[450] | 789 | |
---|
| 790 | // Vertical inter-clusters RAM network DSPIN |
---|
| 791 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
[648] | 792 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 793 | "signal_dspin_ram_cmd_v_inc", x_size, y_size-1); |
---|
[450] | 794 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
[648] | 795 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 796 | "signal_dspin_ram_cmd_v_dec", x_size, y_size-1); |
---|
[450] | 797 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
[648] | 798 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 799 | "signal_dspin_ram_rsp_v_inc", x_size, y_size-1); |
---|
[450] | 800 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
[648] | 801 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 802 | "signal_dspin_ram_rsp_v_dec", x_size, y_size-1); |
---|
[450] | 803 | |
---|
[648] | 804 | // Mesh boundaries RAM network DSPIN |
---|
[450] | 805 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
[648] | 806 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 807 | "signal_dspin_false_ram_cmd_in", x_size, y_size, 4); |
---|
[450] | 808 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
[648] | 809 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >( |
---|
| 810 | "signal_dspin_false_ram_cmd_out", x_size, y_size, 4); |
---|
[450] | 811 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
[648] | 812 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 813 | "signal_dspin_false_ram_rsp_in", x_size, y_size, 4); |
---|
[450] | 814 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
[648] | 815 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >( |
---|
| 816 | "signal_dspin_false_ram_rsp_out", x_size, y_size, 4); |
---|
[450] | 817 | |
---|
| 818 | //////////////////////////// |
---|
[648] | 819 | // Loader |
---|
[450] | 820 | //////////////////////////// |
---|
| 821 | |
---|
| 822 | soclib::common::Loader loader(soft_name); |
---|
| 823 | |
---|
| 824 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 825 | proc_iss::set_loader(loader); |
---|
| 826 | |
---|
| 827 | //////////////////////////////////////// |
---|
| 828 | // Instanciated Hardware Components |
---|
| 829 | //////////////////////////////////////// |
---|
| 830 | |
---|
[648] | 831 | std::cout << std::endl << "External Bus and Peripherals" << std::endl |
---|
[695] | 832 | << std::endl; |
---|
[450] | 833 | |
---|
[717] | 834 | const size_t nb_iox_initiators = (not is_mono_cluster) ? 5 : 4; |
---|
| 835 | const size_t nb_iox_targets = (not is_mono_cluster) ? 8 : 7; |
---|
| 836 | |
---|
[450] | 837 | // IOX network |
---|
| 838 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
[648] | 839 | iox_network = new VciIoxNetwork<vci_param_ext>("iox_network", |
---|
[695] | 840 | maptab_iox, |
---|
[717] | 841 | nb_iox_targets, // number of targets |
---|
| 842 | nb_iox_initiators ); // number of initiators |
---|
[658] | 843 | |
---|
[450] | 844 | // Network Controller |
---|
[550] | 845 | VciMultiNic<vci_param_ext>* mnic; |
---|
[648] | 846 | mnic = new VciMultiNic<vci_param_ext>("mnic", |
---|
[695] | 847 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
| 848 | maptab_iox, |
---|
| 849 | NB_NIC_CHANNELS, |
---|
| 850 | 0, // mac_4 address |
---|
| 851 | 0, // mac_2 address |
---|
| 852 | nic_rx_name, |
---|
| 853 | nic_tx_name); |
---|
[450] | 854 | |
---|
| 855 | // Frame Buffer |
---|
[550] | 856 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
[648] | 857 | fbuf = new VciFrameBuffer<vci_param_ext>("fbuf", |
---|
[695] | 858 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
| 859 | maptab_iox, |
---|
| 860 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
[450] | 861 | |
---|
| 862 | // Block Device |
---|
[550] | 863 | // for AHCI |
---|
| 864 | // std::vector<std::string> filenames; |
---|
[648] | 865 | // filenames.push_back(disk_name); // one single disk |
---|
[550] | 866 | VciBlockDeviceTsar<vci_param_ext>* bdev; |
---|
[648] | 867 | bdev = new VciBlockDeviceTsar<vci_param_ext>("bdev", |
---|
[695] | 868 | maptab_iox, |
---|
| 869 | IntTab(0, BDEV_LOCAL_SRCID), |
---|
| 870 | IntTab(0, IOX_BDEV_TGT_ID), |
---|
| 871 | disk_name, |
---|
| 872 | block_size, |
---|
| 873 | 64, // burst size (bytes) |
---|
| 874 | 0 ); // disk latency |
---|
[450] | 875 | |
---|
| 876 | // Chained Buffer DMA controller |
---|
[550] | 877 | VciChbufDma<vci_param_ext>* cdma; |
---|
[648] | 878 | cdma = new VciChbufDma<vci_param_ext>("cdma", |
---|
[695] | 879 | maptab_iox, |
---|
| 880 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
| 881 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
| 882 | 64, // burst size (bytes) |
---|
[717] | 883 | NB_CMA_CHANNELS); |
---|
| 884 | |
---|
[450] | 885 | // Multi-TTY controller |
---|
| 886 | std::vector<std::string> vect_names; |
---|
[695] | 887 | for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) |
---|
[450] | 888 | { |
---|
| 889 | std::ostringstream term_name; |
---|
[695] | 890 | term_name << "mtty_iox_" << tid; |
---|
[450] | 891 | vect_names.push_back(term_name.str().c_str()); |
---|
| 892 | } |
---|
[550] | 893 | VciMultiTty<vci_param_ext>* mtty; |
---|
[648] | 894 | mtty = new VciMultiTty<vci_param_ext>("mtty_iox", |
---|
[695] | 895 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
| 896 | maptab_iox, |
---|
| 897 | vect_names); |
---|
| 898 | |
---|
[717] | 899 | // IOPIC |
---|
| 900 | VciIopic<vci_param_ext>* xpic; |
---|
| 901 | xpic = new VciIopic<vci_param_ext>( "xpic", |
---|
| 902 | maptab_iox, |
---|
| 903 | IntTab(0, XPIC_LOCAL_SRCID), |
---|
| 904 | IntTab(0, IOX_XPIC_TGT_ID), |
---|
| 905 | 32 ); // number of input HWI |
---|
| 906 | |
---|
| 907 | |
---|
[648] | 908 | TsarIobClusterType* clusters[x_size][y_size]; |
---|
[450] | 909 | |
---|
| 910 | #if USE_OPENMP |
---|
| 911 | #pragma omp parallel |
---|
[695] | 912 | { |
---|
[450] | 913 | #pragma omp for |
---|
| 914 | #endif |
---|
[648] | 915 | |
---|
[695] | 916 | for(size_t i = 0; i < (x_size * y_size); i++) { |
---|
| 917 | size_t x = i / y_size; |
---|
| 918 | size_t y = i % y_size; |
---|
[450] | 919 | |
---|
| 920 | #if USE_OPENMP |
---|
| 921 | #pragma omp critical |
---|
[695] | 922 | { |
---|
[450] | 923 | #endif |
---|
| 924 | std::cout << std::endl; |
---|
| 925 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
| 926 | std::cout << std::endl; |
---|
| 927 | |
---|
| 928 | std::ostringstream sc; |
---|
| 929 | sc << "cluster_" << x << "_" << y; |
---|
| 930 | |
---|
[717] | 931 | bool memc_debug = (cluster(x,y) == debug_memc_id); |
---|
| 932 | bool proc_debug = (cluster(x,y) == (debug_proc_id / NB_PROCS)); |
---|
[450] | 933 | |
---|
[717] | 934 | bool is_io0 = (cluster(x,y) == cluster_iob0); |
---|
| 935 | bool is_io1 = (cluster(x,y) == cluster_iob1); |
---|
| 936 | bool is_io = is_io0 || is_io1; |
---|
| 937 | |
---|
| 938 | IntTab iox_iob_tgtid = |
---|
| 939 | IntTab(0, is_io0 ? IOX_IOB0_TGT_ID : IOX_IOB1_TGT_ID); |
---|
| 940 | IntTab iox_iob_srcid = |
---|
| 941 | IntTab(0, is_io0 ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID); |
---|
| 942 | |
---|
[648] | 943 | TsarIobClusterType::ClusterParams params = { |
---|
| 944 | .insname = sc.str().c_str(), |
---|
[695] | 945 | |
---|
[648] | 946 | .x_id = x, |
---|
| 947 | .y_id = y, |
---|
[695] | 948 | |
---|
[648] | 949 | .mt_int = maptab_int, |
---|
| 950 | .mt_ext = maptab_ram, |
---|
| 951 | .mt_iox = maptab_iox, |
---|
[695] | 952 | |
---|
[717] | 953 | .is_io = is_io, |
---|
| 954 | .iox_iob_tgtid = iox_iob_tgtid, |
---|
| 955 | .iox_iob_srcid = iox_iob_srcid, |
---|
| 956 | |
---|
[648] | 957 | .memc_ways = MEMC_WAYS, |
---|
| 958 | .memc_sets = MEMC_SETS, |
---|
| 959 | .l1_i_ways = L1_IWAYS, |
---|
| 960 | .l1_i_sets = L1_ISETS, |
---|
| 961 | .l1_d_ways = L1_DWAYS, |
---|
| 962 | .l1_d_sets = L1_DSETS, |
---|
| 963 | .xram_latency = XRAM_LATENCY, |
---|
[695] | 964 | |
---|
[648] | 965 | .loader = loader, |
---|
[695] | 966 | |
---|
[717] | 967 | .distboot = distboot, |
---|
| 968 | |
---|
[648] | 969 | .frozen_cycles = frozen_cycles, |
---|
| 970 | .debug_start_cycle = debug_from, |
---|
[717] | 971 | .memc_debug_ok = memc_debug, |
---|
| 972 | .proc_debug_ok = proc_debug, |
---|
| 973 | .iob_debug_ok = debug_iob |
---|
[648] | 974 | }; |
---|
[450] | 975 | |
---|
[648] | 976 | clusters[x][y] = new TsarIobClusterType(params); |
---|
[450] | 977 | |
---|
| 978 | #if USE_OPENMP |
---|
[695] | 979 | } // end critical |
---|
[450] | 980 | #endif |
---|
[695] | 981 | } // end for |
---|
[450] | 982 | #if USE_OPENMP |
---|
[695] | 983 | } |
---|
[450] | 984 | #endif |
---|
| 985 | |
---|
[695] | 986 | std::cout << std::endl; |
---|
[450] | 987 | |
---|
[695] | 988 | /////////////////////////////////////////////////////////////////////////// |
---|
| 989 | // Net-list |
---|
| 990 | /////////////////////////////////////////////////////////////////////////// |
---|
[450] | 991 | |
---|
[695] | 992 | // IOX network connexion |
---|
| 993 | iox_network->p_clk (signal_clk); |
---|
| 994 | iox_network->p_resetn (signal_resetn); |
---|
| 995 | iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); |
---|
| 996 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
[717] | 997 | iox_network->p_to_ini[IOX_XPIC_INI_ID] (signal_vci_ini_xpic); |
---|
| 998 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
[695] | 999 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
| 1000 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
| 1001 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
| 1002 | iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); |
---|
| 1003 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
[717] | 1004 | iox_network->p_to_tgt[IOX_XPIC_TGT_ID] (signal_vci_tgt_xpic); |
---|
| 1005 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
[450] | 1006 | |
---|
[717] | 1007 | if (not is_mono_cluster) { |
---|
| 1008 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
| 1009 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
| 1010 | } |
---|
| 1011 | |
---|
[695] | 1012 | // BDEV connexion |
---|
[717] | 1013 | bdev->p_clk (signal_clk); |
---|
| 1014 | bdev->p_resetn (signal_resetn); |
---|
| 1015 | bdev->p_irq (signal_irq_bdev); |
---|
[695] | 1016 | bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
| 1017 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
[450] | 1018 | |
---|
[695] | 1019 | std::cout << " - BDEV connected" << std::endl; |
---|
[450] | 1020 | |
---|
[695] | 1021 | // FBUF connexion |
---|
| 1022 | fbuf->p_clk (signal_clk); |
---|
| 1023 | fbuf->p_resetn (signal_resetn); |
---|
| 1024 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
[450] | 1025 | |
---|
[695] | 1026 | std::cout << " - FBUF connected" << std::endl; |
---|
[450] | 1027 | |
---|
[695] | 1028 | // MNIC connexion |
---|
| 1029 | mnic->p_clk (signal_clk); |
---|
| 1030 | mnic->p_resetn (signal_resetn); |
---|
| 1031 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
| 1032 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
| 1033 | { |
---|
| 1034 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 1035 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
| 1036 | } |
---|
[450] | 1037 | |
---|
[695] | 1038 | std::cout << " - MNIC connected" << std::endl; |
---|
[450] | 1039 | |
---|
[695] | 1040 | // MTTY connexion |
---|
| 1041 | mtty->p_clk (signal_clk); |
---|
| 1042 | mtty->p_resetn (signal_resetn); |
---|
| 1043 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
| 1044 | for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) { |
---|
| 1045 | mtty->p_irq[i] (signal_irq_mtty[i]); |
---|
| 1046 | } |
---|
[450] | 1047 | |
---|
[695] | 1048 | std::cout << " - MTTY connected" << std::endl; |
---|
[450] | 1049 | |
---|
[695] | 1050 | // CDMA connexion |
---|
| 1051 | cdma->p_clk (signal_clk); |
---|
| 1052 | cdma->p_resetn (signal_resetn); |
---|
| 1053 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
| 1054 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
[717] | 1055 | for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++) { |
---|
[695] | 1056 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
| 1057 | } |
---|
[450] | 1058 | |
---|
[695] | 1059 | std::cout << " - CDMA connected" << std::endl; |
---|
[450] | 1060 | |
---|
[717] | 1061 | // XPIC connexion |
---|
| 1062 | xpic->p_clk (signal_clk); |
---|
| 1063 | xpic->p_resetn (signal_resetn); |
---|
| 1064 | xpic->p_vci_target (signal_vci_tgt_xpic); |
---|
| 1065 | xpic->p_vci_initiator (signal_vci_ini_xpic); |
---|
| 1066 | for ( size_t i=0 ; i<32 ; i++) |
---|
| 1067 | { |
---|
| 1068 | if (i < NB_NIC_CHANNELS) xpic->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
| 1069 | else if (i < 2) xpic->p_hwi[i] (signal_irq_false); |
---|
| 1070 | else if (i < 2+NB_NIC_CHANNELS) xpic->p_hwi[i] (signal_irq_mnic_tx[i-2]); |
---|
| 1071 | else if (i < 4) xpic->p_hwi[i] (signal_irq_false); |
---|
| 1072 | else if (i < 4+NB_CMA_CHANNELS) xpic->p_hwi[i] (signal_irq_cdma[i-4]); |
---|
| 1073 | else if (i < 8) xpic->p_hwi[i] (signal_irq_false); |
---|
| 1074 | else if (i < 9) xpic->p_hwi[i] (signal_irq_bdev); |
---|
| 1075 | else if (i < 9+NB_TTY_CHANNELS) xpic->p_hwi[i] (signal_irq_mtty[i-9]); |
---|
| 1076 | else xpic->p_hwi[i] (signal_irq_false); |
---|
[695] | 1077 | } |
---|
[450] | 1078 | |
---|
[717] | 1079 | std::cout << " - XPIC connected" << std::endl; |
---|
| 1080 | |
---|
[695] | 1081 | // IOB0 cluster connexion to IOX network |
---|
| 1082 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
| 1083 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
[450] | 1084 | |
---|
[695] | 1085 | // IOB1 cluster connexion to IOX network |
---|
[717] | 1086 | if (not is_mono_cluster) { |
---|
| 1087 | (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
| 1088 | (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
| 1089 | } |
---|
[450] | 1090 | |
---|
[695] | 1091 | // All clusters Clock & RESET connexions |
---|
| 1092 | for ( size_t x = 0; x < (x_size); x++ ) { |
---|
| 1093 | for (size_t y = 0; y < y_size; y++) { |
---|
| 1094 | clusters[x][y]->p_clk (signal_clk); |
---|
| 1095 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 1096 | } |
---|
| 1097 | } |
---|
[450] | 1098 | |
---|
[648] | 1099 | const int& NORTH = VirtualDspinRouter<dspin_int_cmd_width>::NORTH; |
---|
| 1100 | const int& SOUTH = VirtualDspinRouter<dspin_int_cmd_width>::SOUTH; |
---|
| 1101 | const int& EAST = VirtualDspinRouter<dspin_int_cmd_width>::EAST; |
---|
| 1102 | const int& WEST = VirtualDspinRouter<dspin_int_cmd_width>::WEST; |
---|
| 1103 | |
---|
[450] | 1104 | // Inter Clusters horizontal connections |
---|
[695] | 1105 | if (x_size > 1) { |
---|
| 1106 | for (size_t x = 0; x < (x_size-1); x++) { |
---|
| 1107 | for (size_t y = 0; y < y_size; y++) { |
---|
| 1108 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1109 | clusters[x][y]->p_dspin_int_cmd_out[EAST][k]( |
---|
| 1110 | signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1111 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k]( |
---|
| 1112 | signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1113 | clusters[x][y]->p_dspin_int_cmd_in[EAST][k]( |
---|
| 1114 | signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1115 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k]( |
---|
| 1116 | signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
[468] | 1117 | } |
---|
| 1118 | |
---|
[695] | 1119 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1120 | clusters[x][y]->p_dspin_int_rsp_out[EAST][k]( |
---|
| 1121 | signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1122 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k]( |
---|
| 1123 | signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1124 | clusters[x][y]->p_dspin_int_rsp_in[EAST][k]( |
---|
| 1125 | signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1126 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k]( |
---|
| 1127 | signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
[450] | 1128 | } |
---|
| 1129 | |
---|
[648] | 1130 | clusters[x][y]->p_dspin_ram_cmd_out[EAST]( |
---|
| 1131 | signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1132 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST]( |
---|
| 1133 | signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1134 | clusters[x][y]->p_dspin_ram_cmd_in[EAST]( |
---|
| 1135 | signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1136 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST]( |
---|
| 1137 | signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1138 | clusters[x][y]->p_dspin_ram_rsp_out[EAST]( |
---|
| 1139 | signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1140 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST]( |
---|
| 1141 | signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1142 | clusters[x][y]->p_dspin_ram_rsp_in[EAST]( |
---|
| 1143 | signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1144 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST]( |
---|
| 1145 | signal_dspin_ram_rsp_h_dec[x][y]); |
---|
[450] | 1146 | } |
---|
| 1147 | } |
---|
| 1148 | } |
---|
| 1149 | |
---|
[648] | 1150 | std::cout << std::endl << "Horizontal connections established" |
---|
[695] | 1151 | << std::endl; |
---|
[450] | 1152 | |
---|
| 1153 | // Inter Clusters vertical connections |
---|
[695] | 1154 | if (y_size > 1) { |
---|
| 1155 | for (size_t y = 0; y < (y_size-1); y++) { |
---|
| 1156 | for (size_t x = 0; x < x_size; x++) { |
---|
| 1157 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1158 | clusters[x][y]->p_dspin_int_cmd_out[NORTH][k]( |
---|
| 1159 | signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1160 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k]( |
---|
| 1161 | signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1162 | clusters[x][y]->p_dspin_int_cmd_in[NORTH][k]( |
---|
| 1163 | signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1164 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k]( |
---|
| 1165 | signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
[468] | 1166 | } |
---|
| 1167 | |
---|
[695] | 1168 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1169 | clusters[x][y]->p_dspin_int_rsp_out[NORTH][k]( |
---|
| 1170 | signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1171 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k]( |
---|
| 1172 | signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1173 | clusters[x][y]->p_dspin_int_rsp_in[NORTH][k]( |
---|
| 1174 | signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1175 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k]( |
---|
| 1176 | signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
[450] | 1177 | } |
---|
| 1178 | |
---|
[648] | 1179 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH]( |
---|
| 1180 | signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1181 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH]( |
---|
| 1182 | signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1183 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH]( |
---|
| 1184 | signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1185 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH]( |
---|
| 1186 | signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1187 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH]( |
---|
| 1188 | signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1189 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH]( |
---|
| 1190 | signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1191 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH]( |
---|
| 1192 | signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1193 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH]( |
---|
| 1194 | signal_dspin_ram_rsp_v_dec[x][y]); |
---|
[450] | 1195 | } |
---|
| 1196 | } |
---|
| 1197 | } |
---|
| 1198 | |
---|
| 1199 | std::cout << "Vertical connections established" << std::endl; |
---|
| 1200 | |
---|
| 1201 | // East & West boundary cluster connections |
---|
[695] | 1202 | for (size_t y = 0; y < y_size; y++) { |
---|
[717] | 1203 | // L1-L2 cmd network boundary connections |
---|
[695] | 1204 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1205 | clusters[0][y]->p_dspin_int_cmd_in[WEST][k]( |
---|
| 1206 | signal_dspin_false_int_cmd_in[0][y][WEST][k]); |
---|
| 1207 | clusters[0][y]->p_dspin_int_cmd_out[WEST][k]( |
---|
| 1208 | signal_dspin_false_int_cmd_out[0][y][WEST][k]); |
---|
| 1209 | clusters[x_size-1][y]->p_dspin_int_cmd_in[EAST][k]( |
---|
| 1210 | signal_dspin_false_int_cmd_in[x_size-1][y][EAST][k]); |
---|
| 1211 | clusters[x_size-1][y]->p_dspin_int_cmd_out[EAST][k]( |
---|
| 1212 | signal_dspin_false_int_cmd_out[x_size-1][y][EAST][k]); |
---|
[468] | 1213 | } |
---|
| 1214 | |
---|
[717] | 1215 | // L1-L2 rsp network boundary connections |
---|
[695] | 1216 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1217 | clusters[0][y]->p_dspin_int_rsp_in[WEST][k]( |
---|
| 1218 | signal_dspin_false_int_rsp_in[0][y][WEST][k]); |
---|
| 1219 | clusters[0][y]->p_dspin_int_rsp_out[WEST][k]( |
---|
| 1220 | signal_dspin_false_int_rsp_out[0][y][WEST][k]); |
---|
| 1221 | clusters[x_size-1][y]->p_dspin_int_rsp_in[EAST][k]( |
---|
| 1222 | signal_dspin_false_int_rsp_in[x_size-1][y][EAST][k]); |
---|
| 1223 | clusters[x_size-1][y]->p_dspin_int_rsp_out[EAST][k]( |
---|
| 1224 | signal_dspin_false_int_rsp_out[x_size-1][y][EAST][k]); |
---|
[450] | 1225 | } |
---|
| 1226 | |
---|
[717] | 1227 | // L2-XRAM cmd network boundary connections |
---|
| 1228 | clusters[0][y]->p_dspin_ram_cmd_in[WEST]( |
---|
| 1229 | signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
| 1230 | clusters[0][y]->p_dspin_ram_cmd_out[WEST]( |
---|
| 1231 | signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
| 1232 | clusters[x_size-1][y]->p_dspin_ram_cmd_in[EAST]( |
---|
| 1233 | signal_dspin_false_ram_cmd_in[x_size-1][y][EAST]); |
---|
| 1234 | clusters[x_size-1][y]->p_dspin_ram_cmd_out[EAST]( |
---|
| 1235 | signal_dspin_false_ram_cmd_out[x_size-1][y][EAST]); |
---|
[550] | 1236 | |
---|
[717] | 1237 | // L2-XRAM rsp network boundary connections |
---|
| 1238 | clusters[0][y]->p_dspin_ram_rsp_in[WEST]( |
---|
| 1239 | signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
| 1240 | clusters[0][y]->p_dspin_ram_rsp_out[WEST]( |
---|
| 1241 | signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
| 1242 | clusters[x_size-1][y]->p_dspin_ram_rsp_in[EAST]( |
---|
| 1243 | signal_dspin_false_ram_rsp_in[x_size-1][y][EAST]); |
---|
| 1244 | clusters[x_size-1][y]->p_dspin_ram_rsp_out[EAST]( |
---|
| 1245 | signal_dspin_false_ram_rsp_out[x_size-1][y][EAST]); |
---|
[450] | 1246 | } |
---|
| 1247 | |
---|
| 1248 | std::cout << "East & West boundaries established" << std::endl; |
---|
| 1249 | |
---|
| 1250 | // North & South boundary clusters connections |
---|
[695] | 1251 | for (size_t x = 0; x < x_size; x++) { |
---|
| 1252 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1253 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k]( |
---|
| 1254 | signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); |
---|
| 1255 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k]( |
---|
| 1256 | signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); |
---|
| 1257 | clusters[x][y_size-1]->p_dspin_int_cmd_in[NORTH][k]( |
---|
| 1258 | signal_dspin_false_int_cmd_in[x][y_size-1][NORTH][k]); |
---|
| 1259 | clusters[x][y_size-1]->p_dspin_int_cmd_out[NORTH][k]( |
---|
| 1260 | signal_dspin_false_int_cmd_out[x][y_size-1][NORTH][k]); |
---|
[468] | 1261 | } |
---|
| 1262 | |
---|
[695] | 1263 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1264 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k]( |
---|
| 1265 | signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); |
---|
| 1266 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k]( |
---|
| 1267 | signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); |
---|
| 1268 | clusters[x][y_size-1]->p_dspin_int_rsp_in[NORTH][k]( |
---|
| 1269 | signal_dspin_false_int_rsp_in[x][y_size-1][NORTH][k]); |
---|
| 1270 | clusters[x][y_size-1]->p_dspin_int_rsp_out[NORTH][k]( |
---|
| 1271 | signal_dspin_false_int_rsp_out[x][y_size-1][NORTH][k]); |
---|
[450] | 1272 | } |
---|
| 1273 | |
---|
[648] | 1274 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH]( |
---|
| 1275 | signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
| 1276 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH]( |
---|
| 1277 | signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
| 1278 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH]( |
---|
| 1279 | signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
| 1280 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH]( |
---|
| 1281 | signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
[450] | 1282 | |
---|
[648] | 1283 | clusters[x][y_size-1]->p_dspin_ram_cmd_in[NORTH]( |
---|
| 1284 | signal_dspin_false_ram_cmd_in[x][y_size-1][NORTH]); |
---|
| 1285 | clusters[x][y_size-1]->p_dspin_ram_cmd_out[NORTH]( |
---|
| 1286 | signal_dspin_false_ram_cmd_out[x][y_size-1][NORTH]); |
---|
| 1287 | clusters[x][y_size-1]->p_dspin_ram_rsp_in[NORTH]( |
---|
| 1288 | signal_dspin_false_ram_rsp_in[x][y_size-1][NORTH]); |
---|
| 1289 | clusters[x][y_size-1]->p_dspin_ram_rsp_out[NORTH]( |
---|
| 1290 | signal_dspin_false_ram_rsp_out[x][y_size-1][NORTH]); |
---|
[450] | 1291 | } |
---|
| 1292 | |
---|
[648] | 1293 | std::cout << "North & South boundaries established" << std::endl |
---|
[695] | 1294 | << std::endl; |
---|
[450] | 1295 | |
---|
| 1296 | //////////////////////////////////////////////////////// |
---|
| 1297 | // Simulation |
---|
| 1298 | /////////////////////////////////////////////////////// |
---|
| 1299 | |
---|
| 1300 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
[584] | 1301 | |
---|
[450] | 1302 | signal_resetn = false; |
---|
[584] | 1303 | signal_irq_false = false; |
---|
| 1304 | |
---|
[450] | 1305 | // network boundaries signals |
---|
[695] | 1306 | for (size_t x = 0; x < x_size ; x++) { |
---|
| 1307 | for (size_t y = 0; y < y_size ; y++) { |
---|
| 1308 | for (size_t a = 0; a < 4; a++) { |
---|
| 1309 | for (size_t k = 0; k < 3; k++) { |
---|
[648] | 1310 | signal_dspin_false_int_cmd_in[x][y][a][k].write = false; |
---|
| 1311 | signal_dspin_false_int_cmd_in[x][y][a][k].read = true; |
---|
[468] | 1312 | signal_dspin_false_int_cmd_out[x][y][a][k].write = false; |
---|
[648] | 1313 | signal_dspin_false_int_cmd_out[x][y][a][k].read = true; |
---|
[468] | 1314 | } |
---|
| 1315 | |
---|
[695] | 1316 | for (size_t k = 0; k < 2; k++) { |
---|
[648] | 1317 | signal_dspin_false_int_rsp_in[x][y][a][k].write = false; |
---|
| 1318 | signal_dspin_false_int_rsp_in[x][y][a][k].read = true; |
---|
[468] | 1319 | signal_dspin_false_int_rsp_out[x][y][a][k].write = false; |
---|
[648] | 1320 | signal_dspin_false_int_rsp_out[x][y][a][k].read = true; |
---|
[450] | 1321 | } |
---|
| 1322 | |
---|
[648] | 1323 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
| 1324 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
[450] | 1325 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
[648] | 1326 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
[450] | 1327 | |
---|
[648] | 1328 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
| 1329 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
[450] | 1330 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
[648] | 1331 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
[450] | 1332 | } |
---|
| 1333 | } |
---|
| 1334 | } |
---|
| 1335 | |
---|
[695] | 1336 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1337 | signal_resetn = true; |
---|
[450] | 1338 | |
---|
[695] | 1339 | struct timeval t1, t2; |
---|
| 1340 | const uint64_t stats_period = 100000; |
---|
| 1341 | gettimeofday(&t1, NULL); |
---|
| 1342 | for (uint64_t n = 1; n < ncycles; n++) { |
---|
| 1343 | // stats display |
---|
| 1344 | if((n % stats_period) == 0) { |
---|
| 1345 | gettimeofday(&t2, NULL); |
---|
[450] | 1346 | |
---|
[695] | 1347 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000 + |
---|
| 1348 | (uint64_t) t1.tv_usec / 1000; |
---|
| 1349 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000 + |
---|
| 1350 | (uint64_t) t2.tv_usec / 1000; |
---|
| 1351 | double freq = (double) stats_period / (ms2 - ms1); |
---|
[607] | 1352 | |
---|
[695] | 1353 | std::cerr << "Platform Clock Frequency: " << freq << " Khz" |
---|
| 1354 | << std::endl; |
---|
[607] | 1355 | |
---|
[695] | 1356 | gettimeofday(&t1, NULL); |
---|
| 1357 | } |
---|
[450] | 1358 | |
---|
[695] | 1359 | if (debug_ok and (n > debug_from) and ((n % debug_period) == 0)) { |
---|
| 1360 | std::cout << " ***********************" |
---|
| 1361 | << " cycle " << std::dec << n |
---|
| 1362 | << " ***********************" |
---|
| 1363 | << std::endl; |
---|
[450] | 1364 | |
---|
[695] | 1365 | // trace proc[debug_proc_id] |
---|
| 1366 | if ( debug_proc_id != 0xFFFFFFFF ) { |
---|
| 1367 | size_t l = debug_proc_id % NB_PROCS ; |
---|
| 1368 | size_t cluster_xy = debug_proc_id / NB_PROCS ; |
---|
| 1369 | size_t x = cluster_xy >> Y_WIDTH; |
---|
| 1370 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
---|
[450] | 1371 | |
---|
[695] | 1372 | clusters[x][y]->proc[l]->print_trace(1); |
---|
[450] | 1373 | |
---|
[695] | 1374 | std::ostringstream proc_signame; |
---|
| 1375 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
| 1376 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace( |
---|
| 1377 | proc_signame.str()); |
---|
[584] | 1378 | |
---|
[695] | 1379 | clusters[x][y]->xicu->print_trace(l); |
---|
[584] | 1380 | |
---|
[695] | 1381 | std::ostringstream xicu_signame; |
---|
| 1382 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
| 1383 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace( |
---|
| 1384 | xicu_signame.str()); |
---|
| 1385 | |
---|
| 1386 | if( clusters[x][y]->signal_proc_it[l].read() ) { |
---|
| 1387 | std::cout << "### IRQ_PROC_" << std::dec |
---|
| 1388 | << x << "_" << y << "_" << l |
---|
| 1389 | << " ACTIVE" << std::endl; |
---|
[648] | 1390 | } |
---|
[695] | 1391 | } |
---|
[450] | 1392 | |
---|
[717] | 1393 | // trace RAM xbar (between MEMC and IOB) |
---|
| 1394 | // clusters[0][0]->ram_xbar_cmd->print_trace(); |
---|
| 1395 | // clusters[0][0]->ram_xbar_rsp->print_trace(); |
---|
| 1396 | // clusters[x_size-1][y_size-1]->ram_xbar_cmd->print_trace(); |
---|
| 1397 | // clusters[x_size-1][y_size-1]->ram_xbar_rsp->print_trace(); |
---|
| 1398 | |
---|
[695] | 1399 | // trace INT network |
---|
[717] | 1400 | // clusters[0][0]->int_xbar_d->print_trace(); |
---|
[450] | 1401 | |
---|
[717] | 1402 | // clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace( |
---|
| 1403 | // "[SIG] INT_CMD_L2G_D_0_0"); |
---|
| 1404 | // clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace( |
---|
| 1405 | // "[SIG] INT_RSP_G2L_D_0_0"); |
---|
[607] | 1406 | |
---|
[717] | 1407 | // clusters[0][0]->int_router_cmd->print_trace(0); |
---|
| 1408 | // clusters[0][0]->int_router_rsp->print_trace(0); |
---|
[450] | 1409 | |
---|
[695] | 1410 | // trace INT_CMD_D xbar and router in cluster 0_1 |
---|
[717] | 1411 | // clusters[0][1]->int_router_cmd->print_trace(0); |
---|
| 1412 | // clusters[0][1]->int_router_rsp->print_trace(0); |
---|
[648] | 1413 | |
---|
[717] | 1414 | // clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace( |
---|
| 1415 | // "[SIG] INT_CMD_G2L_D_0_0"); |
---|
| 1416 | // clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace( |
---|
| 1417 | // "[SIG] INT_RSP_L2G_D_0_0"); |
---|
[648] | 1418 | |
---|
[717] | 1419 | // clusters[0][1]->int_xbar_cmd_d->print_trace(); |
---|
[607] | 1420 | |
---|
[695] | 1421 | // trace memc[debug_memc_id] |
---|
| 1422 | if ( debug_memc_id != 0xFFFFFFFF ) { |
---|
| 1423 | size_t x = debug_memc_id >> Y_WIDTH; |
---|
| 1424 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
---|
[648] | 1425 | |
---|
[695] | 1426 | clusters[x][y]->memc->print_trace(0); |
---|
| 1427 | std::ostringstream smemc_tgt; |
---|
| 1428 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
| 1429 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace( |
---|
| 1430 | smemc_tgt.str()); |
---|
| 1431 | std::ostringstream smemc_ini; |
---|
| 1432 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
| 1433 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace( |
---|
| 1434 | smemc_ini.str()); |
---|
| 1435 | clusters[x][y]->xram->print_trace(); |
---|
| 1436 | std::ostringstream sxram_tgt; |
---|
| 1437 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1438 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace( |
---|
| 1439 | sxram_tgt.str()); |
---|
| 1440 | } |
---|
[450] | 1441 | |
---|
[695] | 1442 | // trace iob, iox and external peripherals |
---|
[717] | 1443 | //if ( debug_iob ) { |
---|
| 1444 | // clusters[0][0]->iob->print_trace(); |
---|
| 1445 | // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( |
---|
| 1446 | // "[SIG]IOB0_INT_TGT"); |
---|
| 1447 | // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( |
---|
| 1448 | // "[SIG]IOB0_INT_INI"); |
---|
| 1449 | // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( |
---|
| 1450 | // "[SIG]IOB0_RAM_INI"); |
---|
[648] | 1451 | |
---|
[717] | 1452 | // signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
| 1453 | // signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
[450] | 1454 | |
---|
[717] | 1455 | // cdma->print_trace(); |
---|
| 1456 | // signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); |
---|
| 1457 | // signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); |
---|
[450] | 1458 | |
---|
[717] | 1459 | // iox_network->print_trace(); |
---|
[450] | 1460 | |
---|
[717] | 1461 | // // interrupts |
---|
| 1462 | // if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED" |
---|
| 1463 | // << std::endl; |
---|
| 1464 | //} |
---|
[695] | 1465 | } |
---|
| 1466 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1467 | } |
---|
[450] | 1468 | |
---|
[648] | 1469 | delete iox_network; |
---|
| 1470 | delete mnic; |
---|
| 1471 | delete fbuf; |
---|
| 1472 | delete bdev; |
---|
| 1473 | delete cdma; |
---|
| 1474 | delete mtty; |
---|
[717] | 1475 | delete xpic; |
---|
[648] | 1476 | |
---|
[695] | 1477 | for(size_t x = 0; x < x_size; x++) { |
---|
| 1478 | for(size_t y = 0; y < y_size; y++) { |
---|
[648] | 1479 | delete clusters[x][y]; |
---|
| 1480 | } |
---|
| 1481 | } |
---|
| 1482 | return EXIT_SUCCESS; |
---|
[450] | 1483 | } |
---|
| 1484 | |
---|
[695] | 1485 | int sc_main (int argc, char *argv[]) { |
---|
[450] | 1486 | try { |
---|
| 1487 | return _main(argc, argv); |
---|
| 1488 | } catch (std::exception &e) { |
---|
| 1489 | std::cout << e.what() << std::endl; |
---|
| 1490 | } catch (...) { |
---|
| 1491 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1492 | throw; |
---|
| 1493 | } |
---|
| 1494 | return 1; |
---|
| 1495 | } |
---|
| 1496 | |
---|
| 1497 | |
---|
| 1498 | // Local Variables: |
---|
| 1499 | // tab-width: 3 |
---|
| 1500 | // c-basic-offset: 3 |
---|
| 1501 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1502 | // indent-tabs-mode: nil |
---|
| 1503 | // End: |
---|
| 1504 | |
---|
| 1505 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
| 1506 | |
---|