[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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| 9 | // These two clusters contain 6 extra components: |
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| 10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 11 | // - 3 vci_dspin_wrapper for the IOB. |
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| 12 | // - 2 dspin_local_crossbar for commands and responses. |
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| 13 | ////////////////////////////////////////////////////////////////////////////// |
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| 14 | |
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| 15 | #include "../include/tsar_iob_cluster.h" |
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| 16 | |
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| 17 | namespace soclib { namespace caba { |
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| 18 | |
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| 19 | ////////////////////////////////////////////////////////////////////////// |
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| 20 | // Constructor |
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| 21 | ////////////////////////////////////////////////////////////////////////// |
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| 22 | template<typename vci_param_int, |
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| 23 | typename vci_param_ext, |
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| 24 | size_t dspin_int_cmd_width, |
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| 25 | size_t dspin_int_rsp_width, |
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| 26 | size_t dspin_ram_cmd_width, |
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| 27 | size_t dspin_ram_rsp_width> |
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| 28 | TsarIobCluster<vci_param_int, |
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| 29 | vci_param_ext, |
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| 30 | dspin_int_cmd_width, |
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| 31 | dspin_int_rsp_width, |
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| 32 | dspin_ram_cmd_width, |
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| 33 | dspin_ram_rsp_width>::TsarIobCluster( |
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| 34 | ////////////////////////////////////////////////////////////////////////// |
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| 35 | sc_module_name insname, |
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| 36 | size_t nb_procs, |
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| 37 | size_t nb_dmas, |
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| 38 | size_t x_id, |
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| 39 | size_t y_id, |
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| 40 | size_t xmax, |
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| 41 | size_t ymax, |
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| 42 | |
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| 43 | const soclib::common::MappingTable &mt_int, |
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| 44 | const soclib::common::MappingTable &mt_ram, |
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| 45 | const soclib::common::MappingTable &mt_iox, |
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| 46 | |
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| 47 | size_t x_width, |
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| 48 | size_t y_width, |
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| 49 | size_t l_width, |
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| 50 | |
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| 51 | size_t memc_int_tgtid, |
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| 52 | size_t xicu_int_tgtid, |
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| 53 | size_t mdma_int_tgtid, |
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| 54 | size_t iobx_int_tgtid, |
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| 55 | |
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| 56 | size_t proc_int_srcid, |
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| 57 | size_t mdma_int_srcid, |
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| 58 | size_t iobx_int_srcid, |
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| 59 | |
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| 60 | size_t xram_ram_tgtid, |
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| 61 | |
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| 62 | size_t memc_ram_srcid, |
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| 63 | size_t iobx_ram_srcid, |
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| 64 | |
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| 65 | size_t memc_ways, |
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| 66 | size_t memc_sets, |
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| 67 | size_t l1_i_ways, |
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| 68 | size_t l1_i_sets, |
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| 69 | size_t l1_d_ways, |
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| 70 | size_t l1_d_sets, |
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| 71 | size_t xram_latency, |
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| 72 | |
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| 73 | const Loader &loader, |
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| 74 | |
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| 75 | uint32_t frozen_cycles, |
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| 76 | uint32_t debug_start_cycle, |
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| 77 | bool memc_debug_ok, |
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| 78 | bool proc_debug_ok, |
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| 79 | bool iob_debug_ok ) |
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| 80 | : soclib::caba::BaseModule(insname), |
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| 81 | p_clk("clk"), |
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| 82 | p_resetn("resetn") |
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| 83 | { |
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| 84 | assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); |
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| 85 | |
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| 86 | size_t cluster_id = x_id * ymax + y_id; |
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| 87 | size_t cluster_iob0 = 0; |
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| 88 | size_t cluster_iob1 = xmax*ymax-1; |
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| 89 | |
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| 90 | // Vectors of DSPIN ports for inter-cluster communications |
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[468] | 91 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 92 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 93 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 94 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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[450] | 95 | |
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| 96 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 97 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 98 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 99 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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| 100 | |
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| 101 | // VCI ports to IOB0 and IOB1 in cluster_iob0 and cluster_iob1 |
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| 102 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 103 | { |
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| 104 | p_vci_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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| 105 | p_vci_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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| 106 | } |
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| 107 | |
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| 108 | // IRQ ports in cluster_iob0 only |
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| 109 | if ( cluster_id == cluster_iob0 ) |
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| 110 | { |
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| 111 | for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_in<bool>; |
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| 112 | } |
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| 113 | |
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| 114 | ///////////////////////////////////////////////////////////////////////////// |
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| 115 | // Hardware components |
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| 116 | ///////////////////////////////////////////////////////////////////////////// |
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| 117 | |
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| 118 | //////////// PROCS |
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| 119 | for (size_t p = 0; p < nb_procs; p++) |
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| 120 | { |
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| 121 | std::ostringstream s_proc; |
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| 122 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 123 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 124 | dspin_int_cmd_width, |
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| 125 | dspin_int_rsp_width, |
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| 126 | GdbServer<Mips32ElIss> >( |
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| 127 | s_proc.str().c_str(), |
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| 128 | cluster_id*nb_procs + p, // GLOBAL PROC_ID |
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| 129 | mt_int, // Mapping Table INT network |
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| 130 | IntTab(cluster_id,p), // SRCID |
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| 131 | (cluster_id << l_width) + p, // CC_GLOBAL_ID |
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| 132 | 8, // ITLB ways |
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| 133 | 8, // ITLB sets |
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| 134 | 8, // DTLB ways |
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| 135 | 8, // DTLB sets |
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| 136 | l1_i_ways,l1_i_sets,16, // ICACHE size |
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| 137 | l1_d_ways,l1_d_sets,16, // DCACHE size |
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| 138 | 4, // WBUF nlines |
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| 139 | 4, // WBUF nwords |
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| 140 | x_width, |
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| 141 | y_width, |
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| 142 | frozen_cycles, // max frozen cycles |
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| 143 | debug_start_cycle, |
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| 144 | proc_debug_ok); |
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| 145 | |
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| 146 | std::ostringstream s_wi_proc; |
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| 147 | s_wi_proc << "proc_wi_" << x_id << "_" << y_id << "_" << p; |
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| 148 | proc_wi[p] = new VciDspinInitiatorWrapper<vci_param_int, |
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| 149 | dspin_int_cmd_width, |
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| 150 | dspin_int_rsp_width>( |
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| 151 | s_wi_proc.str().c_str(), |
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| 152 | x_width + y_width + l_width); |
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| 153 | } |
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| 154 | |
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| 155 | /////////// MEMC |
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| 156 | std::ostringstream s_memc; |
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| 157 | s_memc << "memc_" << x_id << "_" << y_id; |
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| 158 | memc = new VciMemCache<vci_param_int, |
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| 159 | vci_param_ext, |
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| 160 | dspin_int_rsp_width, |
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| 161 | dspin_int_cmd_width>( |
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| 162 | s_memc.str().c_str(), |
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| 163 | mt_int, // Mapping Table INT network |
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| 164 | mt_ram, // Mapping Table RAM network |
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| 165 | IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network |
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| 166 | IntTab(cluster_id, memc_int_tgtid), // TGTID INT network |
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| 167 | (cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID |
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| 168 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 169 | 3, // MAX NUMBER OF COPIES |
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| 170 | 4096, // HEAP SIZE |
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| 171 | 8, // TRANSACTION TABLE DEPTH |
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| 172 | 8, // UPDATE TABLE DEPTH |
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[468] | 173 | 8, // INVALIDATE TABLE DEPTH |
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[450] | 174 | debug_start_cycle, |
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| 175 | memc_debug_ok ); |
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| 176 | |
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| 177 | std::ostringstream s_wt_memc; |
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| 178 | s_wt_memc << "memc_wt_" << x_id << "_" << y_id; |
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| 179 | memc_int_wt = new VciDspinTargetWrapper<vci_param_int, |
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| 180 | dspin_int_cmd_width, |
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| 181 | dspin_int_rsp_width>( |
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| 182 | s_wt_memc.str().c_str(), |
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| 183 | x_width + y_width + l_width); |
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| 184 | |
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| 185 | std::ostringstream s_wi_memc; |
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| 186 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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| 187 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 188 | dspin_ram_cmd_width, |
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| 189 | dspin_ram_rsp_width>( |
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| 190 | s_wi_memc.str().c_str(), |
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| 191 | x_width + y_width + l_width); |
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| 192 | |
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| 193 | /////////// XICU |
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| 194 | std::ostringstream s_xicu; |
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| 195 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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| 196 | xicu = new VciXicu<vci_param_int>( |
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| 197 | s_xicu.str().c_str(), |
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| 198 | mt_int, // mapping table INT network |
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| 199 | IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space |
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| 200 | nb_procs, // number of timer IRQs |
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| 201 | 32, // number of hard IRQs |
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| 202 | 32, // number of soft IRQs |
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| 203 | nb_procs); // number of output IRQs |
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| 204 | |
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| 205 | std::ostringstream s_wt_xicu; |
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| 206 | s_wt_xicu << "xicu_wt_" << x_id << "_" << y_id; |
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| 207 | xicu_int_wt = new VciDspinTargetWrapper<vci_param_int, |
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| 208 | dspin_int_cmd_width, |
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| 209 | dspin_int_rsp_width>( |
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| 210 | s_wt_xicu.str().c_str(), |
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| 211 | x_width + y_width + l_width); |
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| 212 | |
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| 213 | //////////// MDMA |
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| 214 | std::ostringstream s_mdma; |
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| 215 | s_mdma << "mdma_" << x_id << "_" << y_id; |
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| 216 | mdma = new VciMultiDma<vci_param_int>( |
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| 217 | s_mdma.str().c_str(), |
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| 218 | mt_int, |
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| 219 | IntTab(cluster_id, nb_procs), // SRCID |
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| 220 | IntTab(cluster_id, mdma_int_tgtid), // TGTID |
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| 221 | 64, // burst size |
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| 222 | nb_dmas); // number of IRQs |
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| 223 | |
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| 224 | std::ostringstream s_wt_mdma; |
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| 225 | s_wt_mdma << "mdma_wt_" << x_id << "_" << y_id; |
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| 226 | mdma_int_wt = new VciDspinTargetWrapper<vci_param_int, |
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| 227 | dspin_int_cmd_width, |
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| 228 | dspin_int_rsp_width>( |
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| 229 | s_wt_mdma.str().c_str(), |
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| 230 | x_width + y_width + l_width); |
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| 231 | |
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| 232 | std::ostringstream s_wi_mdma; |
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| 233 | s_wi_mdma << "mdma_wi_" << x_id << "_" << y_id; |
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| 234 | mdma_int_wi = new VciDspinInitiatorWrapper<vci_param_int, |
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| 235 | dspin_int_cmd_width, |
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| 236 | dspin_int_rsp_width>( |
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| 237 | s_wi_mdma.str().c_str(), |
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| 238 | x_width + y_width + l_width); |
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| 239 | |
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| 240 | /////////// Direct LOCAL_XBAR(S) |
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| 241 | size_t nb_direct_initiators = nb_procs + 1; |
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| 242 | size_t nb_direct_targets = 3; |
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| 243 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 244 | { |
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| 245 | nb_direct_initiators = nb_procs + 2; |
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| 246 | nb_direct_targets = 4; |
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| 247 | } |
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| 248 | |
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| 249 | std::ostringstream s_int_xbar_cmd_d; |
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| 250 | s_int_xbar_cmd_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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| 251 | int_xbar_cmd_d = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 252 | s_int_xbar_cmd_d.str().c_str(), |
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| 253 | mt_int, // mapping table |
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| 254 | x_id, y_id, // cluster coordinates |
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| 255 | x_width, y_width, l_width, |
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| 256 | nb_direct_initiators, // number of local of sources |
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| 257 | nb_direct_targets, // number of local dests |
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| 258 | 2, 2, // fifo depths |
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| 259 | true, // CMD crossbar |
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| 260 | true, // use routing table |
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| 261 | false ); // no broacast |
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| 262 | |
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| 263 | std::ostringstream s_int_xbar_rsp_d; |
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| 264 | s_int_xbar_rsp_d << "int_xbar_rsp_d_" << x_id << "_" << y_id; |
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| 265 | int_xbar_rsp_d = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 266 | s_int_xbar_rsp_d.str().c_str(), |
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| 267 | mt_int, // mapping table |
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| 268 | x_id, y_id, // cluster coordinates |
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| 269 | x_width, y_width, l_width, |
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| 270 | nb_direct_targets, // number of local sources |
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| 271 | nb_direct_initiators, // number of local dests |
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| 272 | 2, 2, // fifo depths |
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| 273 | false, // RSP crossbar |
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| 274 | false, // don't use routing table |
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| 275 | false ); // no broacast |
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| 276 | |
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| 277 | //////////// Coherence LOCAL_XBAR(S) |
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| 278 | std::ostringstream s_int_xbar_m2p_c; |
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| 279 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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| 280 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 281 | s_int_xbar_m2p_c.str().c_str(), |
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| 282 | mt_int, // mapping table |
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| 283 | x_id, y_id, // cluster coordinates |
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| 284 | x_width, y_width, l_width, // several dests |
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| 285 | 1, // number of local sources |
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| 286 | nb_procs, // number of local dests |
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| 287 | 2, 2, // fifo depths |
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| 288 | true, // pseudo CMD |
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| 289 | false, // no routing table |
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| 290 | true ); // broacast |
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| 291 | |
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| 292 | std::ostringstream s_int_xbar_p2m_c; |
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| 293 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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| 294 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 295 | s_int_xbar_p2m_c.str().c_str(), |
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| 296 | mt_int, // mapping table |
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| 297 | x_id, y_id, // cluster coordinates |
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| 298 | x_width, y_width, 0, // only one dest |
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| 299 | nb_procs, // number of local sources |
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| 300 | 1, // number of local dests |
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| 301 | 2, 2, // fifo depths |
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| 302 | false, // pseudo RSP |
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| 303 | false, // no routing table |
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| 304 | false ); // no broacast |
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| 305 | |
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[468] | 306 | std::ostringstream s_int_xbar_clack_c; |
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| 307 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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| 308 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 309 | s_int_xbar_clack_c.str().c_str(), |
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| 310 | mt_int, // mapping table |
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| 311 | x_id, y_id, // cluster coordinates |
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| 312 | x_width, y_width, l_width, |
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| 313 | 1, // number of local sources |
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| 314 | nb_procs, // number of local targets |
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| 315 | 1, 1, // fifo depths |
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| 316 | true, // CMD |
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| 317 | false, // don't use local routing table |
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| 318 | false); // broadcast |
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| 319 | |
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[450] | 320 | ////////////// INT ROUTER(S) |
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| 321 | std::ostringstream s_int_router_cmd; |
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| 322 | s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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| 323 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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| 324 | s_int_router_cmd.str().c_str(), |
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| 325 | x_id,y_id, // coordinate in the mesh |
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| 326 | x_width, y_width, // x & y fields width |
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[468] | 327 | 3, // nb virtual channels |
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[450] | 328 | 4,4); // input & output fifo depths |
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| 329 | |
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| 330 | std::ostringstream s_int_router_rsp; |
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| 331 | s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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| 332 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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| 333 | s_int_router_rsp.str().c_str(), |
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| 334 | x_id,y_id, // coordinates in mesh |
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| 335 | x_width, y_width, // x & y fields width |
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[468] | 336 | 2, // nb virtual channels |
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[450] | 337 | 4,4); // input & output fifo depths |
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| 338 | |
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| 339 | ////////////// XRAM |
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| 340 | std::ostringstream s_xram; |
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| 341 | s_xram << "xram_" << x_id << "_" << y_id; |
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| 342 | xram = new VciSimpleRam<vci_param_ext>( |
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| 343 | s_xram.str().c_str(), |
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| 344 | IntTab(cluster_id, xram_ram_tgtid ), |
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| 345 | mt_ram, |
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| 346 | loader, |
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| 347 | xram_latency); |
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| 348 | |
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| 349 | std::ostringstream s_wt_xram; |
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| 350 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
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| 351 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
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| 352 | dspin_ram_cmd_width, |
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| 353 | dspin_ram_rsp_width>( |
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| 354 | s_wt_xram.str().c_str(), |
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| 355 | x_width + y_width + l_width); |
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| 356 | |
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| 357 | ///////////// RAM ROUTER(S) |
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| 358 | std::ostringstream s_ram_router_cmd; |
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| 359 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
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| 360 | ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>( |
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| 361 | s_ram_router_cmd.str().c_str(), |
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| 362 | x_id,y_id, // coordinate in the mesh |
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| 363 | x_width, y_width, // x & y fields width |
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| 364 | 4,4); // input & output fifo depths |
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| 365 | |
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| 366 | std::ostringstream s_ram_router_rsp; |
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| 367 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
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| 368 | ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>( |
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| 369 | s_ram_router_rsp.str().c_str(), |
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| 370 | x_id,y_id, // coordinates in mesh |
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| 371 | x_width, y_width, // x & y fields width |
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| 372 | 4,4); // input & output fifo depths |
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| 373 | |
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| 374 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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| 375 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 376 | { |
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| 377 | /////////// IO_BRIDGE |
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| 378 | size_t iox_local_id; |
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| 379 | size_t global_id; |
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| 380 | bool has_irqs; |
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| 381 | if ( cluster_id == cluster_iob0 ) |
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| 382 | { |
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| 383 | iox_local_id = 0; |
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| 384 | global_id = cluster_iob0; |
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| 385 | has_irqs = true; |
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| 386 | } |
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| 387 | else |
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| 388 | { |
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| 389 | iox_local_id = 1; |
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| 390 | global_id = cluster_iob1; |
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| 391 | has_irqs = false; |
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| 392 | } |
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| 393 | |
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| 394 | std::ostringstream s_iob; |
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| 395 | s_iob << "iob_" << x_id << "_" << y_id; |
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| 396 | iob = new VciIoBridge<vci_param_int, |
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| 397 | vci_param_ext>( |
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| 398 | s_iob.str().c_str(), |
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| 399 | mt_ram, // EXT network maptab |
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| 400 | mt_int, // INT network maptab |
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| 401 | mt_iox, // IOX network maptab |
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| 402 | IntTab( global_id, iobx_int_tgtid ), // INT TGTID |
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| 403 | IntTab( global_id, iobx_int_srcid ), // INT SRCID |
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| 404 | IntTab( global_id, iox_local_id ), // IOX TGTID |
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| 405 | has_irqs, |
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| 406 | 16, // cache line words |
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| 407 | 8, // IOTLB ways |
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| 408 | 8, // IOTLB sets |
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| 409 | debug_start_cycle, |
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| 410 | iob_debug_ok ); |
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| 411 | |
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| 412 | std::ostringstream s_iob_int_wi; |
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| 413 | s_iob_int_wi << "iob_int_wi_" << x_id << "_" << y_id; |
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| 414 | iob_int_wi = new VciDspinInitiatorWrapper<vci_param_int, |
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| 415 | dspin_int_cmd_width, |
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| 416 | dspin_int_rsp_width>( |
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| 417 | s_iob_int_wi.str().c_str(), |
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| 418 | x_width + y_width + l_width); |
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| 419 | |
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| 420 | std::ostringstream s_iob_int_wt; |
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| 421 | s_iob_int_wt << "iob_int_wt_" << x_id << "_" << y_id; |
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| 422 | iob_int_wt = new VciDspinTargetWrapper<vci_param_int, |
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| 423 | dspin_int_cmd_width, |
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| 424 | dspin_int_rsp_width>( |
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| 425 | s_iob_int_wt.str().c_str(), |
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| 426 | x_width + y_width + l_width); |
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| 427 | |
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| 428 | std::ostringstream s_iob_ram_wi; |
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| 429 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
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| 430 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 431 | dspin_ram_cmd_width, |
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| 432 | dspin_ram_rsp_width>( |
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| 433 | s_iob_ram_wi.str().c_str(), |
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| 434 | x_width + y_width + l_width); |
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| 435 | |
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| 436 | ///////////// RAM LOCAL_XBAR(S) |
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| 437 | std::ostringstream s_ram_xbar_cmd; |
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| 438 | s_ram_xbar_cmd << "ram_xbar_cmd_" << x_id << "_" << y_id; |
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| 439 | ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( |
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| 440 | s_ram_xbar_cmd.str().c_str(), |
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| 441 | mt_ram, // mapping table |
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| 442 | x_id, y_id, // cluster coordinates |
---|
| 443 | x_width, y_width, 0, // one dest on ram_cmd network |
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| 444 | 2, // number of local sources |
---|
| 445 | 1, // number of local dests |
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| 446 | 2, 2, // fifo depths |
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| 447 | true, // CMD crossbar |
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| 448 | false, // no routing table (one dest) |
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| 449 | false ); // no broadcast |
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| 450 | |
---|
| 451 | std::ostringstream s_ram_xbar_rsp; |
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| 452 | s_ram_xbar_rsp << "ram_xbar_rsp_" << x_id << "_" << y_id; |
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| 453 | ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( |
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| 454 | s_ram_xbar_rsp.str().c_str(), |
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| 455 | mt_ram, // mapping table |
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| 456 | x_id, y_id, // cluster coordinates |
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| 457 | x_width, y_width, l_width, // two sources on ram_rsp network |
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| 458 | 1, // number of local sources |
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| 459 | 2, // number of local dests |
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| 460 | 2, 2, // fifo depths |
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| 461 | false, // RSP crossbar |
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| 462 | true, // use routing table |
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| 463 | false ); // no broadcast |
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| 464 | } |
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| 465 | |
---|
| 466 | //////////////////////////////////// |
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| 467 | // Connections are defined here |
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| 468 | //////////////////////////////////// |
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| 469 | |
---|
| 470 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
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| 471 | // : local srcid[memc] = nb_procs |
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| 472 | |
---|
| 473 | //////////////////////// internal CMD & RSP routers |
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| 474 | int_router_cmd->p_clk (this->p_clk); |
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| 475 | int_router_cmd->p_resetn (this->p_resetn); |
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| 476 | int_router_rsp->p_clk (this->p_clk); |
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| 477 | int_router_rsp->p_resetn (this->p_resetn); |
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[468] | 478 | |
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| 479 | for (int i = 0; i < 4; i++) |
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[450] | 480 | { |
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[468] | 481 | for(int k = 0; k < 3; k++) |
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[450] | 482 | { |
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[468] | 483 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
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| 484 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
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[450] | 485 | } |
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[468] | 486 | |
---|
| 487 | for(int k = 0; k < 2; k++) |
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| 488 | { |
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| 489 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
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| 490 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
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| 491 | } |
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[450] | 492 | } |
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| 493 | |
---|
| 494 | // local ports |
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[468] | 495 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
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| 496 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
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| 497 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
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| 498 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
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| 499 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
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| 500 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
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[450] | 501 | |
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[468] | 502 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
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| 503 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
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| 504 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
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| 505 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
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[450] | 506 | |
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| 507 | ///////////////////// CMD DSPIN local crossbar direct |
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| 508 | int_xbar_cmd_d->p_clk (this->p_clk); |
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| 509 | int_xbar_cmd_d->p_resetn (this->p_resetn); |
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| 510 | int_xbar_cmd_d->p_global_out (signal_int_dspin_cmd_l2g_d); |
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| 511 | int_xbar_cmd_d->p_global_in (signal_int_dspin_cmd_g2l_d); |
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| 512 | |
---|
| 513 | int_xbar_cmd_d->p_local_out[memc_int_tgtid] (signal_int_dspin_cmd_memc_t); |
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| 514 | int_xbar_cmd_d->p_local_out[xicu_int_tgtid] (signal_int_dspin_cmd_xicu_t); |
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| 515 | int_xbar_cmd_d->p_local_out[mdma_int_tgtid] (signal_int_dspin_cmd_mdma_t); |
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| 516 | |
---|
| 517 | int_xbar_cmd_d->p_local_in[mdma_int_srcid] (signal_int_dspin_cmd_mdma_i); |
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| 518 | |
---|
| 519 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 520 | int_xbar_cmd_d->p_local_in[proc_int_srcid+p] (signal_int_dspin_cmd_proc_i[p]); |
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| 521 | |
---|
| 522 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
---|
| 523 | { |
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| 524 | int_xbar_cmd_d->p_local_out[iobx_int_tgtid] (signal_int_dspin_cmd_iobx_t); |
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| 525 | int_xbar_cmd_d->p_local_in[iobx_int_srcid] (signal_int_dspin_cmd_iobx_i); |
---|
| 526 | } |
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| 527 | |
---|
| 528 | //////////////////////// RSP DSPIN local crossbar direct |
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| 529 | int_xbar_rsp_d->p_clk (this->p_clk); |
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| 530 | int_xbar_rsp_d->p_resetn (this->p_resetn); |
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| 531 | int_xbar_rsp_d->p_global_out (signal_int_dspin_rsp_l2g_d); |
---|
| 532 | int_xbar_rsp_d->p_global_in (signal_int_dspin_rsp_g2l_d); |
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| 533 | |
---|
| 534 | int_xbar_rsp_d->p_local_in[memc_int_tgtid] (signal_int_dspin_rsp_memc_t); |
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| 535 | int_xbar_rsp_d->p_local_in[xicu_int_tgtid] (signal_int_dspin_rsp_xicu_t); |
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| 536 | int_xbar_rsp_d->p_local_in[mdma_int_tgtid] (signal_int_dspin_rsp_mdma_t); |
---|
| 537 | |
---|
| 538 | int_xbar_rsp_d->p_local_out[mdma_int_srcid] (signal_int_dspin_rsp_mdma_i); |
---|
| 539 | |
---|
| 540 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 541 | int_xbar_rsp_d->p_local_out[proc_int_srcid+p] (signal_int_dspin_rsp_proc_i[p]); |
---|
| 542 | |
---|
| 543 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
---|
| 544 | { |
---|
| 545 | int_xbar_rsp_d->p_local_in[iobx_int_tgtid] (signal_int_dspin_rsp_iobx_t); |
---|
| 546 | int_xbar_rsp_d->p_local_out[iobx_int_srcid] (signal_int_dspin_rsp_iobx_i); |
---|
| 547 | } |
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| 548 | |
---|
| 549 | ////////////////////// M2P DSPIN local crossbar coherence |
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| 550 | int_xbar_m2p_c->p_clk (this->p_clk); |
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| 551 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
---|
| 552 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
---|
| 553 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
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| 554 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
---|
| 555 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 556 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
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| 557 | |
---|
| 558 | ////////////////////////// P2M DSPIN local crossbar coherence |
---|
| 559 | int_xbar_p2m_c->p_clk (this->p_clk); |
---|
| 560 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
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| 561 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
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| 562 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
---|
| 563 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
---|
| 564 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 565 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
---|
| 566 | |
---|
[468] | 567 | ////////////////////// CLACK DSPIN local crossbar coherence |
---|
| 568 | int_xbar_clack_c->p_clk (this->p_clk); |
---|
| 569 | int_xbar_clack_c->p_resetn (this->p_resetn); |
---|
| 570 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
---|
| 571 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
---|
| 572 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
---|
| 573 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 574 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
---|
| 575 | |
---|
[450] | 576 | //////////////////////////////////// Processors |
---|
| 577 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 578 | { |
---|
| 579 | proc[p]->p_clk (this->p_clk); |
---|
| 580 | proc[p]->p_resetn (this->p_resetn); |
---|
| 581 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
[468] | 582 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
---|
| 583 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
---|
| 584 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
---|
[450] | 585 | proc[p]->p_irq[0] (signal_proc_it[p]); |
---|
| 586 | for ( size_t j = 1 ; j < 6 ; j++) |
---|
| 587 | { |
---|
| 588 | proc[p]->p_irq[j] (signal_false); |
---|
| 589 | } |
---|
| 590 | |
---|
| 591 | proc_wi[p]->p_clk (this->p_clk); |
---|
| 592 | proc_wi[p]->p_resetn (this->p_resetn); |
---|
| 593 | proc_wi[p]->p_dspin_cmd (signal_int_dspin_cmd_proc_i[p]); |
---|
| 594 | proc_wi[p]->p_dspin_rsp (signal_int_dspin_rsp_proc_i[p]); |
---|
| 595 | proc_wi[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
| 596 | } |
---|
| 597 | |
---|
| 598 | ///////////////////////////////////// XICU |
---|
[468] | 599 | xicu->p_clk (this->p_clk); |
---|
| 600 | xicu->p_resetn (this->p_resetn); |
---|
| 601 | xicu->p_vci (signal_int_vci_tgt_xicu); |
---|
[450] | 602 | for ( size_t p=0 ; p<nb_procs ; p++) |
---|
| 603 | { |
---|
[468] | 604 | xicu->p_irq[p] (signal_proc_it[p]); |
---|
[450] | 605 | } |
---|
| 606 | for ( size_t i=0 ; i<4 ; i++) |
---|
| 607 | { |
---|
| 608 | xicu->p_hwi[i] (signal_irq_mdma[i]); |
---|
| 609 | } |
---|
| 610 | for ( size_t i=4 ; i<32 ; i++) |
---|
| 611 | { |
---|
| 612 | if (cluster_id == cluster_iob0) |
---|
| 613 | xicu->p_hwi[i] (*(this->p_irq[i])); |
---|
| 614 | else |
---|
| 615 | xicu->p_hwi[i] (signal_false); |
---|
| 616 | } |
---|
| 617 | |
---|
| 618 | // wrapper XICU |
---|
| 619 | xicu_int_wt->p_clk (this->p_clk); |
---|
| 620 | xicu_int_wt->p_resetn (this->p_resetn); |
---|
| 621 | xicu_int_wt->p_dspin_cmd (signal_int_dspin_cmd_xicu_t); |
---|
| 622 | xicu_int_wt->p_dspin_rsp (signal_int_dspin_rsp_xicu_t); |
---|
| 623 | xicu_int_wt->p_vci (signal_int_vci_tgt_xicu); |
---|
| 624 | |
---|
| 625 | ///////////////////////////////////// MEMC |
---|
[468] | 626 | memc->p_clk (this->p_clk); |
---|
| 627 | memc->p_resetn (this->p_resetn); |
---|
| 628 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
---|
| 629 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
---|
| 630 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
---|
| 631 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
---|
| 632 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
---|
[450] | 633 | |
---|
| 634 | // wrapper to INT network |
---|
| 635 | memc_int_wt->p_clk (this->p_clk); |
---|
| 636 | memc_int_wt->p_resetn (this->p_resetn); |
---|
| 637 | memc_int_wt->p_dspin_cmd (signal_int_dspin_cmd_memc_t); |
---|
| 638 | memc_int_wt->p_dspin_rsp (signal_int_dspin_rsp_memc_t); |
---|
| 639 | memc_int_wt->p_vci (signal_int_vci_tgt_memc); |
---|
| 640 | |
---|
| 641 | // wrapper to RAM network |
---|
| 642 | memc_ram_wi->p_clk (this->p_clk); |
---|
| 643 | memc_ram_wi->p_resetn (this->p_resetn); |
---|
| 644 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
---|
| 645 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
---|
| 646 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
---|
| 647 | |
---|
| 648 | //////////////////////////////////// XRAM |
---|
[468] | 649 | xram->p_clk (this->p_clk); |
---|
| 650 | xram->p_resetn (this->p_resetn); |
---|
| 651 | xram->p_vci (signal_ram_vci_tgt_xram); |
---|
[450] | 652 | |
---|
| 653 | // wrapper to RAM network |
---|
| 654 | xram_ram_wt->p_clk (this->p_clk); |
---|
| 655 | xram_ram_wt->p_resetn (this->p_resetn); |
---|
| 656 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
---|
| 657 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
---|
| 658 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
---|
| 659 | |
---|
| 660 | /////////////////////////////////// MDMA |
---|
[468] | 661 | mdma->p_clk (this->p_clk); |
---|
[450] | 662 | mdma->p_resetn (this->p_resetn); |
---|
[468] | 663 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
---|
| 664 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
---|
[450] | 665 | for (size_t i=0 ; i<nb_dmas ; i++) |
---|
| 666 | mdma->p_irq[i] (signal_irq_mdma[i]); |
---|
| 667 | |
---|
| 668 | // target wrapper |
---|
| 669 | mdma_int_wt->p_clk (this->p_clk); |
---|
| 670 | mdma_int_wt->p_resetn (this->p_resetn); |
---|
| 671 | mdma_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mdma_t); |
---|
| 672 | mdma_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mdma_t); |
---|
| 673 | mdma_int_wt->p_vci (signal_int_vci_tgt_mdma); |
---|
| 674 | |
---|
| 675 | // initiator wrapper |
---|
| 676 | mdma_int_wi->p_clk (this->p_clk); |
---|
| 677 | mdma_int_wi->p_resetn (this->p_resetn); |
---|
| 678 | mdma_int_wi->p_dspin_cmd (signal_int_dspin_cmd_mdma_i); |
---|
| 679 | mdma_int_wi->p_dspin_rsp (signal_int_dspin_rsp_mdma_i); |
---|
| 680 | mdma_int_wi->p_vci (signal_int_vci_ini_mdma); |
---|
| 681 | |
---|
| 682 | // For the IO bridge and the RAM network components, the connexions |
---|
| 683 | // depend on cluster type: The vci_io_bridge and dspin_local_crossbar |
---|
| 684 | // components are only in cluster_iob0 & cluster_iob1 |
---|
| 685 | |
---|
| 686 | if ( (cluster_id != cluster_iob0) and (cluster_id != cluster_iob1) ) |
---|
| 687 | { |
---|
| 688 | // RAM network CMD & RSP routers |
---|
| 689 | ram_router_cmd->p_clk (this->p_clk); |
---|
| 690 | ram_router_cmd->p_resetn (this->p_resetn); |
---|
| 691 | ram_router_rsp->p_clk (this->p_clk); |
---|
| 692 | ram_router_rsp->p_resetn (this->p_resetn); |
---|
| 693 | for( size_t n=0 ; n<4 ; n++) |
---|
| 694 | { |
---|
| 695 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
---|
| 696 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
---|
| 697 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
---|
| 698 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
---|
| 699 | } |
---|
| 700 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
---|
| 701 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
---|
| 702 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
---|
| 703 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
---|
| 704 | } |
---|
| 705 | else // IO cluster |
---|
| 706 | { |
---|
| 707 | // IO bridge |
---|
| 708 | iob->p_clk (this->p_clk); |
---|
| 709 | iob->p_resetn (this->p_resetn); |
---|
| 710 | iob->p_vci_ini_iox (*(this->p_vci_iox_ini)); |
---|
| 711 | iob->p_vci_tgt_iox (*(this->p_vci_iox_tgt)); |
---|
| 712 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
---|
| 713 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
---|
| 714 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
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| 715 | if ( cluster_id == cluster_iob0 ) |
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| 716 | for ( size_t n=0 ; n<32 ; n++ ) |
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| 717 | iob->p_irq[n]->bind (*(this->p_irq[n])); |
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| 718 | |
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| 719 | // initiator wrapper to RAM network |
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| 720 | iob_ram_wi->p_clk (this->p_clk); |
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| 721 | iob_ram_wi->p_resetn (this->p_resetn); |
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| 722 | iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iobx_i); |
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| 723 | iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iobx_i); |
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| 724 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
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| 725 | |
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| 726 | // initiator wrapper to INT network |
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| 727 | iob_int_wi->p_clk (this->p_clk); |
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| 728 | iob_int_wi->p_resetn (this->p_resetn); |
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| 729 | iob_int_wi->p_dspin_cmd (signal_int_dspin_cmd_iobx_i); |
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| 730 | iob_int_wi->p_dspin_rsp (signal_int_dspin_rsp_iobx_i); |
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| 731 | iob_int_wi->p_vci (signal_int_vci_ini_iobx); |
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| 732 | |
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| 733 | // target wrapper to INT network |
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| 734 | iob_int_wt->p_clk (this->p_clk); |
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| 735 | iob_int_wt->p_resetn (this->p_resetn); |
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| 736 | iob_int_wt->p_dspin_cmd (signal_int_dspin_cmd_iobx_t); |
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| 737 | iob_int_wt->p_dspin_rsp (signal_int_dspin_rsp_iobx_t); |
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| 738 | iob_int_wt->p_vci (signal_int_vci_tgt_iobx); |
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| 739 | |
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| 740 | // RAM network CMD local crossbar |
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| 741 | ram_xbar_cmd->p_clk (this->p_clk); |
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| 742 | ram_xbar_cmd->p_resetn (this->p_resetn); |
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| 743 | ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_l2g); |
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| 744 | ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_g2l); |
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| 745 | ram_xbar_cmd->p_local_in[0] (signal_ram_dspin_cmd_memc_i); |
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| 746 | ram_xbar_cmd->p_local_in[1] (signal_ram_dspin_cmd_iobx_i); |
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| 747 | ram_xbar_cmd->p_local_out[0] (signal_ram_dspin_cmd_xram_t); |
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| 748 | |
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| 749 | // RAM network RSP local crossbar |
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| 750 | ram_xbar_rsp->p_clk (this->p_clk); |
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| 751 | ram_xbar_rsp->p_resetn (this->p_resetn); |
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| 752 | ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_l2g); |
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| 753 | ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_g2l); |
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| 754 | ram_xbar_rsp->p_local_in[0] (signal_ram_dspin_rsp_xram_t); |
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| 755 | ram_xbar_rsp->p_local_out[0] (signal_ram_dspin_rsp_memc_i); |
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| 756 | ram_xbar_rsp->p_local_out[1] (signal_ram_dspin_rsp_iobx_i); |
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| 757 | |
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| 758 | // RAM network CMD & RSP routers |
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| 759 | ram_router_cmd->p_clk (this->p_clk); |
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| 760 | ram_router_cmd->p_resetn (this->p_resetn); |
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| 761 | ram_router_rsp->p_clk (this->p_clk); |
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| 762 | ram_router_rsp->p_resetn (this->p_resetn); |
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| 763 | for( size_t n=0 ; n<4 ; n++) |
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| 764 | { |
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| 765 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
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| 766 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
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| 767 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
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| 768 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
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| 769 | } |
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| 770 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_g2l); |
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| 771 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_l2g); |
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| 772 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_g2l); |
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| 773 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_l2g); |
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| 774 | } |
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| 775 | |
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| 776 | } // end constructor |
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| 777 | |
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| 778 | }} |
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| 779 | |
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| 780 | |
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| 781 | // Local Variables: |
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| 782 | // tab-width: 3 |
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| 783 | // c-basic-offset: 3 |
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| 784 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 785 | // indent-tabs-mode: nil |
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| 786 | // End: |
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| 787 | |
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| 788 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 789 | |
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| 790 | |
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| 791 | |
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