source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd @ 468

Last change on this file since 468 was 468, checked in by cfuguet, 11 years ago


Merging vci_mem_cache from branches/v5 to trunk [441-467]

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r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port

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r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

  • Adding missing "strings" for print_trace() function
  • Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

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r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface


Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

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r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

  • Renaming FROM_MC DSPIN flits fields in M2P
  • Renaming FROM_L1 DSPIN flits fields in P2M
  • Renaming CLEANUP_ACK DSPIN flits fields in CLACK

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r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

  • Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.
  • Adding third port for the clack coherence network.
  • Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

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r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

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r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

  • In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

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r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

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r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.


Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

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r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

  • This platform contains a third local crossbar interconnect for the CLACK network.
  • It works only in a monocluster topology

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r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

  • Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

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r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

  • Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

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r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

  • Adding preprocessor conditional statements for ALMOS support


Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK
File size: 3.6 KB
Line 
1
2# -*- python -*-
3
4Module('caba:tsar_xbar_cluster', 
5    classname = 'soclib::caba::TsarXbarCluster',
6        tmpl_parameters = [
7                parameter.Int('dspin_cmd_width'),
8                parameter.Int('dspin_rsp_width'),
9        parameter.Module('vci_param_int', default = 'caba:vci_param',
10                          cell_size = parameter.Reference('vci_data_width_int')),
11        parameter.Module('vci_param_ext', default = 'caba:vci_param',
12                          cell_size = parameter.Reference('vci_data_width_ext')),
13        ],
14
15        header_files = [ '../source/include/tsar_xbar_cluster.h', 
16        ],
17
18        implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', 
19        ],
20
21        uses = [
22                Uses('caba:base_module'),
23                Uses('common:mapping_table'),
24                Uses('common:iss2'),
25             
26                Uses('caba:vci_cc_vcache_wrapper', 
27              cell_size       = parameter.Reference('vci_data_width_int'),
28              dspin_in_width  = parameter.Reference('dspin_cmd_width'),
29              dspin_out_width = parameter.Reference('dspin_rsp_width'),
30              iss_t           = 'common:gdb_iss', 
31              gdb_iss_t       = 'common:mips32el'),
32
33                Uses('caba:vci_mem_cache',
34              memc_cell_size_int = parameter.Reference('vci_data_width_int'),
35              memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),
36              dspin_in_width  = parameter.Reference('dspin_rsp_width'),
37              dspin_out_width = parameter.Reference('dspin_cmd_width')),
38
39                Uses('caba:vci_simple_rom',
40              cell_size       = parameter.Reference('vci_data_width_int')),
41
42                Uses('caba:vci_simple_ram',
43              cell_size       = parameter.Reference('vci_data_width_ext')),
44
45        Uses('caba:vci_xicu',
46              cell_size       = parameter.Reference('vci_data_width_int')),
47
48        Uses('caba:dspin_local_crossbar', 
49              flit_width      = parameter.Reference('dspin_cmd_width')),
50
51        Uses('caba:dspin_local_crossbar', 
52              flit_width      = parameter.Reference('dspin_rsp_width')),
53
54        Uses('caba:virtual_dspin_router', 
55              flit_width      = parameter.Reference('dspin_cmd_width')),
56
57        Uses('caba:virtual_dspin_router', 
58              flit_width      = parameter.Reference('dspin_rsp_width')),
59
60        Uses('caba:vci_multi_tty',
61              cell_size       = parameter.Reference('vci_data_width_int')),
62
63        Uses('caba:vci_framebuffer',
64              cell_size       = parameter.Reference('vci_data_width_int')),
65
66        Uses('caba:vci_multi_nic',
67              cell_size       = parameter.Reference('vci_data_width_int')),
68
69                Uses('caba:vci_block_device_tsar',
70              cell_size       = parameter.Reference('vci_data_width_int')),
71
72                Uses('caba:vci_multi_dma',
73              cell_size       = parameter.Reference('vci_data_width_int')),
74
75        Uses('caba:vci_dspin_target_wrapper',
76              cell_size       = parameter.Reference('vci_data_width_int')),
77
78        Uses('caba:vci_dspin_initiator_wrapper',
79              cell_size       = parameter.Reference('vci_data_width_int')),
80
81                Uses('common:elf_file_loader'),
82                ],
83
84        ports = [
85                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
86                Port('caba:clock_in', 'p_clk', auto = 'clock'),
87                Port('caba:dspin_output', 'p_cmd_out', [4, 3], 
88              dspin_data_size = parameter.Reference('dspin_cmd_width')),
89                Port('caba:dspin_input', 'p_cmd_in', [4, 3], 
90              dspin_data_size = parameter.Reference('dspin_cmd_width')),
91                Port('caba:dspin_output', 'p_rsp_out', [4, 2], 
92              dspin_data_size = parameter.Reference('dspin_rsp_width')), 
93                Port('caba:dspin_input', 'p_rsp_in', [4, 2], 
94              dspin_data_size = parameter.Reference('dspin_rsp_width')),
95                ],
96)
97
98
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