- Timestamp:
- Jan 24, 2011, 5:36:50 PM (14 years ago)
- Location:
- trunk
- Files:
-
- 35 added
- 14 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_xcache_wrapper_v4/caba/metadata/vci_cc_xcache_wrapper_v4.sd
r20 r134 21 21 Uses('common:mapping_table'), 22 22 Uses('common:iss2'), 23 Uses('caba: write_buffer'),23 Uses('caba:multi_write_buffer'), 24 24 Uses('caba:generic_cache', addr_t = 'uint32_t'), 25 25 ], 26 26 ports = [ 27 27 Port('caba:vci_initiator', 'p_vci_ini_rw'), 28 28 Port('caba:vci_initiator', 'p_vci_ini_c'), 29 29 Port('caba:vci_target', 'p_vci_tgt'), 30 30 Port('caba:bit_in', 'p_irq', parameter.Constant('n_irq')), … … 45 45 parameter.Int('dcache_sets'), 46 46 parameter.Int('dcache_words'), 47 parameter.Int('ram_width_access'), 48 parameter.Int('wbuf_nwords'), 49 parameter.Int('wbuf_nlines'), 50 parameter.Int('wbuf_timeout'), 47 51 ], 48 49 'dsx:get_ident='50 51 52 53 'dsx:cpu=wrapper:iss_t',54 'dsx:addressable=target_index',55 56 'dsx:mapping_type=processor:proc_id',57 52 extensions = [ 53 'dsx:get_ident=' 54 'initiator_rw_index:p_vci_ini_rw:mt,' 55 'initiator_c_index:p_vci_ini_c:mc,' 56 'target_index:p_vci_tgt:mc', 57 'dsx:cpu=wrapper:iss_t', 58 'dsx:addressable=target_index', 59 'dsx:on_segment=mc:add_index:initiator_rw_index', 60 'dsx:mapping_type=processor:proc_id', 61 ], 58 62 ) 59 60 -
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r118 r134 32 32 #include <inttypes.h> 33 33 #include <systemc> 34 #include <queue> 34 35 #include "caba_base_module.h" 35 #include " write_buffer.h"36 #include "multi_write_buffer.h" 36 37 #include "generic_cache.h" 37 38 #include "vci_initiator.h" … … 40 41 #include "static_assert.h" 41 42 43 /* 44 * CC_XCACHE_WRAPPER_SELECT_VICTIM : 45 * The selection and the update of cache (after a read miss) 46 * are separated in two step 47 * Also, the cleanup can be send in parallel at the read miss. 48 * 49 * CC_XCACHE_WRAPPER_FIFO_RSP 50 * Two simple fifo (each 2x32 depth) receive the cache line from 51 * RAM. Instead of two buffers (m_icache_words and m_dcache_words) 52 * 53 * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 54 * Update cache in "2*cache_words" cycles (read+mask, write) 55 * 56 * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 57 * Update cache with only modified data (be != 0) 58 * 59 * CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 60 * Write buffer scheme for update step : 61 * 1 - multi_scan 62 * 2 - round_robin_scan 63 * 3 - one_scan 64 * else - default scheme 65 * 66 * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 67 * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req 68 * 1 - two access authorized 69 * 2 - one access with static priority (dcache prior) 70 * 3 - one access with static priority (icache prior) 71 * 4 - one access with round robin priority 72 * 73 * CC_XCACHE_WRAPPER_STOP_SIMULATION : 74 * stop simulation if processor is stall after a long time 75 * (configurable with "stop_simulation" function) 76 * 77 * CC_XCACHE_WRAPPER_DEBUG : 78 * Add log to help the debugging 79 * 80 * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN : 81 * Number of cycle before to prinf debug message 82 * 83 * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 84 * Print transaction between the cpu and the cache 85 */ 86 87 // implementation 88 #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM 89 #define CC_XCACHE_WRAPPER_SELECT_VICTIM 0 90 #endif 91 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP 92 #define CC_XCACHE_WRAPPER_FIFO_RSP 0 93 #endif 94 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 95 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 96 #endif 97 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 98 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 99 #endif 100 #ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 101 #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 0 102 #endif 103 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 104 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 2 105 #endif 106 // debugging 107 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION 108 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 109 #endif 110 #ifndef CC_XCACHE_WRAPPER_DEBUG 111 #define CC_XCACHE_WRAPPER_DEBUG 0 112 #endif 113 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 114 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 200000 115 #endif 116 #ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 117 #define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 0 118 #endif 42 119 43 120 namespace soclib { … … 58 135 typedef uint32_t be_t; 59 136 typedef typename vci_param::fast_addr_t vci_addr_t; 137 60 138 enum dcache_fsm_state_e { 61 139 DCACHE_IDLE, 62 140 DCACHE_WRITE_UPDT, 63 DCACHE_WRITE_REQ, 141 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 142 DCACHE_MISS_VICTIM, 143 #endif 64 144 DCACHE_MISS_WAIT, 65 145 DCACHE_MISS_UPDT, … … 67 147 DCACHE_SC_WAIT, 68 148 DCACHE_INVAL, 149 DCACHE_SYNC, 69 150 DCACHE_ERROR, 70 151 DCACHE_CC_CHECK, … … 76 157 enum icache_fsm_state_e { 77 158 ICACHE_IDLE, 159 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 160 ICACHE_MISS_VICTIM, 161 #endif 78 162 ICACHE_MISS_WAIT, 79 163 ICACHE_MISS_UPDT, … … 94 178 CMD_DATA_WRITE, 95 179 CMD_DATA_SC, 96 CMD_INS_CLEANUP,97 CMD_DATA_CLEANUP,98 180 }; 99 181 … … 106 188 RSP_DATA_WRITE, 107 189 RSP_DATA_SC, 108 RSP_INS_CLEANUP,109 RSP_DATA_CLEANUP,110 190 }; 111 191 … … 122 202 }; 123 203 204 enum cleanup_fsm_state_e { 205 CLEANUP_IDLE, 206 CLEANUP_DCACHE, 207 CLEANUP_ICACHE, 208 }; 209 210 enum transaction_type_c_e { 211 // convention with memcache 212 TYPE_DATA_CLEANUP = 0x0, 213 TYPE_INS_CLEANUP = 0x1 214 }; 215 216 enum transaction_type_rw_e { 217 // convention with memcache 218 // b0 : 1 if cached 219 // b1 : 1 if instruction 220 // b2 : 1 if sc 221 TYPE_DATA_UNC = 0x0, 222 TYPE_DATA_MISS = 0x1, 223 TYPE_INS_UNC = 0x2, 224 TYPE_INS_MISS = 0x3, 225 TYPE_DATA_SC = 0x4, // sc is data and no cached 226 }; 227 124 228 public: 125 229 … … 143 247 const size_t m_dcache_ways; 144 248 const size_t m_dcache_words; 249 const uint32_t m_dcache_words_shift; 145 250 const size_t m_dcache_yzmask; 146 251 const size_t m_icache_ways; 147 252 const size_t m_icache_words; 253 const uint32_t m_icache_words_shift; 148 254 const size_t m_icache_yzmask; 255 const size_t m_cache_words; // max between m_dcache_words and m_icache_words 256 257 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 258 bool m_stop_simulation; 259 uint32_t m_stop_simulation_nb_frz_cycles_max; 260 uint32_t m_stop_simulation_nb_frz_cycles; 261 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 149 262 150 263 // REGISTERS … … 154 267 sc_signal<data_t> r_dcache_wdata_save; 155 268 sc_signal<data_t> r_dcache_rdata_save; 156 sc_signal<data_64> r_dcache_ll_data;157 sc_signal<addr_40> r_dcache_ll_addr;158 sc_signal<bool> r_dcache_ll_valid;159 269 sc_signal<int> r_dcache_type_save; 160 270 sc_signal<be_t> r_dcache_be_save; … … 163 273 sc_signal<addr_40> r_dcache_cleanup_line; 164 274 sc_signal<bool> r_dcache_miss_req; 275 sc_signal<size_t> r_dcache_miss_way; 276 sc_signal<size_t> r_dcache_miss_set; 165 277 sc_signal<bool> r_dcache_unc_req; 166 278 sc_signal<bool> r_dcache_sc_req; 167 sc_signal<bool> r_dcache_write_req;168 279 sc_signal<bool> r_dcache_inval_rsp; 280 sc_signal<size_t> r_dcache_update_addr; 281 sc_signal<data_64> r_dcache_ll_data; 282 sc_signal<addr_40> r_dcache_ll_addr; 283 sc_signal<bool> r_dcache_ll_valid; 284 sc_signal<bool> r_dcache_previous_unc; 169 285 170 286 sc_signal<int> r_icache_fsm; … … 172 288 sc_signal<addr_40> r_icache_addr_save; 173 289 sc_signal<bool> r_icache_miss_req; 290 sc_signal<size_t> r_icache_miss_way; 291 sc_signal<size_t> r_icache_miss_set; 174 292 sc_signal<bool> r_icache_unc_req; 175 293 sc_signal<bool> r_icache_cleanup_req; 176 294 sc_signal<addr_40> r_icache_cleanup_line; 177 295 sc_signal<bool> r_icache_inval_rsp; 296 sc_signal<size_t> r_icache_update_addr; 178 297 179 298 sc_signal<int> r_vci_cmd_fsm; … … 181 300 sc_signal<size_t> r_vci_cmd_max; 182 301 sc_signal<size_t> r_vci_cmd_cpt; 302 sc_signal<bool> r_vci_cmd_dcache_prior; 183 303 184 304 sc_signal<int> r_vci_rsp_fsm; … … 186 306 sc_signal<bool> r_vci_rsp_data_error; 187 307 sc_signal<size_t> r_vci_rsp_cpt; 188 189 data_t *r_icache_miss_buf; 190 data_t *r_dcache_miss_buf; 308 sc_signal<bool> r_vci_rsp_ack; 309 310 #if CC_XCACHE_WRAPPER_FIFO_RSP 311 std::queue<data_t> r_icache_miss_buf; 312 std::queue<data_t> r_dcache_miss_buf; 313 #else 314 bool *r_icache_miss_val; //[m_icache_words] 315 data_t *r_icache_miss_buf; //[m_icache_words] 316 bool *r_dcache_miss_val; //[m_dcache_words] 317 data_t *r_dcache_miss_buf; //[m_dcache_words] 318 #endif 191 319 sc_signal<bool> r_icache_buf_unc_valid; 192 320 193 data_t *r_tgt_buf; 194 be_t *r_tgt_be; 321 data_t *r_tgt_buf; //[m_cache_words] 322 be_t *r_tgt_be; //[m_cache_words] 323 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 324 sc_signal<uint32_t> r_cache_word; 325 #endif 195 326 196 327 sc_signal<int> r_vci_tgt_fsm; … … 199 330 sc_signal<bool> r_tgt_update; 200 331 sc_signal<bool> r_tgt_update_data; 201 332 //sc_signal<bool> r_tgt_brdcast; 202 333 sc_signal<size_t> r_tgt_srcid; 203 334 sc_signal<size_t> r_tgt_pktid; 204 335 sc_signal<size_t> r_tgt_trdid; 205 336 //sc_signal<size_t> r_tgt_plen; 206 337 sc_signal<bool> r_tgt_icache_req; 207 338 sc_signal<bool> r_tgt_dcache_req; … … 209 340 sc_signal<bool> r_tgt_dcache_rsp; 210 341 211 WriteBuffer<addr_40> r_wbuf; 342 sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network 343 344 MultiWriteBuffer<addr_40> r_wbuf; 212 345 GenericCache<vci_addr_t> r_icache; 213 346 GenericCache<vci_addr_t> r_dcache; 214 347 348 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 349 std::ofstream log_dcache_transaction_file; 350 #endif 351 215 352 // Activity counters 216 uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ 217 uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE 218 uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ 219 uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE 220 221 uint32_t m_cpt_icache_data_read; // ICACHE DATA READ 222 uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE 223 uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ 224 uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE 225 226 uint32_t m_cpt_cc_update; // number of coherence update packets 227 uint32_t m_cpt_cc_inval; // number of coherence inval packets 228 229 uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen 230 uint32_t m_cpt_total_cycles; // total number of cycles 231 232 uint32_t m_cpt_read; // total number of read instructions 233 uint32_t m_cpt_write; // total number of write instructions 234 uint32_t m_cpt_data_miss; // number of read miss 235 uint32_t m_cpt_ins_miss; // number of instruction miss 236 uint32_t m_cpt_unc_read; // number of read uncached 237 uint32_t m_cpt_write_cached; // number of cached write 238 239 uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer 240 uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss 241 uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read 242 uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss 243 244 uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions 245 uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions 246 uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions 247 uint32_t m_cpt_write_transaction; // number of VCI write transactions 248 249 uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions 250 uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions 251 uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions 252 uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions 253 uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions 353 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 354 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 355 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 356 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 357 358 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 359 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 360 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 361 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 362 363 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 364 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 365 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 366 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 367 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 368 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 369 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 370 371 uint32_t m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 372 uint32_t m_cpt_total_cycles; // total number of cycles 373 374 uint32_t m_cpt_data_read; // number of data read 375 uint32_t m_cpt_data_read_miss; // number of data read miss 376 uint32_t m_cpt_data_read_uncached; // number of data read uncached 377 uint32_t m_cpt_data_write; // number of data write 378 uint32_t m_cpt_data_write_miss; // number of data write miss 379 uint32_t m_cpt_data_write_uncached; // number of data write uncached 380 uint32_t m_cpt_ins_miss; // * number of instruction miss 381 382 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 383 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 384 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 385 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 386 387 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 388 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 389 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 390 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 391 392 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 393 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 394 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 395 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 396 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 254 397 255 398 protected: … … 271 414 size_t dcache_ways, 272 415 size_t dcache_sets, 273 size_t dcache_words ); 416 size_t dcache_words, 417 size_t wbuf_nwords, 418 size_t wbuf_nlines, 419 size_t wbuf_timeout 420 ); 274 421 275 422 ~VciCcXCacheWrapperV4(); … … 278 425 void print_cpi(); 279 426 void print_stats(); 427 428 // #if CC_XCACHE_WRAPPER_STOP_SIMULATION 429 void stop_simulation (uint32_t); 430 // #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 280 431 281 432 private: … … 300 451 301 452 // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 302 303 304 -
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
r114 r134 56 56 57 57 #include <cassert> 58 #include <iomanip> 58 59 #include "arithmetics.h" 59 60 #include "../include/vci_cc_xcache_wrapper_v4.h" 60 61 61 //#define DEBUG_CC_XCACHE_WRAPPER 1 62 #if CC_XCACHE_WRAPPER_DEBUG 63 # define PRINTF(msg...) do { if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) printf(msg); } while (0); 64 #else 65 # define PRINTF(msg...) 66 #endif 67 68 # define ASSERT(cond,msg) assert ((cond) and msg); 69 70 #if CC_XCACHE_WRAPPER_FIFO_RSP 71 # define CACHE_MISS_BUF_ALLOC 72 # define CACHE_MISS_BUF_DEALLOC 73 # define CACHE_MISS_BUF_RESET(c) while (r_##c##cache_miss_buf.size()>0) {r_##c##cache_miss_buf.pop();} 74 # define CACHE_MISS_BUF_REQ_INIT(c) 75 # define CACHE_MISS_BUF_RSP_VAL(c,n) (r_##c##cache_miss_buf.size()>0) 76 # define CACHE_MISS_BUF_RSP_ACK(c) (r_##c##cache_miss_buf.size()<2) 77 # define CACHE_MISS_BUF_RSP_DATA(c,n) r_##c##cache_miss_buf.front() 78 # define CACHE_MISS_BUF_RSP_POP(c) do { r_##c##cache_miss_buf.pop();} while (0) 79 # define CACHE_MISS_BUF_RSP_PUSH(c,n,d) do { r_##c##cache_miss_buf.push(d);} while (0) 80 # define CACHE_MISS_BUF_RSP_PRINT(c) do { PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf.size());} while (0) 81 #else 82 # define CACHE_MISS_BUF_ALLOC do { \ 83 r_icache_miss_val = new bool [m_icache_words]; \ 84 r_icache_miss_buf = new data_t[m_icache_words]; \ 85 r_dcache_miss_val = new bool [m_dcache_words]; \ 86 r_dcache_miss_buf = new data_t[m_dcache_words]; \ 87 } while (0) 88 # define CACHE_MISS_BUF_DEALLOC do { \ 89 delete [] r_icache_miss_val; \ 90 delete [] r_icache_miss_buf; \ 91 delete [] r_dcache_miss_val; \ 92 delete [] r_dcache_miss_buf; \ 93 } while (0) 94 # define CACHE_MISS_BUF_RESET(c) 95 # define CACHE_MISS_BUF_REQ_INIT(c) do {for (uint32_t i=0; i<m_##c##cache_words;++i) r_##c##cache_miss_val[i] = false;} while (0) 96 # define CACHE_MISS_BUF_RSP_VAL(c,n) r_##c##cache_miss_val[n] 97 # define CACHE_MISS_BUF_RSP_ACK(c) true 98 # define CACHE_MISS_BUF_RSP_DATA(c,n) r_##c##cache_miss_buf[n] 99 # define CACHE_MISS_BUF_RSP_POP(c) 100 # define CACHE_MISS_BUF_RSP_PUSH(c,n,d) do {r_##c##cache_miss_val[n] = true; r_##c##cache_miss_buf[n] = d;} while (0) 101 # define CACHE_MISS_BUF_RSP_PRINT(c) do {for (uint32_t i=0; i<m_##c##cache_words;++i) PRINTF("%d %x |",r_##c##cache_miss_val[i],r_##c##cache_miss_buf[i]); PRINTF("\n");} while (0) 102 #endif 62 103 63 104 namespace soclib { 64 105 namespace caba { 65 66 106 namespace { 107 67 108 const char *dcache_fsm_state_str[] = { 68 109 "DCACHE_IDLE", 69 110 "DCACHE_WRITE_UPDT", 70 "DCACHE_WRITE_REQ", 111 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 112 "DCACHE_MISS_VICTIM", 113 #endif 71 114 "DCACHE_MISS_WAIT", 72 115 "DCACHE_MISS_UPDT", … … 74 117 "DCACHE_SC_WAIT", 75 118 "DCACHE_INVAL", 119 "DCACHE_SYNC", 76 120 "DCACHE_ERROR", 77 121 "DCACHE_CC_CHECK", … … 82 126 const char *icache_fsm_state_str[] = { 83 127 "ICACHE_IDLE", 128 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 129 "ICACHE_MISS_VICTIM", 130 #endif 84 131 "ICACHE_MISS_WAIT", 85 132 "ICACHE_MISS_UPDT", … … 99 146 "CMD_DATA_WRITE", 100 147 "CMD_DATA_SC", 101 "CMD_INS_CLEANUP",102 "CMD_DATA_CLEANUP",103 148 }; 104 149 const char *rsp_fsm_state_str[] = { … … 110 155 "RSP_DATA_WRITE", 111 156 "RSP_DATA_SC", 112 "RSP_INS_CLEANUP",113 "RSP_DATA_CLEANUP",114 157 }; 115 158 const char *tgt_fsm_state_str[] = { … … 123 166 "TGT_RSP_ICACHE", 124 167 "TGT_RSP_DCACHE", 168 }; 169 170 const char *cleanup_fsm_state_str[] = { 171 "CLEANUP_IDLE", 172 "CLEANUP_DCACHE", 173 "CLEANUP_ICACHE", 125 174 }; 126 175 } … … 145 194 size_t dcache_ways, 146 195 size_t dcache_sets, 147 size_t dcache_words ) 196 size_t dcache_words, 197 size_t wbuf_nwords, 198 size_t wbuf_nlines, 199 size_t wbuf_timeout 200 ) 148 201 : 149 202 soclib::caba::BaseModule(name), 150 203 151 p_clk ("clk"),152 p_resetn ("resetn"),204 p_clk ("clk"), 205 p_resetn ("resetn"), 153 206 p_vci_ini_rw("vci_ini_rw"), 154 p_vci_ini_c ("vci_ini_c"),155 p_vci_tgt ("vci_tgt"),207 p_vci_ini_c ("vci_ini_c"), 208 p_vci_tgt ("vci_tgt"), 156 209 157 210 m_cacheability_table(mtp.getCacheabilityTable<vci_addr_t>()), … … 163 216 m_dcache_ways(dcache_ways), 164 217 m_dcache_words(dcache_words), 165 m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)), 218 m_dcache_words_shift(uint32_log2(dcache_words)+2), 219 m_dcache_yzmask((~0)<<m_dcache_words_shift), 166 220 m_icache_ways(icache_ways), 167 221 m_icache_words(icache_words), 168 m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)), 222 m_icache_words_shift(uint32_log2(icache_words)+2), 223 m_icache_yzmask((~0)<<m_icache_words_shift), 224 m_cache_words((dcache_words)?dcache_words:icache_words), 169 225 170 226 r_dcache_fsm("r_dcache_fsm"), … … 173 229 r_dcache_wdata_save("r_dcache_wdata_save"), 174 230 r_dcache_rdata_save("r_dcache_rdata_save"), 175 r_dcache_ll_data("r_dcache_ll_data"),176 r_dcache_ll_addr("r_dcache_ll_addr"),177 r_dcache_ll_valid("r_dcache_ll_valid"),178 231 r_dcache_type_save("r_dcache_type_save"), 179 232 r_dcache_be_save("r_dcache_be_save"), … … 182 235 r_dcache_cleanup_line("r_dcache_cleanup_line"), 183 236 r_dcache_miss_req("r_dcache_miss_req"), 237 r_dcache_miss_way("r_dcache_miss_way"), 238 r_dcache_miss_set("r_dcache_miss_set"), 184 239 r_dcache_unc_req("r_dcache_unc_req"), 185 r_dcache_write_req("r_dcache_write_req"), 240 r_dcache_sc_req("r_dcache_sc_req"), 241 r_dcache_inval_rsp("r_dcache_inval_rsp"), 242 r_dcache_update_addr("r_dcache_update_addr"), 243 r_dcache_ll_data("r_dcache_ll_data"), 244 r_dcache_ll_addr("r_dcache_ll_addr"), 245 r_dcache_ll_valid("r_dcache_ll_valid"), 246 r_dcache_previous_unc("r_dcache_previous_unc"), 186 247 187 248 r_icache_fsm("r_icache_fsm"), … … 189 250 r_icache_addr_save("r_icache_addr_save"), 190 251 r_icache_miss_req("r_icache_miss_req"), 252 r_icache_miss_way("r_icache_miss_way"), 253 r_icache_miss_set("r_icache_miss_set"), 254 r_icache_unc_req("r_icache_unc_req"), 191 255 r_icache_cleanup_req("r_icache_cleanup_req"), 192 256 r_icache_cleanup_line("r_icache_cleanup_line"), 257 r_icache_inval_rsp("r_icache_inval_rsp"), 258 r_icache_update_addr("r_icache_update_addr"), 193 259 194 260 r_vci_cmd_fsm("r_vci_cmd_fsm"), … … 196 262 r_vci_cmd_max("r_vci_cmd_max"), 197 263 r_vci_cmd_cpt("r_vci_cmd_cpt"), 264 r_vci_cmd_dcache_prior("r_vci_cmd_dcache_prior"), 198 265 199 266 r_vci_rsp_fsm("r_vci_rsp_fsm"), … … 201 268 r_vci_rsp_data_error("r_vci_rsp_data_error"), 202 269 r_vci_rsp_cpt("r_vci_rsp_cpt"), 270 r_vci_rsp_ack("r_vci_rsp_ack"), 203 271 204 272 r_icache_buf_unc_valid("r_icache_buf_unc_valid"), 273 274 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 275 r_cache_word("r_cache_word"), 276 #endif 205 277 206 278 r_vci_tgt_fsm("r_vci_tgt_fsm"), … … 208 280 r_tgt_word("r_tgt_word"), 209 281 r_tgt_update("r_tgt_update"), 282 r_tgt_update_data("r_tgt_update_data"), 283 // r_tgt_brdcast("r_tgt_brdcast"), 210 284 r_tgt_srcid("r_tgt_srcid"), 211 285 r_tgt_pktid("r_tgt_pktid"), 212 286 r_tgt_trdid("r_tgt_trdid"), 287 // r_tgt_plen("r_tgt_plen"), 213 288 r_tgt_icache_req("r_tgt_icache_req"), 214 289 r_tgt_dcache_req("r_tgt_dcache_req"), 215 216 r_wbuf("r_wbuf", dcache_words ), 290 r_tgt_icache_rsp("r_tgt_icache_rsp"), 291 r_tgt_dcache_rsp("r_tgt_dcache_rsp"), 292 293 r_cleanup_fsm("r_cleanup_fsm"), 294 295 r_wbuf("r_wbuf", wbuf_nwords, wbuf_nlines, wbuf_timeout, dcache_words), 217 296 r_icache("icache", icache_ways, icache_sets, icache_words), 218 297 r_dcache("dcache", dcache_ways, dcache_sets, dcache_words) 219 220 298 { 221 r_icache_miss_buf = new data_t[icache_words]; 222 r_dcache_miss_buf = new data_t[dcache_words]; 223 r_tgt_buf = new data_t[dcache_words]; 224 r_tgt_be = new be_t[dcache_words]; 299 // Size of word is 32 bits 300 ASSERT( (icache_words*vci_param::B) < (1<<vci_param::K), 301 "I need more PLEN bits"); 302 303 ASSERT( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= wbuf_nlines), 304 "I need more TRDID bits"); 305 306 CACHE_MISS_BUF_ALLOC; 307 308 r_tgt_buf = new data_t[m_cache_words]; 309 r_tgt_be = new be_t [m_cache_words]; 225 310 226 311 SC_METHOD(transition); … … 234 319 235 320 typename iss_t::CacheInfo cache_info; 236 cache_info.has_mmu = false;321 cache_info.has_mmu = false; 237 322 cache_info.icache_line_size = icache_words*sizeof(data_t); 238 cache_info.icache_assoc = icache_ways;239 cache_info.icache_n_lines = icache_sets;323 cache_info.icache_assoc = icache_ways; 324 cache_info.icache_n_lines = icache_sets; 240 325 cache_info.dcache_line_size = dcache_words*sizeof(data_t); 241 cache_info.dcache_assoc = dcache_ways;242 cache_info.dcache_n_lines = dcache_sets;326 cache_info.dcache_assoc = dcache_ways; 327 cache_info.dcache_n_lines = dcache_sets; 243 328 m_iss.setCacheInfo(cache_info); 329 330 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 331 m_stop_simulation = false; 332 m_stop_simulation_nb_frz_cycles = 0; 333 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 334 335 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 336 std::ostringstream filename(""); 337 filename << "Instruction_flow_" << proc_id << ".log"; 338 339 log_dcache_transaction_file.open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 340 #endif 244 341 } // end constructor 245 342 … … 248 345 /////////////////////////////////// 249 346 { 250 delete [] r_icache_miss_buf; 251 delete [] r_dcache_miss_buf; 252 delete [] r_tgt_be; 347 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 348 log_dcache_transaction_file.close(); 349 #endif 350 253 351 delete [] r_tgt_buf; 352 delete [] r_tgt_be ; 353 354 CACHE_MISS_BUF_DEALLOC; 254 355 } 255 356 … … 266 367 { 267 368 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); 369 370 uint32_t m_cpt_data_read_cached = m_cpt_data_read-m_cpt_data_read_uncached; 371 uint32_t m_cpt_data_write_cached = m_cpt_data_write-m_cpt_data_write_uncached; 268 372 std::cout << "------------------------------------" << std:: dec << std::endl; 269 373 std::cout << "CPU " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl; 270 std::cout << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl ; 271 std::cout << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl ; 272 std::cout << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl; 273 std::cout << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl ; 274 std::cout << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl ; 275 std::cout << "- IMISS_RATE = " << (float)m_cpt_ins_miss/run_cycles << std::endl; 276 std::cout << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl ; 277 std::cout << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl; 278 std::cout << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl; 279 std::cout << "- DMISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl; 280 std::cout << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl; 281 std::cout << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl; 282 std::cout << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl; 283 std::cout << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl; 284 std::cout << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl; 285 std::cout << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl; 374 std::cout << "- CPI : " << (float)m_cpt_total_cycles/run_cycles << std::endl ; 375 std::cout << "- IPC : " << (float)run_cycles/m_cpt_total_cycles << std::endl ; 376 std::cout << "- DATA READ * : " << m_cpt_data_read << std::endl ; 377 std::cout << " + Uncached : " << m_cpt_data_read_uncached << " (" << (float)m_cpt_data_read_uncached*100.0/(float)m_cpt_data_read << "%)" << std::endl ; 378 std::cout << " + Cached and miss : " << m_cpt_data_read_miss << " (" << (float)m_cpt_data_read_miss*100.0/(float)m_cpt_data_read_cached << "%)" << std::endl; 379 std::cout << "- DATA WRITE * : " << m_cpt_data_write << std::endl ; 380 std::cout << " + Uncached : " << m_cpt_data_write_uncached << " (" << (float)m_cpt_data_write_uncached*100.0/(float)m_cpt_data_write << "%)" << std::endl ; 381 std::cout << " + Cached and miss : " << m_cpt_data_write_miss << " (" << (float)m_cpt_data_write_miss*100.0/(float)m_cpt_data_write_cached << "%)" << std::endl; 382 // std::cout << "- WRITE RATE : " << (float)m_cpt_data_write/run_cycles << std::endl; 383 // std::cout << "- UNCACHED READ RATE : " << (float)m_cpt_data_read_uncached/m_cpt_data_read << std::endl ; 384 // std::cout << "- CACHED WRITE RATE : " << (float)m_cpt_data_write_cached/m_cpt_data_write << std::endl ; 385 // std::cout << "- IMISS_RATE : " << (float)m_cpt_ins_miss/run_cycles << std::endl; 386 // std::cout << "- DMISS RATE : " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_data_read_uncached) << std::endl ; 387 // std::cout << "- INS MISS COST : " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl; 388 // std::cout << "- IMISS TRANSACTION : " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl; 389 // std::cout << "- DMISS COST : " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl; 390 // std::cout << "- DMISS TRANSACTION : " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl; 391 // std::cout << "- UNC COST : " << (float)m_cost_unc_read_frz/m_cpt_data_read_uncached << std::endl; 392 // std::cout << "- UNC TRANSACTION : " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl; 393 // std::cout << "- WRITE COST : " << (float)m_cost_write_frz/m_cpt_data_write << std::endl; 394 // std::cout << "- WRITE TRANSACTION : " << (float)m_cost_write_transaction/m_cpt_data_write_transaction << std::endl; 395 // std::cout << "- WRITE LENGTH : " << (float)m_length_write_transaction/m_cpt_data_write_transaction << std::endl; 396 397 std::cout << "- CC_UPDATE_ICACHE : " << m_cpt_cc_update_icache << std::endl; 398 std::cout << " + AVERAGE WORD USEFUL : " << (float)m_cpt_cc_update_icache_word_useful/(float)m_cpt_cc_update_icache << " on " << m_icache_words << " words" << std::endl; 399 std::cout << "- CC_UPDATE_DCACHE : " << m_cpt_cc_update_dcache << std::endl; 400 std::cout << " + AVERAGE WORD USEFUL : " << (float)m_cpt_cc_update_dcache_word_useful/(float)m_cpt_cc_update_dcache << " on " << m_dcache_words << " words" << std::endl; 401 uint32_t m_cpt_cc_inval = m_cpt_cc_inval_broadcast+m_cpt_cc_inval_icache+m_cpt_cc_inval_dcache; 402 std::cout << "- CC_INVALID : " << m_cpt_cc_inval << std::endl; 403 std::cout << " + ICACHE Only : " << (float)m_cpt_cc_inval_icache *100.0/(float)m_cpt_cc_inval << "%" << std::endl; 404 std::cout << " + DCACHE Only : " << (float)m_cpt_cc_inval_dcache *100.0/(float)m_cpt_cc_inval << "%" << std::endl; 405 std::cout << " + BROADCAST : " << (float)m_cpt_cc_inval_broadcast*100.0/(float)m_cpt_cc_inval << "%" << std::endl; 406 std::cout << "* : accepted or not by the cache" << std::endl ; 407 408 r_wbuf.printStatistics(); 286 409 } 410 287 411 //////////////////////////////////// 288 412 tmpl(void)::print_trace(size_t mode) 289 413 //////////////////////////////////// 290 414 { 415 // b0 : write buffer print trace 416 // b1 : write buffer verbose 417 // b2 : dcache print trace 418 // b3 : icache print trace 419 291 420 typename iss_t::InstructionRequest ireq; 292 421 typename iss_t::DataRequest dreq; 422 293 423 m_iss.getRequests( ireq, dreq ); 294 295 std::cout << std::dec << "CC_XCACHE_WRAPPER " << name() << std::endl; 296 std::cout << " proc state : PC = " << std::hex << ireq.addr << " / AD = " << dreq.addr 297 << std::dec << " / V = " << dreq.valid << " / TYPE = " << dreq.type << std::endl; 298 std::cout << " cache state : " << icache_fsm_state_str[r_icache_fsm] << " / " 299 << dcache_fsm_state_str[r_dcache_fsm] << " / " 300 << cmd_fsm_state_str[r_vci_cmd_fsm] << " / " 301 << rsp_fsm_state_str[r_vci_rsp_fsm] << " / " 302 << tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl; 303 if( r_vci_tgt_fsm != TGT_IDLE ) 304 { 305 std::cout << " ... coherence request address = " << std::hex << r_tgt_addr.read() << std::endl; 306 } 424 std::cout << std::dec << "Proc \"" << name() << "\"" << std::endl; 425 std::cout << ireq << std::endl; 426 std::cout << dreq << std::endl; 427 std::cout << " " << dcache_fsm_state_str[r_dcache_fsm] 428 << " " << icache_fsm_state_str[r_icache_fsm] 429 << " " << cmd_fsm_state_str[r_vci_cmd_fsm] 430 << " " << rsp_fsm_state_str[r_vci_rsp_fsm] 431 << " " << tgt_fsm_state_str[r_vci_tgt_fsm] 432 << " " << cleanup_fsm_state_str[r_cleanup_fsm] << std::endl; 433 307 434 if(mode & 0x1) 308 435 { 309 r_wbuf.printTrace( );436 r_wbuf.printTrace((mode>>1)&1); 310 437 } 438 if(mode & 0x4) 439 { 440 std::cout << " Data cache" << std::endl; 441 r_dcache.printTrace(); 442 } 443 if(mode & 0x8) 444 { 445 std::cout << " Instruction cache" << std::endl; 446 r_icache.printTrace(); 447 } 448 449 // if(mode & 0x10) 450 // { 451 // std::cout << " Icache miss buffer : "; 452 // CACHE_MISS_BUF_RSP_PRINT(i); 453 // std::cout << std::endl; 454 455 // std::cout << " Dcache miss buffer : "; 456 // CACHE_MISS_BUF_RSP_PRINT(d); 457 // std::cout << std::endl; 458 // } 311 459 } 460 312 461 ////////////////////////// 313 462 tmpl(void)::transition() 314 463 ////////////////////////// 315 464 { 316 if ( !p_resetn.read() ) {465 if ( not p_resetn.read() ) { 317 466 318 467 m_iss.reset(); 319 468 320 469 // FSM states 321 r_dcache_fsm = DCACHE_IDLE;322 r_icache_fsm = ICACHE_IDLE;470 r_dcache_fsm = DCACHE_IDLE; 471 r_icache_fsm = ICACHE_IDLE; 323 472 r_vci_cmd_fsm = CMD_IDLE; 324 473 r_vci_rsp_fsm = RSP_IDLE; 325 474 r_vci_tgt_fsm = TGT_IDLE; 475 r_cleanup_fsm = CLEANUP_IDLE; 326 476 327 477 // write buffer & caches … … 337 487 r_dcache_unc_req = false; 338 488 r_dcache_sc_req = false; 339 r_dcache_write_req = false;340 489 r_dcache_cleanup_req = false; 490 r_dcache_previous_unc= false; 341 491 342 492 // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs 343 493 r_tgt_icache_req = false; 344 494 r_tgt_dcache_req = false; 495 r_tgt_icache_rsp = false; 496 r_tgt_dcache_rsp = false; 497 498 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 499 r_cache_word = 0; 500 #endif 501 345 502 346 503 // internal messages in DCACHE et ICACHE FSMs … … 351 508 r_dcache_ll_valid = false; 352 509 r_icache_buf_unc_valid = false; 510 511 r_vci_cmd_dcache_prior = false; 512 353 513 r_vci_rsp_data_error = false; 354 514 r_vci_rsp_ins_error = false; 515 516 CACHE_MISS_BUF_RESET(i); 517 CACHE_MISS_BUF_RESET(d); 355 518 356 519 // activity counters 357 520 m_cpt_dcache_data_read = 0; 358 521 m_cpt_dcache_data_write = 0; 359 m_cpt_dcache_dir_read = 0;360 m_cpt_dcache_dir_write = 0;522 m_cpt_dcache_dir_read = 0; 523 m_cpt_dcache_dir_write = 0; 361 524 m_cpt_icache_data_read = 0; 362 525 m_cpt_icache_data_write = 0; 363 m_cpt_icache_dir_read = 0; 364 m_cpt_icache_dir_write = 0; 365 366 m_cpt_cc_update = 0; 367 m_cpt_cc_inval = 0; 368 369 m_cpt_frz_cycles = 0; 526 m_cpt_icache_dir_read = 0; 527 m_cpt_icache_dir_write = 0; 528 529 m_cpt_cc_update_icache = 0; 530 m_cpt_cc_update_dcache = 0; 531 m_cpt_cc_inval_broadcast = 0; 532 m_cpt_cc_inval_icache = 0; 533 m_cpt_cc_inval_dcache = 0; 534 m_cpt_cc_update_icache_word_useful = 0; 535 m_cpt_cc_update_dcache_word_useful = 0; 536 537 m_cpt_frz_cycles = 0; 370 538 m_cpt_total_cycles = 0; 371 539 372 m_cpt_read = 0; 373 m_cpt_write = 0; 374 m_cpt_data_miss = 0; 375 m_cpt_ins_miss = 0; 376 m_cpt_unc_read = 0; 377 m_cpt_write_cached = 0; 540 m_cpt_data_read = 0; 541 m_cpt_data_read_miss = 0; 542 m_cpt_data_read_uncached = 0; 543 m_cpt_data_write = 0; 544 m_cpt_data_write_miss = 0; 545 m_cpt_data_write_uncached = 0; 546 547 m_cpt_ins_miss = 0; 378 548 379 549 m_cost_write_frz = 0; … … 385 555 m_cpt_dmiss_transaction = 0; 386 556 m_cpt_unc_transaction = 0; 387 m_cpt_ write_transaction = 0;557 m_cpt_data_write_transaction = 0; 388 558 389 559 m_cost_imiss_transaction = 0; … … 396 566 } 397 567 398 #if DEBUG_CC_XCACHE_WRAPPER 399 std::cout << "--------------------------------------------" << std::endl; 400 std::cout << std::dec << "CC_XCACHE_WRAPPER " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl; 401 std::cout << " tgt fsm = " << tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl 402 << " dcache fsm = " << dcache_fsm_state_str[r_dcache_fsm] << std::endl 403 << " icache fsm = " << icache_fsm_state_str[r_icache_fsm] << std::endl 404 << " cmd fsm = " << cmd_fsm_state_str[r_vci_cmd_fsm] << std::endl 405 << " rsp fsm = " << rsp_fsm_state_str[r_vci_rsp_fsm] << std::endl; 568 // printf("%d\n",(uint32_t)m_cpt_total_cycles); 569 570 PRINTF("--------------------------------------------\n"); 571 PRINTF(" * CC_XCACHE_WRAPPER \"%s\" - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); 572 PRINTF(" * fsm dcache = %s\n",dcache_fsm_state_str[r_dcache_fsm]); 573 PRINTF(" * fsm icache = %s\n",icache_fsm_state_str[r_icache_fsm]); 574 PRINTF(" * fsm cmd = %s\n",cmd_fsm_state_str[r_vci_cmd_fsm]); 575 PRINTF(" * fsm rsp = %s\n",rsp_fsm_state_str[r_vci_rsp_fsm]); 576 PRINTF(" * fsm tgt = %s\n",tgt_fsm_state_str[r_vci_tgt_fsm]); 577 PRINTF(" * fsm cleanup = %s\n",cleanup_fsm_state_str[r_cleanup_fsm]); 578 PRINTF(" * ll info : %d %llx %llx\n",r_dcache_ll_valid.read(), (uint64_t)r_dcache_ll_addr.read(), (uint64_t)r_dcache_ll_data.read()); 579 PRINTF(" * dcache_previous_unc : %d\n",r_dcache_previous_unc.read()); 580 // CACHE_MISS_BUF_RSP_PRINT(i); 581 // CACHE_MISS_BUF_RSP_PRINT(d); 582 583 #if CC_XCACHE_WRAPPER_DEBUG 584 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 585 { 586 r_wbuf.printTrace(1); 587 } 406 588 #endif 407 589 … … 444 626 if ( p_vci_tgt.cmdval.read() ) 445 627 { 628 PRINTF(" * <TGT> request\n"); 629 446 630 addr_40 address = p_vci_tgt.address.read(); 447 631 … … 450 634 std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; 451 635 std::cout << "coherence request is not a write" << std::endl; 452 std::cout << "oddress = " << std::hex << address << std:: endl;453 std::cout << "srcid = " << std::hex <<p_vci_tgt.srcid.read() << std::endl;636 std::cout << "oddress = " << std::hex << address << std::dec << std::endl; 637 std::cout << "srcid = " << p_vci_tgt.srcid.read() << std::endl; 454 638 exit(0); 455 639 } 456 640 457 641 // multi-update or multi-invalidate for data type 458 if ( ((address&0x3) != 0x3) && (!m_segment.contains(address)) )642 if ( ((address&0x3) != 0x3) and (not m_segment.contains(address)) ) 459 643 { 460 644 std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; 461 645 std::cout << "out of segment coherence request" << std::endl; 462 std::cout << "oddress = " << std::hex << address << std:: endl;463 std::cout << "srcid = " << std::hex <<p_vci_tgt.srcid.read() << std::endl;646 std::cout << "oddress = " << std::hex << address << std::dec << std::endl; 647 std::cout << "srcid = " << p_vci_tgt.srcid.read() << std::endl; 464 648 exit(0); 465 649 } … … 470 654 r_tgt_trdid = p_vci_tgt.trdid.read(); 471 655 r_tgt_pktid = p_vci_tgt.pktid.read(); 472 656 // r_tgt_plen = p_vci_tgt.plen.read(); 473 657 658 PRINTF(" * <TGT> address : %llx\n",(uint64_t)address); 659 PRINTF(" * <TGT> address : %llx\n",(uint64_t)((((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | 660 ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4)); 661 474 662 if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type 475 663 { 476 if ( !p_vci_tgt.eop.read() )664 if ( not p_vci_tgt.eop.read() ) 477 665 { 478 666 std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; … … 481 669 } 482 670 r_tgt_update = false; 483 r_tgt_brdcast= true;671 // r_tgt_brdcast= true; 484 672 r_vci_tgt_fsm = TGT_REQ_BROADCAST; 485 m_cpt_cc_inval ++ ;673 m_cpt_cc_inval_broadcast++ ; 486 674 } 487 675 else // multi-update or multi-invalidate for data type 488 676 { 489 677 uint32_t cell = address - m_segment.baseAddress(); // addr_40 490 r_tgt_brdcast = false;678 // r_tgt_brdcast = false; 491 679 if (cell == 0) 492 680 { // invalidate data 493 if ( !p_vci_tgt.eop.read() )681 if ( not p_vci_tgt.eop.read() ) 494 682 { 495 683 std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; … … 499 687 r_tgt_update = false; 500 688 r_vci_tgt_fsm = TGT_REQ_DCACHE; 501 m_cpt_cc_inval ++ ;689 m_cpt_cc_inval_dcache++ ; 502 690 } 503 691 else if (cell == 4) // invalidate instruction 504 692 { 505 if ( !p_vci_tgt.eop.read() )693 if ( not p_vci_tgt.eop.read() ) 506 694 { 507 695 std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; … … 511 699 r_tgt_update = false; 512 700 r_vci_tgt_fsm = TGT_REQ_ICACHE; 513 m_cpt_cc_inval ++ ;701 m_cpt_cc_inval_icache++ ; 514 702 } 515 else if ( (cell == 8) ||(cell==12) ) // update data or instruction703 else if ( (cell == 8) or (cell==12) ) // update data or instruction 516 704 { 517 705 if ( p_vci_tgt.eop.read() ) … … 522 710 } 523 711 if(cell == 8) 712 { 713 m_cpt_cc_update_dcache++; 524 714 r_tgt_update_data = true; 715 } 525 716 else 717 { 718 m_cpt_cc_update_icache++; 526 719 r_tgt_update_data = false; 720 } 527 721 r_tgt_update = true; 528 722 r_vci_tgt_fsm = TGT_UPDT_WORD; 529 m_cpt_cc_update++ ;530 723 } 531 724 … … 556 749 { 557 750 size_t word = r_tgt_word.read(); 558 if ( word >= m_ dcache_words )751 if ( word >= m_cache_words ) 559 752 { 560 753 std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; … … 565 758 std::cout << "PROC " << m_srcid_rw << " update, data : " << p_vci_tgt.wdata.read() << " be : " << std::hex << p_vci_tgt.be.read() << std::dec << std::endl; 566 759 #endif 760 567 761 r_tgt_buf[word] = p_vci_tgt.wdata.read(); 568 r_tgt_be[word] = p_vci_tgt.be.read(); 762 r_tgt_be [word] = p_vci_tgt.be.read(); 763 764 if (p_vci_tgt.be.read()) 765 { 766 if(r_tgt_update_data.read()) 767 m_cpt_cc_update_dcache_word_useful++ ; 768 else 769 m_cpt_cc_update_icache_word_useful++ ; 770 } 771 569 772 r_tgt_word = word + 1; 570 773 if (p_vci_tgt.eop.read()){ 774 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 775 uint32_t word=0; 776 for (; word<m_cache_words; ++word) 777 if (r_tgt_be[word] != 0) 778 break; 779 r_cache_word = word; 780 #endif 571 781 if(r_tgt_update_data.read()){ 572 782 r_vci_tgt_fsm = TGT_REQ_DCACHE; … … 579 789 580 790 case TGT_REQ_BROADCAST: 581 if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )791 if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) 582 792 { 583 793 r_vci_tgt_fsm = TGT_RSP_BROADCAST; … … 589 799 case TGT_REQ_ICACHE: 590 800 { 591 if ( !r_tgt_icache_req.read() )801 if ( not r_tgt_icache_req.read() ) 592 802 { 593 803 r_vci_tgt_fsm = TGT_RSP_ICACHE; … … 598 808 599 809 case TGT_REQ_DCACHE: 600 if ( !r_tgt_dcache_req.read() )810 if ( not r_tgt_dcache_req.read() ) 601 811 { 602 812 r_vci_tgt_fsm = TGT_RSP_DCACHE; … … 606 816 607 817 case TGT_RSP_BROADCAST: 608 if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )818 if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) 609 819 { 610 820 // one response 611 if ( !r_tgt_icache_rsp || !r_tgt_dcache_rsp )821 if ( not r_tgt_icache_rsp or not r_tgt_dcache_rsp ) 612 822 { 613 823 if ( p_vci_tgt.rspack.read() ) … … 620 830 621 831 // if data and instruction have the inval line, need two responses 622 if ( r_tgt_icache_rsp &&r_tgt_dcache_rsp )832 if ( r_tgt_icache_rsp and r_tgt_dcache_rsp ) 623 833 { 624 834 if ( p_vci_tgt.rspack.read() ) … … 629 839 630 840 // if there is no need for a response 631 if ( !r_tgt_icache_rsp && !r_tgt_dcache_rsp )841 if ( not r_tgt_icache_rsp and not r_tgt_dcache_rsp ) 632 842 { 633 843 r_vci_tgt_fsm = TGT_IDLE; … … 639 849 case TGT_RSP_ICACHE: 640 850 { 641 if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() )851 if ( (p_vci_tgt.rspack.read() or not r_tgt_icache_rsp.read()) and not r_tgt_icache_req.read() ) 642 852 { 643 853 r_vci_tgt_fsm = TGT_IDLE; … … 649 859 case TGT_RSP_DCACHE: 650 860 { 651 if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )861 if ( (p_vci_tgt.rspack.read() or not r_tgt_dcache_rsp.read()) and not r_tgt_dcache_req.read() ) 652 862 { 653 863 r_vci_tgt_fsm = TGT_IDLE; … … 667 877 // - r_icache_unc_req set 668 878 // - r_icache_buf_unc_valid set 879 // - r_vci_rsp_icache_miss_ok reset 669 880 // - r_vci_rsp_ins_error reset 670 881 // - r_tgt_icache_req reset … … 692 903 typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER; 693 904 694 typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;695 typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;905 typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER; 906 typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER; 696 907 697 908 m_iss.getRequests( ireq, dreq ); 698 909 699 #if DEBUG_CC_XCACHE_WRAPPER 700 std::cout << " Instruction Request: " << ireq << std::endl; 910 #if CC_XCACHE_WRAPPER_DEBUG 911 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 912 std::cout << " * Instruction Request : " << ireq << std::endl; 701 913 #endif 702 914 … … 715 927 bool icache_hit = false; 716 928 bool icache_cached = m_cacheability_table[(vci_addr_t)ireq.addr]; 929 bool icache_cleanup_hit = r_icache_cleanup_req and (((addr_40)ireq.addr >> (addr_40)m_icache_words_shift) == r_icache_cleanup_line.read()); 930 717 931 // icache_hit & icache_ins evaluation 718 932 if ( icache_cached ) { 719 933 icache_hit = r_icache.read((vci_addr_t) ireq.addr, &icache_ins); 720 934 } else { 721 icache_hit = ( r_icache_buf_unc_valid && ((addr_40) ireq.addr == (addr_40)r_icache_addr_save) ); 722 icache_ins = r_icache_miss_buf[0]; 935 // if uncache, again in the icache_miss_buf 936 icache_hit = ( r_icache_buf_unc_valid and ((addr_40) ireq.addr == (addr_40)r_icache_addr_save)); 937 icache_ins = CACHE_MISS_BUF_RSP_DATA(i,0); 938 CACHE_MISS_BUF_RSP_POP(i); 723 939 } 724 if ( ! icache_hit ) { 940 941 PRINTF(" * <ICACHE> hit %d - cached %d - cleanup_hit %d\n",icache_hit, icache_cached, icache_cleanup_hit); 942 943 ASSERT( not (icache_hit and icache_cleanup_hit), 944 "Icache hit and icache_cleanup_hit"); 945 946 if ( not icache_hit and not icache_cleanup_hit) { 725 947 m_cpt_ins_miss++; 726 948 m_cost_ins_miss_frz++; 727 949 r_icache_addr_save = (addr_40) ireq.addr; 950 951 CACHE_MISS_BUF_REQ_INIT(i); 952 728 953 if ( icache_cached ) { 954 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 955 r_icache_fsm = ICACHE_MISS_VICTIM; 956 #else 729 957 r_icache_fsm = ICACHE_MISS_WAIT; 958 #endif 730 959 r_icache_miss_req = true; 960 731 961 } else { 732 962 r_icache_fsm = ICACHE_UNC_WAIT; … … 744 974 } 745 975 ////////////////////// 976 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 977 case ICACHE_MISS_VICTIM: 978 { 979 if (not r_icache_cleanup_req) 980 { 981 size_t way; 982 size_t set; 983 vci_addr_t addr = (vci_addr_t) r_icache_addr_save.read(); 984 vci_addr_t victim; 985 986 r_icache_cleanup_req = r_icache.victim_select(addr, &victim, &way, &set ); 987 r_icache_cleanup_line = (addr_40) victim; 988 r_icache_miss_way = way; 989 r_icache_miss_set = set; 990 991 r_icache_fsm = ICACHE_MISS_WAIT; 992 } 993 break; 994 } 995 #endif 996 ////////////////////// 746 997 case ICACHE_MISS_WAIT: 747 998 { … … 751 1002 r_icache_fsm_save = r_icache_fsm.read(); 752 1003 break; 753 } 754 if ( !r_icache_miss_req && !r_icache_inval_rsp ) { // Miss read response and no invalidation 755 if ( r_vci_rsp_ins_error ) { 756 r_icache_fsm = ICACHE_ERROR; 757 } else { 758 r_icache_fsm = ICACHE_MISS_UPDT; 759 } 760 } 761 if ( !r_icache_miss_req && r_icache_inval_rsp ) { // Miss read response and invalidation 762 if ( r_vci_rsp_ins_error ) { 763 r_icache_inval_rsp = false; 764 r_icache_fsm = ICACHE_ERROR; 765 } else { 766 r_icache_inval_rsp = false; 767 r_icache_fsm = ICACHE_CC_CLEANUP; 768 } 1004 } 1005 1006 bool val = CACHE_MISS_BUF_RSP_VAL(i,0); 1007 1008 PRINTF(" * <ICACHE> val : %d\n",val); 1009 1010 if (val) 1011 { 1012 PRINTF(" * <ICACHE> r_icache_inval_rsp : %d\n",(int) r_icache_inval_rsp ); 1013 PRINTF(" * <ICACHE> r_vci_rsp_ins_error : %d\n",(int) r_vci_rsp_ins_error ); 1014 PRINTF(" * <ICACHE> r_icache_cleanup_req : %d\n",(int) r_icache_cleanup_req); 1015 1016 // if (not r_icache_inval_rsp ) 1017 // { 1018 // Miss read response and no invalidation 1019 if ( r_vci_rsp_ins_error ) { 1020 r_icache_fsm = ICACHE_ERROR; 1021 } else { 1022 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM 1023 if (not r_icache_cleanup_req.read()) 1024 #endif 1025 { 1026 r_icache_update_addr = 0; 1027 r_icache_fsm = ICACHE_MISS_UPDT; 1028 } 1029 } 1030 // } 1031 // else 1032 // { 1033 // r_icache_inval_rsp = false; 1034 1035 // // Miss read response and invalidation 1036 // if ( r_vci_rsp_ins_error ) 1037 // r_icache_fsm = ICACHE_ERROR; 1038 // else 1039 // r_icache_fsm = ICACHE_CC_CLEANUP; 1040 // } 769 1041 } 770 1042 break; … … 778 1050 r_icache_fsm_save = r_icache_fsm.read(); 779 1051 break; 780 } 781 if ( !r_icache_unc_req ) { 1052 } 1053 1054 bool ok = CACHE_MISS_BUF_RSP_VAL(i,0); 1055 1056 if (ok) 1057 { 782 1058 if ( r_vci_rsp_ins_error ) { 783 1059 r_icache_fsm = ICACHE_ERROR; … … 803 1079 case ICACHE_MISS_UPDT: 804 1080 { 805 if ( r_tgt_icache_req ) { // external request 806 r_icache_fsm = ICACHE_CC_CHECK; 807 r_icache_fsm_save = r_icache_fsm.read(); 808 break; 809 } 810 if(!r_icache_cleanup_req.read() && !r_icache_inval_rsp){ 811 vci_addr_t ad = 0; 812 ad = (vci_addr_t) r_icache_addr_save.read(); 813 data_t* buf = r_icache_miss_buf; 814 vci_addr_t victim_index = 0; 815 m_cpt_icache_dir_write++; 816 m_cpt_icache_data_write++; 817 if ( ireq.valid ) m_cost_ins_miss_frz++; 818 819 r_icache_cleanup_req = r_icache.update(ad, buf, &victim_index); 820 r_icache_cleanup_line = (addr_40) victim_index; 821 822 r_icache_fsm = ICACHE_IDLE; 823 break; 824 } 825 if(r_icache_inval_rsp){ 826 if ( ireq.valid ) m_cost_ins_miss_frz++; 827 r_icache_inval_rsp = false; 828 r_icache_fsm = ICACHE_CC_CLEANUP; 829 break; 830 } 831 if ( ireq.valid ) m_cost_ins_miss_frz++; 1081 size_t word = r_icache_update_addr.read(); 1082 vci_addr_t addr = (vci_addr_t) r_icache_addr_save.read(); 1083 size_t way = 0; 1084 size_t set = 0; 1085 1086 // need invalid rsp, don't select a victim 1087 if (not r_icache_inval_rsp ) 1088 { 1089 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1090 way = r_icache_miss_way.read(); 1091 set = r_icache_miss_set.read(); 1092 #else 1093 1094 // First word : select an victim ! 1095 if (word == 0) 1096 { 1097 vci_addr_t victim; 1098 1099 // r_icache_cleanup_req is false because is the transition condition to go in ICACHE_MISS_UPDT state 1100 r_icache_cleanup_req = r_icache.victim_select(addr, &victim, &way, &set ); 1101 r_icache.victim_update_tag(addr, way, set); 1102 1103 r_icache_cleanup_line = (addr_40) victim; 1104 r_icache_miss_way = way; 1105 r_icache_miss_set = set; 1106 } 1107 else 1108 { 1109 way = r_icache_miss_way.read(); 1110 set = r_icache_miss_set.read(); 1111 } 1112 #endif 1113 } 1114 bool val = CACHE_MISS_BUF_RSP_VAL(i,word); 1115 1116 if (val) 1117 { 1118 PRINTF(" * <ICACHE> rsp_val : %d/%d\n",(int)r_icache_update_addr,m_icache_words); 1119 PRINTF(" * <ICACHE> r_icache_inval_rsp : %d\n",(int)r_icache_inval_rsp); 1120 PRINTF(" * <ICACHE> ins : %x\n",(int)CACHE_MISS_BUF_RSP_DATA(i,word)); 1121 1122 // m_cpt_icache_dir_write++; 1123 // m_cpt_icache_data_write++; 1124 // if ( ireq.valid ) m_cost_ins_miss_frz++; 1125 1126 // if need invalid rsp, don't modify the cache, but pop the buf_rsp 1127 if (not r_icache_inval_rsp ) 1128 r_icache.write(way, set, word, CACHE_MISS_BUF_RSP_DATA(i,word)); 1129 CACHE_MISS_BUF_RSP_POP(i); 1130 1131 r_icache_update_addr = ++word; 1132 1133 // if last word, finish the update 1134 if (word >= m_icache_words) 1135 { 1136 // Last word : if previous invalid_rsp, can cleanup, else update the TAG 1137 if (r_icache_inval_rsp) 1138 { 1139 r_icache_inval_rsp = false; 1140 r_icache_fsm = ICACHE_CC_CLEANUP; 1141 } 1142 else 1143 { 1144 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1145 r_icache.victim_update_tag(addr, way, set); 1146 #endif 1147 r_icache_fsm = ICACHE_IDLE; 1148 } 1149 } 1150 } 1151 1152 break; 832 1153 } 833 1154 //////////////////// … … 842 1163 } 843 1164 // cleanup 844 if( !r_icache_cleanup_req){1165 if(not r_icache_cleanup_req){ 845 1166 r_icache_cleanup_req = true; 846 r_icache_cleanup_line = r_icache_addr_save.read() >> (uint32_log2(m_icache_words) + 2);1167 r_icache_cleanup_line = r_icache_addr_save.read() >> m_icache_words_shift; 847 1168 r_icache_fsm = ICACHE_IDLE; 848 1169 } … … 853 1174 { 854 1175 855 m_cpt_icache_dir_read += m_icache_ways;1176 m_cpt_icache_dir_read += m_icache_ways; 856 1177 m_cpt_icache_data_read += m_icache_ways; 857 addr_40 ad= r_tgt_addr;1178 addr_40 ad = r_tgt_addr; 858 1179 data_t icache_rdata = 0; 859 1180 860 if(( ( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) &&1181 if((r_icache_fsm_save == ICACHE_MISS_WAIT) and 861 1182 ( (r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) { 862 1183 r_icache_inval_rsp = true; … … 870 1191 } else { 871 1192 bool icache_hit = r_icache.read(ad, &icache_rdata); 872 if ( icache_hit && r_tgt_update ) { 1193 if ( icache_hit and r_tgt_update ) 1194 { 1195 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1196 uint32_t word = r_cache_word; 1197 data_t mask = vci_param::be2mask(r_tgt_be[word]); 1198 data_t rdata = 0; 1199 1200 r_icache.read(ad+word*4,&rdata); 1201 r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); 1202 1203 word ++; 1204 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1205 for (; word<m_icache_words; ++word) 1206 if (r_tgt_be[word] != 0) 1207 break; 1208 #endif 1209 1210 if (word==m_icache_words) 1211 { 1212 r_icache_fsm = ICACHE_CC_UPDT; 1213 1214 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1215 for (word=0; word<m_icache_words; ++word) 1216 if (r_tgt_be[word] != 0) 1217 break; 1218 #else 1219 word = 0; 1220 #endif 1221 } 1222 r_cache_word = word; 1223 #else //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 873 1224 r_icache_fsm = ICACHE_CC_UPDT; 874 1225 // complete the line buffer in case of update … … 879 1230 r_tgt_buf[i] = (mask & r_tgt_buf[i]) | (~mask & rdata); 880 1231 } 881 } else if ( icache_hit && !r_tgt_update ) { 1232 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1233 } else if ( icache_hit and not r_tgt_update ) { 882 1234 r_icache_fsm = ICACHE_CC_INVAL; 883 1235 } else { // instruction not found (can happen) … … 908 1260 case ICACHE_CC_UPDT: 909 1261 { 1262 addr_40 ad = r_tgt_addr.read(); 910 1263 m_cpt_icache_dir_write++; 911 1264 m_cpt_icache_data_write++; 912 addr_40 ad = r_tgt_addr.read(); 1265 1266 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1267 uint32_t word = r_cache_word; 1268 1269 if(r_tgt_be[word]) 1270 r_icache.write(ad+word*4, r_tgt_buf[word]); 1271 1272 word ++; 1273 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1274 for (; word<m_icache_words; ++word) 1275 if (r_tgt_be[word] != 0) 1276 break; 1277 #endif 1278 1279 if (word==m_icache_words) 1280 { 1281 r_tgt_icache_req = false; 1282 r_tgt_icache_rsp = true; 1283 r_icache_fsm = r_icache_fsm_save.read(); 1284 word = 0; 1285 } 1286 r_cache_word = word; 1287 #else //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 913 1288 data_t* buf = r_tgt_buf; 914 1289 for(size_t i=0; i<m_icache_words;i++){ … … 918 1293 r_tgt_icache_rsp = true; 919 1294 r_icache_fsm = r_icache_fsm_save.read(); 1295 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1296 920 1297 break; 921 1298 } … … 923 1300 } // end switch r_icache_fsm 924 1301 925 #if DEBUG_CC_XCACHE_WRAPPER 926 std::cout << " Instruction Response: " << irsp << std::endl; 1302 #if CC_XCACHE_WRAPPER_DEBUG 1303 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 1304 std::cout << " * Instruction Response : " << irsp << std::endl; 927 1305 #endif 928 1306 … … 940 1318 // - r_dcache_miss_req set 941 1319 // - r_dcache_unc_req set 942 // - r_dcache_write_req set943 1320 // - r_dcache_cleanup_req set 944 1321 // - r_vci_rsp_data_error reset … … 984 1361 /////////////////////////////////////////////////////////////////////////////////// 985 1362 986 #if DEBUG_CC_XCACHE_WRAPPER 987 std::cout << " Data Request: " << dreq << std::endl; 988 #endif 989 990 //if( (m_cpt_total_cycles % 10000) ==0 ) std::cout << std::dec << "Proc " << m_srcid << " Data Request: " << dreq << std::endl; 1363 #if CC_XCACHE_WRAPPER_DEBUG 1364 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 1365 std::cout << " * Data Request : " << dreq << std::endl; 1366 #endif 991 1367 992 1368 switch ( r_dcache_fsm ) { 993 1369 994 /////////////////////995 case DCACHE_WRITE_REQ:996 {997 if ( r_tgt_dcache_req ) { // external request998 r_dcache_fsm = DCACHE_CC_CHECK;999 r_dcache_fsm_save = r_dcache_fsm;1000 break;1001 }1002 // try to post the write request in the write buffer1003 if ( !r_dcache_write_req ) { // no previous write transaction1004 if ( r_wbuf.wok(r_dcache_addr_save) ) { // write request in the same cache line1005 r_wbuf.write(r_dcache_addr_save, r_dcache_be_save, r_dcache_wdata_save);1006 // close the write packet if uncached1007 if ( !r_dcache_cached_save ){1008 r_dcache_write_req = true ;1009 }1010 } else {1011 // close the write packet if write request not in the same cache line1012 r_dcache_write_req = true;1013 if(!m_srcid_rw) {1014 }1015 m_cost_write_frz++;1016 break; // posting request not possible : stay in DCACHE_WRITEREQ state1017 }1018 } else { // previous write transaction not completed1019 m_cost_write_frz++;1020 break; // posting request not possible : stay in DCACHE_WRITEREQ state1021 }1022 1023 // close the write packet if the next processor request is not a write1024 if ( !dreq.valid || (dreq.type != iss_t::DATA_WRITE) ) {1025 r_dcache_write_req = true ;1026 }1027 1028 // The next state and the processor request parameters are computed1029 // as in the DCACHE_IDLE state (see below ...)1030 }1031 1370 ///////////////// 1032 1371 case DCACHE_IDLE: … … 1038 1377 } 1039 1378 1040 if ( dreq.valid ) { 1041 bool dcache_hit = false; 1042 data_t dcache_rdata = 0; 1043 bool dcache_cached; 1379 if ( dreq.valid ) { 1380 PRINTF(" * <DCACHE> Have dreq\n"); 1381 1382 data_t dcache_rdata = 0; 1383 // dcache_cached and dcache_hit don't used with dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} 1384 bool dcache_cached = m_cacheability_table[(vci_addr_t)dreq.addr]; 1385 bool dcache_hit = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata); 1386 bool dcache_cleanup_hit = r_dcache_cleanup_req and (((addr_40)dreq.addr >> (addr_40)m_dcache_words_shift) == r_dcache_cleanup_line.read()); 1387 1388 PRINTF(" * <DCACHE> hit %d - cached %d - cleanup_hit %d\n",dcache_hit, dcache_cached, dcache_cleanup_hit); 1389 1044 1390 m_cpt_dcache_data_read += m_dcache_ways; 1045 m_cpt_dcache_dir_read += m_dcache_ways; 1046 1047 // dcache_cached evaluation 1048 switch (dreq.type) { 1049 case iss_t::DATA_SC: 1050 case iss_t::XTN_READ: 1051 case iss_t::XTN_WRITE: 1052 dcache_cached = false; 1053 break; 1054 default: 1055 dcache_cached = m_cacheability_table[(vci_addr_t)dreq.addr]; 1056 } 1057 1058 // dcache_hit & dcache_rdata evaluation 1059 if ( dcache_cached ) { 1060 dcache_hit = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata); 1061 } else { 1062 dcache_hit = false; 1063 } 1391 m_cpt_dcache_dir_read += m_dcache_ways; 1064 1392 1065 1393 switch( dreq.type ) { 1066 1394 case iss_t::DATA_READ: 1067 1395 case iss_t::DATA_LL: 1068 m_cpt_read++; 1069 if ( dcache_hit ) { 1070 r_dcache_fsm = DCACHE_IDLE; 1071 drsp.valid = true; 1072 drsp.rdata = dcache_rdata; 1073 if(dreq.type == iss_t::DATA_LL){ 1074 r_dcache_ll_valid = true; 1075 r_dcache_ll_data = dcache_rdata; 1076 r_dcache_ll_addr = (vci_addr_t) dreq.addr; 1396 { 1397 m_cpt_data_read++; // new dcache read 1398 1399 if (dcache_hit) // no special test for uncached read, because it's always miss 1400 { 1401 // address is in the cache : return the word 1402 r_dcache_fsm = DCACHE_IDLE; 1403 drsp.valid = true; 1404 drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) 1405 1406 // if the request is a Load Linked instruction, save request information 1407 if(dreq.type == iss_t::DATA_LL) 1408 { 1409 PRINTF(" * <DCACHE> ll_valid = true\n"); 1410 1411 r_dcache_ll_valid = true; 1412 r_dcache_ll_data = dcache_rdata; 1413 r_dcache_ll_addr = (vci_addr_t) dreq.addr; 1077 1414 #ifdef COHERENCE_DEBUG 1078 std::cout << "Value returned for LL at address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; 1079 r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata); 1080 std::cout << "Value stored at this address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; 1081 #endif 1082 } 1083 } else { 1084 if ( dcache_cached ) { 1085 m_cpt_data_miss++; 1086 m_cost_data_miss_frz++; 1087 r_dcache_miss_req = true; 1088 r_dcache_fsm = DCACHE_MISS_WAIT; 1089 } else { 1090 m_cpt_unc_read++; 1091 m_cost_unc_read_frz++; 1092 r_dcache_unc_req = true; 1093 r_dcache_fsm = DCACHE_UNC_WAIT; 1094 } 1415 std::cout << "Value returned for LL at address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; 1416 r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata); 1417 std::cout << "Value stored at this address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; 1418 #endif 1419 } 1420 } 1421 else 1422 { 1423 if (not dcache_cleanup_hit) 1424 { 1425 CACHE_MISS_BUF_REQ_INIT(d); 1426 1427 // Miss : send signal at the CMD_FSM (via r_dcache_miss_req or r_dcache_unc_req) 1428 if ( dcache_cached ) { 1429 m_cpt_data_read_miss++; 1430 m_cost_data_miss_frz++; 1431 r_dcache_miss_req = true; 1432 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1433 r_dcache_fsm = DCACHE_MISS_VICTIM; 1434 #else 1435 r_dcache_fsm = DCACHE_MISS_WAIT; 1436 #endif 1437 1438 } else { 1439 if (not r_dcache_previous_unc.read()) // strongly order to the uncached access 1440 { 1441 r_dcache_previous_unc = true; 1442 1443 m_cpt_data_read_uncached++; 1444 m_cost_unc_read_frz++; 1445 r_dcache_unc_req = true; 1446 r_dcache_fsm = DCACHE_UNC_WAIT; 1447 } 1448 } 1449 } 1450 } 1095 1451 } 1096 1452 break; 1097 1453 case iss_t::DATA_SC: 1098 1454 { 1099 m_cpt_unc_read++; 1100 m_cost_unc_read_frz++; 1101 if(r_dcache_ll_valid.read() && (r_dcache_ll_addr.read() == (vci_addr_t)dreq.addr)){ 1102 r_dcache_sc_req = true; 1103 r_dcache_fsm = DCACHE_SC_WAIT; 1104 } else { 1105 drsp.valid = true; 1106 drsp.rdata = 1; // SC rsp NOK 1107 r_dcache_ll_valid = false; 1455 PRINTF(" * <DCACHE> DATA_SC - ll_valid = %d\n",r_dcache_ll_valid.read()); 1456 1457 if (not r_dcache_previous_unc.read() and not dcache_cleanup_hit) // strongly order to the uncached access 1458 { 1459 //m_cpt_data_read_unc++; // instruction must read the memory in uncached mode 1460 m_cost_unc_read_frz++; 1461 1462 // if previous load linked (with the same address), make a transaction 1463 // else, keep in IDLE state and return 1 (no OK) 1464 if(r_dcache_ll_valid.read() and (r_dcache_ll_addr.read() == (vci_addr_t)dreq.addr)){ 1465 PRINTF(" * <DCACHE> have previous load linked\n"); 1466 1467 r_dcache_previous_unc = true; 1468 1469 r_dcache_sc_req = true; 1470 1471 CACHE_MISS_BUF_REQ_INIT(d); 1472 1473 r_dcache_fsm = DCACHE_SC_WAIT; 1474 } else { 1475 PRINTF(" * <DCACHE> don't have previous load linked\n"); 1476 1477 drsp.valid = true; 1478 drsp.rdata = 1; // SC rsp NOK 1479 r_dcache_ll_valid = false; 1480 } 1108 1481 } 1482 1109 1483 break; 1110 1484 } 1111 1485 case iss_t::XTN_READ: 1112 1486 case iss_t::XTN_WRITE: 1113 // only DCACHE INVALIDATE request are supported 1114 if ( dreq.addr/4 == iss_t::XTN_DCACHE_INVAL ){ 1115 r_dcache_fsm = DCACHE_INVAL; 1116 } else { 1117 r_dcache_fsm = DCACHE_IDLE; 1118 } 1119 drsp.valid = true; 1487 { 1488 bool drsp_valid = false; 1489 // only DCACHE INVALIDATE and SYNC request are supported 1490 switch (dreq.addr>>2) 1491 { 1492 case iss_t::XTN_DCACHE_INVAL : 1493 { 1494 drsp_valid = true; 1495 r_dcache_fsm = DCACHE_INVAL; 1496 break; 1497 } 1498 case iss_t::XTN_SYNC : 1499 { 1500 // Test if write buffer is already empty 1501 // * gain : 1 cycle 1502 // * cost : can be on the critical path 1503 if (r_wbuf.empty()) 1504 { 1505 drsp_valid = true; 1506 r_dcache_fsm = DCACHE_IDLE; 1507 } 1508 else 1509 { 1510 drsp_valid = false; 1511 r_dcache_fsm = DCACHE_SYNC; 1512 } 1513 break; 1514 } 1515 default : 1516 { 1517 // std::cout << "Warning in VCI_CC_XCACHE_WRAPPER " << name() << std::endl; 1518 // std::cout << "Unsupported external access : " << (dreq.addr>>2) << std::endl; 1519 1520 r_dcache_fsm = DCACHE_IDLE; 1521 } 1522 }//end switch (dreq.addr>>2) 1523 1524 drsp.valid = drsp_valid; 1120 1525 drsp.rdata = 0; 1121 1526 break; 1527 } 1122 1528 case iss_t::DATA_WRITE: 1123 m_cpt_write++; 1124 if ( dcache_hit && dcache_cached ) { 1125 r_dcache_fsm = DCACHE_WRITE_UPDT; 1126 m_cpt_write_cached++; 1127 } else { 1128 r_dcache_fsm = DCACHE_WRITE_REQ; 1529 1530 if (dcache_cached or not r_dcache_previous_unc.read()) // strongly order to the uncached access 1531 { 1532 bool drsp_valid; 1533 1534 drsp_valid = r_wbuf.write((addr_40) dreq.addr, dreq.be, dreq.wdata, dcache_cached); 1535 1536 if (drsp_valid) 1537 { 1538 m_cpt_data_write++; 1539 1540 if (not dcache_cached) 1541 { 1542 r_dcache_previous_unc = true; 1543 m_cpt_data_write_uncached++; 1544 } 1545 else if (not dcache_hit) 1546 m_cpt_data_write_miss++; 1547 1548 if ( dcache_hit) { 1549 r_dcache_fsm = DCACHE_WRITE_UPDT; 1550 } else { 1551 r_dcache_fsm = DCACHE_IDLE; 1552 } 1129 1553 } 1130 drsp.valid = true; 1554 1555 drsp.valid = drsp_valid; 1131 1556 drsp.rdata = 0; 1132 break; 1557 } 1558 break; 1133 1559 } // end switch dreq.type 1134 1560 … … 1139 1565 r_dcache_rdata_save = dcache_rdata; 1140 1566 r_dcache_cached_save = dcache_cached; 1141 1567 1142 1568 } else { // end if dreq.valid 1143 1569 r_dcache_fsm = DCACHE_IDLE; 1144 1570 } 1145 // processor request are not accepted in the WRITE_REQUEST state 1146 // when the write buffer is not writeable 1147 if ( (r_dcache_fsm == DCACHE_WRITE_REQ) && 1148 (r_dcache_write_req || !r_wbuf.wok(r_dcache_addr_save)) ) { 1149 drsp.valid = false; 1150 drsp.rdata = 0; 1151 } 1571 1152 1572 break; 1153 1573 } … … 1160 1580 vci_addr_t ad = r_dcache_addr_save.read(); 1161 1581 r_dcache.write(ad, wdata); 1162 r_dcache_fsm = DCACHE_WRITE_REQ; 1582 1583 r_dcache_fsm = DCACHE_IDLE; 1584 1163 1585 break; 1164 1586 } 1587 ////////////////////// 1588 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1589 case DCACHE_MISS_VICTIM: 1590 { 1591 if (not r_dcache_cleanup_req.read()) 1592 { 1593 size_t way; 1594 size_t set; 1595 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save.read(); 1596 vci_addr_t victim; 1597 1598 r_dcache_cleanup_req = r_dcache.victim_select(addr, &victim, &way, &set ); 1599 r_dcache_cleanup_line = (addr_40) victim; 1600 r_dcache_miss_way = way; 1601 r_dcache_miss_set = set; 1602 1603 r_dcache_fsm = DCACHE_MISS_WAIT; 1604 } 1605 1606 break; 1607 } 1608 #endif 1165 1609 ////////////////////// 1166 1610 case DCACHE_MISS_WAIT: … … 1173 1617 break; 1174 1618 } 1175 if ( !r_dcache_miss_req && !r_dcache_inval_rsp ) { // Miss read response and no invalidation 1176 if ( r_vci_rsp_data_error ) { 1619 1620 bool val = CACHE_MISS_BUF_RSP_VAL(d,0); 1621 if (val) 1622 { 1623 // if (not r_dcache_inval_rsp ) 1624 // { 1625 1626 // Miss read response and no invalidation 1627 if ( r_vci_rsp_data_error ) 1628 { 1177 1629 r_dcache_fsm = DCACHE_ERROR; 1178 } else { 1179 r_dcache_fsm = DCACHE_MISS_UPDT; 1630 } 1631 else 1632 { 1633 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM 1634 if (not r_dcache_cleanup_req.read()) 1635 #endif 1636 { 1637 r_dcache_update_addr = 0; 1638 r_dcache_fsm = DCACHE_MISS_UPDT; 1639 } 1180 1640 } 1181 break; 1182 } 1183 if ( !r_dcache_miss_req && r_dcache_inval_rsp ) { // Miss read response and invalidation 1184 if ( r_vci_rsp_data_error ) { 1185 r_dcache_inval_rsp = false; 1186 r_dcache_fsm = DCACHE_ERROR; 1187 } else { 1188 r_dcache_inval_rsp = false; 1189 r_dcache_fsm = DCACHE_CC_CLEANUP; 1190 } 1191 break; 1641 // } 1642 // else 1643 // { 1644 // r_dcache_inval_rsp = false; 1645 1646 // // Miss read response and invalidation 1647 // if ( r_vci_rsp_data_error ) { 1648 // r_dcache_fsm = DCACHE_ERROR; 1649 // } else { 1650 // r_dcache_fsm = DCACHE_CC_CLEANUP; 1651 // } 1652 // } 1192 1653 } 1193 1654 break; … … 1195 1656 ////////////////////// 1196 1657 case DCACHE_MISS_UPDT: 1197 1198 { 1199 if ( r_tgt_dcache_req.read() ) { // external request 1200 r_dcache_fsm = DCACHE_CC_CHECK; 1201 r_dcache_fsm_save = r_dcache_fsm; 1202 break; 1203 } 1204 if( !r_dcache_cleanup_req.read() && !r_dcache_inval_rsp ){ 1205 vci_addr_t ad = 0; 1206 ad = (vci_addr_t) r_dcache_addr_save.read(); 1207 data_t* buf = new data_t[m_dcache_words]; 1208 for(size_t i=0; i<m_dcache_words; i++) { 1209 buf[i] = r_dcache_miss_buf[i]; 1658 { 1659 size_t word = r_dcache_update_addr.read(); 1660 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save.read(); 1661 size_t way = 0; 1662 size_t set = 0; 1663 1664 // need invalid rsp, don't select a victim 1665 if (not r_dcache_inval_rsp ) 1666 { 1667 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1668 way = r_dcache_miss_way.read(); 1669 set = r_dcache_miss_set.read(); 1670 #else 1671 // First word : select an victim ! 1672 if (word == 0) 1673 { 1674 vci_addr_t victim; 1675 1676 // r_dcache_cleanup_req is false (condition to enter in DCACHE_MISS_UPDT 1677 r_dcache_cleanup_req = r_dcache.victim_select(addr, &victim, &way, &set ); 1678 r_dcache.victim_update_tag(addr, way, set); 1679 r_dcache_cleanup_line = (addr_40) victim; 1680 1681 r_dcache_miss_way = way; 1682 r_dcache_miss_set = set; 1210 1683 } 1211 vci_addr_t victim_index = 0; 1212 if ( dreq.valid ) m_cost_data_miss_frz++; 1213 m_cpt_dcache_data_write++; 1214 m_cpt_dcache_dir_write++; 1215 1216 r_dcache_cleanup_req = r_dcache.update(ad, buf, &victim_index); 1217 r_dcache_cleanup_line = (addr_40) victim_index; 1218 1219 r_dcache_fsm = DCACHE_IDLE; 1220 delete [] buf; 1221 break; 1222 } 1223 if( r_dcache_inval_rsp ){ 1224 r_dcache_inval_rsp = false; 1225 r_dcache_fsm = DCACHE_CC_CLEANUP; 1226 break; 1227 } 1684 else 1685 { 1686 way = r_dcache_miss_way.read(); 1687 set = r_dcache_miss_set.read(); 1688 } 1689 #endif 1690 } 1691 1692 bool val = CACHE_MISS_BUF_RSP_VAL(d,word); 1693 if (val) 1694 { 1695 // m_cpt_dcache_dir_write++; 1696 // if ( ireq.valid ) m_cost_data_miss_frz++; 1697 1698 // if need invalid rsp, don't modify the cache, but pop the buf_rsp 1699 if (not r_dcache_inval_rsp ) 1700 { 1701 r_dcache.write(way, set, word, CACHE_MISS_BUF_RSP_DATA(d,word)); 1702 m_cpt_dcache_data_write++; 1703 } 1704 1705 CACHE_MISS_BUF_RSP_POP(d); 1706 r_dcache_update_addr = ++word; 1707 1708 // if last word, finish the update 1709 if (word >= m_dcache_words) 1710 { 1711 // Last word : if previous invalid_rsp, can cleanup, else update the TAG 1712 if (r_dcache_inval_rsp) 1713 { 1714 r_dcache_inval_rsp = false; 1715 r_dcache_fsm = DCACHE_CC_CLEANUP; 1716 } 1717 else 1718 { 1719 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1720 r_dcache.victim_update_tag(addr, way, set); 1721 #endif 1722 r_dcache_fsm = DCACHE_IDLE; 1723 } 1724 } 1725 } 1726 1228 1727 break; 1229 1728 } … … 1237 1736 break; 1238 1737 } 1239 if ( !r_dcache_unc_req ) { 1738 1739 bool ok = CACHE_MISS_BUF_RSP_VAL(d,0); 1740 1741 if (ok) { 1240 1742 if ( r_vci_rsp_data_error ) { 1241 1743 r_dcache_fsm = DCACHE_ERROR; 1242 1744 } else { 1745 data_t rdata = CACHE_MISS_BUF_RSP_DATA(d,0); 1746 CACHE_MISS_BUF_RSP_POP(d); 1747 1243 1748 if(dreq.type == iss_t::DATA_LL){ 1749 PRINTF(" * <DCACHE> ll_valid = true\n"); 1750 1244 1751 r_dcache_ll_valid = true; 1245 r_dcache_ll_data = r _dcache_miss_buf[0];1752 r_dcache_ll_data = rdata; 1246 1753 r_dcache_ll_addr = (vci_addr_t) dreq.addr; 1247 1754 } 1248 1755 r_dcache_fsm = DCACHE_IDLE; 1249 1756 drsp.valid = true; 1250 drsp.rdata = r _dcache_miss_buf[0];1757 drsp.rdata = rdata; 1251 1758 } 1252 1759 } … … 1262 1769 break; 1263 1770 } 1264 if ( !r_dcache_sc_req ) { 1771 1772 bool ok = CACHE_MISS_BUF_RSP_VAL(d,0); 1773 1774 if (ok) { 1265 1775 if ( r_vci_rsp_data_error ) { 1266 1776 r_dcache_fsm = DCACHE_ERROR; … … 1268 1778 r_dcache_fsm = DCACHE_IDLE; 1269 1779 drsp.valid = true; 1270 drsp.rdata = r_dcache_miss_buf[0]; 1780 drsp.rdata = CACHE_MISS_BUF_RSP_DATA(d,0); 1781 CACHE_MISS_BUF_RSP_POP(d); 1271 1782 r_dcache_ll_valid = false; 1272 1783 } … … 1292 1803 break; 1293 1804 } 1294 if( !r_dcache_cleanup_req.read() ){1805 if( not r_dcache_cleanup_req.read() ){ 1295 1806 m_cpt_dcache_dir_read += m_dcache_ways; 1296 1807 vci_addr_t ad = r_dcache_addr_save.read(); 1297 1808 r_dcache_cleanup_req = r_dcache.inval(ad); 1298 r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words)+2);1809 r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift; 1299 1810 1300 1811 r_dcache_fsm = DCACHE_IDLE; 1301 1812 } 1813 break; 1814 } 1815 case DCACHE_SYNC : 1816 { 1817 if ( r_tgt_dcache_req ) { // external request 1818 r_dcache_fsm = DCACHE_CC_CHECK; 1819 r_dcache_fsm_save = r_dcache_fsm; 1820 break; 1821 } 1822 1823 if (r_wbuf.empty()) 1824 { 1825 drsp.valid = true; // end, can accept the sync request 1826 r_dcache_fsm = DCACHE_IDLE; 1827 } 1302 1828 break; 1303 1829 } … … 1305 1831 case DCACHE_CC_CHECK: // read directory in case of invalidate or update request 1306 1832 { 1307 1308 m_cpt_dcache_dir_read += m_dcache_ways; 1309 m_cpt_dcache_data_read += m_dcache_ways; 1310 addr_40 ad = r_tgt_addr; 1833 addr_40 ad = r_tgt_addr; 1311 1834 data_t dcache_rdata = 0; 1312 1835 1313 if(( ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) &&1836 if((r_dcache_fsm_save == DCACHE_MISS_WAIT) and 1314 1837 ( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) { 1315 1838 r_dcache_inval_rsp = true; … … 1323 1846 } else { 1324 1847 bool dcache_hit = r_dcache.read(ad, &dcache_rdata); 1848 1849 m_cpt_dcache_data_read += m_dcache_ways; 1850 m_cpt_dcache_dir_read += m_dcache_ways; 1851 1325 1852 #ifdef COHERENCE_DEBUG 1326 1853 std::cout << "PROC " << m_srcid_rw << " DCACHE_CC_CHECK, hit ? : " << dcache_hit << std::endl; 1327 1854 #endif 1328 if ( dcache_hit && r_tgt_update ) { 1855 if ( dcache_hit and r_tgt_update ) 1856 { 1857 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1858 uint32_t word = r_cache_word; 1859 data_t mask = vci_param::be2mask(r_tgt_be[word]); 1860 data_t rdata = 0; 1861 1862 r_dcache.read(ad+word*4,&rdata); 1863 1864 r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); 1865 1866 word ++; 1867 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1868 for (; word<m_dcache_words; ++word) 1869 if (r_tgt_be[word] != 0) 1870 break; 1871 #endif 1872 1873 if (word==m_dcache_words) 1874 { 1875 r_dcache_fsm = DCACHE_CC_UPDT; 1876 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1877 for (word=0; word<m_dcache_words; ++word) 1878 if (r_tgt_be[word] != 0) 1879 break; 1880 #else 1881 word = 0; 1882 #endif 1883 } 1884 r_cache_word = word; 1885 #else //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1329 1886 // complete the line buffer in case of update 1330 1887 for(size_t i=0; i<m_dcache_words; i++){ … … 1335 1892 } 1336 1893 r_dcache_fsm = DCACHE_CC_UPDT; 1337 } else if ( dcache_hit && !r_tgt_update ) { 1894 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1895 } else if ( dcache_hit and not r_tgt_update ) { 1338 1896 r_dcache_fsm = DCACHE_CC_INVAL; 1339 1897 } else { … … 1352 1910 case DCACHE_CC_UPDT: // update directory and data cache 1353 1911 { 1912 addr_40 ad = r_tgt_addr; 1913 1354 1914 m_cpt_dcache_dir_write++; 1355 1915 m_cpt_dcache_data_write++; 1356 addr_40 ad = r_tgt_addr; 1357 data_t* buf = r_tgt_buf; 1358 #ifdef COHERENCE_DEBUG 1916 1917 # ifdef COHERENCE_DEBUG 1359 1918 std::cout << "PROC " << m_srcid_rw << " DCACHE_CC_UPDT, update : " << std::endl; 1360 #endif 1919 # endif 1920 1921 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1922 uint32_t word = r_cache_word; 1923 1924 if(r_tgt_be[word]) 1925 r_dcache.write(ad+word*4, r_tgt_buf[word]); 1926 # ifdef COHERENCE_DEBUG 1927 std::cout << " address " << std::hex << ad+word*4 << " data " << std::dec << r_tgt_buf[word] << std::endl; 1928 data_t rdata = 0xAAAAAAAA; 1929 r_dcache.read(ad+word*4,&rdata); 1930 std::cout << "data written " << rdata << std::endl; 1931 # endif 1932 1933 word ++; 1934 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1935 for (; word<m_dcache_words; ++word) 1936 if (r_tgt_be[word] != 0) 1937 break; 1938 #endif 1939 1940 if (word==m_dcache_words) 1941 { 1942 r_tgt_dcache_req = false; 1943 r_tgt_dcache_rsp = true; 1944 r_dcache_fsm = r_dcache_fsm_save; 1945 word = 0; 1946 } 1947 r_cache_word = word; 1948 #else //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1949 data_t* buf = r_tgt_buf; 1361 1950 for(size_t i=0; i<m_dcache_words; i++){ 1362 1951 if(r_tgt_be[i]) { 1363 1952 r_dcache.write( ad + i*4, buf[i]); 1364 # ifdef COHERENCE_DEBUG1953 # ifdef COHERENCE_DEBUG 1365 1954 std::cout << " address " << std::hex << ad+i*4 << " data " << std::dec << buf[i] << std::endl; 1366 1955 data_t rdata = 0xAAAAAAAA; 1367 1956 r_dcache.read(ad + i*4,&rdata); 1368 1957 std::cout << "data written " << rdata << std::endl; 1369 # endif1958 # endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1370 1959 } 1371 1960 } … … 1373 1962 r_tgt_dcache_rsp = true; 1374 1963 r_dcache_fsm = r_dcache_fsm_save; 1964 #endif 1375 1965 break; 1376 1966 } … … 1396 1986 } 1397 1987 // cleanup 1398 if( !r_dcache_cleanup_req){1988 if(not r_dcache_cleanup_req){ 1399 1989 r_dcache_cleanup_req = true; 1400 r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words) + 2);1990 r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift; 1401 1991 r_dcache_fsm = DCACHE_IDLE; 1402 1992 } … … 1405 1995 1406 1996 } // end switch r_dcache_fsm 1407 1408 #if DEBUG_CC_XCACHE_WRAPPER 1409 std::cout << " Data Response: " << drsp << std::endl; 1997 1998 ////////// write buffer state update ///////////// 1999 // The update() method must be called at each cycle to update the internal state. 2000 // All pending write requests must be locked in case of SYNC 2001 bool wbuf_flush=(r_dcache_fsm == DCACHE_SYNC); 2002 #if (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==1) 2003 r_wbuf.update_multi_scan (wbuf_flush); 2004 #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==2) 2005 r_wbuf.update_round_robin_scan(wbuf_flush); 2006 #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==3) 2007 r_wbuf.update_one_scan (wbuf_flush); 2008 #else 2009 r_wbuf.update (wbuf_flush); 2010 #endif 2011 2012 #if CC_XCACHE_WRAPPER_DEBUG 2013 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 2014 std::cout << " * Data Response : " << drsp << std::endl; 1410 2015 #endif 1411 2016 … … 1418 2023 } 1419 2024 1420 if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) ) m_cpt_frz_cycles++; 1421 2025 if ( (ireq.valid and not irsp.valid) or 2026 (dreq.valid and not drsp.valid)) 2027 { 2028 m_cpt_frz_cycles++; 2029 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 2030 m_stop_simulation_nb_frz_cycles ++; 2031 2032 if (m_stop_simulation and (m_stop_simulation_nb_frz_cycles >= m_stop_simulation_nb_frz_cycles_max)) 2033 { 2034 std::cout << std::dec << "CC_XCACHE_WRAPPER \"" << name() << "\" : cycle " << m_cpt_total_cycles << ", the cpu is frozen since " << m_stop_simulation_nb_frz_cycles << " cycles." << std::endl; 2035 ASSERT(false,"CPU : anormal activity"); // exit 2036 } 2037 } 2038 else 2039 { 2040 m_stop_simulation_nb_frz_cycles = 0; // reinit counter 2041 #endif //CC_XCACHE_WRAPPER_STOP_SIMULATION 2042 } 2043 2044 2045 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 2046 if (dreq.valid and drsp.valid) 2047 { 2048 log_dcache_transaction_file 2049 << "[" << m_cpt_total_cycles << "]" 2050 << std::hex 2051 << " @ " << std::setw(8) << (uint32_t)dreq.addr 2052 << " be " << std::setw(1) << (uint32_t)dreq.be 2053 << " W " << std::setw(8) << (uint32_t)dreq.wdata 2054 << " R " << std::setw(8) << (uint32_t)drsp.rdata 2055 << " error " << (uint32_t)drsp.error 2056 << std::dec 2057 << " " << type_str(dreq.type); 2058 2059 if ((dreq.type == iss_t::XTN_READ) or 2060 (dreq.type == iss_t::XTN_WRITE)) 2061 //log_dcache_transaction_file << xtn_str(dreq.addr>>2); 2062 switch (dreq.addr>>2) 2063 { 2064 case iss_t::XTN_DCACHE_INVAL : log_dcache_transaction_file << " INVAL"; break; 2065 case iss_t::XTN_SYNC : log_dcache_transaction_file << " SYNC"; break; 2066 default : log_dcache_transaction_file << " invalid"; break; 2067 } 2068 2069 log_dcache_transaction_file << std::endl; 2070 2071 // printf("[%d] @ %.8x be %.1x W %.8x R %.8x error %d - %s" 2072 // ,(uint32_t)m_cpt_total_cycles 2073 // ,(uint32_t)dreq.addr 2074 // ,(uint32_t)dreq.be 2075 // ,(uint32_t)dreq.wdata 2076 // ,(uint32_t)drsp.rdata 2077 // ,(uint32_t)drsp.error 2078 // ,type_str(dreq.type)); 2079 // if ((dreq.type == iss_t::XTN_READ) or 2080 // (dreq.type == iss_t::XTN_WRITE)) 2081 // // printf(" %s",xtn_str(dreq.addr>>2)); 2082 // switch (dreq.addr>>2) 2083 // { 2084 // case iss_t::XTN_DCACHE_INVAL : printf(" INVAL"); break; 2085 // case iss_t::XTN_SYNC : printf(" SYNC"); break; 2086 // default : printf(" invalid"); break; 2087 // } 2088 // printf("\n"); 2089 } 2090 #endif //CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 2091 2092 //////////////////////////////////////////////////////////////////////////// 2093 // This CLEANUP FSM controls the transmission of the cleanup transactions 2094 // on the coherence network. It controls the following ressources: 2095 // - r_cleanup_fsm 2096 // - r_dcache_cleanup_req (reset) 2097 // - r_icache_cleanup_req (reset) 2098 // 2099 // This FSM handles cleanup requests from both the DCACHE FSM & ICACHE FSM 2100 // - Instruction Cleanup : r_icache_cleanup_req 2101 // - Data Cleanup : r_dcache_cleanup_req 2102 // In case of simultaneous requests, the data request have highest priority. 2103 // There is only one cleanup transaction at a given time (sequencial behavior) 2104 // because the same FSM controls both command & response. 2105 // The the r_icache_cleanup_req & r_dcache_cleanup_req are reset only 2106 // when the response packet is received. 2107 // Error handling : 2108 // As the coherence trafic is controled by hardware, errors are not reported 2109 // to software : In case of errors, the simulation stops. 2110 //////////////////////////////////////////////////////////////////////////// 2111 2112 switch (r_cleanup_fsm) { 2113 2114 case CLEANUP_IDLE: 2115 { 2116 if ( p_vci_ini_c.cmdack ) 2117 { 2118 if (r_dcache_cleanup_req) r_cleanup_fsm = CLEANUP_DCACHE; 2119 else if (r_icache_cleanup_req) r_cleanup_fsm = CLEANUP_ICACHE; 2120 } 2121 break; 2122 } 2123 case CLEANUP_DCACHE: 2124 { 2125 if ( p_vci_ini_c.rspval ) 2126 { 2127 PRINTF(" * <CLEANUP> rerror : %d (%d)\n",(uint32_t)p_vci_ini_c.rerror.read(),0x2 & ( (1 << vci_param::E) - 1)); 2128 2129 ASSERT(p_vci_ini_c.reop and (p_vci_ini_c.rtrdid.read() == TYPE_DATA_CLEANUP), 2130 "illegal response packet received for a cleanup transaction"); 2131 ASSERT(p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL, 2132 "error signaled in a cleanup response" ); 2133 2134 r_cleanup_fsm = CLEANUP_IDLE; 2135 r_dcache_cleanup_req = false; 2136 // m_cpt_cc_cleanup_data++; TODO 2137 } 2138 break; 2139 } 2140 case CLEANUP_ICACHE: 2141 { 2142 if ( p_vci_ini_c.rspval ) 2143 { 2144 PRINTF(" * <CLEANUP> rerror : %d (%d)\n",(uint32_t)p_vci_ini_c.rerror.read(),0x2 & ( (1 << vci_param::E) - 1)); 2145 2146 ASSERT(p_vci_ini_c.reop and (p_vci_ini_c.rtrdid.read() == TYPE_INS_CLEANUP), 2147 "illegal response packet received for a cleanup transaction"); 2148 ASSERT(p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL, 2149 "error signaled in a cleanup response" ); 2150 2151 r_cleanup_fsm = CLEANUP_IDLE; 2152 r_icache_cleanup_req = false; 2153 // m_cpt_cc_cleanup_ins++; TODO 2154 } 2155 break; 2156 } 2157 } // end switch r_cleanup_fsm 1422 2158 1423 2159 //////////////////////////////////////////////////////////////////////////// … … 1427 2163 // - r_vci_cmd_max 1428 2164 // - r_vci_cmd_cpt 1429 // - wbuf reset 2165 // - wbuf (reset) 2166 // - r_icache_miss_req (reset) 2167 // - r_icache_unc_req (reset) 2168 // - r_dcache_miss_req (reset) 2169 // - r_dcache_sc_req (reset) 1430 2170 // 1431 2171 // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM. 1432 2172 // There is 7 request types, with the following priorities : 1433 // 1 - Instruction Miss : r_icache_miss_req1434 // 2 - Data Write : r_dcache_write_req1435 // 3 - Data Read Miss : r_dcache_miss_req1436 // 4 - Data Read Uncached : r_dcache_unc_req1437 // 5 - Instruction Cleanup : r_icache_cleanup_req1438 // 6 - Data Cleanup : r_dcache_cleanup_req2173 // 1 - Data Read Miss : r_dcache_miss_req and miss in the write buffer 2174 // 2 - Data Read Uncachable : r_dcache_unc_req and miss in the write buffer 2175 // 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer 2176 // 4 - Instruction Uncachable : r_icache_unc_req and miss in the write buffer 2177 // 5 - Data Write : r_wbuf.rok() 2178 // 6 - Data Store Conditionnal: r_dcache_sc_req 1439 2179 // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM 1440 2180 // and RSP_FSM exit simultaneously the IDLE state. … … 1447 2187 ////////////////////////////////////////////////////////////////////////////// 1448 2188 2189 r_vci_cmd_dcache_prior = not r_vci_cmd_dcache_prior; 2190 1449 2191 switch (r_vci_cmd_fsm) { 1450 2192 1451 2193 case CMD_IDLE: 1452 if (r_vci_rsp_fsm != RSP_IDLE) break; 2194 { 2195 // if (r_vci_rsp_fsm != RSP_IDLE) break; 2196 2197 size_t min; 2198 size_t max; 1453 2199 1454 2200 r_vci_cmd_cpt = 0; 1455 if ( r_icache_cleanup_req ) { 1456 r_vci_cmd_fsm = CMD_INS_CLEANUP; 1457 } else if ( r_dcache_cleanup_req ) { 1458 r_vci_cmd_fsm = CMD_DATA_CLEANUP; 1459 } else if ( r_icache_miss_req ) { 2201 2202 // Requests : 2203 2204 // multi_write_buffer access is conditionnal with dcache_miss_req and icache_miss_req 2205 2206 #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1) 2207 // 1) two access authorized 2208 bool dcache_miss_req = r_dcache_miss_req; 2209 bool icache_miss_req = r_icache_miss_req; 2210 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2) 2211 // 2) one access with static priority (dcache prior) 2212 bool dcache_miss_req = r_dcache_miss_req; // dcache prior 2213 bool icache_miss_req = not dcache_miss_req and r_icache_miss_req; 2214 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==3) 2215 // 3) one access with static priority (icache prior) 2216 bool icache_miss_req = r_icache_miss_req; 2217 bool dcache_miss_req = not icache_miss_req and r_dcache_miss_req; // dcache prior 2218 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) 2219 // 4) one access with round robin priority 2220 bool dcache_miss_req = ((r_dcache_miss_req and not r_icache_miss_req) or // only dcache 2221 (r_dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior 2222 bool icache_miss_req = not dcache_miss_req and r_icache_miss_req; 2223 #else 2224 #error "Invalid value to CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY" 2225 #endif 2226 // 1 - Data Read 2227 if (dcache_miss_req and r_wbuf.miss(r_dcache_addr_save)) 2228 { 2229 r_vci_cmd_fsm = CMD_DATA_MISS; 2230 r_dcache_miss_req = false; 2231 m_cpt_dmiss_transaction++; 2232 } 2233 2234 // 2 - Data Read Uncachable 2235 else if ( r_dcache_unc_req ) 2236 { 2237 r_vci_cmd_fsm = CMD_DATA_UNC; 2238 r_dcache_unc_req = false; 2239 // m_cpt_data_unc_transaction++; 2240 } 2241 2242 // 3 - Instruction Miss 2243 else if (icache_miss_req and r_wbuf.miss(r_icache_addr_save)) 2244 { 1460 2245 r_vci_cmd_fsm = CMD_INS_MISS; 2246 r_icache_miss_req = false; 1461 2247 m_cpt_imiss_transaction++; 1462 } else if ( r_icache_unc_req ) { 2248 } 2249 2250 // 4 - Instruction Uncachable 2251 else if ( r_icache_unc_req ) 2252 { 1463 2253 r_vci_cmd_fsm = CMD_INS_UNC; 1464 m_cpt_imiss_transaction++; 1465 } else if ( r_dcache_write_req ) { 2254 r_icache_unc_req = false; 2255 // m_cpt_ins_unc_transaction++; 2256 } 2257 2258 // 5 - Data Write 2259 else if ( r_wbuf.rok(&min, &max) ) 2260 { 1466 2261 r_vci_cmd_fsm = CMD_DATA_WRITE; 1467 r_vci_cmd_cpt = r_wbuf.getMin(); 1468 r_vci_cmd_min = r_wbuf.getMin(); 1469 r_vci_cmd_max = r_wbuf.getMax(); 1470 m_cpt_write_transaction++; 1471 m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1); 1472 } else if ( r_dcache_miss_req ) { 1473 r_vci_cmd_fsm = CMD_DATA_MISS; 1474 m_cpt_dmiss_transaction++; 1475 } else if ( r_dcache_unc_req ) { 1476 r_vci_cmd_fsm = CMD_DATA_UNC; 1477 m_cpt_unc_transaction++; 1478 } else if ( r_dcache_sc_req ) { 2262 r_vci_cmd_cpt = min; 2263 r_vci_cmd_min = min; 2264 r_vci_cmd_max = max; 2265 m_cpt_data_write_transaction++; 2266 m_length_write_transaction += (max-min+1); 2267 } 2268 2269 // 6 - Data Store Conditionnal 2270 else if ( r_dcache_sc_req ) 2271 { 1479 2272 r_vci_cmd_fsm = CMD_DATA_SC; 1480 2273 r_vci_cmd_max = 1; 1481 2274 m_cpt_unc_transaction++; 1482 } 1483 break; 1484 2275 r_dcache_sc_req = false; 2276 } 2277 2278 break; 2279 } 1485 2280 case CMD_DATA_WRITE: 1486 2281 if ( p_vci_ini_rw.cmdack.read() ) { … … 1488 2283 if (r_vci_cmd_cpt == r_vci_cmd_max) { 1489 2284 r_vci_cmd_fsm = CMD_IDLE ; 1490 r_wbuf. reset() ;2285 r_wbuf.sent() ; 1491 2286 } 1492 2287 } … … 1509 2304 } 1510 2305 break; 1511 case CMD_INS_CLEANUP:1512 case CMD_DATA_CLEANUP:1513 if ( p_vci_ini_c.cmdack.read() ) {1514 r_vci_cmd_fsm = CMD_IDLE;1515 }1516 break;1517 2306 1518 2307 } // end switch r_vci_cmd_fsm … … 1523 2312 // - r_icache_miss_buf[m_icache_words] 1524 2313 // - r_dcache_miss_buf[m_dcache_words] 1525 // - r_icache_miss_req reset1526 // - r_icache_unc_req reset1527 // - r_dcache_miss_req reset1528 // - r_icache_cleanup_req reset1529 // - r_dcache_cleanup_req reset1530 2314 // - r_vci_rsp_data_error set 1531 2315 // - r_vci_rsp_ins_error set … … 1552 2336 1553 2337 case RSP_IDLE: 1554 if(p_vci_ini_rw.rspval.read()|| 1555 p_vci_ini_c.rspval.read()) 1556 { 1557 std::cout << "CC_XCache " << m_srcid_rw << " Unexpected response" << std::endl; 1558 } 1559 assert( ! p_vci_ini_rw.rspval.read() && ! p_vci_ini_c.rspval.read() && "Unexpected response" ); 1560 if (r_vci_cmd_fsm != CMD_IDLE) break; 1561 1562 r_vci_rsp_cpt = 0; 1563 if ( r_icache_cleanup_req ) r_vci_rsp_fsm = RSP_INS_CLEANUP; 1564 else if ( r_dcache_cleanup_req ) r_vci_rsp_fsm = RSP_DATA_CLEANUP; 1565 else if ( r_icache_miss_req ) r_vci_rsp_fsm = RSP_INS_MISS; 1566 else if ( r_icache_unc_req ) r_vci_rsp_fsm = RSP_INS_UNC; 1567 else if ( r_dcache_write_req ) r_vci_rsp_fsm = RSP_DATA_WRITE; 1568 else if ( r_dcache_miss_req ) r_vci_rsp_fsm = RSP_DATA_MISS; 1569 else if ( r_dcache_unc_req ) r_vci_rsp_fsm = RSP_DATA_UNC; 1570 else if ( r_dcache_sc_req ) r_vci_rsp_fsm = RSP_DATA_SC; 2338 2339 if( p_vci_ini_rw.rspval.read() ) 2340 { 2341 PRINTF(" * <RSP> have rsp - trdid : %x\n",(uint32_t)p_vci_ini_rw.rtrdid.read()); 2342 2343 r_vci_rsp_cpt = 0; 2344 2345 if ((p_vci_ini_rw.rtrdid.read()>>(vci_param::T-1)) != 0 ) 2346 r_vci_rsp_fsm = RSP_DATA_WRITE; 2347 else 2348 { 2349 switch (p_vci_ini_rw.rtrdid.read()) 2350 { 2351 case TYPE_INS_MISS : r_vci_rsp_fsm = RSP_INS_MISS; break; 2352 case TYPE_INS_UNC : r_vci_rsp_fsm = RSP_INS_UNC; break; 2353 case TYPE_DATA_MISS : r_vci_rsp_fsm = RSP_DATA_MISS; break; 2354 case TYPE_DATA_UNC : r_vci_rsp_fsm = RSP_DATA_UNC; break; 2355 case TYPE_DATA_SC : r_vci_rsp_fsm = RSP_DATA_SC; break; 2356 default : 2357 { 2358 ASSERT(false, "Unexpected response"); 2359 } 2360 } 2361 } 2362 } 1571 2363 break; 1572 2364 1573 2365 case RSP_INS_MISS: 2366 1574 2367 m_cost_imiss_transaction++; 1575 if ( ! p_vci_ini_rw.rspval.read() ) 1576 break; 1577 assert( (r_vci_rsp_cpt < m_icache_words) && 1578 "The VCI response packet for instruction miss is too long" ); 1579 r_vci_rsp_cpt = r_vci_rsp_cpt + 1; 1580 r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read(); 1581 1582 if ( p_vci_ini_rw.reop.read() ) { 1583 assert( ((r_vci_rsp_cpt == m_icache_words - 1) || 1584 p_vci_ini_rw.rerror.read() || 1585 (r_vci_rsp_ins_error.read()&0x1))&& 1586 "The VCI response packet for instruction miss is too short"); 1587 r_icache_miss_req = false; 2368 PRINTF(" * <RSP> rspval/ack : %d - %d\n",(uint32_t)p_vci_ini_rw.rspval.read(), (uint32_t)r_vci_rsp_ack); 2369 2370 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) 2371 { 2372 PRINTF(" * <RSP> have rsp - r_vci_rsp_cpt : %d/%d\n",(uint32_t)r_vci_rsp_cpt.read(),(uint32_t)m_icache_words); 2373 PRINTF(" * <RSP> ins : %x\n",(int)p_vci_ini_rw.rdata.read()); 2374 2375 ASSERT( (r_vci_rsp_cpt < m_icache_words), 2376 "The VCI response packet for instruction miss is too long" ); 2377 r_vci_rsp_cpt = r_vci_rsp_cpt + 1; 2378 CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read()); 2379 if ( p_vci_ini_rw.reop.read() ) 2380 { 2381 PRINTF(" * <RSP> have reop\n"); 2382 2383 ASSERT( ((r_vci_rsp_cpt == m_icache_words - 1) or 2384 p_vci_ini_rw.rerror.read() or 2385 (r_vci_rsp_ins_error.read()&0x1)), 2386 "The VCI response packet for instruction miss is too short"); 2387 r_vci_rsp_cpt = 0; 2388 r_vci_rsp_fsm = RSP_IDLE; 2389 2390 } 2391 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true; 2392 } 2393 break; 2394 2395 case RSP_INS_UNC: 2396 2397 m_cost_imiss_transaction++; 2398 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) 2399 { 2400 ASSERT(p_vci_ini_rw.reop.read(), 2401 "illegal VCI response packet for uncached instruction"); 2402 2403 CACHE_MISS_BUF_RSP_PUSH(i,0,(data_t)p_vci_ini_rw.rdata.read()); 2404 1588 2405 r_vci_rsp_fsm = RSP_IDLE; 1589 } 1590 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true; 1591 break; 1592 1593 case RSP_INS_UNC: 1594 m_cost_imiss_transaction++; 1595 if ( ! p_vci_ini_rw.rspval.read() ) 1596 break; 1597 assert(p_vci_ini_rw.reop.read() && 1598 "illegal VCI response packet for uncached instruction"); 1599 r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read(); 1600 r_vci_rsp_fsm = RSP_IDLE; 1601 r_icache_unc_req = false; 1602 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true; 2406 2407 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true; 2408 } 1603 2409 break; 1604 2410 1605 2411 case RSP_DATA_MISS: 2412 1606 2413 m_cost_dmiss_transaction++; 1607 if ( ! p_vci_ini_rw.rspval.read() ) 1608 break; 1609 assert(r_vci_rsp_cpt != m_dcache_words && 1610 "illegal VCI response packet for data read miss"); 1611 r_vci_rsp_cpt = r_vci_rsp_cpt + 1; 1612 r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read(); 1613 if ( p_vci_ini_rw.reop.read() ) { 1614 assert( ((r_vci_rsp_cpt == m_dcache_words - 1) 1615 || (p_vci_ini_rw.rerror.read()&0x1) 1616 || r_vci_rsp_data_error.read()) && 1617 "illegal VCI response packet for data read miss"); 1618 r_dcache_miss_req = false; 2414 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) 2415 { 2416 PRINTF(" * <RSP> have rspval - error : %d\n",(int)p_vci_ini_rw.rerror.read()); 2417 2418 ASSERT(r_vci_rsp_cpt < m_dcache_words, 2419 "illegal VCI response packet for data read miss"); 2420 r_vci_rsp_cpt = r_vci_rsp_cpt + 1; 2421 2422 CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read()); 2423 2424 if ( p_vci_ini_rw.reop.read() ) { 2425 ASSERT( ((r_vci_rsp_cpt == m_dcache_words - 1) 2426 or (p_vci_ini_rw.rerror.read()&0x1) 2427 or r_vci_rsp_data_error.read()), 2428 "illegal VCI response packet for data read miss"); 2429 r_vci_rsp_cpt = 0; 2430 r_vci_rsp_fsm = RSP_IDLE; 2431 } 2432 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true; 2433 } 2434 break; 2435 2436 case RSP_DATA_WRITE: 2437 2438 m_cost_write_transaction++; 2439 if (p_vci_ini_rw.rspval.read()) 2440 { 2441 PRINTF(" * <RSP> have rspval - error : %d\n",(int)p_vci_ini_rw.rerror.read()); 2442 2443 ASSERT(p_vci_ini_rw.reop.read(), 2444 "A VCI response packet must contain one flit for a write transaction"); 1619 2445 r_vci_rsp_fsm = RSP_IDLE; 1620 } 1621 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true; 1622 break; 1623 1624 case RSP_DATA_WRITE: 1625 m_cost_write_transaction++; 1626 if ( ! p_vci_ini_rw.rspval.read() ) 1627 break; 1628 if ( p_vci_ini_rw.reop.read() ) { 1629 r_vci_rsp_fsm = RSP_IDLE; 1630 r_dcache_write_req = false; 1631 } 1632 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) m_iss.setWriteBerr(); 2446 bool cached = r_wbuf.completed(p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1)) ); 2447 2448 PRINTF(" * <RSP> cached : %d\n",cached); 2449 2450 if (not cached) 2451 r_dcache_previous_unc = false; 2452 2453 if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) m_iss.setWriteBerr(); 2454 } 1633 2455 break; 1634 2456 1635 2457 case RSP_DATA_UNC: 1636 2458 m_cost_unc_transaction++; 1637 if ( ! p_vci_ini_rw.rspval.read() ) 1638 break; 1639 assert(p_vci_ini_rw.reop.read() && 1640 "illegal VCI response packet for data read uncached"); 1641 r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read(); 1642 r_vci_rsp_fsm = RSP_IDLE; 1643 r_dcache_unc_req = false; 1644 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true; 2459 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) 2460 { 2461 ASSERT(p_vci_ini_rw.reop.read(), 2462 "illegal VCI response packet for data read uncached"); 2463 2464 CACHE_MISS_BUF_RSP_PUSH(d,0,(data_t)p_vci_ini_rw.rdata.read()); 2465 2466 r_vci_rsp_fsm = RSP_IDLE; 2467 r_dcache_previous_unc = false; 2468 2469 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true; 2470 } 1645 2471 break; 1646 2472 1647 2473 case RSP_DATA_SC: 1648 2474 m_cost_unc_transaction++; 1649 if ( ! p_vci_ini_rw.rspval.read() ) 1650 break; 1651 assert(p_vci_ini_rw.reop.read() && 1652 "illegal VCI response packet for data SC"); 1653 r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read(); 1654 r_vci_rsp_fsm = RSP_IDLE; 1655 r_dcache_sc_req = false; 1656 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true; 1657 break; 1658 1659 case RSP_INS_CLEANUP: 1660 case RSP_DATA_CLEANUP: 1661 if ( ! p_vci_ini_c.rspval.read() ) 1662 break; 1663 assert( p_vci_ini_c.reop.read() && 1664 "illegal VCI response packet for icache cleanup"); 1665 assert( ((p_vci_ini_c.rerror.read()&0x1) == vci_param::ERR_NORMAL) && 1666 "error in response packet for icache cleanup"); 1667 if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) r_icache_cleanup_req = false; 1668 else r_dcache_cleanup_req = false; 1669 r_vci_rsp_fsm = RSP_IDLE; 2475 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) 2476 { 2477 ASSERT(p_vci_ini_rw.reop.read(), 2478 "illegal VCI response packet for data SC"); 2479 2480 CACHE_MISS_BUF_RSP_PUSH(d,0,(data_t)p_vci_ini_rw.rdata.read()); 2481 2482 r_vci_rsp_fsm = RSP_IDLE; 2483 r_dcache_previous_unc = false; 2484 2485 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true; 2486 } 1670 2487 break; 1671 2488 … … 1678 2495 ////////////////////////////////////////////////////////////////////////////////// 1679 2496 { 2497 1680 2498 // VCI initiator response 1681 1682 p_vci_ini_rw.rspack = true; 1683 p_vci_ini_c.rspack = true; 2499 switch ( r_cleanup_fsm.read() ) { 2500 2501 case CLEANUP_IDLE: 2502 p_vci_ini_c.rspack = false; 2503 p_vci_ini_c.cmdval = r_icache_cleanup_req || r_dcache_cleanup_req; 2504 if ( r_dcache_cleanup_req ) 2505 { 2506 p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words << 2); 2507 p_vci_ini_c.trdid = TYPE_DATA_CLEANUP; 2508 } 2509 else 2510 { 2511 p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words << 2); 2512 p_vci_ini_c.trdid = TYPE_INS_CLEANUP; 2513 } 2514 p_vci_ini_c.wdata = 0; 2515 p_vci_ini_c.be = 0xF; 2516 p_vci_ini_c.plen = 4; 2517 p_vci_ini_c.cmd = vci_param::CMD_WRITE; 2518 p_vci_ini_c.pktid = 0; 2519 p_vci_ini_c.srcid = m_srcid_c; 2520 p_vci_ini_c.cons = false; 2521 p_vci_ini_c.wrap = false; 2522 p_vci_ini_c.contig = false; 2523 p_vci_ini_c.clen = 0; 2524 p_vci_ini_c.cfixed = false; 2525 p_vci_ini_c.eop = true; 2526 break; 2527 2528 case CLEANUP_DCACHE: 2529 p_vci_ini_c.rspack = true; 2530 p_vci_ini_c.cmdval = false; 2531 p_vci_ini_c.address = 0; 2532 p_vci_ini_c.wdata = 0; 2533 p_vci_ini_c.be = 0; 2534 p_vci_ini_c.plen = 0; 2535 p_vci_ini_c.cmd = vci_param::CMD_WRITE; 2536 p_vci_ini_c.trdid = 0; 2537 p_vci_ini_c.pktid = 0; 2538 p_vci_ini_c.srcid = 0; 2539 p_vci_ini_c.cons = false; 2540 p_vci_ini_c.wrap = false; 2541 p_vci_ini_c.contig = false; 2542 p_vci_ini_c.clen = 0; 2543 p_vci_ini_c.cfixed = false; 2544 p_vci_ini_c.eop = false; 2545 break; 2546 2547 case CLEANUP_ICACHE: 2548 p_vci_ini_c.rspack = true; 2549 p_vci_ini_c.cmdval = false; 2550 p_vci_ini_c.address = 0; 2551 p_vci_ini_c.wdata = 0; 2552 p_vci_ini_c.be = 0; 2553 p_vci_ini_c.plen = 0; 2554 p_vci_ini_c.cmd = vci_param::CMD_WRITE; 2555 p_vci_ini_c.trdid = 0; 2556 p_vci_ini_c.pktid = 0; 2557 p_vci_ini_c.srcid = 0; 2558 p_vci_ini_c.cons = false; 2559 p_vci_ini_c.wrap = false; 2560 p_vci_ini_c.contig = false; 2561 p_vci_ini_c.clen = 0; 2562 p_vci_ini_c.cfixed = false; 2563 p_vci_ini_c.eop = false; 2564 break; 2565 } // end switch r_cleanup_fsm 1684 2566 1685 2567 // VCI initiator command … … 1704 2586 p_vci_ini_rw.eop = false; 1705 2587 1706 p_vci_ini_c.cmdval = false;1707 p_vci_ini_c.address = 0;1708 p_vci_ini_c.wdata = 0;1709 p_vci_ini_c.be = 0;1710 p_vci_ini_c.plen = 0;1711 p_vci_ini_c.cmd = vci_param::CMD_NOP;1712 p_vci_ini_c.trdid = 0;1713 p_vci_ini_c.pktid = 0;1714 p_vci_ini_c.srcid = 0;1715 p_vci_ini_c.cons = false;1716 p_vci_ini_c.wrap = false;1717 p_vci_ini_c.contig = false;1718 p_vci_ini_c.clen = 0;1719 p_vci_ini_c.cfixed = false;1720 p_vci_ini_c.eop = false;1721 1722 2588 break; 1723 2589 … … 1737 2603 break; 1738 2604 default: 1739 assert("this should not happen");2605 ASSERT(false,"this should not happen"); 1740 2606 } 1741 2607 p_vci_ini_rw.plen = 4; 1742 p_vci_ini_rw.trdid = 0; // data cache uncached read2608 p_vci_ini_rw.trdid = TYPE_DATA_UNC; // data cache uncached read 1743 2609 p_vci_ini_rw.pktid = 0; 1744 2610 p_vci_ini_rw.srcid = m_srcid_rw; … … 1750 2616 p_vci_ini_rw.eop = true; 1751 2617 1752 p_vci_ini_c.cmdval = false;1753 p_vci_ini_c.address = 0;1754 p_vci_ini_c.wdata = 0;1755 p_vci_ini_c.be = 0;1756 p_vci_ini_c.plen = 0;1757 p_vci_ini_c.cmd = vci_param::CMD_NOP;1758 p_vci_ini_c.trdid = 0;1759 p_vci_ini_c.pktid = 0;1760 p_vci_ini_c.srcid = 0;1761 p_vci_ini_c.cons = false;1762 p_vci_ini_c.wrap = false;1763 p_vci_ini_c.contig = false;1764 p_vci_ini_c.clen = 0;1765 p_vci_ini_c.cfixed = false;1766 p_vci_ini_c.eop = false;1767 1768 2618 break; 1769 2619 … … 1772 2622 p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3; 1773 2623 if(r_vci_cmd_max.read() == 3){ 1774 assert(false &&"Not handled yet");2624 ASSERT(false, "Not handled yet"); 1775 2625 } else { // r_vci_cmd_cpt == 1 1776 2626 switch(r_vci_cmd_cpt.read()){ … … 1786 2636 p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND; 1787 2637 p_vci_ini_rw.plen = 4*(r_vci_cmd_max.read()+1); 1788 p_vci_ini_rw.trdid = 0; // data cache uncached read2638 p_vci_ini_rw.trdid = TYPE_DATA_SC; // data cache uncached read 1789 2639 p_vci_ini_rw.pktid = 0; 1790 2640 p_vci_ini_rw.srcid = m_srcid_rw; … … 1796 2646 p_vci_ini_rw.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); 1797 2647 1798 p_vci_ini_c.cmdval = false;1799 p_vci_ini_c.address = 0;1800 p_vci_ini_c.wdata = 0;1801 p_vci_ini_c.be = 0;1802 p_vci_ini_c.plen = 0;1803 p_vci_ini_c.cmd = vci_param::CMD_NOP;1804 p_vci_ini_c.trdid = 0;1805 p_vci_ini_c.pktid = 0;1806 p_vci_ini_c.srcid = 0;1807 p_vci_ini_c.cons = false;1808 p_vci_ini_c.wrap = false;1809 p_vci_ini_c.contig = false;1810 p_vci_ini_c.clen = 0;1811 p_vci_ini_c.cfixed = false;1812 p_vci_ini_c.eop = false;1813 1814 2648 break; 1815 2649 … … 1821 2655 p_vci_ini_rw.plen = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2; 1822 2656 p_vci_ini_rw.cmd = vci_param::CMD_WRITE; 1823 p_vci_ini_rw.trdid = 0; // data cache write2657 p_vci_ini_rw.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1)); 1824 2658 p_vci_ini_rw.pktid = 0; 1825 2659 p_vci_ini_rw.srcid = m_srcid_rw; … … 1831 2665 p_vci_ini_rw.eop = (r_vci_cmd_cpt == r_vci_cmd_max); 1832 2666 1833 p_vci_ini_c.cmdval = false;1834 p_vci_ini_c.address = 0;1835 p_vci_ini_c.wdata = 0;1836 p_vci_ini_c.be = 0;1837 p_vci_ini_c.plen = 0;1838 p_vci_ini_c.cmd = vci_param::CMD_NOP;1839 p_vci_ini_c.trdid = 0;1840 p_vci_ini_c.pktid = 0;1841 p_vci_ini_c.srcid = 0;1842 p_vci_ini_c.cons = false;1843 p_vci_ini_c.wrap = false;1844 p_vci_ini_c.contig = false;1845 p_vci_ini_c.clen = 0;1846 p_vci_ini_c.cfixed = false;1847 p_vci_ini_c.eop = false;1848 1849 2667 break; 1850 2668 … … 1855 2673 p_vci_ini_rw.plen = m_dcache_words << 2; 1856 2674 p_vci_ini_rw.cmd = vci_param::CMD_READ; 1857 p_vci_ini_rw.trdid = 1; // data cache cached read2675 p_vci_ini_rw.trdid = TYPE_DATA_MISS; // data cache cached read 1858 2676 p_vci_ini_rw.pktid = 0; 1859 2677 p_vci_ini_rw.srcid = m_srcid_rw; … … 1865 2683 p_vci_ini_rw.eop = true; 1866 2684 1867 p_vci_ini_c.cmdval = false;1868 p_vci_ini_c.address = 0;1869 p_vci_ini_c.wdata = 0;1870 p_vci_ini_c.be = 0;1871 p_vci_ini_c.plen = 0;1872 p_vci_ini_c.cmd = vci_param::CMD_NOP;1873 p_vci_ini_c.trdid = 0;1874 p_vci_ini_c.pktid = 0;1875 p_vci_ini_c.srcid = 0;1876 p_vci_ini_c.cons = false;1877 p_vci_ini_c.wrap = false;1878 p_vci_ini_c.contig = false;1879 p_vci_ini_c.clen = 0;1880 p_vci_ini_c.cfixed = false;1881 p_vci_ini_c.eop = false;1882 1883 2685 break; 1884 2686 … … 1889 2691 p_vci_ini_rw.plen = m_icache_words << 2; 1890 2692 p_vci_ini_rw.cmd = vci_param::CMD_READ; 1891 p_vci_ini_rw.trdid = 3; // ins cache cached read2693 p_vci_ini_rw.trdid = TYPE_INS_MISS; // ins cache cached read 1892 2694 p_vci_ini_rw.pktid = 0; 1893 2695 p_vci_ini_rw.srcid = m_srcid_rw; … … 1899 2701 p_vci_ini_rw.eop = true; 1900 2702 1901 p_vci_ini_c.cmdval = false;1902 p_vci_ini_c.address = 0;1903 p_vci_ini_c.wdata = 0;1904 p_vci_ini_c.be = 0;1905 p_vci_ini_c.plen = 0;1906 p_vci_ini_c.cmd = vci_param::CMD_NOP;1907 p_vci_ini_c.trdid = 0;1908 p_vci_ini_c.pktid = 0;1909 p_vci_ini_c.srcid = 0;1910 p_vci_ini_c.cons = false;1911 p_vci_ini_c.wrap = false;1912 p_vci_ini_c.contig = false;1913 p_vci_ini_c.clen = 0;1914 p_vci_ini_c.cfixed = false;1915 p_vci_ini_c.eop = false;1916 1917 2703 break; 1918 2704 … … 1923 2709 p_vci_ini_rw.plen = 4; 1924 2710 p_vci_ini_rw.cmd = vci_param::CMD_READ; 1925 p_vci_ini_rw.trdid = 2; // ins cache uncached read2711 p_vci_ini_rw.trdid = TYPE_INS_UNC; // ins cache uncached read 1926 2712 p_vci_ini_rw.pktid = 0; 1927 2713 p_vci_ini_rw.srcid = m_srcid_rw; … … 1933 2719 p_vci_ini_rw.eop = true; 1934 2720 1935 p_vci_ini_c.cmdval = false;1936 p_vci_ini_c.address = 0;1937 p_vci_ini_c.wdata = 0;1938 p_vci_ini_c.be = 0;1939 p_vci_ini_c.plen = 0;1940 p_vci_ini_c.cmd = vci_param::CMD_NOP;1941 p_vci_ini_c.trdid = 0;1942 p_vci_ini_c.pktid = 0;1943 p_vci_ini_c.srcid = 0;1944 p_vci_ini_c.cons = false;1945 p_vci_ini_c.wrap = false;1946 p_vci_ini_c.contig = false;1947 p_vci_ini_c.clen = 0;1948 p_vci_ini_c.cfixed = false;1949 p_vci_ini_c.eop = false;1950 1951 1952 break;1953 1954 case CMD_INS_CLEANUP:1955 p_vci_ini_rw.cmdval = false;1956 p_vci_ini_rw.address = 0;1957 p_vci_ini_rw.wdata = 0;1958 p_vci_ini_rw.be = 0;1959 p_vci_ini_rw.plen = 0;1960 p_vci_ini_rw.cmd = vci_param::CMD_NOP;1961 p_vci_ini_rw.trdid = 0;1962 p_vci_ini_rw.pktid = 0;1963 p_vci_ini_rw.srcid = 0;1964 p_vci_ini_rw.cons = false;1965 p_vci_ini_rw.wrap = false;1966 p_vci_ini_rw.contig = false;1967 p_vci_ini_rw.clen = 0;1968 p_vci_ini_rw.cfixed = false;1969 p_vci_ini_rw.eop = false;1970 1971 p_vci_ini_c.cmdval = true;1972 p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);1973 p_vci_ini_c.wdata = 0;1974 p_vci_ini_c.be = 0;1975 p_vci_ini_c.plen = 4;1976 p_vci_ini_c.cmd = vci_param::CMD_WRITE;1977 p_vci_ini_c.trdid = 1; // cleanup instruction1978 p_vci_ini_c.pktid = 0;1979 p_vci_ini_c.srcid = m_srcid_c;1980 p_vci_ini_c.cons = false;1981 p_vci_ini_c.wrap = false;1982 p_vci_ini_c.contig = false;1983 p_vci_ini_c.clen = 0;1984 p_vci_ini_c.cfixed = false;1985 p_vci_ini_c.eop = true;1986 1987 break;1988 1989 1990 case CMD_DATA_CLEANUP:1991 p_vci_ini_rw.cmdval = false;1992 p_vci_ini_rw.address = 0;1993 p_vci_ini_rw.wdata = 0;1994 p_vci_ini_rw.be = 0;1995 p_vci_ini_rw.plen = 0;1996 p_vci_ini_rw.cmd = vci_param::CMD_NOP;1997 p_vci_ini_rw.trdid = 0;1998 p_vci_ini_rw.pktid = 0;1999 p_vci_ini_rw.srcid = 0;2000 p_vci_ini_rw.cons = false;2001 p_vci_ini_rw.wrap = false;2002 p_vci_ini_rw.contig = false;2003 p_vci_ini_rw.clen = 0;2004 p_vci_ini_rw.cfixed = false;2005 p_vci_ini_rw.eop = false;2006 2007 p_vci_ini_c.cmdval = true;2008 p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);2009 p_vci_ini_c.wdata = 0;2010 p_vci_ini_c.be = 0;2011 p_vci_ini_c.plen = 4;2012 p_vci_ini_c.cmd = vci_param::CMD_WRITE;2013 p_vci_ini_c.trdid = 0; // cleanup data2014 p_vci_ini_c.pktid = 0;2015 p_vci_ini_c.srcid = m_srcid_c;2016 p_vci_ini_c.cons = false;2017 p_vci_ini_c.wrap = false;2018 p_vci_ini_c.contig = false;2019 p_vci_ini_c.clen = 0;2020 p_vci_ini_c.cfixed = false;2021 p_vci_ini_c.eop = true;2022 2023 2721 break; 2024 2722 2025 2723 } // end switch r_vci_cmd_fsm 2026 2724 2725 bool ack; 2726 2727 switch (r_vci_rsp_fsm.read() ) { 2728 case RSP_IDLE : ack = false; break; 2729 case RSP_DATA_WRITE : ack = true; break; 2730 case RSP_INS_MISS : 2731 case RSP_INS_UNC : ack = CACHE_MISS_BUF_RSP_ACK(i); break; 2732 case RSP_DATA_MISS : 2733 case RSP_DATA_UNC : 2734 case RSP_DATA_SC : ack = CACHE_MISS_BUF_RSP_ACK(d); break; 2735 } // end switch r_vci_cmd_fsm 2736 2737 r_vci_rsp_ack = ack; 2738 p_vci_ini_rw.rspack = ack; 2739 2027 2740 // VCI_TGT 2028 2741 … … 2038 2751 case TGT_RSP_BROADCAST: 2039 2752 p_vci_tgt.cmdack = false; 2040 p_vci_tgt.rspval = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() &&( r_tgt_icache_rsp | r_tgt_dcache_rsp );2753 p_vci_tgt.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() and ( r_tgt_icache_rsp | r_tgt_dcache_rsp ); 2041 2754 p_vci_tgt.rsrcid = r_tgt_srcid.read(); 2042 2755 p_vci_tgt.rpktid = r_tgt_pktid.read(); … … 2049 2762 case TGT_RSP_ICACHE: 2050 2763 p_vci_tgt.cmdack = false; 2051 p_vci_tgt.rspval = !r_tgt_icache_req.read() &&r_tgt_icache_rsp.read();2764 p_vci_tgt.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read(); 2052 2765 p_vci_tgt.rsrcid = r_tgt_srcid.read(); 2053 2766 p_vci_tgt.rpktid = r_tgt_pktid.read(); … … 2060 2773 case TGT_RSP_DCACHE: 2061 2774 p_vci_tgt.cmdack = false; 2062 p_vci_tgt.rspval = !r_tgt_dcache_req.read() &&r_tgt_dcache_rsp.read();2775 p_vci_tgt.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read(); 2063 2776 p_vci_tgt.rsrcid = r_tgt_srcid.read(); 2064 2777 p_vci_tgt.rpktid = r_tgt_pktid.read(); … … 2079 2792 } // end genMoore() 2080 2793 2794 ////////////////////////////////////////////////////////////////////////////////// 2795 tmpl(void)::stop_simulation (uint32_t nb_frz_cycles) 2796 ////////////////////////////////////////////////////////////////////////////////// 2797 { 2798 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 2799 if (nb_frz_cycles == 0) 2800 { 2801 PRINTF("CC_XCACHE_WRAPPER \"%s\" : don't stop the simulation.\n",name().c_str()); 2802 m_stop_simulation = false; 2803 } 2804 else 2805 { 2806 PRINTF("CC_XCACHE_WRAPPER \"%s\" : stop the simulation after %d cycles.\n",name().c_str(),nb_frz_cycles); 2807 m_stop_simulation = true; 2808 m_stop_simulation_nb_frz_cycles_max = nb_frz_cycles; 2809 } 2810 #else 2811 std::cout << "CC_XCACHE_WRAPPER \"" << name() << "\" : flag CC_XCACHE_WRAPPER_STOP_SIMULATION is unset, you can't use stop_simulation." << std::endl; 2812 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 2813 2814 } 2815 2081 2816 }} // end namespace 2082 2817 … … 2089 2824 2090 2825 // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 2091 2092 2093 2094 -
trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r116 r134 33 33 //#define DDEBUG // Directory debug 34 34 //#define LOCK_DEBUG // Lock debug 35 //#define DEBUG_VCI_MEM_CACHE 1 36 #define DEBUG_START_CYCLE 875000035 #define DEBUG_VCI_MEM_CACHE 0 36 #define DEBUG_START_CYCLE 200000 37 37 #define RANDOMIZE_SC 38 39 #if DEBUG_VCI_MEM_CACHE 40 # define PRINTF(msg...) do { if (m_cpt_cycles > DEBUG_START_CYCLE) printf(msg); } while (0); 41 #else 42 # define PRINTF(msg...) 43 #endif 44 38 45 namespace soclib { namespace caba { 39 46 … … 641 648 { 642 649 if ( p_vci_tgt.cmdval ) { 650 651 PRINTF(" * <TGT> Request from %d at address %llx\n",(uint32_t)p_vci_tgt.srcid.read(),(uint64_t)p_vci_tgt.address.read()); 652 643 653 assert( (p_vci_tgt.srcid.read() < m_initiators) && 644 654 "VCI_MEM_CACHE error in direct request : received SRCID is larger than the number of initiators"); … … 653 663 } 654 664 } 655 656 665 657 666 if ( !reached ) … … 666 675 r_tgt_cmd_fsm = TGT_CMD_READ; 667 676 } 668 else if (( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) && ( p_vci_tgt.trdid.read() == 0x0 )) 677 // else if (( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) && ( p_vci_tgt.trdid.read() == 0x0 )) 678 else if ( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) 669 679 { 670 680 r_tgt_cmd_fsm = TGT_CMD_WRITE; … … 838 848 //////////////////////////////////////////////////////////////////////////////////// 839 849 850 PRINTF(" * TOP : Request from %d at address %llx\n",(uint32_t)m_cmd_read_srcid_fifo.read(),(uint64_t)m_cmd_read_addr_fifo.read()); 851 840 852 switch ( r_read_fsm.read() ) { 841 853 … … 844 856 { 845 857 if (m_cmd_read_addr_fifo.rok()) { 858 PRINTF(" * <READ> Request from %d at address %llx\n",(uint32_t)m_cmd_read_srcid_fifo.read(),(uint64_t)m_cmd_read_addr_fifo.read()); 859 846 860 m_cpt_read++; 847 861 r_read_fsm = READ_DIR_LOCK; … … 2591 2605 hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index); 2592 2606 if(!hit_inval) { 2593 #if defDEBUG_VCI_MEM_CACHE2607 #if DEBUG_VCI_MEM_CACHE 2594 2608 if(m_cpt_cycles > DEBUG_START_CYCLE) 2595 2609 std::cout << "MEM_CACHE WARNING: cleanup with no corresponding entry at address : " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::dec << std::endl; -
trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/Makefile
r107 r134 1 ARCH=mips32el 2 SIMULATION_ARGS=100000 3 SOCLIB?=$(shell soclib-cc --getpath) 4 SOCLIB_CC_ADD_ARGS= -t systemcass 1 #NO_SOFT = 1 2 ARCH = mips32el 3 #SIMULATION_ARGS = 100000 4 #SOCLIB_CC_ADD_ARGS = "-DCC_XCACHE_WRAPPER_DEBUG=1" 5 SOCLIB ?= $(shell soclib-cc --getpath) 5 6 export SOCLIB 7 SOCLIB_TTY = FILES; 8 export SOCLIB_TTY 6 9 include $(SOCLIB)/soclib/platform/topcells/all.mk -
trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/platform_desc
r107 r134 4 4 5 5 todo = Platform('caba', 'top.cpp', 6 6 uses = [ 7 7 Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'), 8 8 Uses('caba:vci_simple_ram'), 9 Uses('caba:vci_logger'),9 Uses('caba:vci_simhelper'), 10 10 Uses('caba:vci_multi_tty'), 11 11 Uses('caba:vci_vgmn'), … … 15 15 Uses('caba:vci_mem_cache_v4'), 16 16 Uses('common:elf_file_loader'), 17 Uses('caba:vci_xicu'), 17 18 ], 18 19 cell_size = 4, -
trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/segmentation.h
r107 r134 19 19 // base address required by MIPS processor 20 20 ///////////////////////////////////////////////////////////////// 21 #define MMU22 23 21 #define RESET_BASE 0xBFC00000 24 22 #define RESET_SIZE 0x00010000 … … 29 27 #define TEXT_BASE 0x00400000 30 28 #define TEXT_SIZE 0x00050000 29 31 30 ///////////////////////////////////////////////////////////////// 32 31 // global data segment (initialised) … … 34 33 35 34 #define MC_M_BASE 0x10000000 36 #define MC_M_SIZE 0x00 10000035 #define MC_M_SIZE 0x000F0000 37 36 38 /////////////////////////////////////////////////////////////////39 // page table (initialised)40 /////////////////////////////////////////////////////////////////41 #define PTD_ADDR 0x4040000042 #define PTE_ADDR 0x4040200043 #define IPTE_ADDR 0x4040300044 #define TAB_SIZE 0x0001000045 46 #define V_TTY_BASE 0x0080000047 #define V_TIMER_BASE 0x00C00000 // timer virtual address48 37 ////////////////////////////////////////////////////////// 49 38 // System devices … … 53 42 #define TTY_SIZE 0x00000100 54 43 55 #define TIMER_BASE 0xD020000056 #define TIMER_SIZE 0x0000010044 #define XICU_BASE 0xD0200000 45 #define XICU_SIZE 0x00000100 57 46 58 #define LOCKS_BASE 0xE020000059 #define LOCKS_SIZE 0x0000010047 #define SIMHELPER_BASE 0xF0200000 48 #define SIMHELPER_SIZE 0x00000100 60 49 61 #define C_PROC0_BASE 0x01200000 62 #define C_PROC0_SIZE 0x00000010 63 64 #define C_PROC1_BASE 0x02200000 65 #define C_PROC1_SIZE 0x00000010 66 67 #define C_PROC2_BASE 0x03200000 68 #define C_PROC2_SIZE 0x00000010 69 70 #define C_PROC3_BASE 0x04200000 71 #define C_PROC3_SIZE 0x00000010 72 73 #define C_MC_M_BASE 0x00200000 74 #define C_MC_M_SIZE 0x00000008 75 76 #define XRAM_BASE 0xB0200000 77 #define XRAM_SIZE 0x00000008 50 #define C_PROC_BASE 0x01200000 51 #define C_PROC_SIZE 0x00000010 52 #define C_PROC_SPAN 0x01000000 78 53 79 54 #define MC_R_BASE 0x20200000 80 55 #define MC_R_SIZE 0x00000008 81 56 82 #define CLEANUP_OFFSET 0x20200000 57 //#define C_MC_M_BASE 0x00200000 58 //#define C_MC_M_SIZE 0x00000008 59 60 //#define XRAM_BASE 0xB0200000 61 //#define XRAM_SIZE 0x00000008 62 63 //#define CLEANUP_OFFSET 0x20200000 -
trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/Makefile
r107 r134 1 ADD_OBJS= stdio.o stdlib.o exception.o system.o 2 SOCLIB?=$(shell soclib-cc --getpath) 1 ADD_OBJS = stdio.o stdlib.o exception.o system.o \ 2 $(patsubst %.c,%.o,$(wildcard *.c)) \ 3 $(patsubst common/%.c,common/%.o,$(wildcard common/*.c)) \ 4 $(patsubst irq/%.c,irq/%.o,$(wildcard irq/*.c)) \ 5 $(patsubst benchmark/%.c,benchmark/%.o,$(wildcard benchmark/*.c)) \ 6 $(patsubst matrix_multiplication/%.c,matrix_multiplication/%.o,$(wildcard matrix_multiplication/*.c)) \ 7 $(patsubst sort/%.c,sort/%.o,$(wildcard sort/*.c)) \ 8 $(patsubst dhrystone/%.c,dhrystone/%.o,$(wildcard dhrystone/*.c)) 9 10 ADD_CFLAGS = 11 SOCLIB ?= $(shell soclib-cc --getpath) 12 3 13 export SOCLIB 4 14 include $(SOCLIB)/soclib/platform/topcells/soft.mk -
trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/main.c
r107 r134 1 1 #include "system.h" 2 2 #include "stdio.h" 3 #include "stdlib.h"4 //#include "matrice.h"5 3 6 #include "../segmentation.h" 7 8 #define NPROCS 4 9 #define SIZE 500 10 #define SORT_TYPE 2 11 12 volatile int nprocs=NPROCS; 13 unsigned int gQSortNum0[16000] = { 14 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 15 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 16 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 17 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 18 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 19 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 20 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 21 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 22 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 23 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 24 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 25 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 26 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 27 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 28 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 29 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 30 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 31 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 32 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 33 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 34 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 35 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 36 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 37 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 38 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 39 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 40 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 41 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 42 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 43 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 44 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 45 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 46 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 47 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 48 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 49 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 50 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 51 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 52 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 53 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 54 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 55 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 56 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 57 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 58 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 59 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 60 61 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 62 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 63 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 64 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 65 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 66 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 67 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 68 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 69 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 70 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 71 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 72 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 73 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 74 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 75 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 76 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 77 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 78 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 79 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 80 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 81 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 82 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 83 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 84 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 85 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 86 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 87 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 88 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 89 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 90 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 91 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 92 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 93 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 94 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 95 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 96 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 97 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 98 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 99 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 100 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 101 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 102 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 103 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 104 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 105 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 106 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 107 108 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 109 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 110 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 111 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 112 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 113 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 114 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 115 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 116 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 117 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 118 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 119 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 120 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 121 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 122 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 123 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 124 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 125 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 126 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 127 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 128 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 129 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 130 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 131 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 132 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 133 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 134 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 135 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 136 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 137 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 138 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 139 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 140 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 141 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 142 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 143 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 144 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 145 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 146 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 147 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 148 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 149 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 150 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 151 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 152 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 153 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 154 155 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 156 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 157 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 158 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 159 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 160 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 161 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 162 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 163 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 164 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 165 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 166 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 167 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 169 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 170 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 171 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 172 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 173 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 174 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 175 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 176 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 177 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 178 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 179 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 180 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 181 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 182 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 183 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 184 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 185 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 187 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 188 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 189 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 190 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 191 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 192 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 193 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 194 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 195 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 196 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 197 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 198 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 199 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 200 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 201 202 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 203 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 204 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 205 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 206 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 207 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 208 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 209 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 210 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 211 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 212 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 213 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 214 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 215 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 216 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 217 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 218 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 219 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 220 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 221 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 222 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 223 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 224 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 225 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 226 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 227 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 228 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 229 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 230 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 231 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 232 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 233 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 234 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 235 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 236 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 237 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 238 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 239 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 240 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 241 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 242 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 243 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 244 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 245 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 246 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 247 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 248 249 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 250 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 251 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 252 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 253 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 254 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 255 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 256 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 257 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 258 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 259 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 260 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 261 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 262 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 263 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 264 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 265 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 266 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 267 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 268 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 269 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 270 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 271 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 272 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 273 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 274 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 275 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 276 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 277 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 278 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 279 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 280 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 281 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 282 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 283 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 284 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 285 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 286 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 287 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 288 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 289 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 290 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 291 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 292 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 293 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 294 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 295 296 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 297 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 298 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 299 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 300 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 301 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 302 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 303 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 304 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 305 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 306 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 307 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 308 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 309 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 310 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 311 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 312 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 313 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 314 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 315 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 316 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 317 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 318 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 319 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 320 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 321 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 322 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 323 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 324 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 325 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 326 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 327 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 328 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 329 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 330 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 331 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 332 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 333 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 334 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 335 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 336 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 337 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 338 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 339 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 340 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 341 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 342 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 343 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 344 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 345 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 346 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 347 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 348 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 349 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 350 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 351 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 352 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 353 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 354 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 355 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 356 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 357 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 358 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 359 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 360 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 361 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 362 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 363 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 364 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 365 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6, 366 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 367 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137, 368 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181, 369 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161, 370 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 371 254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 372 254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 373 186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117, 374 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169, 375 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 376 32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 377 60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 378 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 379 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147, 380 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 381 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 382 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 383 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 384 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 385 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 386 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 387 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 388 57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31, 389 6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114, 390 81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151, 391 124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76, 392 107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189, 393 78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186, 394 149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211, 395 16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168, 396 79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89, 397 30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166, 398 25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 399 92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 400 141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75, 401 182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174, 402 221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139, 403 152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80, 404 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 405 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 406 225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249, 407 204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252, 408 123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83, 409 30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22, 410 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 411 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 412 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 413 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 414 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193, 415 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44, 416 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 417 122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 418 147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251, 419 232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160, 420 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 421 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 422 113, 228, 219, 423 250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119, 424 228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172, 425 117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157, 426 238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230, 427 181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77, 428 144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72, 429 430 57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31, 431 6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114, 432 81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151, 433 124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76, 434 107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189, 435 78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186, 436 149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211, 437 16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168, 438 79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89, 439 30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166, 440 25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 441 92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 442 141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75, 443 182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174, 444 221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139, 445 152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80, 446 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 447 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 448 225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249, 449 204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252, 450 123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83, 451 30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22, 452 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 453 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 454 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 455 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 456 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193, 457 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44, 458 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 459 122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 460 147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251, 461 232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160, 462 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 463 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 464 113, 228, 219, 465 250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119, 466 228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172, 467 117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157, 468 238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230, 469 181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77, 470 144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72, 471 472 57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31, 473 6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114, 474 81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151, 475 124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76, 476 107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189, 477 78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186, 478 149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211, 479 16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168, 480 79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89, 481 30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166, 482 25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 483 92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 484 141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75, 485 182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174, 486 221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139, 487 152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80, 488 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 489 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 490 225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249, 491 204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252, 492 123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83, 493 30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22, 494 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 495 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 496 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 497 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 498 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193, 499 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44, 500 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 501 122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 502 147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251, 503 232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160, 504 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 505 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 506 113, 228, 219, 507 250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119, 508 228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172, 509 117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157, 510 238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230, 511 181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77, 512 144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72, 513 514 57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31, 515 6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114, 516 81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151, 517 124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76, 518 107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189, 519 78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186, 520 149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211, 521 16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168, 522 79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89, 523 30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166, 524 25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 525 92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 526 141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75, 527 182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174, 528 221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139, 529 152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80, 530 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 531 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 532 225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249, 533 204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252, 534 123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83, 535 30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22, 536 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 537 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 538 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 539 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 540 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193, 541 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44, 542 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 543 122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 544 147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251, 545 232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160, 546 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 547 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 548 113, 228, 219, 549 250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119, 550 228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172, 551 117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157, 552 238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230, 553 181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77, 554 144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72, 555 556 57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31, 557 6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114, 558 81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151, 559 124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76, 560 107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189, 561 78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186, 562 149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211, 563 16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168, 564 79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89, 565 30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166, 566 25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 567 92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 568 141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75, 569 182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174, 570 221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139, 571 152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80, 572 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 573 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 574 225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249, 575 204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252, 576 123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83, 577 30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22, 578 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 579 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 580 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 581 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 582 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193, 583 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44, 584 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 585 122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 586 147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251, 587 232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160, 588 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 589 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 590 113, 228, 219, 591 250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119, 592 228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172, 593 117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157, 594 238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230, 595 181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77, 596 144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72, 597 598 57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31, 599 6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114, 600 81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151, 601 124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76, 602 107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189, 603 78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186, 604 149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211, 605 16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168, 606 79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89, 607 30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166, 608 25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 609 92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 610 141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75, 611 182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174, 612 221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139, 613 152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80, 614 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 615 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 616 225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249, 617 204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252, 618 123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83, 619 30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22, 620 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 621 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 622 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 623 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 624 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193, 625 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44, 626 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 627 122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 628 147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251, 629 232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160, 630 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 631 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 632 113, 228, 219, 633 250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119, 634 228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172, 635 117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157, 636 238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230, 637 181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77, 638 144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72, 639 640 57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31, 641 6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114, 642 81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151, 643 124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76, 644 107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189, 645 78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186, 646 149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211, 647 16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168, 648 79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89, 649 30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166, 650 25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 651 92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 652 141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75, 653 182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174, 654 221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139, 655 152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80, 656 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 657 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 658 225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249, 659 204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252, 660 123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83, 661 30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22, 662 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 663 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 664 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 665 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 666 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193, 667 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44, 668 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 669 122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 670 147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251, 671 232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160, 672 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 673 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 674 113, 228, 219, 675 250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119, 676 228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172, 677 117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157, 678 238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230, 679 181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77, 680 144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72, 681 682 57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31, 683 6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114, 684 81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151, 685 124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76, 686 107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189, 687 78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186, 688 149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211, 689 16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168, 690 79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89, 691 30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166, 692 25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 693 92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 694 141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75, 695 182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174, 696 221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139, 697 152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80, 698 215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209, 699 202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190, 700 225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249, 701 204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252, 702 123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83, 703 30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22, 704 37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67, 705 192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 706 161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183, 707 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42, 708 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193, 709 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44, 710 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 711 122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 712 147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251, 713 232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160, 714 231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63, 715 154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18, 716 113, 228, 219, 717 250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119, 718 228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172, 719 117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157, 720 238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230, 721 181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77, 722 144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72 723 }; 724 725 726 727 unsigned int SortArr0[NPROCS*(SIZE+200)]; 728 //unsigned int SortArr0[4*4*SIZE]; 729 730 void SORT(unsigned int *base, unsigned int n, int type); 731 void insertion_sort(unsigned int *base, unsigned int n); // type 2 732 void selection_sort(unsigned int *base, unsigned int n); // type 1 733 void bubble_sort(unsigned int *base, unsigned int n); // type 3 734 void shellSortPhase(unsigned int a[],unsigned int length, int gap); 735 void shellSort(unsigned int *base, unsigned int n); // type 0 4 #include "define.h" 5 #include "common/common.h" 6 #include "benchmark/benchmark.h" 7 #include "irq/irq.h" 736 8 737 9 int main() 738 10 { 739 register int p; 11 system_start(); 12 13 #if TIMER_INTERRUPT 14 irq_init(); 15 #endif 16 17 benchmark(); 18 19 EXIT(0); 740 20 741 int beg_cycle, end_cycle; 742 743 beg_cycle = cpu_cycles(); 744 745 p=procnum(); 746 747 puts("Hello from processor "); 748 putchar(p+'0'); 749 putchar('\n'); 750 751 int i; 752 int j; 753 unsigned int* SortArray; 754 755 if(p+1 <= nprocs) 756 { 757 i=1; 758 puts("Memory copy \n"); 759 SortArray = SortArr0 + p*(SIZE+200); 760 memcpy(SortArray, gQSortNum0 + p*SIZE,SIZE*4); 761 puts("Sort... \n"); 762 SORT((unsigned int *) (SortArray), (unsigned int) SIZE, SORT_TYPE); 763 764 for (j = 1; j < SIZE; j++) 765 { 766 if (SortArray[j] < SortArray[j-1]) 767 { 768 puts("ucbqsort: failed\n"); 769 while(1); 770 } 771 772 } 773 774 puts("ucbqsort: success\n"); 775 end_cycle = cpu_cycles(); 776 printf( "nombre cycles cpu : %i\n", end_cycle-beg_cycle); 777 } 778 779 780 // puts("Display the sorted array : \n"); 781 // for(j = 0; j < SIZE; j++) 782 // { 783 // puti(SortArray[j]); 784 // putchar('\n'); 785 // } 786 787 // printf( "------------------------------ \n"); 788 // printf( "nombre cycles cpu : %i\n", end_cycle-beg_cycle); 789 // printf( "------------------------------ \n"); 790 791 792 while(1); 21 return 1; 793 22 } 794 795 796 //---- insertion sort : non adapté pour tableaux de grande taille (> 100) --797 void insertion_sort(unsigned int *base, unsigned int n)798 {799 /* Spécifications externes : Tri du tableau base par insertion séquentielle */800 int i,p,j;801 int x;802 803 puts("Insertion Sort\n");804 805 for (i = 1; i < n; i++)806 {807 808 putchar('-'); // added for debug809 810 /* stockage de la valeur en i */811 x = base[i];812 813 /* recherche du plus petit indice p inférieur à i tel que base[p] >= base[i] */814 for(p = 0; base[p] < x; p++);815 /* p pointe une valeur de base supérieure à celle en i */816 817 /* décalage avant des valeurs de base entre p et i */818 for (j = i-1; j >= p; j--) {819 base[j+1] = base[j];820 }821 822 base[p] = x; /* insertion de la valeur stockée à la place vacante */823 824 putchar('+'); // added for debug825 826 }827 }828 829 //------ simple_sort -------------------------------830 void selection_sort(unsigned int *base, unsigned int n)831 {832 int i, min, j , x;833 puts("Selection Sort\n");834 835 for(i = 0 ; i < n - 1 ; i++)836 {837 838 putchar('-'); // added for debug839 840 min = i;841 842 843 for(j = i+1 ; j < n ; j++)844 {845 846 if(base[j] < base[min])847 min = j;848 849 }850 851 if(min != i)852 {853 x = base[i];854 base[i] = base[min];855 base[min] = x;856 }857 858 putchar('+'); // added for debug859 860 }861 }862 //-------------------------------863 void bubble_sort(unsigned int *base, unsigned int n)864 {865 int i = 0; /* Indice de répétition du tri */866 int j = 0; /* Variable de boucle */867 int tmp = 0; /* Variable de stockage temporaire */868 int en_desordre = 1; /* Booléen marquant l'arrêt du tri si le tableau est ordonné */869 870 puts("Bubble Sort\n");871 872 /* Boucle de répétition du tri et le test qui arrête le tri dès que le tableau est ordonné */873 for(i = 0 ; (i < n) && en_desordre; i++)874 {875 putchar('-'); // added for debug876 877 /* Supposons le tableau ordonné */878 en_desordre = 0;879 /* Vérification des éléments des places j et j-1 */880 for(j = 1 ; j < n - i ; j++)881 {882 /* Si les 2 éléments sont mal triés */883 if(base[j] < base[j-1])884 {885 /* Inversion des 2 éléments */886 tmp = base[j-1];887 base[j-1] = base[j];888 base[j] = tmp;889 890 /* Le tableau n'est toujours pas trié */891 en_desordre = 1;892 }893 }894 895 putchar('+'); // added for debug896 }897 898 }899 //------------------------------------------------------900 /*901 * Exécute un tri par insertion avec la séparation donnée902 * If gap == 1, on fait un tri ordinaire.903 * If gap >= length, on ne fait rien.904 */905 void shellSortPhase(unsigned int a[],unsigned int length, int gap) {906 int i;907 908 puti(gap);909 for (i = gap; i < length; ++i) {910 unsigned int value = a[i];911 int j;912 for (j = i - gap; j >= 0 && a[j] > value; j -= gap) {913 putchar('+');914 a[j + gap] = a[j];915 putchar('-');916 }917 a[j + gap] = value;918 }919 }920 921 void shellSort(unsigned int *base, unsigned int n) {922 /*923 * gaps[] doit approximer une Série géométrique.924 * La sequence suivante est la meilleure connue en terme925 * de nombre moyen de comparaisons. voir:926 * http://www.research.att.com/~njas/sequences/A102549927 */928 static const int gaps[] = {929 1, 4, 10, 23, 57, 132, 301, 701930 };931 int sizeIndex;932 933 puts("Shell Sort\n");934 for (sizeIndex = sizeof(gaps)/sizeof(gaps[0]) - 1;935 sizeIndex >= 0;936 --sizeIndex)937 shellSortPhase(base, n, gaps[sizeIndex]);938 }939 940 //-------------------------------------*/941 void SORT(unsigned int *base, unsigned int n, int type)942 {943 switch(type)944 {945 case 0:946 shellSort(base, n);947 break;948 case 1:949 selection_sort(base, n);950 break;951 case 2:952 insertion_sort(base, n);953 break;954 case 3:955 bubble_sort(base, n);956 break;957 default:958 break;959 }960 }961 -
trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp
r107 r134 1 2 1 #include <systemc> 3 2 #include <sys/time.h> 4 3 #include <iostream> 4 #include <sstream> 5 5 #include <cstdlib> 6 6 #include <cstdarg> 7 #include <stdint.h> 8 #include <fstream> 7 9 8 10 #include "mapping_table.h" 9 11 #include "mips32.h" 12 #include "vci_simhelper.h" 10 13 #include "vci_simple_ram.h" 11 14 #include "vci_multi_tty.h" 15 #include "vci_xicu.h" 12 16 #include "vci_simple_ring_network_2.h" 13 17 #include "vci_vgmn.h" 14 18 #include "vci_mem_cache_v4.h" 15 19 #include "vci_cc_xcache_wrapper_v4.h" 16 #include " vci_logger.h"20 #include "alloc_elems.h" 17 21 18 22 #include "iss/gdbserver.h" 19 23 20 //#define VCI_LOGGER21 24 #include "segmentation.h" 22 #define USE_VGMN 25 26 //=========================================== 27 // Define before include 28 //=========================================== 29 30 // Parameters 31 // * Platforms 32 # define PARAM_VCI 4,8,32,1,1,1,8,4,4,1 33 34 # define USE_OLD_XCACHE 1 35 # define USE_VGMN 1 36 # define NB_PROC_MIN 1 37 # define NB_PROC_MAX 15 38 // min_latency, fifo_depth 39 # define PARAM_VGMN_P 1 , 8 40 # define PARAM_VGMN_C 1 , 8 41 # define PARAM_VGMN_X 2 , 8 42 // wrapper_fifo_depth 43 # define PARAM_RING_P 2 44 # define PARAM_RING_C 2 45 # define PARAM_RING_X 2 46 // pti , hwi , wti, irq 47 # define PARAM_XICU nb_proc, nb_proc, 0 , nb_proc 48 49 // * Debug 50 # define DEBUG_TOP 0 51 # define SOCVIEW 0 52 # define STOP_SIMULATION_NB_FRZ_CYCLES 100000 53 54 // * Simulation 55 # define FILE_DEFAULT "configuration/default.cfg" 56 # define NCYCLES_DEFAULT 0 57 # define SOFT_DEFAULT "soft/bin.soft" 58 //=========================================== 59 60 void usage (char * funcname) 61 { 62 std::cout << funcname << " [nb_cycle [file [soft]]] " << std::endl; 63 std::cout << " * nb_cycle : number of simulated cycle, if 0 then no stop condition. (default : " << NCYCLES_DEFAULT << " cycle(s))" << endl; 64 std::cout << " * file : Configuration file : nb_proc, iways, isets, iwords, dways, dsets, dwords, wnwords, wnlines, wtimeout, memc_nways, memc_nsets, memc_words, memc_heap_size. (default : " << FILE_DEFAULT << " cycle(s))" << endl; 65 std::cout << " * soft : software executed by this platforms. (default : \"" << SOFT_DEFAULT << "\")" << endl; 66 67 exit(1); 68 } 23 69 24 70 int _main(int argc, char *argv[]) 25 71 { 72 if ((argc < 1) or (argc > 4)) 73 { 74 std::cout << "Invalid parameters number." << std::endl; 75 usage(argv[0]); 76 } 77 78 #if not SOCVIEW 79 int ncycles = 0; 80 81 if (argc >= 2) 82 ncycles = std::atoi(argv[1]); 83 else 84 ncycles = NCYCLES_DEFAULT; 85 86 if (ncycles == 0) 87 ncycles = -1; 88 #endif 89 90 uint32_t nb_proc; 91 uint32_t iways, isets, iwords; 92 uint32_t dways, dsets, dwords; 93 uint32_t wnwords, wnlines, wtimeout; 94 uint32_t memc_nways, memc_nsets, memc_words, memc_heap_size; 95 96 std::ifstream inFile; 97 const char * filename = (argc>=3)?argv[2]:FILE_DEFAULT; 98 99 inFile.open(filename); 100 101 if (!inFile) 102 { 103 std::cout << "Can't open file : \"" << filename << "\"." << std::endl; 104 usage(argv[0]); 105 } 106 107 std::string str; 108 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 109 nb_proc =std::atoi(str.c_str()); 110 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 111 iways =std::atoi(str.c_str()); 112 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 113 isets =std::atoi(str.c_str()); 114 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 115 iwords =std::atoi(str.c_str()); 116 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 117 dways =std::atoi(str.c_str()); 118 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 119 dsets =std::atoi(str.c_str()); 120 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 121 dwords =std::atoi(str.c_str()); 122 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 123 wnwords =std::atoi(str.c_str()); 124 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 125 wnlines =std::atoi(str.c_str()); 126 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 127 wtimeout =std::atoi(str.c_str()); 128 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 129 memc_nways =std::atoi(str.c_str()); 130 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 131 memc_nsets =std::atoi(str.c_str()); 132 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 133 memc_words =std::atoi(str.c_str()); 134 if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);} 135 memc_heap_size =std::atoi(str.c_str()); 136 137 if ((nb_proc<NB_PROC_MIN) or 138 (nb_proc>NB_PROC_MAX)) 139 { 140 std::cout << "Parameters nb_proc is out of bound." << std::endl; 141 usage(argv[0]); 142 } 143 144 char * soft; 145 146 if (argc >= 4) 147 soft = argv[3]; 148 else 149 soft = SOFT_DEFAULT; 150 151 std::cout << " * Parameters : " << std::endl; 152 std::cout << " * nb_proc : " << nb_proc << std::endl; 153 std::cout << " * iways : " << iways << std::endl; 154 std::cout << " * isets : " << isets << std::endl; 155 std::cout << " * iwords : " << iwords << std::endl; 156 std::cout << " * dways : " << dways << std::endl; 157 std::cout << " * dsets : " << dsets << std::endl; 158 std::cout << " * dwords : " << dwords << std::endl; 159 std::cout << " * wnwords : " << wnwords << std::endl; 160 std::cout << " * wnlines : " << wnlines << std::endl; 161 std::cout << " * wtimeout : " << wtimeout << std::endl; 162 std::cout << " * memc_nways : " << memc_nways << std::endl; 163 std::cout << " * memc_nsets : " << memc_nsets << std::endl; 164 std::cout << " * memc_words : " << memc_words << std::endl; 165 std::cout << " * memc_heap_size : " << memc_heap_size << std::endl; 166 std::cout << " * Simulation : " << std::endl; 167 std::cout << " * ncycles : " << ncycles << std::endl; 168 std::cout << " * soft : " << soft << std::endl; 169