Changeset 143 for trunk/modules
- Timestamp:
- Mar 28, 2011, 6:46:33 PM (14 years ago)
- Location:
- trunk/modules
- Files:
-
- 4 edited
-
vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h (modified) (8 diffs)
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vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp (modified) (59 diffs)
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vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h (modified) (1 diff)
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vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r140 r143 43 43 44 44 /* 45 * CC_XCACHE_WRAPPER_SELECT_VICTIM :46 * The selection and the update of cache (after a read miss)47 * are separated in two step48 * Also, the cleanup can be send in parallel at the read miss.49 *50 45 * CC_XCACHE_WRAPPER_FIFO_RSP 51 46 * Two simple fifo (each 2x32 depth) receive the cache line from 52 47 * RAM. Instead of two buffers (m_icache_words and m_dcache_words) 48 * 1 - nb_icache+nb_dcache simple fifo 49 * 2 - 2 simple fifo 50 * else - two buffers (m_icache_words and m_dcache_words) 53 51 * 54 52 * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 67 65 * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 68 66 * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req 69 * 1 - two access authorized70 * 2 - one access with static priority ( dcache prior)71 * 3 - one access with static priority (icache prior)72 * 4 - one access with round robin priority67 * 1 - one access with static priority (dcache prior) 68 * 2 - one access with static priority (icache prior) 69 * 3 - one access with round robin priority 70 * 4 - two access authorized 73 71 * 74 72 * CC_XCACHE_WRAPPER_MULTI_CACHE : … … 95 93 96 94 // implementation 97 #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM98 #define CC_XCACHE_WRAPPER_SELECT_VICTIM 199 #endif100 95 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP 101 96 #define CC_XCACHE_WRAPPER_FIFO_RSP 1 … … 111 106 #endif 112 107 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 113 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 4108 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3 114 109 #endif 115 110 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE 116 111 #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 117 #endif 112 // if multi_cache : 113 // <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 114 // <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1 115 #endif 116 118 117 // debugging 118 #ifndef CC_XCACHE_WRAPPER_VERBOSE 119 #define CC_XCACHE_WRAPPER_VERBOSE 1 120 #endif 119 121 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION 120 122 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 … … 124 126 #endif 125 127 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 126 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 949900128 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1500 127 129 #endif 128 130 #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION … … 158 160 DCACHE_IDLE, 159 161 DCACHE_WRITE_UPDT, 160 #if CC_XCACHE_WRAPPER_SELECT_VICTIM161 162 DCACHE_MISS_VICTIM, 162 #endif163 163 DCACHE_MISS_WAIT, 164 164 DCACHE_MISS_UPDT, … … 176 176 enum icache_fsm_state_e { 177 177 ICACHE_IDLE, 178 #if CC_XCACHE_WRAPPER_SELECT_VICTIM179 178 ICACHE_MISS_VICTIM, 180 #endif181 179 ICACHE_MISS_WAIT, 182 180 ICACHE_MISS_UPDT, … … 341 339 sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] 342 340 343 #if CC_XCACHE_WRAPPER_FIFO_RSP341 #if (CC_XCACHE_WRAPPER_FIFO_RSP==1) 344 342 std::queue<data_t> * r_icache_miss_buf; //[m_nb_icache] 345 343 std::queue<data_t> * r_dcache_miss_buf; //[m_nb_dcache] 344 #elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) 345 typedef struct 346 { 347 data_t data; 348 uint32_t num_cache; 349 } miss_buf_t; 350 351 std::queue<miss_buf_t> r_icache_miss_buf; 352 std::queue<miss_buf_t> r_dcache_miss_buf; 346 353 #else 347 354 bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words] -
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
r140 r143 75 75 // =====[ FIFO_RSP ]================================= 76 76 77 // FIXME : une FIFO avec le numéro du cache ! 78 #if CC_XCACHE_WRAPPER_FIFO_RSP 77 #if (CC_XCACHE_WRAPPER_FIFO_RSP==1) 79 78 # define CACHE_MISS_BUF_ALLOC do { \ 80 79 r_icache_miss_buf = new std::queue<data_t> [m_nb_icache]; \ … … 106 105 PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf[x].size()); \ 107 106 } \ 107 } while (0) 108 #elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) 109 # define CACHE_MISS_BUF_ALLOC 110 # define CACHE_MISS_BUF_DEALLOC 111 # define CACHE_MISS_BUF_RESET(c) do { \ 112 while (r_##c##cache_miss_buf.size()>0) { \ 113 r_##c##cache_miss_buf.pop(); \ 114 } \ 115 } while (0) 116 # define CACHE_MISS_BUF_REQ_INIT(c,x) 117 # define CACHE_MISS_BUF_RSP_VAL(c,x,n) ((r_##c##cache_miss_buf.size()>0) and (r_##c##cache_miss_buf.front().num_cache==x)) 118 # define CACHE_MISS_BUF_RSP_ACK(c,x) (r_##c##cache_miss_buf.size()<2) 119 # define CACHE_MISS_BUF_RSP_DATA(c,x,n) r_##c##cache_miss_buf.front().data 120 # define CACHE_MISS_BUF_RSP_POP(c,x) do { \ 121 r_##c##cache_miss_buf.pop(); \ 122 } while (0) 123 # define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \ 124 miss_buf_t miss_buf; \ 125 miss_buf.data = d; \ 126 miss_buf.num_cache = x; \ 127 r_##c##cache_miss_buf.push(miss_buf); \ 128 } while (0) 129 # define CACHE_MISS_BUF_RSP_PRINT(c) do { \ 130 PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf.size()); \ 108 131 } while (0) 109 132 #else … … 187 210 "DCACHE_IDLE", 188 211 "DCACHE_WRITE_UPDT", 189 #if CC_XCACHE_WRAPPER_SELECT_VICTIM190 212 "DCACHE_MISS_VICTIM", 191 #endif192 213 "DCACHE_MISS_WAIT", 193 214 "DCACHE_MISS_UPDT", … … 204 225 const char *icache_fsm_state_str[] = { 205 226 "ICACHE_IDLE", 206 #if CC_XCACHE_WRAPPER_SELECT_VICTIM207 227 "ICACHE_MISS_VICTIM", 208 #endif209 228 "ICACHE_MISS_WAIT", 210 229 "ICACHE_MISS_UPDT", … … 254 273 } 255 274 275 typedef long long unsigned int blob_t; 276 256 277 #define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcXCacheWrapperV4<vci_param, iss_t> 257 278 … … 382 403 "When multi cache is activated, need 4 bits (16 word) to the cache set ."); 383 404 405 if (m_nb_cpu > 1) 406 ASSERT(CC_XCACHE_MULTI_CPU!=0, 407 "Macro CC_XCACHE_MULTI_CPU in wbuf must be set at 1."); 408 384 409 p_irq = new sc_in<bool> * [m_nb_cpu]; 385 410 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) … … 537 562 538 563 564 #if CC_XCACHE_WRAPPER_VERBOSE 539 565 std::cout << "<VciCcXCacheWrapperV4> Parameters :" << std::endl; 540 566 std::cout << " * nb_cpu : " << nb_cpu << std::endl; … … 546 572 std::cout << " * wbuf (total) : " << wbuf_nlines << " line(s), " << wbuf_nwords << " word(s), timeout : " << wbuf_timeout << std::endl; 547 573 std::cout << " * wbuf (per cache) : " << _wbuf_nlines << " line(s), " << _wbuf_nwords << " word(s), timeout : " << _wbuf_timeout << std::endl; 574 #endif 548 575 549 576 r_icache = new GenericCache<vci_addr_t> * [m_nb_icache]; … … 1088 1115 PRINTF(" * CC_XCACHE_WRAPPER \"%s\" Transition - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); 1089 1116 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1090 PRINTF(" * fsm dcache = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,dcache_fsm_state_str[r_dcache_fsm[num_cache]],r_dcache_lock[num_cache].read(),( uint64_t)r_dcache_addr_save[num_cache].read(),(uint64_t)set_num_dcache_only(r_dcache_addr_save[num_cache].read(),num_cache));1117 PRINTF(" * fsm dcache = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,dcache_fsm_state_str[r_dcache_fsm[num_cache]],r_dcache_lock[num_cache].read(),(blob_t)r_dcache_addr_save[num_cache].read(),(blob_t)set_num_dcache_only(r_dcache_addr_save[num_cache].read(),num_cache)); 1091 1118 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1092 PRINTF(" * fsm icache = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,icache_fsm_state_str[r_icache_fsm[num_cache]],r_icache_lock[num_cache].read(),( uint64_t)r_icache_addr_save[num_cache].read(),(uint64_t)set_num_icache_only(r_icache_addr_save[num_cache].read(),num_cache));1119 PRINTF(" * fsm icache = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,icache_fsm_state_str[r_icache_fsm[num_cache]],r_icache_lock[num_cache].read(),(blob_t)r_icache_addr_save[num_cache].read(),(blob_t)set_num_icache_only(r_icache_addr_save[num_cache].read(),num_cache)); 1093 1120 PRINTF(" * fsm cmd = (%.2d) %s\n",r_vci_cmd_num_cache.read(), cmd_fsm_state_str[r_vci_cmd_fsm]); 1094 1121 PRINTF(" * fsm rsp = (%.2d) %s\n",r_vci_rsp_num_cache.read(), rsp_fsm_state_str[r_vci_rsp_fsm]); 1095 PRINTF(" * fsm tgt = (%.2d) %s - i %llx d %llx\n",r_tgt_num_cache.read(), tgt_fsm_state_str[r_vci_tgt_fsm],( uint64_t)r_tgt_iaddr.read(),(uint64_t)r_tgt_daddr.read());1096 //PRINTF(" * fsm tgt = %s - %llx\n",tgt_fsm_state_str[r_vci_tgt_fsm],( uint64_t)r_tgt_addr.read());1122 PRINTF(" * fsm tgt = (%.2d) %s - i %llx d %llx\n",r_tgt_num_cache.read(), tgt_fsm_state_str[r_vci_tgt_fsm],(blob_t)r_tgt_iaddr.read(),(blob_t)r_tgt_daddr.read()); 1123 //PRINTF(" * fsm tgt = %s - %llx\n",tgt_fsm_state_str[r_vci_tgt_fsm],(blob_t)r_tgt_addr.read()); 1097 1124 PRINTF(" * fsm cleanup = (%.2d) %s\n",r_cleanup_num_cache.read(), cleanup_fsm_state_str[r_cleanup_fsm]); 1098 1125 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) … … 1103 1130 ,num_cpu 1104 1131 , r_dcache_ll_valid [num_cache][num_cpu].read() 1105 ,( uint64_t)r_dcache_ll_addr [num_cache][num_cpu].read()1106 ,( uint64_t)set_num_dcache_only(r_dcache_ll_addr [num_cache][num_cpu].read(),num_cache)1107 ,( uint64_t)r_dcache_ll_data [num_cache][num_cpu].read());1132 ,(blob_t)r_dcache_ll_addr [num_cache][num_cpu].read() 1133 ,(blob_t)set_num_dcache_only(r_dcache_ll_addr [num_cache][num_cpu].read(),num_cache) 1134 ,(blob_t)r_dcache_ll_data [num_cache][num_cpu].read()); 1108 1135 1109 1136 PRINTF(" * dcache_previous_unc : [%.2d] %d\n",num_cache,r_dcache_previous_unc[num_cache].read()); … … 1196 1223 PRINTF(" * <TGT> trdid : %d\n",(uint32_t)p_vci_tgt.trdid.read()); 1197 1224 PRINTF(" * <TGT> pktid : %d\n",(uint32_t)p_vci_tgt.pktid.read()); 1198 PRINTF(" * <TGT> address (before) : %llx\n",( uint64_t)tgt_iaddr);1225 PRINTF(" * <TGT> address (before) : %llx\n",(blob_t)tgt_iaddr); 1199 1226 1200 1227 r_tgt_srcid = p_vci_tgt.srcid.read(); … … 1231 1258 << "BROADCAST " 1232 1259 << std::hex 1233 << " L " << std::setw(10) << ( uint64_t)tgt_addr1260 << " L " << std::setw(10) << (blob_t)tgt_addr 1234 1261 << std::dec 1235 1262 << " - " << tgt_num_cache … … 1268 1295 << "INVAL DATA " 1269 1296 << std::hex 1270 << " L " << std::setw(10) << ( uint64_t)tgt_addr1297 << " L " << std::setw(10) << (blob_t)tgt_addr 1271 1298 << std::dec 1272 1299 << " - " << tgt_num_cache … … 1301 1328 << "INVAL INS " 1302 1329 << std::hex 1303 << " L " << std::setw(10) << ( uint64_t)tgt_addr1330 << " L " << std::setw(10) << (blob_t)tgt_addr 1304 1331 << std::dec 1305 1332 << " - " << tgt_num_cache … … 1334 1361 << "UPT DATA " 1335 1362 << std::hex 1336 << " L " << std::setw(10) << ( uint64_t)tgt_addr1363 << " L " << std::setw(10) << (blob_t)tgt_addr 1337 1364 << std::dec 1338 1365 << " - " << tgt_num_cache … … 1359 1386 << "UPT INS " 1360 1387 << std::hex 1361 << " L " << std::setw(10) << ( uint64_t)tgt_addr1388 << " L " << std::setw(10) << (blob_t)tgt_addr 1362 1389 << std::dec 1363 1390 << " - " << tgt_num_cache … … 1374 1401 r_tgt_iaddr = tgt_iaddr; 1375 1402 r_tgt_daddr = tgt_daddr; 1376 PRINTF(" * <TGT> address (after) : i %llx, d %llx\n",( uint64_t)tgt_iaddr,(uint64_t)tgt_daddr);1403 PRINTF(" * <TGT> address (after) : i %llx, d %llx\n",(blob_t)tgt_iaddr,(blob_t)tgt_daddr); 1377 1404 1378 1405 } // end if cmdval … … 1562 1589 // } 1563 1590 1564 PRINTF(" * <TGT> icache_rsp : %d\n",(uint32_t) r_tgt_icache_rsp );1591 PRINTF(" * <TGT> icache_rsp : %d\n",(uint32_t) r_tgt_icache_rsp[r_tgt_num_cache]); 1565 1592 PRINTF(" * <TGT> dcache_rsp[%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read()); 1566 1593 // if there is no need for a response … … 1816 1843 if ( icache_cached ) 1817 1844 { 1818 #if CC_XCACHE_WRAPPER_SELECT_VICTIM1819 1845 r_icache_fsm [num_cache] = ICACHE_MISS_VICTIM; 1820 #else1821 r_icache_fsm [num_cache] = ICACHE_MISS_WAIT;1822 #endif1823 1846 r_icache_miss_req[num_cache] = true; 1824 1847 … … 1844 1867 } 1845 1868 ////////////////////// 1846 #if CC_XCACHE_WRAPPER_SELECT_VICTIM1847 1869 case ICACHE_MISS_VICTIM: 1848 1870 { … … 1863 1885 break; 1864 1886 } 1865 #endif1866 1887 ////////////////////// 1867 1888 case ICACHE_MISS_WAIT: … … 1888 1909 r_icache_fsm[num_cache] = ICACHE_ERROR; 1889 1910 } else { 1890 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM 1891 if (not r_icache_cleanup_req[num_cache].read()) 1892 #endif 1893 { 1894 r_icache_update_addr[num_cache] = 0; 1895 r_icache_fsm [num_cache] = ICACHE_MISS_UPDT; 1896 } 1911 r_icache_update_addr[num_cache] = 0; 1912 r_icache_fsm [num_cache] = ICACHE_MISS_UPDT; 1897 1913 } 1898 1914 } … … 1941 1957 size_t word = r_icache_update_addr[num_cache].read(); 1942 1958 vci_addr_t addr = (vci_addr_t) r_icache_addr_save [num_cache].read(); 1943 size_t way = 0; 1944 size_t set = 0; 1945 1946 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1947 way = r_icache_miss_way[num_cache].read(); 1948 set = r_icache_miss_set[num_cache].read(); 1949 #else 1950 // need invalid rsp, don't select a victim 1951 if (not r_icache_inval_rsp[num_cache]) 1952 { 1953 // First word : select an victim ! 1954 if (word == 0) 1955 { 1956 vci_addr_t victim; 1957 1958 // r_icache_cleanup_req is false because is the transition condition to go in ICACHE_MISS_UPDT state 1959 r_icache_cleanup_req[num_cache] = r_icache[num_cache]->victim_select(addr, &victim, &way, &set ); 1960 r_icache[num_cache]->victim_update_tag(addr, way, set); 1961 1962 r_icache_cleanup_line[num_cache] = (addr_40) victim; 1963 r_icache_miss_way [num_cache] = way; 1964 r_icache_miss_set [num_cache] = set; 1965 } 1966 else 1967 { 1968 way = r_icache_miss_way[num_cache].read(); 1969 set = r_icache_miss_set[num_cache].read(); 1970 } 1971 } 1972 #endif 1959 size_t way = r_icache_miss_way[num_cache].read(); 1960 size_t set = r_icache_miss_set[num_cache].read(); 1961 1973 1962 bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,word); 1974 1963 1975 1964 if (val) 1976 1965 { 1977 PRINTF(" * <ICACHE [%d]> rsp_val : %d/%d\n",num_cache,(int)r_icache_update_addr[num_cache], m_icache_words);1966 PRINTF(" * <ICACHE [%d]> rsp_val : %d/%d\n",num_cache,(int)r_icache_update_addr[num_cache],(int)m_icache_words); 1978 1967 PRINTF(" * <ICACHE [%d]> r_icache_inval_rsp : %d\n" ,num_cache,(int)r_icache_inval_rsp[num_cache]); 1979 1968 PRINTF(" * <ICACHE [%d]> ins : %x\n" ,num_cache,(int)CACHE_MISS_BUF_RSP_DATA(i,num_cache,word)); … … 1994 1983 if (word >= m_icache_words) 1995 1984 { 1996 #if CC_XCACHE_WRAPPER_SELECT_VICTIM1997 1985 // in all case (inval_rsp or not), update the victim tag 1998 1986 r_icache[num_cache]->victim_update_tag(addr, way, set); 1999 #endif2000 1987 2001 1988 // Last word : if previous invalid_rsp, can cleanup, else update the TAG … … 2017 2004 case ICACHE_CC_CLEANUP: 2018 2005 { 2019 // external cache invalidate request2020 if ( r_tgt_icache_req[num_cache])2021 {2022 r_icache_fsm [num_cache] = ICACHE_CC_CHECK;2023 r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache].read();2024 break;2025 }2026 2006 // cleanup 2027 2007 if(not r_icache_cleanup_req[num_cache]){ … … 2030 2010 r_icache_fsm [num_cache] = ICACHE_IDLE; 2031 2011 2032 // FIXME : too many access at the cache in this cycle2033 2012 m_cpt_icache_dir_read += m_icache_ways; 2034 2013 r_icache[num_cache]->inval((addr_40)r_icache_addr_save[num_cache]); … … 2313 2292 m_cost_data_miss_frz++; 2314 2293 r_dcache_miss_req [num_cache] = true; 2315 #if CC_XCACHE_WRAPPER_SELECT_VICTIM2316 2294 r_dcache_fsm [num_cache] = DCACHE_MISS_VICTIM; 2317 #else2318 r_dcache_fsm [num_cache] = DCACHE_MISS_WAIT;2319 #endif2320 2295 2321 2296 } else { … … 2425 2400 set_num_dcache(addr,num_cache); 2426 2401 2427 // FIXME : virer le set_num_dcache ! 2428 valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached); 2429 2402 // FIXME : 2403 // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) 2404 // * pour cela, virer le set_num_dcache ! 2405 valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); 2430 2406 PRINTF(" * <DCACHE [%d]> r_wbuf valid : %d\n",num_cache,valid); 2431 2407 … … 2485 2461 } 2486 2462 ////////////////////// 2487 #if CC_XCACHE_WRAPPER_SELECT_VICTIM2488 2463 case DCACHE_MISS_VICTIM: 2489 2464 { … … 2501 2476 r_dcache_miss_set [num_cache] = set; 2502 2477 2503 PRINTF(" * <DCACHE [%d]> MISS_VICTIM : Victim %d - %llx (way %d, set %d)\n",num_cache,victim_val, ( uint64_t)victim, way,set);2478 PRINTF(" * <DCACHE [%d]> MISS_VICTIM : Victim %d - %llx (way %d, set %d)\n",num_cache,victim_val, (blob_t)victim, (int)way, (int)set); 2504 2479 2505 2480 r_dcache_fsm [num_cache] = DCACHE_MISS_WAIT; … … 2508 2483 break; 2509 2484 } 2510 #endif2511 2485 ////////////////////// 2512 2486 case DCACHE_MISS_WAIT: … … 2530 2504 else 2531 2505 { 2532 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM 2533 if (not r_dcache_cleanup_req[num_cache].read()) 2534 #endif 2535 { 2536 r_dcache_update_addr[num_cache] = 0; 2537 r_dcache_fsm [num_cache] = DCACHE_MISS_UPDT; 2538 } 2506 r_dcache_update_addr[num_cache] = 0; 2507 r_dcache_fsm [num_cache] = DCACHE_MISS_UPDT; 2539 2508 } 2540 2509 } … … 2546 2515 size_t word = r_dcache_update_addr[num_cache].read(); 2547 2516 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save[num_cache].read(); 2548 size_t way = 0;2549 size_t set = 0;2517 size_t way = r_dcache_miss_way[num_cache].read(); 2518 size_t set = r_dcache_miss_set[num_cache].read(); 2550 2519 2551 // need invalid rsp, don't select a victim 2552 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 2553 way = r_dcache_miss_way[num_cache].read(); 2554 set = r_dcache_miss_set[num_cache].read(); 2555 #else 2556 if (not r_dcache_inval_rsp[num_cache] ) 2557 { 2558 // First word : select an victim ! 2559 if (word == 0) 2560 { 2561 vci_addr_t victim; 2562 2563 // r_dcache_cleanup_req is false (condition to enter in DCACHE_MISS_UPDT 2564 r_dcache_cleanup_req [num_cache] = r_dcache[num_cache]->victim_select(addr, &victim, &way, &set ); 2565 r_dcache[num_cache]->victim_update_tag(addr, way, set); 2566 r_dcache_cleanup_line[num_cache] = (addr_40) victim; 2567 2568 r_dcache_miss_way [num_cache] = way; 2569 r_dcache_miss_set [num_cache] = set; 2570 } 2571 else 2572 { 2573 way = r_dcache_miss_way[num_cache].read(); 2574 set = r_dcache_miss_set[num_cache].read(); 2575 } 2576 } 2577 #endif 2578 2579 PRINTF(" * <DCACHE [%d]> MISS_UPDT : Victim way %d, set %d\n",num_cache, way, set); 2520 PRINTF(" * <DCACHE [%d]> MISS_UPDT : Victim way %d, set %d\n",num_cache, (int)way, (int)set); 2580 2521 2581 2522 if (CACHE_MISS_BUF_RSP_VAL(d,num_cache,word)) … … 2598 2539 if (word >= m_dcache_words) 2599 2540 { 2600 #if CC_XCACHE_WRAPPER_SELECT_VICTIM2601 2541 // in all case (inval_rsp or not), update the victim tag 2602 2542 // because victim is already cleanup 2603 2543 r_dcache[num_cache]->victim_update_tag(addr, way, set); 2604 #endif2605 2544 2606 2545 // Last word : if previous invalid_rsp, can cleanup, else update the TAG … … 2736 2675 PRINTF(" * <DCACHE [%d]> CC_CHECK\n",num_cache); 2737 2676 2677 // 2738 2678 if((r_dcache_fsm_save[num_cache] == DCACHE_MISS_WAIT) and 2739 2679 ((r_dcache_addr_save[num_cache].read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) { … … 2886 2826 case DCACHE_CC_CLEANUP: 2887 2827 { 2888 // external cache invalidate request2889 if ( r_tgt_dcache_req[num_cache] )2890 {2891 r_dcache_fsm [num_cache] = DCACHE_CC_CHECK;2892 r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache];2893 break;2894 }2895 2828 // cleanup 2896 2829 if(not r_dcache_cleanup_req[num_cache]){ … … 2899 2832 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2900 2833 2901 // FIXME : too many access at the cache in this cycle2902 2834 m_cpt_dcache_dir_read += m_dcache_ways; 2903 2835 r_dcache[num_cache]->inval((addr_40)r_dcache_addr_save[num_cache]); … … 3108 3040 r_cleanup_num_cache = num_cache; 3109 3041 3110 PRINTF(" * <CLEANUP> address : %llx\n",((cleanup_icache_req)?(( uint64_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((uint64_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache))));3042 PRINTF(" * <CLEANUP> address : %llx\n",((cleanup_icache_req)?((blob_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((blob_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache)))); 3111 3043 3112 3044 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION … … 3116 3048 << num_cache << " : " 3117 3049 << std::hex 3118 << " L " << std::setw(10) << ((cleanup_icache_req)?(( uint64_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((uint64_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache)))3050 << " L " << std::setw(10) << ((cleanup_icache_req)?((blob_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((blob_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache))) 3119 3051 // << " (" << std::setw(10) << addr << ")" 3120 3052 << std::dec … … 3248 3180 PRINTF(" * <CMD> dcache_miss_req (before) : %d\n",dcache_miss_req); 3249 3181 3250 // #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1) 3251 // // 1) two access authorized 3252 // dcache_miss_req = r_dcache_miss_req[cache_miss_num_cache]; 3253 // icache_miss_req = r_icache_miss_req[cache_miss_num_cache]; 3254 // #el 3255 #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2) 3256 // 2) one access with static priority (dcache prior) 3182 #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1) 3183 // 1) one access with static priority (dcache prior) 3257 3184 icache_miss_req &= not dcache_miss_req; 3185 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2) 3186 // 2) one access with static priority (icache prior) 3187 dcache_miss_req &= not icache_miss_req; 3258 3188 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==3) 3259 // 3) one access with static priority (icache prior) 3260 dcache_miss_req &= not icache_miss_req; 3261 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) 3262 // 4) one access with round robin priority 3189 // 3) one access with round robin priority 3263 3190 dcache_miss_req = ((dcache_miss_req and not icache_miss_req) or // only dcache 3264 3191 (dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior 3265 3192 icache_miss_req &= not dcache_miss_req; 3193 // #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) 3194 // // 4) two access authorized 3195 // dcache_miss_req = r_dcache_miss_req[cache_miss_num_cache]; 3196 // icache_miss_req = r_icache_miss_req[cache_miss_num_cache]; 3266 3197 #else 3267 3198 #error "Invalid value to CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY" … … 3278 3209 addr = (icache_miss_req)?r_icache_addr_save[icache_miss_num_cache].read():r_dcache_addr_save[dcache_miss_num_cache].read(); 3279 3210 3280 PRINTF(" * <CMD> addr : %llx\n",( uint64_t)addr);3211 PRINTF(" * <CMD> addr : %llx\n",(blob_t)addr); 3281 3212 3282 3213 if (icache_miss_req) … … 3291 3222 set_num_dcache(addr,dcache_miss_num_cache); 3292 3223 3293 PRINTF(" * <CMD> addr : %llx\n",( uint64_t)addr);3224 PRINTF(" * <CMD> addr : %llx\n",(blob_t)addr); 3294 3225 } 3295 3226 } … … 3335 3266 << "(" << dcache_miss_num_cache << ") " 3336 3267 << std::hex 3337 << " @ " << std::setw(10) << ( uint64_t)addr3338 << " (L " << std::setw(10) << (( uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")"3268 << " @ " << std::setw(10) << (blob_t)addr 3269 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" 3339 3270 << std::dec 3340 3271 << std::endl; … … 3362 3293 << "(" << dcache_unc_num_cache << ") " 3363 3294 << std::hex 3364 << " @ " << std::setw(10) << ( uint64_t)addr3365 << " (L " << std::setw(10) << (( uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")"3295 << " @ " << std::setw(10) << (blob_t)addr 3296 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" 3366 3297 << std::dec 3367 3298 << std::endl; … … 3386 3317 << "(" << icache_miss_num_cache << ") " 3387 3318 << std::hex 3388 << " @ " << std::setw(10) << ( uint64_t)addr3389 << " (L " << std::setw(10) << (( uint64_t)addr&(uint64_t)m_icache_yzmask) << ")"3319 << " @ " << std::setw(10) << (blob_t)addr 3320 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_icache_yzmask) << ")" 3390 3321 << std::dec 3391 3322 << std::endl; … … 3412 3343 << "(" << icache_unc_num_cache << ") " 3413 3344 << std::hex 3414 << " @ " << std::setw(10) << ( uint64_t)addr3415 << " (L " << std::setw(10) << (( uint64_t)addr&(uint64_t)m_icache_yzmask) << ")"3345 << " @ " << std::setw(10) << (blob_t)addr 3346 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_icache_yzmask) << ")" 3416 3347 << std::dec 3417 3348 << std::endl; … … 3440 3371 << "(" << dcache_write_num_cache << ") " 3441 3372 << std::hex 3442 << " @ " << std::setw(10) << ( uint64_t)addr3443 << " (L " << std::setw(10) << (( uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")"3373 << " @ " << std::setw(10) << (blob_t)addr 3374 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" 3444 3375 << " [" << wbuf_min << ":" << wbuf_max << "]" 3445 3376 << " {" << wbuf_index << "}" … … 3469 3400 << "(" << dcache_sc_num_cache << ") " 3470 3401 << std::hex 3471 << " @ " << std::setw(10) << ( uint64_t)addr3472 << " (L " << std::setw(10) << (( uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")"3402 << " @ " << std::setw(10) << (blob_t)addr 3403 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" 3473 3404 << std::dec 3474 3405 << std::endl; … … 3737 3668 "A VCI response packet must contain one flit for a write transaction"); 3738 3669 r_vci_rsp_fsm = RSP_IDLE; 3739 bool cached = r_wbuf[r_vci_rsp_num_cache]->completed(p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1))); 3670 uint32_t wbuf_index = p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1)); 3671 bool cached = r_wbuf[r_vci_rsp_num_cache]->completed(wbuf_index); 3740 3672 3741 3673 PRINTF(" * <RSP> cached : %d\n",cached); … … 3744 3676 r_dcache_previous_unc[r_vci_rsp_num_cache] = false; 3745 3677 3746 // FIXME : r_vci_rsp_num_cache != num_cpu ! -> pktid3747 if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) m_iss[r_vci_rsp_num_cache]->setWriteBerr();3678 if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) 3679 m_iss[r_wbuf[r_vci_rsp_num_cache]->getCpuId(wbuf_index)]->setWriteBerr(); 3748 3680 } 3749 3681 break; … … 3821 3753 set_num_icache(addr,r_cleanup_num_cache); 3822 3754 3823 PRINTF(" * <CLEANUP> icache : %llx\n",( uint64_t)addr);3755 PRINTF(" * <CLEANUP> icache : %llx\n",(blob_t)addr); 3824 3756 } 3825 3757 else … … 3828 3760 set_num_dcache(addr,r_cleanup_num_cache); 3829 3761 3830 PRINTF(" * <CLEANUP> dcache : %llx\n",( uint64_t)addr);3762 PRINTF(" * <CLEANUP> dcache : %llx\n",(blob_t)addr); 3831 3763 } 3832 3764 … … 3920 3852 set_num_dcache(addr,r_vci_cmd_num_cache); 3921 3853 3922 PRINTF(" * <CMD> DATA_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,( uint64_t)(addr));3854 PRINTF(" * <CMD> DATA_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); 3923 3855 3924 3856 p_vci_ini_rw.address = addr; … … 3957 3889 set_num_dcache(addr,r_vci_cmd_num_cache); 3958 3890 3959 PRINTF(" * <CMD> DATA_SC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,( uint64_t)(addr));3891 PRINTF(" * <CMD> DATA_SC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); 3960 3892 3961 3893 p_vci_ini_rw.address = addr; … … 3993 3925 addr_40 addr = (addr_40) r_wbuf[r_vci_cmd_num_cache]->getAddress(r_vci_cmd_cpt)&~0x3; 3994 3926 3995 PRINTF(" * <CMD> DATA_WRITE : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,( uint64_t)(addr));3927 PRINTF(" * <CMD> DATA_WRITE : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); 3996 3928 3997 3929 p_vci_ini_rw.address = addr; … … 4019 3951 set_num_dcache(addr,r_vci_cmd_num_cache); 4020 3952 4021 PRINTF(" * <CMD> DATA_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,( uint64_t)(addr));3953 PRINTF(" * <CMD> DATA_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); 4022 3954 4023 3955 p_vci_ini_rw.address = addr; … … 4044 3976 set_num_icache(addr,r_vci_cmd_num_cache); 4045 3977 4046 PRINTF(" * <CMD> INS_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,( uint64_t)(addr));3978 PRINTF(" * <CMD> INS_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); 4047 3979 4048 3980 p_vci_ini_rw.address = addr; … … 4069 4001 set_num_icache(addr,r_vci_cmd_num_cache); 4070 4002 4071 PRINTF(" * <CMD> INS_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,( uint64_t)(addr));4003 PRINTF(" * <CMD> INS_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); 4072 4004 4073 4005 p_vci_ini_rw.address = addr; … … 4250 4182 4251 4183 ////////////////////////////////////////////////////////////////////////////////// 4252 // fixme: mettre le type addr_404184 // FIXME : mettre le type addr_40 4253 4185 tmpl(sc_dt::sc_uint<40>)::set_num_cache_only(addr_40 addr, uint32_t num_cache) 4254 4186 ////////////////////////////////////////////////////////////////////////////////// -
trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h
r142 r143 7 7 #include "arithmetics.h" 8 8 9 #define L1_MULTI_CACHE 9 #define L1_MULTI_CACHE 1 10 10 //#define RANDOM_EVICTION 11 11 -
trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r141 r143 29 29 #include "../include/vci_mem_cache_v4.h" 30 30 31 // #define TDEBUG // Transaction tab debug32 // #define IDEBUG // Update tab debug33 // #define DDEBUG // Directory debug34 // #define LOCK_DEBUG // Lock debug35 36 31 #define DEBUG_VCI_MEM_CACHE 0 37 #define DEBUG_START_CYCLE 94990032 #define DEBUG_START_CYCLE 1500 38 33 #define RANDOMIZE_SC 39 34 40 35 #define ASSERT_VERBOSE 41 36 #define ASSERT_NCYCLES m_cpt_cycles 37 38 #if DEBUG_VCI_MEM_CACHE 39 #define TDEBUG // Transaction tab debug 40 #define IDEBUG // Update tab debug 41 #define DDEBUG // Directory debug 42 #define LOCK_DEBUG // Lock debug 43 #endif 44 42 45 43 46 #include "debug.h" … … 2660 2663 bool match_heap = match_heap_srcid and match_heap_cache_id and match_heap_inst; 2661 2664 2665 PRINTF(" * <MEM_CACHE.CLEANUP> %s - srcid %d\n",name().c_str(),r_cleanup_srcid.read()); 2666 2662 2667 #if L1_MULTI_CACHE 2663 2668 PRINTF(" * <MEM_CACHE.CLEANUP> match_dir %d (match_dir_srcid %d, match_dir_cache_id %d, match_dir_inst %d)\n", … … 2683 2688 if(match_dir){ 2684 2689 DirectoryEntry dir_entry; 2685 dir_entry.valid = true;2690 dir_entry.valid = true; 2686 2691 dir_entry.is_cnt = r_cleanup_is_cnt.read(); 2687 dir_entry.dirty = r_cleanup_dirty.read();2692 dir_entry.dirty = r_cleanup_dirty.read(); 2688 2693 dir_entry.tag = r_cleanup_tag.read(); 2689 dir_entry.lock = r_cleanup_lock.read();2694 dir_entry.lock = r_cleanup_lock.read(); 2690 2695 dir_entry.ptr = heap_entry.next; 2691 2696 dir_entry.count = r_cleanup_count.read()-1;
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