Changeset 144 for trunk/modules
- Timestamp:
- Mar 30, 2011, 6:30:22 PM (14 years ago)
- Location:
- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_xcache_wrapper_v4.h (modified) (6 diffs)
-
src/vci_cc_xcache_wrapper_v4.cpp (modified) (17 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r143 r144 74 74 * 2 - icache dedicated 75 75 * 76 * CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 77 * (In multi-cache) 78 * A dcache used by a cpu and in miss_wait state can be use by 79 * an another cpu to make a load cached access. 80 * 81 * CC_XCACHE_WRAPPER_STORE_AFTER_STORE 82 * Store access in dcache (and hit) is make in two cycle : 83 * - first read directory and read data 84 * - second make a mask with old data and write new data. 85 * If data part has a write enable per byte, read data access can be suppress 86 * and we can pipeline consecutive store access. 87 * 76 88 * CC_XCACHE_WRAPPER_STOP_SIMULATION : 77 89 * stop simulation if processor is stall after a long time … … 94 106 // implementation 95 107 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP 96 #define CC_XCACHE_WRAPPER_FIFO_RSP 1108 #define CC_XCACHE_WRAPPER_FIFO_RSP 2 97 109 #endif 98 110 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 107 119 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 108 120 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3 109 #endif 121 #endif 110 122 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE 111 123 #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 … … 113 125 // <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 114 126 // <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1 127 #endif 128 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 129 #define CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 1 130 #endif 131 #ifndef CC_XCACHE_WRAPPER_STORE_AFTER_STORE 132 #define CC_XCACHE_WRAPPER_STORE_AFTER_STORE 1 115 133 #endif 116 134 … … 444 462 uint32_t * m_cpt_icache_access; //[m_nb_icache] 445 463 uint32_t * m_cpt_dcache_access; //[m_nb_dcache] 464 uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache] 465 uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache] 466 uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache] 467 uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache] 468 uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache] 446 469 447 470 uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] … … 495 518 ~VciCcXCacheWrapperV4(); 496 519 497 498 499 void print_stats();520 void print_trace(size_t mode = 0); 521 void print_cpi(); 522 void print_stats(bool print_wbuf=true, bool print_fsm=true); 500 523 501 524 // #if CC_XCACHE_WRAPPER_STOP_SIMULATION -
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
r143 r144 490 490 dreq_num_cpu = new uint32_t [m_nb_dcache]; 491 491 492 m_cpt_icache_access = new uint32_t [m_nb_icache]; 493 m_cpt_dcache_access = new uint32_t [m_nb_dcache]; 494 492 m_cpt_icache_access = new uint32_t [m_nb_icache]; 493 m_cpt_dcache_access = new uint32_t [m_nb_dcache]; 494 m_cpt_icache_miss_victim_wait = new uint32_t [m_nb_icache]; 495 m_cpt_dcache_miss_victim_wait = new uint32_t [m_nb_dcache]; 496 497 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE 498 m_cpt_dcache_store_after_store = new uint32_t [m_nb_dcache]; 499 #endif 500 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 501 m_cpt_dcache_hit_after_miss_read = new uint32_t [m_nb_dcache]; 502 m_cpt_dcache_hit_after_miss_write = new uint32_t [m_nb_dcache]; 503 #endif 495 504 496 505 m_cpt_fsm_dcache = new uint32_t * [m_nb_dcache]; … … 754 763 delete [] m_cpt_icache_access ; 755 764 delete [] m_cpt_dcache_access ; 756 765 delete [] m_cpt_icache_miss_victim_wait; 766 delete [] m_cpt_dcache_miss_victim_wait; 767 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE 768 delete [] m_cpt_dcache_store_after_store; 769 #endif 770 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 771 delete [] m_cpt_dcache_hit_after_miss_read; 772 delete [] m_cpt_dcache_hit_after_miss_write; 773 #endif 757 774 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 758 775 delete [] m_cpt_fsm_dcache [num_cache]; … … 801 818 } 802 819 //////////////////////// 803 tmpl(void)::print_stats()820 tmpl(void)::print_stats(bool print_wbuf, bool print_fsm) 804 821 //////////////////////// 805 822 { … … 860 877 std::cout << "- DCACHE ACCESS : " << m_cpt_dcache_access_all << std::endl; 861 878 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 862 std::cout << " + [" << num_cache << "] : " << m_cpt_dcache_access [num_cache] << " (" << (float)m_cpt_dcache_access [num_cache]*100.0/(float)m_cpt_dcache_access_all << "%)" << std::endl; 863 864 std::cout << "- DCACHE FSM" << std::endl; 865 for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i) 866 { 867 std::cout << " + " << dcache_fsm_state_str[i] << " :\t "; 868 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 869 std::cout << m_cpt_fsm_dcache [num_cache][i] << ", "; 870 std::cout << std::endl; 871 } 872 std::cout << "- ICACHE FSM" << std::endl; 873 for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i) 874 { 875 std::cout << " + " << icache_fsm_state_str[i] << " :\t "; 876 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 877 std::cout << m_cpt_fsm_icache [num_cache][i] << ", "; 878 std::cout << std::endl; 879 } 880 std::cout << "- CMD FSM" << std::endl; 881 for (uint32_t i=0; i<soclib::common::size(cmd_fsm_state_str ); ++i) 882 std::cout << " + " << cmd_fsm_state_str[i] << " :\t " << m_cpt_fsm_cmd [i] << std::endl; 883 std::cout << "- RSP FSM" << std::endl; 884 for (uint32_t i=0; i<soclib::common::size(rsp_fsm_state_str ); ++i) 885 std::cout << " + " << rsp_fsm_state_str[i] << " :\t " << m_cpt_fsm_rsp [i] << std::endl; 886 std::cout << "- TGT FSM" << std::endl; 887 for (uint32_t i=0; i<soclib::common::size(tgt_fsm_state_str ); ++i) 888 std::cout << " + " << tgt_fsm_state_str[i] << " :\t " << m_cpt_fsm_tgt [i] << std::endl; 889 std::cout << "- CLEANUP FSM" << std::endl; 890 for (uint32_t i=0; i<soclib::common::size(cleanup_fsm_state_str ); ++i) 891 std::cout << " + " << cleanup_fsm_state_str[i] << " :\t " << m_cpt_fsm_cleanup [i] << std::endl; 879 { 880 std::cout << " + [" << num_cache << "] : " << m_cpt_dcache_access [num_cache] << " (" << (float)m_cpt_dcache_access [num_cache]*100.0/(float)m_cpt_dcache_access_all << "%)"; 881 882 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE 883 std::cout << " - store after store : " << m_cpt_dcache_store_after_store [num_cache]; 884 #endif 885 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 886 std::cout << " - Hit after Miss : Read " << m_cpt_dcache_hit_after_miss_read [num_cache] << ", Write " << m_cpt_dcache_hit_after_miss_write [num_cache]; 887 #endif 888 std::cout << std::endl; 889 } 890 891 uint32_t m_cpt_icache_miss_victim_wait_all = 0; 892 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 893 m_cpt_icache_miss_victim_wait_all += m_cpt_icache_miss_victim_wait [num_cache]; 894 std::cout << "- ICACHE MISS VICTIM WAIT : " << m_cpt_icache_miss_victim_wait_all << std::endl; 895 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 896 std::cout << " + [" << num_cache << "] : " << m_cpt_icache_miss_victim_wait [num_cache] << std::endl; 897 898 uint32_t m_cpt_dcache_miss_victim_wait_all = 0; 899 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 900 m_cpt_dcache_miss_victim_wait_all += m_cpt_dcache_miss_victim_wait [num_cache]; 901 std::cout << "- DCACHE MISS VICTIM WAIT : " << m_cpt_dcache_miss_victim_wait_all << std::endl; 902 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 903 std::cout << " + [" << num_cache << "] : " << m_cpt_dcache_miss_victim_wait [num_cache] << std::endl; 904 905 if (print_fsm) 906 { 907 std::cout << "- DCACHE FSM" << std::endl; 908 for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i) 909 { 910 std::cout << " + " << dcache_fsm_state_str[i] << " :\t "; 911 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 912 std::cout << m_cpt_fsm_dcache [num_cache][i] << ", "; 913 std::cout << std::endl; 914 } 915 std::cout << "- ICACHE FSM" << std::endl; 916 for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i) 917 { 918 std::cout << " + " << icache_fsm_state_str[i] << " :\t "; 919 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 920 std::cout << m_cpt_fsm_icache [num_cache][i] << ", "; 921 std::cout << std::endl; 922 } 923 std::cout << "- CMD FSM" << std::endl; 924 for (uint32_t i=0; i<soclib::common::size(cmd_fsm_state_str ); ++i) 925 std::cout << " + " << cmd_fsm_state_str[i] << " :\t " << m_cpt_fsm_cmd [i] << std::endl; 926 std::cout << "- RSP FSM" << std::endl; 927 for (uint32_t i=0; i<soclib::common::size(rsp_fsm_state_str ); ++i) 928 std::cout << " + " << rsp_fsm_state_str[i] << " :\t " << m_cpt_fsm_rsp [i] << std::endl; 929 std::cout << "- TGT FSM" << std::endl; 930 for (uint32_t i=0; i<soclib::common::size(tgt_fsm_state_str ); ++i) 931 std::cout << " + " << tgt_fsm_state_str[i] << " :\t " << m_cpt_fsm_tgt [i] << std::endl; 932 std::cout << "- CLEANUP FSM" << std::endl; 933 for (uint32_t i=0; i<soclib::common::size(cleanup_fsm_state_str ); ++i) 934 std::cout << " + " << cleanup_fsm_state_str[i] << " :\t " << m_cpt_fsm_cleanup [i] << std::endl; 935 } 892 936 893 937 std::cout << "* : accepted or not by the cache" << std::endl ; 894 938 939 if (print_wbuf) 895 940 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 896 941 r_wbuf[num_cache]->printStatistics(); … … 1085 1130 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1086 1131 { 1087 m_cpt_icache_access [num_cache] = 0; 1132 m_cpt_icache_access [num_cache] = 0; 1133 m_cpt_icache_miss_victim_wait [num_cache] = 0; 1088 1134 1089 1135 for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i) … … 1092 1138 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1093 1139 { 1094 m_cpt_dcache_access [num_cache] = 0; 1095 1140 m_cpt_dcache_access [num_cache] = 0; 1141 m_cpt_dcache_miss_victim_wait [num_cache] = 0; 1142 1143 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE 1144 m_cpt_dcache_store_after_store [num_cache] = 0; 1145 #endif 1146 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 1147 m_cpt_dcache_hit_after_miss_read [num_cache] = 0; 1148 m_cpt_dcache_hit_after_miss_write [num_cache] = 0; 1149 #endif 1096 1150 for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i) 1097 1151 m_cpt_fsm_dcache [num_cache][i] = 0; … … 1676 1730 num_cache = get_num_icache(addr,num_cpu); 1677 1731 1678 // test if already used 1679 if (not ireq[num_cache].valid and 1680 (r_icache_lock [num_cache] == m_nb_cpu) or 1681 (r_icache_lock [num_cache] == num_cpu)) 1732 bool icache_req_valid = ((not ireq[num_cache].valid and // no previous request in this cycle 1733 (r_icache_lock [num_cache] == m_nb_cpu)) or // no previous request in previous cycle 1734 (r_icache_lock [num_cache] == num_cpu)); // previous request in previous cycle by this cpu 1735 1736 if (icache_req_valid) 1682 1737 { 1683 1738 bool valid = _ireq.valid; … … 1709 1764 addr = (addr_40)_dreq.addr; 1710 1765 num_cache = get_num_dcache(addr); 1766 1767 1768 bool dcache_no_lock = (r_dcache_lock [num_cache] == m_nb_cpu); 1769 bool dcache_lock_owner = (r_dcache_lock [num_cache] == num_cpu); 1770 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 1771 bool dcache_lock_no_owner= not dcache_no_lock and not dcache_lock_owner; 1772 bool dcache_wait = ((r_dcache_fsm[num_cache] == DCACHE_MISS_WAIT)// or 1773 // (r_dcache_fsm[num_cache] == DCACHE_UNC_WAIT) or 1774 // (r_dcache_fsm[num_cache] == DCACHE_SC_WAIT) 1775 ); 1776 1777 bool dcache_req_valid = ((not dreq[num_cache].valid and // no previous request in this cycle 1778 not have_sync and // no sync instruction 1779 (dcache_no_lock or 1780 (dcache_lock_no_owner and dcache_wait))) or // no previous request in previous cycle 1781 (dcache_lock_owner and not dcache_wait)); // previous request in previous cycle by this cpu 1782 #else 1783 bool dcache_req_valid = ((not dreq[num_cache].valid and // no previous request in this cycle 1784 not have_sync and // no sync instruction 1785 dcache_no_lock) or // no previous request in previous cycle 1786 dcache_lock_owner); // previous request in previous cycle by this cpu 1787 #endif 1788 // @@@@ 1789 1711 1790 1712 1791 // test if already used 1713 if (not dreq[num_cache].valid and 1714 not have_sync and 1715 (r_dcache_lock [num_cache] == m_nb_cpu) or 1716 (r_dcache_lock [num_cache] == num_cpu)) 1792 if (dcache_req_valid) 1717 1793 { 1718 1794 bool valid = _dreq.valid; … … 1722 1798 PRINTF(" * <CPU2CACHE> DCACHE : Transaction between cpu %d and cache %d (lock)\n",num_cpu,num_cache); 1723 1799 dreq_num_cache [num_cpu ] = num_cache; 1800 1801 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 1802 if (not dcache_lock_no_owner) 1803 #endif 1724 1804 r_dcache_lock [num_cache] = num_cpu; 1725 1805 } … … 1823 1903 PRINTF(" * <ICACHE [%d]> hit %d - cached %d - cleanup_hit %d\n",num_cache, icache_hit, icache_cached, icache_cleanup_hit); 1824 1904 1825 // ASSERT( not (icache_hit and icache_cleanup_hit),1826 // "Icache hit and icache_cleanup_hit");1827 1828 1905 if (icache_hit and icache_cleanup_hit) 1829 1906 { … … 1837 1914 m_cpt_ins_miss++; 1838 1915 m_cost_ins_miss_frz++; 1916 1839 1917 r_icache_addr_save[num_cache] = (addr_40) _ireq.addr; 1840 1841 CACHE_MISS_BUF_REQ_INIT(i,num_cache); 1842 1918 1843 1919 if ( icache_cached ) 1844 1920 { 1845 r_icache_fsm [num_cache] = ICACHE_MISS_VICTIM; 1846 r_icache_miss_req[num_cache] = true; 1847 1921 // to prevent deadlock, miss victim don't be block 1922 if (not r_icache_cleanup_req[num_cache]) 1923 { 1924 CACHE_MISS_BUF_REQ_INIT(i,num_cache); 1925 r_icache_fsm [num_cache] = ICACHE_MISS_VICTIM; 1926 r_icache_miss_req[num_cache] = true; 1927 } 1928 else 1929 m_cpt_icache_miss_victim_wait [num_cache] ++; 1848 1930 } 1849 1931 else 1850 1932 { 1933 CACHE_MISS_BUF_REQ_INIT(i,num_cache); 1934 r_icache_addr_save[num_cache] = (addr_40) _ireq.addr; 1935 1851 1936 r_icache_fsm [num_cache] = ICACHE_UNC_WAIT; 1852 1937 r_icache_unc_req[num_cache] = true; … … 1863 1948 _irsp.valid = icache_hit; 1864 1949 _irsp.instruction = icache_ins; 1865 }1950 } 1866 1951 break; 1867 1952 } … … 1869 1954 case ICACHE_MISS_VICTIM: 1870 1955 { 1871 if (not r_icache_cleanup_req[num_cache])1956 // if (not r_icache_cleanup_req[num_cache]) 1872 1957 { 1873 1958 size_t way; … … 2285 2370 if (not dcache_cleanup_hit) 2286 2371 { 2287 CACHE_MISS_BUF_REQ_INIT(d,num_cache);2288 2372 2289 2373 // Miss : send signal at the CMD_FSM (via r_dcache_miss_req or r_dcache_unc_req) 2290 2374 if ( dcache_cached ) { 2291 m_cpt_data_read_miss++; 2292 m_cost_data_miss_frz++; 2293 r_dcache_miss_req [num_cache] = true; 2294 r_dcache_fsm [num_cache] = DCACHE_MISS_VICTIM; 2295 2375 // to prevent deadlock, miss victim don't be block 2376 if (not r_dcache_cleanup_req[num_cache].read()) 2377 { 2378 CACHE_MISS_BUF_REQ_INIT(d,num_cache); 2379 2380 m_cpt_data_read_miss++; 2381 m_cost_data_miss_frz++; 2382 r_dcache_miss_req [num_cache] = true; 2383 r_dcache_fsm [num_cache] = DCACHE_MISS_VICTIM; 2384 } 2385 else 2386 m_cpt_icache_miss_victim_wait [num_cache] ++; 2296 2387 } else { 2297 2388 if (not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access 2298 2389 { 2390 CACHE_MISS_BUF_REQ_INIT(d,num_cache); 2391 2299 2392 r_dcache_previous_unc[num_cache] = true; 2300 2393 … … 2451 2544 { 2452 2545 m_cpt_dcache_data_write++; 2453 data_t mask= vci_param::be2mask(r_dcache_be_save[num_cache]);2454 data_t wdata = (mask & r_dcache_wdata_save[num_cache]) | (~mask & r_dcache_rdata_save[num_cache]);2455 vci_addr_t ad = r_dcache_addr_save[num_cache].read();2546 data_t mask = vci_param::be2mask(r_dcache_be_save[num_cache]); 2547 data_t wdata = (mask & r_dcache_wdata_save[num_cache]) | (~mask & r_dcache_rdata_save[num_cache]); 2548 vci_addr_t ad = r_dcache_addr_save[num_cache].read(); 2456 2549 r_dcache[num_cache]->write(ad, wdata); 2457 2550 2458 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2551 int dcache_fsm_next = DCACHE_IDLE; // default 2552 2553 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE 2554 // Test if write after write 2555 2556 if (_dreq.valid and (_dreq.type == iss_t::DATA_WRITE)) 2557 { 2558 PRINTF(" * <DCACHE [%d]> Have dreq (Write after Write)\n",num_cache); 2559 2560 data_t dcache_rdata = 0; 2561 // dcache_cached and dcache_hit don't used with _dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} 2562 bool dcache_cached = dreq_cached [num_cache]; 2563 uint32_t dcache_num_cpu = dreq_num_cpu [num_cache]; 2564 bool dcache_hit = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); 2565 2566 m_cpt_dcache_data_read += m_dcache_ways; 2567 m_cpt_dcache_dir_read += m_dcache_ways; 2568 2569 PRINTF(" * <DCACHE [%d]> r_dcache_previous_unc : %d\n",num_cache,r_dcache_previous_unc[num_cache].read()); 2570 2571 if (dcache_cached or not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access 2572 { 2573 bool valid; 2574 addr_40 addr = _dreq.addr; 2575 set_num_dcache(addr,num_cache); 2576 2577 // FIXME : 2578 // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) 2579 // * pour cela, virer le set_num_dcache ! 2580 valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); 2581 PRINTF(" * <DCACHE [%d]> r_wbuf valid : %d\n",num_cache,valid); 2582 2583 if (valid) 2584 { 2585 m_cpt_dcache_store_after_store [num_cache] ++; 2586 2587 m_cpt_data_write++; 2588 2589 if (not dcache_cached) 2590 { 2591 r_dcache_previous_unc[num_cache] = true; 2592 m_cpt_data_write_uncached++; 2593 } 2594 else if (not dcache_hit) 2595 m_cpt_data_write_miss++; 2596 2597 if (dcache_hit) { 2598 // update data cache 2599 dcache_fsm_next = DCACHE_WRITE_UPDT; 2600 } else { 2601 // write accepted 2602 dcache_fsm_next = DCACHE_IDLE; 2603 } 2604 } 2605 2606 _drsp.valid = valid; 2607 _drsp.rdata = 0; 2608 } 2609 2610 r_dcache_addr_save [num_cache] = (addr_40) _dreq.addr; 2611 // r_dcache_type_save [num_cache] = _dreq.type; 2612 r_dcache_wdata_save [num_cache] = _dreq.wdata; 2613 r_dcache_be_save [num_cache] = _dreq.be; 2614 r_dcache_rdata_save [num_cache] = dcache_rdata; 2615 // r_dcache_cached_save [num_cache] = dcache_cached; 2616 // r_dcache_num_cpu_save[num_cache] = dcache_num_cpu; 2617 } 2618 #endif 2619 2620 r_dcache_fsm [num_cache] = dcache_fsm_next; // default 2459 2621 2460 2622 break; … … 2463 2625 case DCACHE_MISS_VICTIM: 2464 2626 { 2465 if (not r_dcache_cleanup_req[num_cache].read())2627 // if (not r_dcache_cleanup_req[num_cache].read()) 2466 2628 { 2467 2629 size_t way; … … 2486 2648 case DCACHE_MISS_WAIT: 2487 2649 { 2650 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 2651 data_t dcache_rdata = 0; 2652 bool dcache_hit = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); 2653 // bool dcache_cached = dreq_cached [num_cache]; 2654 // uint32_t dcache_num_cpu = dreq_num_cpu [num_cache]; 2655 2656 m_cpt_dcache_data_read += m_dcache_ways; 2657 m_cpt_dcache_dir_read += m_dcache_ways; 2658 2659 if (_dreq.valid) 2660 switch (_dreq.type) 2661 { 2662 case iss_t::DATA_READ : // accept only hit dcache load 2663 { 2664 m_cpt_data_read++; // new dcache read 2665 2666 if (dcache_hit) // no special test for uncached read, because it's always miss 2667 { 2668 m_cpt_dcache_hit_after_miss_read [num_cache] ++; 2669 2670 // address is in the cache : return the word 2671 _drsp.valid = true; 2672 _drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) 2673 } 2674 break; 2675 } 2676 // case iss_t::DATA_WRITE : // accept only cached write and miss in dcache (else need update dcache) 2677 // { 2678 // if (dcache_cached and not dcache_hit) 2679 // { 2680 // bool valid; 2681 // addr_40 addr = _dreq.addr; 2682 // set_num_dcache(addr,num_cache); 2683 2684 // // FIXME : 2685 // // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) 2686 // // * pour cela, virer le set_num_dcache ! 2687 // valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); 2688 // PRINTF(" * <DCACHE [%d]> r_wbuf valid : %d\n",num_cache,valid); 2689 2690 // if (valid) 2691 // { 2692 // m_cpt_dcache_hit_after_miss_write [num_cache] ++; 2693 2694 // m_cpt_data_write++; 2695 // m_cpt_data_write_miss++; 2696 // } 2697 2698 // _drsp.valid = valid; 2699 // _drsp.rdata = 0; 2700 // } 2701 // break; 2702 // } 2703 default : 2704 { 2705 break; 2706 } 2707 } 2708 #endif 2488 2709 2489 2710 // if ( _dreq.valid ) m_cost_data_miss_frz++;
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