- Timestamp:
- Apr 20, 2011, 1:19:10 PM (13 years ago)
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trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r144 r147 31 31 32 32 #include <inttypes.h> 33 #include <fstream>34 33 #include <systemc> 35 34 #include <queue> … … 43 42 44 43 /* 44 * CC_XCACHE_WRAPPER_SELECT_VICTIM : 45 * The selection and the update of cache (after a read miss) 46 * are separated in two step 47 * Also, the cleanup can be send in parallel at the read miss. 48 * 45 49 * CC_XCACHE_WRAPPER_FIFO_RSP 46 50 * Two simple fifo (each 2x32 depth) receive the cache line from 47 51 * RAM. Instead of two buffers (m_icache_words and m_dcache_words) 48 * 1 - nb_icache+nb_dcache simple fifo49 * 2 - 2 simple fifo50 * else - two buffers (m_icache_words and m_dcache_words)51 52 * 52 53 * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 65 66 * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 66 67 * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req 67 * 1 - one access with static priority (dcache prior) 68 * 2 - one access with static priority (icache prior) 69 * 3 - one access with round robin priority 70 * 4 - two access authorized 71 * 72 * CC_XCACHE_WRAPPER_MULTI_CACHE : 73 * 1 - icache static partitionnement 74 * 2 - icache dedicated 75 * 76 * CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 77 * (In multi-cache) 78 * A dcache used by a cpu and in miss_wait state can be use by 79 * an another cpu to make a load cached access. 80 * 81 * CC_XCACHE_WRAPPER_STORE_AFTER_STORE 82 * Store access in dcache (and hit) is make in two cycle : 83 * - first read directory and read data 84 * - second make a mask with old data and write new data. 85 * If data part has a write enable per byte, read data access can be suppress 86 * and we can pipeline consecutive store access. 87 * 68 * 1 - two access authorized 69 * 2 - one access with static priority (dcache prior) 70 * 3 - one access with static priority (icache prior) 71 * 4 - one access with round robin priority 72 * 88 73 * CC_XCACHE_WRAPPER_STOP_SIMULATION : 89 74 * stop simulation if processor is stall after a long time … … 96 81 * Number of cycle before to prinf debug message 97 82 * 98 * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 99 * Print transaction between : 100 * - the cpu and the cache (icache and dcache) 101 * - vci 102 * - cleanup 103 * - coherency 83 * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 84 * Print transaction between the cpu and the cache 104 85 */ 105 86 106 87 // implementation 88 #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM 89 #define CC_XCACHE_WRAPPER_SELECT_VICTIM 0 90 #endif 107 91 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP 108 #define CC_XCACHE_WRAPPER_FIFO_RSP 292 #define CC_XCACHE_WRAPPER_FIFO_RSP 0 109 93 #endif 110 94 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 111 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 95 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 112 96 #endif 113 97 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 114 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 98 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 115 99 #endif 116 100 #ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 117 #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 2101 #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 0 118 102 #endif 119 103 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 120 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3 121 #endif 122 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE 123 #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 124 // if multi_cache : 125 // <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 126 // <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1 127 #endif 128 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 129 #define CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 1 130 #endif 131 #ifndef CC_XCACHE_WRAPPER_STORE_AFTER_STORE 132 #define CC_XCACHE_WRAPPER_STORE_AFTER_STORE 1 133 #endif 134 104 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 2 105 #endif 135 106 // debugging 136 #ifndef CC_XCACHE_WRAPPER_VERBOSE137 #define CC_XCACHE_WRAPPER_VERBOSE 1138 #endif139 107 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION 140 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 108 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 141 109 #endif 142 110 #ifndef CC_XCACHE_WRAPPER_DEBUG 143 #define CC_XCACHE_WRAPPER_DEBUG 111 #define CC_XCACHE_WRAPPER_DEBUG 0 144 112 #endif 145 113 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 146 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1500 147 #endif 148 #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 149 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0 150 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log" 151 #endif 152 153 // don't change 154 #if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 155 #undef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 156 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 0 114 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 200000 115 #endif 116 #ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 117 #define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 0 157 118 #endif 158 119 … … 178 139 DCACHE_IDLE, 179 140 DCACHE_WRITE_UPDT, 141 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 180 142 DCACHE_MISS_VICTIM, 143 #endif 181 144 DCACHE_MISS_WAIT, 182 145 DCACHE_MISS_UPDT, … … 194 157 enum icache_fsm_state_e { 195 158 ICACHE_IDLE, 159 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 196 160 ICACHE_MISS_VICTIM, 161 #endif 197 162 ICACHE_MISS_WAIT, 198 163 ICACHE_MISS_UPDT, … … 239 204 enum cleanup_fsm_state_e { 240 205 CLEANUP_IDLE, 241 CLEANUP_REQ, 242 CLEANUP_RSP_DCACHE, 243 CLEANUP_RSP_ICACHE, 206 CLEANUP_DCACHE, 207 CLEANUP_ICACHE, 244 208 }; 245 209 … … 267 231 sc_in<bool> p_clk; 268 232 sc_in<bool> p_resetn; 269 sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq];233 sc_in<bool> p_irq[iss_t::n_irq]; 270 234 soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; 271 235 soclib::caba::VciInitiator<vci_param> p_vci_ini_c; … … 277 241 const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; 278 242 const soclib::common::Segment m_segment; 279 iss_t ** m_iss; //[m_nb_cpu]243 iss_t m_iss; 280 244 const uint32_t m_srcid_rw; 281 245 const uint32_t m_srcid_c; 282 246 283 const size_t m_nb_cpu;284 const size_t m_nb_icache;285 const size_t m_nb_dcache;286 const size_t m_nb_cache;287 247 const size_t m_dcache_ways; 288 248 const size_t m_dcache_words; … … 298 258 bool m_stop_simulation; 299 259 uint32_t m_stop_simulation_nb_frz_cycles_max; 300 uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu]260 uint32_t m_stop_simulation_nb_frz_cycles; 301 261 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 302 262 303 263 // REGISTERS 304 sc_signal<uint32_t> r_cpu_prior; 305 sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache] 306 sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache] 307 sc_signal<bool> * r_dcache_sync;//[m_nb_dcache] 308 309 sc_signal<int> * r_dcache_fsm; //[m_nb_dcache] 310 sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache] 311 sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache] 312 sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache] 313 sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache] 314 sc_signal<int> * r_dcache_type_save; //[m_nb_dcache] 315 sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache] 316 sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache] 317 sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache] 318 sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache] 319 sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache] 320 sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache] 321 sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache] 322 sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache] 323 sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache] 324 sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache] 325 sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache] 326 sc_signal<data_64> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu] 327 sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu] 328 sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu] 329 sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache] 330 sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache] 331 332 sc_signal<int> * r_icache_fsm; //[m_nb_icache] 333 sc_signal<int> * r_icache_fsm_save; //[m_nb_icache] 334 sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache] 335 sc_signal<bool> * r_icache_miss_req; //[m_nb_icache] 336 sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache] 337 sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache] 338 sc_signal<bool> * r_icache_unc_req; //[m_nb_icache] 339 sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache] 340 sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache] 341 sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache] 342 sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache] 343 sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache] 264 sc_signal<int> r_dcache_fsm; 265 sc_signal<int> r_dcache_fsm_save; 266 sc_signal<addr_40> r_dcache_addr_save; 267 sc_signal<data_t> r_dcache_wdata_save; 268 sc_signal<data_t> r_dcache_rdata_save; 269 sc_signal<int> r_dcache_type_save; 270 sc_signal<be_t> r_dcache_be_save; 271 sc_signal<bool> r_dcache_cached_save; 272 sc_signal<bool> r_dcache_cleanup_req; 273 sc_signal<addr_40> r_dcache_cleanup_line; 274 sc_signal<bool> r_dcache_miss_req; 275 sc_signal<size_t> r_dcache_miss_way; 276 sc_signal<size_t> r_dcache_miss_set; 277 sc_signal<bool> r_dcache_unc_req; 278 sc_signal<bool> r_dcache_sc_req; 279 sc_signal<bool> r_dcache_inval_rsp; 280 sc_signal<size_t> r_dcache_update_addr; 281 sc_signal<data_64> r_dcache_ll_data; 282 sc_signal<addr_40> r_dcache_ll_addr; 283 sc_signal<bool> r_dcache_ll_valid; 284 sc_signal<bool> r_dcache_previous_unc; 285 286 sc_signal<int> r_icache_fsm; 287 sc_signal<int> r_icache_fsm_save; 288 sc_signal<addr_40> r_icache_addr_save; 289 sc_signal<bool> r_icache_miss_req; 290 sc_signal<size_t> r_icache_miss_way; 291 sc_signal<size_t> r_icache_miss_set; 292 sc_signal<bool> r_icache_unc_req; 293 sc_signal<bool> r_icache_cleanup_req; 294 sc_signal<addr_40> r_icache_cleanup_line; 295 sc_signal<bool> r_icache_inval_rsp; 296 sc_signal<size_t> r_icache_update_addr; 344 297 345 298 sc_signal<int> r_vci_cmd_fsm; … … 348 301 sc_signal<size_t> r_vci_cmd_cpt; 349 302 sc_signal<bool> r_vci_cmd_dcache_prior; 350 sc_signal<uint32_t> r_vci_cmd_num_cache; 351 303 352 304 sc_signal<int> r_vci_rsp_fsm; 305 sc_signal<bool> r_vci_rsp_ins_error; 306 sc_signal<bool> r_vci_rsp_data_error; 353 307 sc_signal<size_t> r_vci_rsp_cpt; 354 bool s_vci_rsp_ack; 355 sc_signal<uint32_t> r_vci_rsp_num_cache; 356 sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache] 357 sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] 358 359 #if (CC_XCACHE_WRAPPER_FIFO_RSP==1) 360 std::queue<data_t> * r_icache_miss_buf; //[m_nb_icache] 361 std::queue<data_t> * r_dcache_miss_buf; //[m_nb_dcache] 362 #elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) 363 typedef struct 364 { 365 data_t data; 366 uint32_t num_cache; 367 } miss_buf_t; 368 369 std::queue<miss_buf_t> r_icache_miss_buf; 370 std::queue<miss_buf_t> r_dcache_miss_buf; 308 sc_signal<bool> r_vci_rsp_ack; 309 310 #if CC_XCACHE_WRAPPER_FIFO_RSP 311 std::queue<data_t> r_icache_miss_buf; 312 std::queue<data_t> r_dcache_miss_buf; 371 313 #else 372 bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words] 373 data_t ** r_icache_miss_buf; //[m_nb_icache][m_icache_words] 374 bool ** r_dcache_miss_val; //[m_nb_dcache][m_dcache_words] 375 data_t ** r_dcache_miss_buf; //[m_nb_dcache][m_dcache_words] 376 #endif 377 data_t * r_tgt_buf; //[m_cache_words] 378 be_t * r_tgt_be; //[m_cache_words] 314 bool *r_icache_miss_val; //[m_icache_words] 315 data_t *r_icache_miss_buf; //[m_icache_words] 316 bool *r_dcache_miss_val; //[m_dcache_words] 317 data_t *r_dcache_miss_buf; //[m_dcache_words] 318 #endif 319 sc_signal<bool> r_icache_buf_unc_valid; 320 321 data_t *r_tgt_buf; //[m_cache_words] 322 be_t *r_tgt_be; //[m_cache_words] 379 323 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 380 324 sc_signal<uint32_t> r_cache_word; … … 382 326 383 327 sc_signal<int> r_vci_tgt_fsm; 384 sc_signal<addr_40> r_tgt_iaddr; 385 sc_signal<addr_40> r_tgt_daddr; 328 sc_signal<addr_40> r_tgt_addr; 386 329 sc_signal<size_t> r_tgt_word; 387 330 sc_signal<bool> r_tgt_update; … … 392 335 sc_signal<size_t> r_tgt_trdid; 393 336 //sc_signal<size_t> r_tgt_plen; 394 sc_signal<uint32_t> r_tgt_num_cache; 395 sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache] 396 sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache] 397 sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache] 398 sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache] 337 sc_signal<bool> r_tgt_icache_req; 338 sc_signal<bool> r_tgt_dcache_req; 339 sc_signal<bool> r_tgt_icache_rsp; 340 sc_signal<bool> r_tgt_dcache_rsp; 399 341 400 342 sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network 401 sc_signal<uint32_t> r_cleanup_num_cache; 402 sc_signal<bool> r_cleanup_icache; 403 404 MultiWriteBuffer<addr_40>** r_wbuf; 405 GenericCache<vci_addr_t> ** r_icache; 406 GenericCache<vci_addr_t> ** r_dcache; 407 408 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 409 std::ofstream * log_transaction_file_icache; //[m_nb_cpu] 410 std::ofstream * log_transaction_file_dcache; //[m_nb_cpu] 411 std::ofstream log_transaction_file_cmd; 412 std::ofstream log_transaction_file_tgt; 413 std::ofstream log_transaction_file_cleanup; 343 344 MultiWriteBuffer<addr_40> r_wbuf; 345 GenericCache<vci_addr_t> r_icache; 346 GenericCache<vci_addr_t> r_dcache; 347 348 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 349 std::ofstream log_dcache_transaction_file; 414 350 #endif 415 351 416 352 // Activity counters 417 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 418 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 419 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 420 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 421 422 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 423 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 424 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 425 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 426 427 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 428 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 429 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 430 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 431 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 432 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 433 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 434 435 uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 436 uint32_t m_cpt_total_cycles; // total number of cycles 437 438 uint32_t m_cpt_data_read; // number of data read 439 uint32_t m_cpt_data_read_miss; // number of data read miss 440 uint32_t m_cpt_data_read_uncached; // number of data read uncached 441 uint32_t m_cpt_data_write; // number of data write 442 uint32_t m_cpt_data_write_miss; // number of data write miss 443 uint32_t m_cpt_data_write_uncached; // number of data write uncached 444 uint32_t m_cpt_ins_miss; // * number of instruction miss 445 446 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 447 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 448 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 449 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 450 451 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 452 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 453 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 454 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 455 456 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 457 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 458 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 459 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 460 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 461 462 uint32_t * m_cpt_icache_access; //[m_nb_icache] 463 uint32_t * m_cpt_dcache_access; //[m_nb_dcache] 464 uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache] 465 uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache] 466 uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache] 467 uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache] 468 uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache] 469 470 uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] 471 uint32_t ** m_cpt_fsm_icache; //[m_nb_icache] 472 uint32_t * m_cpt_fsm_cmd; 473 uint32_t * m_cpt_fsm_rsp; 474 uint32_t * m_cpt_fsm_tgt; 475 uint32_t * m_cpt_fsm_cleanup; 476 477 // Non blocking multi-cache 478 typename iss_t::InstructionRequest * ireq ; //[m_nb_icache] 479 typename iss_t::InstructionResponse * irsp ; //[m_nb_icache] 480 bool * ireq_cached ; //[m_nb_icache] 481 uint32_t * ireq_num_cpu; //[m_nb_dcache] 482 typename iss_t::DataRequest * dreq ; //[m_nb_dcache] 483 typename iss_t::DataResponse * drsp ; //[m_nb_dcache] 484 bool * dreq_cached ; //[m_nb_dcache] 485 uint32_t * dreq_num_cpu; //[m_nb_dcache] 486 487 const uint32_t m_num_cache_LSB; 488 const uint32_t m_num_cache_MSB; 489 addr_40 m_num_cache_LSB_mask; 490 addr_40 m_num_cache_mask; 353 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 354 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 355 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 356 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 357 358 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 359 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 360 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 361 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 362 363 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 364 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 365 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 366 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 367 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 368 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 369 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 370 371 uint32_t m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 372 uint32_t m_cpt_total_cycles; // total number of cycles 373 374 uint32_t m_cpt_data_read; // number of data read 375 uint32_t m_cpt_data_read_miss; // number of data read miss 376 uint32_t m_cpt_data_read_uncached; // number of data read uncached 377 uint32_t m_cpt_data_write; // number of data write 378 uint32_t m_cpt_data_write_miss; // number of data write miss 379 uint32_t m_cpt_data_write_uncached; // number of data write uncached 380 uint32_t m_cpt_ins_miss; // * number of instruction miss 381 382 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 383 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 384 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 385 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 386 387 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 388 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 389 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 390 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 391 392 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 393 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 394 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 395 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 396 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 491 397 492 398 protected: … … 503 409 const soclib::common::IntTab &initiator_index_c, 504 410 const soclib::common::IntTab &target_index, 505 size_t nb_cpu,506 size_t nb_cache,507 411 size_t icache_ways, 508 412 size_t icache_sets, … … 518 422 ~VciCcXCacheWrapperV4(); 519 423 520 void print_trace(size_t mode = 0);521 void print_cpi();522 void print_stats(bool print_wbuf=true, bool print_fsm=true);424 void print_trace(size_t mode = 0); 425 void print_cpi(); 426 void print_stats(); 523 427 524 428 // #if CC_XCACHE_WRAPPER_STOP_SIMULATION … … 531 435 void genMoore(); 532 436 533 uint32_t get_num_cache (addr_40 & addr); 534 uint32_t get_num_cache_only(addr_40 addr); 535 void set_num_cache (addr_40 & addr, uint32_t num_cache); 536 addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache); 537 538 soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); 437 soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); 539 438 soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); 540 439 };
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