Changeset 255 for trunk/platforms/tsarv4_generic_mmu
- Timestamp:
- Aug 16, 2012, 7:36:04 PM (12 years ago)
- Location:
- trunk/platforms/tsarv4_generic_mmu
- Files:
-
- 4 edited
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top.cpp (modified) (28 diffs)
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tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd (modified) (3 diffs)
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tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h (modified) (3 diffs)
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tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/platforms/tsarv4_generic_mmu/top.cpp
r249 r255 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 // Date : june 20115 // Date : august 2012 6 6 // This program is released under the GNU public license 7 7 ///////////////////////////////////////////////////////////////////////// … … 11 11 // - It uses the vci_cc_vcache_wrapper_v4 12 12 // - It uses the vci_mem_cache_v4 13 // - It uses one vci_xicu, one vci_multi_tty, 14 // and one vci_multi_dma controler per cluster. 15 // 13 // - It contains one vci_xicu and one vci_multi_dma per cluster. 14 // The peripherals BDEV, FBUF, MTTY, and the boot BROM 15 // are in the cluster containing address 0xBFC00000. 16 // 16 17 // It is build with one single component implementing a cluster: 17 18 // The Tsarv4ClusterMmu component is defined in files 18 19 // tsarv4_cluster_mmu.* (with * = cpp, h, sd) 19 20 // 21 // The IRQs are connected to XICUs as follow: 22 // - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. 23 // - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. 24 // - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. 25 // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. 26 // 20 27 // The physical address space is 32 bits. 21 28 // The number of clusters cannot be larger than 256. 22 // The number of processors per cluster cannot be larger than 4. 23 // The parameters must be power of 2. 24 // - xmax : number of clusters in a row 25 // - ymax : number of clusters in a column 26 // - nprocs : number of processors per cluster 29 // The number of processors per cluster cannot be larger than 8. 27 30 // 28 // The peripherals BDEV, FBUF, and the boot BROM 29 // are in the cluster containing address 0xBFC00000. 30 // - The nprocs TTY IRQs are connected to IRQ_IN[0] to IRQ_IN[3] 31 // - The nprocs DMA IRQs are connected to IRQ_IN[4] to IRQ_IN[7] 32 // - The IOC IRQ is connected to IRQ_IN[8] 31 // The hardware parameters are : 32 // - xmax : number of clusters in a row (power of 2) 33 // - ymax : number of clusters in a column (power of 2) 34 // - nb_procs : number of processors per cluster (power of 2) 35 // - nb_dmas : number of DMA channels per cluster (< 9) 36 // - nb_ttys : number of TTYs in I/O cluster (< 16) 33 37 // 34 38 // General policy for 32 bits physical address decoding: … … 97 101 /////////////////////////////////////////////////// 98 102 99 #define MESH_XMAX 2 100 #define MESH_YMAX 2 101 102 #define NPROCS 4 103 #define XRAM_LATENCY 0 104 105 #define MEMC_WAYS 16 106 #define MEMC_SETS 256 107 108 #define L1_IWAYS 4 109 #define L1_ISETS 64 110 111 #define L1_DWAYS 4 112 #define L1_DSETS 64 113 114 #define FBUF_X_SIZE 512 115 #define FBUF_Y_SIZE 512 116 117 #define BDEV_SECTOR_SIZE 128 118 #define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/couple_512.raw" 119 120 #define BOOT_SOFT_NAME "../../softs/soft_transpose_giet/bin.soft" 121 122 #define MAX_FROZEN_CYCLES 100000 103 #define MESH_XMAX 2 104 #define MESH_YMAX 2 105 106 #define NB_PROCS 1 107 #define NB_TTYS 8 108 #define NB_DMAS 1 109 110 #define XRAM_LATENCY 0 111 112 #define MEMC_WAYS 16 113 #define MEMC_SETS 256 114 115 #define L1_IWAYS 4 116 #define L1_ISETS 64 117 118 #define L1_DWAYS 4 119 #define L1_DSETS 64 120 121 #define FBUF_X_SIZE 128 122 #define FBUF_Y_SIZE 128 123 124 #define BDEV_SECTOR_SIZE 512 125 #define BDEV_IMAGE_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/display/images.raw" 126 127 #define BOOT_SOFT_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/soft.elf" 128 129 #define MAX_FROZEN_CYCLES 10000 130 131 #define TRACE_MEMC_ID 1000000 132 #define TRACE_PROC_ID 1000000 123 133 124 134 ///////////////////////////////////////////////////////// … … 132 142 // There is 4 specific segments in the "IO" cluster 133 143 // (containing address 0xBF000000) 134 // - seg_reset 144 // - seg_reset -> BROM / BASE = 0xBFC00000 (1 Mbytes) 135 145 // - seg_fbuf -> FBUF / BASE = 0xBFD00000 (2 M bytes) 136 146 // - seg_bdev -> BDEV / BASE = 0xBFF10000 … … 142 152 /////////////////////////////////////////////////// 143 153 144 // specific segments in "IO" cluster 154 // specific segments in "IO" cluster : absolute physical address 145 155 146 156 #define BROM_BASE 0xBFC00000 147 157 #define BROM_SIZE 0x00100000 148 158 149 #define FBUF_BASE 0x BFD00000159 #define FBUF_BASE 0x80D00000 150 160 #define FBUF_SIZE 0x00200000 151 161 152 #define BDEV_BASE 0xBFF10000 153 #define BDEV_SIZE 0x00000020 154 155 #define MTTY_BASE 0xBFF20000 156 #define MTTY_SIZE 0x00000040 157 158 // replicated segments 162 #define BDEV_BASE 0x80F10000 163 #define BDEV_SIZE 0x00001000 164 165 #define MTTY_BASE 0x80F20000 166 #define MTTY_SIZE 0x00001000 167 168 // replicated segments : physical address is incremented by an offset 169 // offset = cluster(x,y) << (address_width-x_width-y_width); 159 170 160 171 #define MEMC_BASE 0x00000000 … … 165 176 166 177 #define CDMA_BASE 0x00F30000 167 #define CDMA_SIZE 0x00004000 168 169 #define PROC_BASE 0x00D00000 170 #define PROC_SIZE 0x00000010 178 #define CDMA_SIZE 0x00008000 171 179 172 180 //////////////////////////////////////////////////////////////////// … … 191 199 192 200 193 char soft_name[256] = BOOT_SOFT_NAME; 201 char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code 194 202 size_t ncycles = 1000000000; // simulated cycles 195 size_t xmax = MESH_XMAX; // number of clusters in a row203 size_t xmax = MESH_XMAX; // number of clusters in a row 196 204 size_t ymax = MESH_YMAX; // number of clusters in a column 197 size_t nprocs = NPROCS; // number of processors per cluster 198 size_t xfb = FBUF_X_SIZE; // frameBuffer column number 205 size_t nb_procs = NB_PROCS; // number of processors per cluster 206 size_t nb_dmas = NB_DMAS; // number of RDMA channels per cluster 207 size_t nb_ttys = NB_TTYS; // number of TTY terminals in I/O cluster 208 size_t xfb = FBUF_X_SIZE; // frameBuffer column number 199 209 size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number 200 210 size_t memc_ways = MEMC_WAYS; … … 206 216 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image 207 217 size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes) 208 size_t xram_latency = XRAM_LATENCY; // external RAM latency 209 bool trace_ok = false; // trace activated 210 size_t trace_period = 1; // trace period 211 uint32_t from_cycle = 0; // debug start cycle 218 size_t xram_latency = XRAM_LATENCY; // external RAM latency 219 bool debug_ok = false; // trace activated 220 size_t debug_period = 1; // trace period 221 size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) 222 size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced 223 uint32_t debug_from = 0; // trace start cycle 212 224 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 213 225 214 226 ////////////// command line arguments ////////////////////// 215 if (argc > 1){ 216 for (int n = 1; n < argc; n = n + 2){ 217 if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)){ 227 if (argc > 1) 228 { 229 for (int n = 1; n < argc; n = n + 2) 230 { 231 if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) 232 { 218 233 ncycles = atoi(argv[n+1]); 219 234 } 220 else if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc)){ 221 nprocs = atoi(argv[n+1]); 222 assert( ((nprocs == 1) || (nprocs == 2) || (nprocs == 4)) && 223 "NPROCS must be equal to 1, 2, or 4"); 224 } 225 else if ((strcmp(argv[n],"-XMAX") == 0) && (n+1<argc)){ 235 else if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc)) 236 { 237 nb_procs = atoi(argv[n+1]); 238 assert( ((nb_procs == 1) || (nb_procs == 2) || 239 (nb_procs == 4) || (nb_procs == 8)) && 240 "NPROCS must be equal to 1, 2, 4, or 8"); 241 } 242 else if ((strcmp(argv[n],"-NTTYS") == 0) && (n+1<argc)) 243 { 244 nb_ttys = atoi(argv[n+1]); 245 assert( (nb_ttys < 16) && 246 "The number of TTY terminals cannot be larger than 15"); 247 } 248 else if ((strcmp(argv[n],"-NDMAS") == 0) && (n+1<argc)) 249 { 250 nb_dmas = atoi(argv[n+1]); 251 assert( (nb_dmas < 9) && 252 "The number of DMA channels per cluster cannot be larger than 8"); 253 } 254 else if ((strcmp(argv[n],"-XMAX") == 0) && (n+1<argc)) 255 { 226 256 xmax = atoi(argv[n+1]); 227 257 assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) … … 229 259 } 230 260 231 else if ((strcmp(argv[n],"-YMAX") == 0) && (n+1<argc)){ 261 else if ((strcmp(argv[n],"-YMAX") == 0) && (n+1<argc)) 262 { 232 263 ymax = atoi(argv[n+1]); 233 264 assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) 234 265 && "The YMAX parameter must be 2, 4, 8, or 16" ); 235 266 } 236 else if ((strcmp(argv[n],"-XFB") == 0) && (n+1<argc)){ 267 else if ((strcmp(argv[n],"-XFB") == 0) && (n+1<argc)) 268 { 237 269 xfb = atoi(argv[n+1]); 238 270 } 239 else if ((strcmp(argv[n],"-YFB") == 0) && (n+1<argc) ){ 271 else if ((strcmp(argv[n],"-YFB") == 0) && (n+1<argc) ) 272 { 240 273 yfb = atoi(argv[n+1]); 241 274 } 242 else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ){ 275 else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) 276 { 243 277 strcpy(soft_name, argv[n+1]); 244 278 } 245 else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ){ 279 else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) 280 { 246 281 strcpy(disk_name, argv[n+1]); 247 282 } 248 else if ((strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) ){ 249 trace_ok = true; 250 from_cycle = atoi(argv[n+1]); 251 } 252 else if ((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc)){ 283 else if ((strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) ) 284 { 285 debug_ok = true; 286 debug_from = atoi(argv[n+1]); 287 } 288 else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) 289 { 290 debug_memc_id = atoi(argv[n+1]); 291 assert( (debug_memc_id < (xmax*ymax) ) && 292 "debug_memc_id larger than XMAX * YMAX" ); 293 } 294 else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) 295 { 296 debug_proc_id = atoi(argv[n+1]); 297 assert( (debug_proc_id < (xmax*ymax*nb_procs) ) && 298 "debug_proc_id larger than XMAX * YMAX * BN_PROCS" ); 299 } 300 else if ((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc)) 301 { 253 302 memc_ways = atoi(argv[n+1]); 254 303 } 255 else if ((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc)){ 304 else if ((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc)) 305 { 256 306 memc_sets = atoi(argv[n+1]); 257 307 } 258 else if ((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc)){ 308 else if ((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc)) 309 { 259 310 xram_latency = atoi(argv[n+1]); 260 311 } 261 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)){ 312 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) 313 { 262 314 frozen_cycles = atoi(argv[n+1]); 263 315 } 264 else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)){ 265 trace_period = atoi(argv[n+1]); 316 else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) 317 { 318 debug_period = atoi(argv[n+1]); 266 319 } 267 320 else … … 274 327 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; 275 328 std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl; 329 std::cout << " -NTTYS total_number_of_TTY_terminals" << std::endl; 330 std::cout << " -NDMAS number_of_DMA_channels_per_cluster" << std::endl; 276 331 std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl; 277 332 std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl; … … 284 339 std::cout << " -FROZEN max_number_of_lines" << std::endl; 285 340 std::cout << " -PERIOD number_of_cycles between trace" << std::endl; 341 std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; 342 std::cout << " -PROCID index_proc_to_be_traced" << std::endl; 286 343 exit(0); 287 344 } … … 290 347 291 348 std::cout << std::endl; 292 std::cout << " - NPROCS = " << nprocs << std::endl; 293 std::cout << " - NCLUSTERS = " << xmax*ymax << std::endl; 294 std::cout << " - MAX FROZEN = " << frozen_cycles << std::endl; 349 std::cout << " - NB_CLUSTERS = " << xmax*ymax << std::endl; 350 std::cout << " - NB_PROCS = " << nb_procs << std::endl; 351 std::cout << " - NB_TTYS = " << nb_ttys << std::endl; 352 std::cout << " - NB_DMAS = " << nb_dmas << std::endl; 353 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 295 354 std::cout << " - MEMC_WAYS = " << memc_ways << std::endl; 296 355 std::cout << " - MEMC_SETS = " << memc_sets << std::endl; … … 317 376 wrplen_width> vci_param; 318 377 319 size_t cluster_io_index; 378 // Define parameters depending on mesh size 379 size_t cluster_io_id; 320 380 size_t x_width; 321 381 size_t y_width; … … 333 393 else y_width = 4; 334 394 335 cluster_io_i ndex= 0xBF >> (8 - x_width - y_width);395 cluster_io_id = 0xBF >> (8 - x_width - y_width); 336 396 337 397 ///////////////////// … … 345 405 0x00FF0000); 346 406 347 for (size_t x = 0; x < xmax; x++){ 348 for (size_t y = 0; y < ymax; y++){ 407 for (size_t x = 0; x < xmax; x++) 408 { 409 for (size_t y = 0; y < ymax; y++) 410 { 349 411 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 350 412 … … 361 423 maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); 362 424 363 if ( cluster(x,y) == cluster_io_i ndex)364 { 365 maptabd.add(Segment("d_seg_mtty 366 maptabd.add(Segment("d_seg_fbuf 367 maptabd.add(Segment("d_seg_bdev 368 maptabd.add(Segment("d_seg_brom 425 if ( cluster(x,y) == cluster_io_id ) 426 { 427 maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); 428 maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); 429 maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); 430 maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); 369 431 } 370 432 } … … 374 436 // coherence network 375 437 // - tgtid_c_proc = srcid_c_proc = local procid 376 // - tgtid_c_memc = srcid_c_memc = n procs438 // - tgtid_c_memc = srcid_c_memc = nb_procs 377 439 MappingTable maptabc(address_width, 378 440 IntTab(x_width + y_width, srcid_width - x_width - y_width), … … 380 442 0x00FF0000); 381 443 382 for (size_t x = 0; x < xmax; x++){ 383 for (size_t y = 0; y < ymax; y++){ 444 for (size_t x = 0; x < xmax; x++) 445 { 446 for (size_t y = 0; y < ymax; y++) 447 { 384 448 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 385 449 386 // cleanup requests regarding the memc segmentmust be routed to the memory cache450 // cleanup requests must be routed to the memory cache 387 451 std::ostringstream sh; 388 452 sh << "c_seg_memc_" << x << "_" << y; 389 maptabc.add(Segment(sh.str(), (nprocs << (address_width - srcid_width)) + offset, 0x10, IntTab(cluster(x,y), nprocs), false)); 453 maptabc.add(Segment(sh.str(), (nb_procs << (address_width - srcid_width)) + offset, 454 0x10, IntTab(cluster(x,y), nb_procs), false)); 390 455 391 456 // update & invalidate requests must be routed to the proper processor 392 for ( size_t p = 0 ; p < nprocs ; p++) { 457 for ( size_t p = 0 ; p < nb_procs ; p++) 458 { 393 459 std::ostringstream sp; 394 460 sp << "c_seg_proc_" << x << "_" << y << "_" << p; 395 maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , 0x10 , IntTab(cluster(x,y), p) , false)); 461 maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , 462 0x10 , IntTab(cluster(x,y), p) , false)); 396 463 } 397 464 } … … 402 469 MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); 403 470 404 for (size_t x = 0; x < xmax; x++){ 405 for (size_t y = 0; y < ymax ; y++){ 471 for (size_t x = 0; x < xmax; x++) 472 { 473 for (size_t y = 0; y < ymax ; y++) 474 { 406 475 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 407 476 std::ostringstream sh; 408 477 sh << "x_seg_memc_" << x << "_" << y; 409 maptabx.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y)), false)); 478 maptabx.add(Segment(sh.str(), MEMC_BASE+offset, 479 MEMC_SIZE, IntTab(cluster(x,y)), false)); 410 480 } 411 481 } … … 472 542 { 473 543 #pragma omp for 474 for(size_t i = 0; i < (xmax * ymax); i++) {475 size_t x = i / ymax;476 size_t y = i %ymax;477 544 for(size_t i = 0; i < (xmax * ymax); i++) 545 { 546 size_t x = i / ymax; 547 size_t y = i % ymax; 478 548 #pragma omp critical 479 std::ostringstream sc; 480 sc << "cluster_" << x << "_" << y; 481 clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> 549 550 std::cout << "building cluster_" << x << "_" << y << std::endl; 551 552 std::ostringstream sc; 553 sc << "cluster_" << x << "_" << y; 554 clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> 482 555 (sc.str().c_str(), 483 nprocs, 556 nb_procs, 557 nb_ttys, 558 nb_dmas, 484 559 x, 485 560 y, … … 504 579 l1_d_sets, 505 580 xram_latency, 506 (cluster(x,y) == cluster_io_i ndex),581 (cluster(x,y) == cluster_io_id), 507 582 xfb, 508 583 yfb, … … 511 586 loader, 512 587 frozen_cycles, 513 from_cycle, 514 trace_ok and (cluster_io_index == cluster(x,y)) ); 515 } 588 debug_from, 589 debug_ok and (cluster(x,y) == debug_memc_id), 590 debug_ok and (cluster(x,y) == debug_proc_id) ); 591 592 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; 593 594 } 516 595 } 517 596 518 597 #else // NO OPENMP 519 598 520 for (size_t x = 0; x < xmax; x++){ 521 for (size_t y = 0; y < ymax; y++){ 599 for (size_t x = 0; x < xmax; x++) 600 { 601 for (size_t y = 0; y < ymax; y++) 602 { 522 603 523 604 std::cout << "building cluster_" << x << "_" << y << std::endl; … … 527 608 clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> 528 609 (sc.str().c_str(), 529 nprocs, 610 nb_procs, 611 nb_ttys, 612 nb_dmas, 530 613 x, 531 614 y, … … 550 633 l1_d_sets, 551 634 xram_latency, 552 (cluster(x,y) == cluster_io_i ndex),635 (cluster(x,y) == cluster_io_id), 553 636 xfb, 554 637 yfb, … … 557 640 loader, 558 641 frozen_cycles, 559 from_cycle, 560 trace_ok and (cluster_io_index == cluster(x,y)) ); 642 debug_from, 643 debug_ok and ( cluster(x,y) == debug_memc_id ), 644 debug_ok and ( cluster(x,y) == debug_proc_id ) ); 561 645 562 646 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; … … 618 702 619 703 // East & West boundary cluster connections 620 for (size_t y = 0; y < ymax; y++){ 621 for (size_t k = 0; k < 2; k++){ 704 for (size_t y = 0; y < ymax; y++) 705 { 706 for (size_t k = 0; k < 2; k++) 707 { 622 708 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); 623 709 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); … … 633 719 634 720 // North & South boundary clusters connections 635 for (size_t x = 0; x < xmax; x++){ 636 for (size_t k = 0; k < 2; k++){ 721 for (size_t x = 0; x < xmax; x++) 722 { 723 for (size_t k = 0; k < 2; k++) 724 { 637 725 clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); 638 726 clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); … … 677 765 signal_resetn = true; 678 766 679 for (size_t n = 1; n < ncycles; n++){ 680 if (trace_ok and (n > from_cycle) and (n % trace_period == 0)){ 767 for (size_t n = 1; n < ncycles; n++) 768 { 769 770 if (debug_ok and (n > debug_from) and (n % debug_period == 0)) 771 { 681 772 std::cout << "****************** cycle " << std::dec << n ; 682 773 std::cout << " ************************************************" << std::endl; 683 774 684 // components cluster 00 ///////////////////// 685 // clusters[0][0]->proc[0]->print_trace(); 686 // clusters[0][0]->memc->print_trace(); 687 688 // signals cluster 00 //////////////////////// 689 // clusters[0][0]->signal_vci_ini_d_proc[0].print_trace("proc_0_0_0_ini_d"); 690 // clusters[0][0]->signal_vci_ini_c_proc[0].print_trace("proc_0_0_0_ini_c"); 691 // clusters[0][0]->signal_vci_tgt_c_proc[0].print_trace("proc_0_0_0_tgt_c"); 692 // clusters[0][0]->signal_vci_xram.print_trace("memc_0_0_xram"); 693 694 // components cluster 01 ///////////////////// 695 // clusters[0][1]->proc[0]->print_trace(); 696 // clusters[0][1]->memc->print_trace(); 697 698 // signals cluster 01 /////////////////////// 699 // clusters[0][1]->signal_vci_ini_d_proc[0].print_trace("proc_0_1_0_ini_d"); 700 // clusters[0][1]->signal_vci_ini_c_proc[0].print_trace("proc_0_1_0_ini_c"); 701 // clusters[0][1]->signal_vci_tgt_c_proc[0].print_trace("proc_0_1_0_tgt_c"); 702 // clusters[0][1]->signal_vci_xram.print_trace("memc_0_1_xram"); 703 704 // components cluster 10 //////////////////// 705 clusters[1][0]->proc[0]->print_trace(1); 706 clusters[1][0]->memc->print_trace(); 707 // clusters[1][0]->bdev->print_trace(); 708 // clusters[1][0]->mdma->print_trace(); 709 710 // signals cluster 10 /////////////////////// 711 clusters[1][0]->signal_vci_ini_d_proc[0].print_trace("proc_1_0_0_ini_d"); 712 // clusters[1][0]->signal_vci_ini_c_proc[0].print_trace("proc_1_0_0_ini_c"); 713 // clusters[1][0]->signal_vci_tgt_c_proc[0].print_trace("proc_1_0_0_tgt_c"); 714 clusters[1][0]->signal_vci_tgt_d_memc.print_trace("memc_1_0_tgt_d "); 715 // clusters[1][0]->signal_vci_ini_c_memc.print_trace("memc_1_0_ini_c "); 716 // clusters[1][0]->signal_vci_tgt_c_memc.print_trace("memc_1_0_tgt_c "); 717 // clusters[1][0]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); 718 // clusters[1][0]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); 719 // clusters[1][0]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d "); 720 // clusters[1][0]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d "); 721 clusters[1][0]->signal_vci_tgt_d_mtty.print_trace("mtty_1_0_tgt_d "); 722 clusters[1][0]->signal_vci_xram.print_trace("memc_1_0_xram"); 723 724 // components cluster 11 ///////////////////// 725 // clusters[1][1]->proc[0]->print_trace(); 726 // clusters[1][1]->memc->print_trace(); 727 728 // signals cluster 11 //////////////////////// 729 // clusters[1][1]->signal_vci_ini_d_proc[0].print_trace("proc_1_1_0_ini_d"); 730 // clusters[1][1]->signal_vci_ini_c_proc[0].print_trace("proc_1_1_0_ini_c"); 731 // clusters[1][1]->signal_vci_tgt_c_proc[0].print_trace("proc_1_1_0_tgt_c"); 732 // clusters[1][1]->signal_vci_xram.print_trace("memc_1_1_xram"); 775 // trace proc[debug_proc_id] 776 if ( debug_proc_id < (xmax * ymax * nb_procs) ) 777 { 778 size_t proc_x = debug_proc_id / ymax; 779 size_t proc_y = debug_proc_id % ymax; 780 781 clusters[proc_x][proc_y]->proc[0]->print_trace(); 782 783 clusters[proc_x][proc_y]->signal_vci_ini_d_proc[0].print_trace("proc_ini_d"); 784 clusters[proc_x][proc_y]->signal_vci_ini_c_proc[0].print_trace("proc_ini_c"); 785 clusters[proc_x][proc_y]->signal_vci_tgt_c_proc[0].print_trace("proc_tgt_c"); 786 } 787 788 // trace memc[debug_memc_id] 789 if ( debug_memc_id < (xmax * ymax) ) 790 { 791 size_t memc_x = debug_memc_id / ymax; 792 size_t memc_y = debug_memc_id % ymax; 793 794 clusters[memc_x][memc_y]->memc->print_trace(); 795 796 clusters[memc_x][memc_y]->signal_vci_tgt_d_memc.print_trace("memc_tgt_d"); 797 clusters[memc_x][memc_y]->signal_vci_ini_c_memc.print_trace("memc_ini_c"); 798 clusters[memc_x][memc_y]->signal_vci_tgt_c_memc.print_trace("memc_tgt_c"); 799 } 800 801 // clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0"); 802 // clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1"); 803 // clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0"); 804 // clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1"); 805 806 clusters[1][1]->mdma->print_trace(); 807 clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("dma_tgt_1_1"); 808 clusters[1][1]->signal_vci_ini_d_mdma.print_trace("dma_ini_1_1"); 809 if ( clusters[1][1]->signal_irq_mdma[0].read() ) 810 std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; 811 if ( clusters[1][1]->signal_proc_it[0].read() ) 812 std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; 813 814 // trace peripherals components 815 if ( false ) 816 { 817 size_t io_x = cluster_io_id / ymax; 818 size_t io_y = cluster_io_id % ymax; 819 820 clusters[io_x][io_y]->bdev->print_trace(); 821 clusters[io_x][io_y]->mdma->print_trace(); 822 823 clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); 824 clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); 825 clusters[io_x][io_y]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d "); 826 clusters[io_x][io_y]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d "); 827 } 733 828 } 734 829 -
trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd
r189 r255 16 16 Uses('common:mapping_table'), 17 17 Uses('common:iss2'), 18 18 Uses('caba:vci_cc_vcache_wrapper_v4', 19 19 iss_t = 'common:gdb_iss', 20 20 gdb_iss_t = 'common:mips32el'), 21 22 23 24 25 21 Uses('caba:vci_mem_cache_v4'), 22 Uses('caba:vci_simple_ram'), 23 Uses('caba:vci_xicu'), 24 Uses('caba:vci_local_crossbar'), 25 Uses('caba:virtual_dspin_router', 26 26 flit_width = parameter.Reference('cmd_width')), 27 27 Uses('caba:virtual_dspin_router', 28 28 flit_width = parameter.Reference('rsp_width')), 29 29 Uses('caba:vci_vdspin_target_wrapper', 30 30 dspin_cmd_width = parameter.Reference('cmd_width'), 31 31 dspin_rsp_width = parameter.Reference('rsp_width')), 32 32 Uses('caba:vci_vdspin_initiator_wrapper', 33 33 dspin_cmd_width = parameter.Reference('cmd_width'), 34 34 dspin_rsp_width = parameter.Reference('rsp_width')), … … 39 39 Uses('common:elf_file_loader'), 40 40 ], 41 instance_parameters = [42 parameter.Int('n_x'),43 parameter.Int('n_y'),44 parameter.Int('n_cluster'),45 parameter.Module('mtd', 'common:mapping_table'),46 parameter.Module('mtc', 'common:mapping_table'),47 parameter.Module('mtx', 'common:mapping_table'),48 parameter.Int('x_width'),49 parameter.Int('y_width'),50 parameter.Int('memc_tgtid'),51 parameter.Int('xicu_tgtid'),52 parameter.Int('fbuf_tgtid'),53 parameter.Int('mtty_tgtid'),54 parameter.Int('brom_tgtid'),55 parameter.Int('bdev_tgtid'),56 parameter.Int('cdma_tgtid'),57 parameter.Int('memc_ways'),58 parameter.Int('memc_sets'),59 parameter.Int('l1_i_ways'),60 parameter.Int('l1_i_sets'),61 parameter.Int('l1_d_ways'),62 parameter.Int('l1_d_sets'),63 parameter.Int('xram_latency'),64 parameter.Bool('io'),65 ],66 67 41 ports = [ 68 42 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), … … 71 45 Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), 72 46 Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 73 47 Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 74 48 ], 75 49 ) -
trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h
r234 r255 6 6 // This program is released under the GNU public license 7 7 ////////////////////////////////////////////////////////////////////////////// 8 // This file define a TSAR cluster architecture with virtual memory:9 // - It uses the virtual_dspin_router as distributed global interconnect10 // - It uses the vci_local_crossbar as local interconnect11 // - It uses the vci_cc_vcache_wrapper_v412 // - It uses the vci_mem_cache_v413 // - It contains a private RAM with a variable latency to emulate the L3 cache14 // - It can contains 1, 2 or 4 processors15 // - Each processor has a private dma channel (vci_multi_dma)16 // - It uses the vci_xicu interrupt controller17 // - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster18 // containing address 0xBFC00000.19 // - The Multi-TTY component controls 4 terminals.20 // - The nprocs dma irqs are connected to IRQ_IN[0]...IRQ_IN[3]21 // - The four tty irqs are connected to IRQ_IN[4]...IRQ_IN[7]22 // - The bdev irq is connected to IRQ_IN[8]23 //////////////////////////////////////////////////////////////////////////////////24 8 25 9 #ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H … … 62 46 63 47 // Ports 64 65 48 sc_in<bool> p_clk; 49 sc_in<bool> p_resetn; 66 50 soclib::caba::DspinOutput<cmd_width> **p_cmd_out; 67 51 soclib::caba::DspinInput<cmd_width> **p_cmd_in; 68 soclib::caba::DspinOutput<rsp_width>**p_rsp_out;69 soclib::caba::DspinInput<rsp_width>**p_rsp_in;52 soclib::caba::DspinOutput<rsp_width> **p_rsp_out; 53 soclib::caba::DspinInput<rsp_width> **p_rsp_in; 70 54 71 // interrupt signals 72 sc_signal<bool> signal_false; 73 sc_signal<bool> signal_proc_it[4]; 74 sc_signal<bool> signal_irq_mdma[4]; 75 sc_signal<bool> signal_irq_tty0; 76 sc_signal<bool> signal_irq_tty1; 77 sc_signal<bool> signal_irq_tty2; 78 sc_signal<bool> signal_irq_tty3; 55 // interrupt signals 56 sc_signal<bool> signal_false; 57 sc_signal<bool> signal_proc_it[8]; 58 sc_signal<bool> signal_irq_mdma[8]; 59 sc_signal<bool> signal_irq_mtty[23]; 79 60 sc_signal<bool> signal_irq_bdev; 80 61 … … 117 98 VciSignals<vci_param> signal_vci_xram; 118 99 119 100 // Components 120 101 121 VciCcVCacheWrapperV4<vci_param, iss_t>* proc[4];122 123 124 VciLocalCrossbar<vci_param>*xbard;125 VciLocalCrossbar<vci_param>*xbarc;126 VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*tgtwrapperd;127 VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*iniwrapperd;128 VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*tgtwrapperc;129 VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*iniwrapperc;130 VirtualDspinRouter<cmd_width>*cmdrouter;131 132 VciSimpleRam<vci_param>*brom;133 VciMultiTty<vci_param>*mtty;134 VciFrameBuffer<vci_param>*fbuf;135 VciBlockDeviceTsarV4<vci_param>*bdev;136 VciMultiDma<vci_param>*mdma;137 VciSimpleRam<vci_param>*xram;102 VciCcVCacheWrapperV4<vci_param, iss_t>* proc[8]; 103 VciMemCacheV4<vci_param>* memc; 104 VciXicu<vci_param>* xicu; 105 VciLocalCrossbar<vci_param>* xbard; 106 VciLocalCrossbar<vci_param>* xbarc; 107 VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>* tgtwrapperd; 108 VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* iniwrapperd; 109 VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>* tgtwrapperc; 110 VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* iniwrapperc; 111 VirtualDspinRouter<cmd_width>* cmdrouter; 112 VirtualDspinRouter<rsp_width>* rsprouter; 113 VciSimpleRam<vci_param>* brom; 114 VciMultiTty<vci_param>* mtty; 115 VciFrameBuffer<vci_param>* fbuf; 116 VciBlockDeviceTsarV4<vci_param>* bdev; 117 VciMultiDma<vci_param>* mdma; 118 VciSimpleRam<vci_param>* xram; 138 119 139 TsarV4ClusterMmu(sc_module_name insname, 140 size_t nprocs, // number of processors 141 size_t n_x, // x coordinate 142 size_t n_y, // y coordinate 143 size_t n_cluster, // y + ymax*x 144 const soclib::common::MappingTable &mtd, // direct mapping table 145 const soclib::common::MappingTable &mtc, // coherence mapping table 146 const soclib::common::MappingTable &mtx, // xram mapping table 147 size_t x_width, // x field number of bits 148 size_t y_width, // y field number of bits 149 size_t tgtid_memc, 150 size_t tgtid_xicu, 151 size_t tgtid_fbuf, 152 size_t tgtid_mtty, 153 size_t tgtid_brom, 154 size_t tgtid_bdev, 155 size_t tgtid_mdma, 156 size_t memc_ways, // number of ways for MEMC 157 size_t memc_sets, // number of sets for MEMC 158 size_t l1_i_ways, // number of ways for L1 ICACHE 159 size_t l1_i_sets, // number of sets for L1 ICACHE 160 size_t l1_d_ways, // number of ways for L1 DCACHE 161 size_t l1_d_sets, // number of sets for L1 DCACHE 162 size_t xram_latency, // external ram latency 163 bool io, // I/O cluster if true 164 size_t xfb, // frame buffer pixels 165 size_t yfb, // frame buffer lines 166 char* disk_name, // virtual disk name for BDEV 167 size_t block_size, // block size for BDEV 168 const Loader &loader, // loader for BROM 169 uint32_t frozen_cycles, // max frozen cycles 170 uint32_t start_debug_cycle, 171 bool debug_ok); 120 TsarV4ClusterMmu(sc_module_name insname, 121 size_t nb_procs, // number of processors 122 size_t nb_ttys, // number of TTY terminals 123 size_t nb_dmas, // number of DMA channels 124 size_t x, // x coordinate 125 size_t y, // y coordinate 126 size_t cluster, // y + ymax*x 127 const soclib::common::MappingTable &mtd, // direct mapping table 128 const soclib::common::MappingTable &mtc, // coherence mapping table 129 const soclib::common::MappingTable &mtx, // xram mapping table 130 size_t x_width, // x field number of bits 131 size_t y_width, // y field number of bits 132 size_t tgtid_memc, 133 size_t tgtid_xicu, 134 size_t tgtid_fbuf, 135 size_t tgtid_mtty, 136 size_t tgtid_brom, 137 size_t tgtid_bdev, 138 size_t tgtid_mdma, 139 size_t memc_ways, 140 size_t memc_sets, 141 size_t l1_i_ways, 142 size_t l1_i_sets, 143 size_t l1_d_ways, 144 size_t l1_d_sets, 145 size_t xram_latency, // external ram latency 146 bool io, // I/O cluster if true 147 size_t xfb, // frame buffer pixels 148 size_t yfb, // frame buffer lines 149 char* disk_name, // virtual disk name for BDEV 150 size_t block_size, // block size for BDEV 151 const Loader &loader, // loader for BROM 152 uint32_t frozen_cycles, // max frozen cycles 153 uint32_t start_debug_cycle, 154 bool memc_debug_ok, 155 bool proc_debug_ok); 172 156 173 157 ~TsarV4ClusterMmu(); -
trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
r249 r255 1 ////////////////////////////////////////////////////////////////////////////// 2 // File: tsarv4_cluster_mmu.c 3 // Author: Alain Greiner 4 // Copyright: UPMC/LIP6 5 // Date : march 2011 6 // This program is released under the GNU public license 7 ////////////////////////////////////////////////////////////////////////////// 8 // This file define a TSAR cluster architecture with virtual memory: 9 // - It uses the virtual_dspin_router as distributed global interconnect 10 // - It uses the vci_local_crossbar as local interconnect 11 // - It uses the vci_cc_vcache_wrapper_v4 12 // - It uses the vci_mem_cache_v4 13 // - It contains a private RAM with a variable latency to emulate the L3 cache 14 // - It can contains 1, 2 or 4 processors 15 // - Each processor has a private dma channel (vci_multi_dma) 16 // - It uses the vci_xicu interrupt controller 17 // - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster 18 // containing address 0xBFC00000. 19 // - The Multi-TTY component controls up to 15 terminals. 20 // - Each Multi-DMA component controls up to 8 DMA channels. 21 // - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15] 22 // - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30] 23 // - The BDEV IRQ is connected to IRQ_IN[31] 24 ////////////////////////////////////////////////////////////////////////////////// 25 1 26 #include "../include/tsarv4_cluster_mmu.h" 2 27 … … 8 33 ////////////////////////////////////////////////////////////////////////// 9 34 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 10 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu( 11 sc_module_name insname, 12 size_t nprocs, 13 size_t x_id, 14 size_t y_id, 15 size_t cluster_id, 16 const soclib::common::MappingTable &mtd, 17 const soclib::common::MappingTable &mtc, 18 const soclib::common::MappingTable &mtx, 19 size_t x_width, 20 size_t y_width, 21 size_t tgtid_memc, 22 size_t tgtid_xicu, 23 size_t tgtid_fbuf, 24 size_t tgtid_mtty, 25 size_t tgtid_brom, 26 size_t tgtid_bdev, 27 size_t tgtid_mdma, 28 size_t memc_ways, 29 size_t memc_sets, 30 size_t l1_i_ways, 31 size_t l1_i_sets, 32 size_t l1_d_ways, 33 size_t l1_d_sets, 34 size_t xram_latency, 35 bool io, 36 size_t xfb, 37 size_t yfb, 38 char* disk_name, 39 size_t block_size, 40 const Loader &loader, 41 uint32_t frozen_cycles, 42 uint32_t debug_start_cycle, 43 bool debug_ok) 35 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu( 36 sc_module_name insname, 37 size_t nb_procs, 38 size_t nb_ttys, 39 size_t nb_dmas, 40 size_t x_id, 41 size_t y_id, 42 size_t cluster_id, 43 const soclib::common::MappingTable &mtd, 44 const soclib::common::MappingTable &mtc, 45 const soclib::common::MappingTable &mtx, 46 size_t x_width, 47 size_t y_width, 48 size_t tgtid_memc, 49 size_t tgtid_xicu, 50 size_t tgtid_fbuf, 51 size_t tgtid_mtty, 52 size_t tgtid_brom, 53 size_t tgtid_bdev, 54 size_t tgtid_mdma, 55 size_t memc_ways, 56 size_t memc_sets, 57 size_t l1_i_ways, 58 size_t l1_i_sets, 59 size_t l1_d_ways, 60 size_t l1_d_sets, 61 size_t xram_latency, 62 bool io, 63 size_t xfb, 64 size_t yfb, 65 char* disk_name, 66 size_t block_size, 67 const Loader &loader, 68 uint32_t frozen_cycles, 69 uint32_t debug_start_cycle, 70 bool memc_debug_ok, 71 bool proc_debug_ok) 44 72 : soclib::caba::BaseModule(insname), 45 73 p_clk("clk"), 46 p_resetn("resetn"), 47 48 signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"), 49 signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"), 50 signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"), 51 signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"), 52 signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"), 53 signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"), 54 signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"), 55 signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), 56 57 signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), 58 signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), 59 60 signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), 61 signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"), 62 signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"), 63 signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"), 64 signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"), 65 signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"), 66 signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"), 67 68 signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 69 signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"), 70 71 signal_vci_xram("signal_vci_xram") 72 73 { 74 // Vectors of ports definition 75 76 p_cmd_in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4); 77 p_cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4); 78 p_rsp_in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4); 79 p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); 80 81 // Components definition 82 83 // on direct network : local srcid[proc] in [0...nprocs-1] 84 // on direct network : local srcid[mdma] = nprocs 85 // on direct network : local srcid[bdev] = nprocs + 1 86 87 // on coherence network : local srcid[proc] in [0...nprocs-1] 88 // on coherence network : local srcid[memc] = nprocs 89 90 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; 91 92 for (size_t p = 0; p < nprocs; p++){ 93 std::ostringstream sproc; 94 sproc << "proc_" << x_id << "_" << y_id << "_" << p; 95 proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>( 96 sproc.str().c_str(), 97 cluster_id*nprocs + p, 98 mtd, // Mapping Table Direct 99 mtc, // Mapping Table Coherence 100 IntTab(cluster_id,p), // SRCID_D 101 IntTab(cluster_id,p), // SRCID_C 102 IntTab(cluster_id,p), // TGTID_C 103 8, // ITLB ways 104 8, // ITLB sets 105 8, // DTLB ways 106 8, // DTLB sets 107 l1_i_ways,l1_i_sets,16, // ICACHE size 108 l1_d_ways,l1_d_sets,16, // DCACHE size 109 4, // WBUF width 110 4, // WBUF depth 111 x_width, // X Width 112 y_width, // Y Width 113 nprocs, // Memory Cache Local Id (coherence) 114 frozen_cycles, // max frozen cycles 115 debug_start_cycle, 116 debug_ok); 117 } 118 119 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 120 121 std::ostringstream smemc; 122 smemc << "memc_" << x_id << "_" << y_id; 123 memc = new VciMemCacheV4<vci_param>( 74 p_resetn("resetn") 75 76 { 77 // Vectors of ports definition 78 79 p_cmd_in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4); 80 p_cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4); 81 p_rsp_in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4); 82 p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); 83 84 // Components definition 85 86 // on direct network : local srcid[proc] in [0..nb_procs-1] 87 // on direct network : local srcid[mdma] = nb_procs 88 // on direct network : local srcid[bdev] = nb_procs + 1 89 90 // on coherence network : local srcid[proc] in [0...nb_procs-1] 91 // on coherence network : local srcid[memc] = nb_procs 92 93 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; 94 95 for (size_t p = 0; p < nb_procs; p++) 96 { 97 std::ostringstream sproc; 98 sproc << "proc_" << x_id << "_" << y_id << "_" << p; 99 proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>( 100 sproc.str().c_str(), 101 cluster_id*nb_procs + p, 102 mtd, // Mapping Table Direct 103 mtc, // Mapping Table Coherence 104 IntTab(cluster_id,p), // SRCID_D 105 IntTab(cluster_id,p), // SRCID_C 106 IntTab(cluster_id,p), // TGTID_C 107 8, // ITLB ways 108 8, // ITLB sets 109 8, // DTLB ways 110 8, // DTLB sets 111 l1_i_ways,l1_i_sets,16, // ICACHE size 112 l1_d_ways,l1_d_sets,16, // DCACHE size 113 4, // WBUF nlines 114 4, // WBUF nwords 115 x_width, 116 y_width, 117 nb_procs, // MEMC local index 118 frozen_cycles, // max frozen cycles 119 debug_start_cycle, 120 proc_debug_ok); 121 } 122 123 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 124 125 std::ostringstream smemc; 126 smemc << "memc_" << x_id << "_" << y_id; 127 memc = new VciMemCacheV4<vci_param>( 124 128 smemc.str().c_str(), 125 129 mtd, mtc, mtx, 126 IntTab(cluster_id), 127 IntTab(cluster_id, n procs),// SRCID_C128 IntTab(cluster_id, tgtid_memc), 129 IntTab(cluster_id, n procs),// TGTID_C130 memc_ways, memc_sets, 16, 131 4096, 132 8, 133 8, 130 IntTab(cluster_id), // SRCID_X 131 IntTab(cluster_id, nb_procs), // SRCID_C 132 IntTab(cluster_id, tgtid_memc), // TGTID_D 133 IntTab(cluster_id, nb_procs), // TGTID_C 134 memc_ways, memc_sets, 16, // CACHE SIZE 135 4096, // HEAP SIZE 136 8, // TRANSACTION TABLE DEPTH 137 8, // UPDATE TABLE DEPTH 134 138 debug_start_cycle, 135 debug_ok); 136 137 138 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 139 140 std::ostringstream sxram; 141 sxram << "xram_" << x_id << "_" << y_id; 142 xram = new VciSimpleRam<vci_param>( 139 memc_debug_ok); 140 141 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 142 143 std::ostringstream sxram; 144 sxram << "xram_" << x_id << "_" << y_id; 145 xram = new VciSimpleRam<vci_param>( 143 146 sxram.str().c_str(), 144 147 IntTab(cluster_id), … … 147 150 xram_latency); 148 151 149 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 150 151 size_t nhwi = 4; // always 4 (or 9) ports, even if 152 if (io){ 153 nhwi = 9; // there if less than 4 processors 154 } 155 std::ostringstream sicu; 156 sicu << "xicu_" << x_id << "_" << y_id; 157 xicu = new VciXicu<vci_param>( 152 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 153 154 std::ostringstream sicu; 155 sicu << "xicu_" << x_id << "_" << y_id; 156 xicu = new VciXicu<vci_param>( 158 157 sicu.str().c_str(), 159 mtd, // mapping table 160 IntTab(cluster_id, tgtid_xicu), // TGTID_D 161 0, // number of timer IRQs 162 nhwi, // number of hard IRQs 163 0, // number of soft IRQs 164 nprocs); // number of output IRQs 165 166 std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; 167 168 // dma multi-canaux 169 std::ostringstream sdma; 170 sdma << "dma_" << x_id << "_" << y_id; 171 mdma = new VciMultiDma<vci_param>( 158 mtd, // mapping table 159 IntTab(cluster_id, tgtid_xicu), // TGTID_D 160 nb_procs, // number of timer IRQs 161 32, // number of hard IRQs 162 0, // number of soft IRQs 163 nb_procs); // number of output IRQs 164 165 std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; 166 167 std::ostringstream sdma; 168 sdma << "dma_" << x_id << "_" << y_id; 169 mdma = new VciMultiDma<vci_param>( 172 170 sdma.str().c_str(), 173 171 mtd, 174 IntTab(cluster_id, n procs),// SRCID172 IntTab(cluster_id, nb_procs), // SRCID 175 173 IntTab(cluster_id, tgtid_mdma), // TGTID 176 174 64, // burst size 177 n procs);// number of IRQs178 179 180 181 // direct local crossbar182 size_t nb_direct_initiators = nprocs + 1;183 size_t nb_direct_targets = 3;184 if (io){185 nb_direct_initiators = nprocs + 2;186 187 188 189 190 175 nb_procs); // number of IRQs 176 177 std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; 178 179 size_t nb_direct_initiators = nb_procs + 1; 180 size_t nb_direct_targets = 3; 181 if ( io ) 182 { 183 nb_direct_initiators = nb_procs + 2; 184 nb_direct_targets = 7; 185 } 186 std::ostringstream sd; 187 sd << "xbard_" << x_id << "_" << y_id; 188 xbard = new VciLocalCrossbar<vci_param>( 191 189 sd.str().c_str(), 192 190 mtd, 193 IntTab(cluster_id), // cluster initiator index 194 IntTab(cluster_id), // cluster target index 195 nb_direct_initiators, // number of initiators 196 nb_direct_targets); // number of targets 197 198 std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; 199 200 // coherence local crossbar 201 std::ostringstream sc; 202 sc << "xbarc_" << x_id << "_" << y_id; 203 xbarc = new VciLocalCrossbar<vci_param>( 191 IntTab(cluster_id), // cluster initiator index 192 IntTab(cluster_id), // cluster target index 193 nb_direct_initiators, // number of initiators 194 nb_direct_targets); // number of targets 195 196 std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; 197 198 std::ostringstream sc; 199 sc << "xbarc_" << x_id << "_" << y_id; 200 xbarc = new VciLocalCrossbar<vci_param>( 204 201 sc.str().c_str(), 205 202 mtc, 206 IntTab(cluster_id), 207 IntTab(cluster_id), 208 n procs + 1,// number of initiators209 n procs + 1);// number of targets210 211 212 213 214 215 216 203 IntTab(cluster_id), // cluster initiator index 204 IntTab(cluster_id), // cluster target index 205 nb_procs + 1, // number of initiators 206 nb_procs + 1); // number of targets 207 208 std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; 209 210 // direct initiator wrapper 211 std::ostringstream wid; 212 wid << "iniwrapperd_" << x_id << "_" << y_id; 213 iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 217 214 wid.str().c_str(), 218 215 4, // cmd fifo depth 219 216 4); // rsp fifo depth 220 217 221 222 223 224 218 // direct target wrapper 219 std::ostringstream wtd; 220 wtd << "tgtwrapperd_" << x_id << "_" << y_id; 221 tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 225 222 wtd.str().c_str(), 226 223 4, // cmd fifo depth 227 224 4); // rsp fifo depth 228 225 229 230 231 232 226 // coherence initiator wrapper 227 std::ostringstream wic; 228 wic << "iniwrapperc_" << x_id << "_" << y_id; 229 iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 233 230 wic.str().c_str(), 234 231 4, // cmd fifo depth 235 232 4); // rsp fifo depth 236 233 237 238 239 240 241 234 // coherence target wrapper 235 std::ostringstream wtc; 236 wtc << "tgtwrapperc_" << x_id << "_" << y_id; 237 tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 238 wtc.str().c_str(), 242 239 4, // cmd fifo depth 243 240 4); // rsp fifo depth 244 241 245 std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; 246 247 // CMD router 248 std::ostringstream scmd; 249 scmd << "cmdrouter_" << x_id << "_" << y_id; 250 cmdrouter = new VirtualDspinRouter<cmd_width>( 242 std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; 243 244 std::ostringstream scmd; 245 scmd << "cmdrouter_" << x_id << "_" << y_id; 246 cmdrouter = new VirtualDspinRouter<cmd_width>( 251 247 scmd.str().c_str(), 252 248 x_id,y_id, // coordinate in the mesh … … 254 250 4,4); // input & output fifo depths 255 251 256 257 258 259 260 261 252 std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; 253 254 // RSP router 255 std::ostringstream srsp; 256 srsp << "rsprouter_" << x_id << "_" << y_id; 257 rsprouter = new VirtualDspinRouter<rsp_width>( 262 258 srsp.str().c_str(), 263 259 x_id,y_id, // coordinates in mesh … … 265 261 4,4); // input & output fifo depths 266 262 267 // IO cluster components 268 if (io){ 269 brom = new VciSimpleRam<vci_param>( 263 // IO cluster components 264 if ( io ) 265 { 266 std::cout << " - building brom" << std::endl; 267 268 brom = new VciSimpleRam<vci_param>( 270 269 "brom", 271 270 IntTab(cluster_id, tgtid_brom), … … 273 272 loader); 274 273 275 fbuf = new VciFrameBuffer<vci_param>( 274 std::cout << " - building fbuf" << std::endl; 275 276 fbuf = new VciFrameBuffer<vci_param>( 276 277 "fbuf", 277 278 IntTab(cluster_id, tgtid_fbuf), … … 279 280 xfb, yfb); 280 281 281 bdev = new VciBlockDeviceTsarV4<vci_param>( 282 std::cout << " - building fbuf" << std::endl; 283 284 bdev = new VciBlockDeviceTsarV4<vci_param>( 282 285 "bdev", 283 286 mtd, 284 IntTab(cluster_id, n procs+1),287 IntTab(cluster_id, nb_procs+1), 285 288 IntTab(cluster_id, tgtid_bdev), 286 289 disk_name, 287 block_size); 288 289 mtty = new VciMultiTty<vci_param>( 290 block_size, 291 4); // burst size 292 293 std::cout << " - building mtty" << std::endl; 294 295 std::vector<std::string> vect_names; 296 for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ ) 297 { 298 std::ostringstream term_name; 299 term_name << "term" << tid; 300 vect_names.push_back(term_name.str().c_str()); 301 } 302 mtty = new VciMultiTty<vci_param>( 290 303 "mtty", 291 304 IntTab(cluster_id, tgtid_mtty), 292 305 mtd, 293 "tty0", "tty1", "tty2", "tty3", NULL); 294 } 295 296 std::cout << " - all components constructed" << std::endl; 297 298 //////////////////////////////////// 299 // Connections are defined here 300 //////////////////////////////////// 301 302 // CMDROUTER and RSPROUTER 303 cmdrouter->p_clk (this->p_clk); 304 cmdrouter->p_resetn (this->p_resetn); 305 rsprouter->p_clk (this->p_clk); 306 rsprouter->p_resetn (this->p_resetn); 307 for (int x = 0; x < 2; x++){ 308 for(int y = 0; y < 4; y++){ 309 cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); 310 cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); 311 rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); 312 rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); 313 } 314 } 315 316 cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); 317 cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); 318 cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); 319 cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); 320 321 rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); 322 rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); 323 rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); 324 rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); 325 326 // VCI/DSPIN WRAPPERS 327 iniwrapperd->p_clk (this->p_clk); 328 iniwrapperd->p_resetn (this->p_resetn); 329 iniwrapperd->p_vci (signal_vci_l2g_d); 330 iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); 331 iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); 332 333 tgtwrapperd->p_clk (this->p_clk); 334 tgtwrapperd->p_resetn (this->p_resetn); 335 tgtwrapperd->p_vci (signal_vci_g2l_d); 336 tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); 337 tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); 338 339 iniwrapperc->p_clk (this->p_clk); 340 iniwrapperc->p_resetn (this->p_resetn); 341 iniwrapperc->p_vci (signal_vci_l2g_c); 342 iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); 343 iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); 344 345 tgtwrapperc->p_clk (this->p_clk); 346 tgtwrapperc->p_resetn (this->p_resetn); 347 tgtwrapperc->p_vci (signal_vci_g2l_c); 348 tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); 349 tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); 350 351 // CROSSBAR direct 352 xbard->p_clk (this->p_clk); 353 xbard->p_resetn (this->p_resetn); 354 xbard->p_initiator_to_up (signal_vci_l2g_d); 355 xbard->p_target_to_up (signal_vci_g2l_d); 356 357 xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); 358 xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); 359 xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); 360 361 xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); 362 363 for (size_t p = 0; p < nprocs; p++){ 364 xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); 365 } 366 367 if (io){ 368 xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); 369 xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); 370 xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); 371 xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); 372 373 xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); 374 } 375 376 // CROSSBAR coherence 377 xbarc->p_clk (this->p_clk); 378 xbarc->p_resetn (this->p_resetn); 379 xbarc->p_initiator_to_up (signal_vci_l2g_c); 380 xbarc->p_target_to_up (signal_vci_g2l_c); 381 xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); 382 xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); 383 for (size_t p = 0; p < nprocs; p++) { 384 xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); 385 xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); 386 } 387 388 // Processors 389 for (size_t p = 0; p < nprocs; p++){ 390 proc[p]->p_clk (this->p_clk); 391 proc[p]->p_resetn (this->p_resetn); 392 proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); 393 proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); 394 proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); 395 proc[p]->p_irq[0] (signal_proc_it[p]); 396 for ( size_t j = 1 ; j < 6 ; j++){ 397 proc[p]->p_irq[j] (signal_false); 398 } 399 } 400 401 // XICU 402 xicu->p_clk (this->p_clk); 403 xicu->p_resetn (this->p_resetn); 404 xicu->p_vci (signal_vci_tgt_d_xicu); 405 for (size_t p = 0; p < nprocs; p++){ 406 xicu->p_irq[p] (signal_proc_it[p]); 407 } 408 for (size_t p = 0; p < nprocs; p++){ 409 xicu->p_hwi[p] (signal_irq_mdma[p]); 410 } 411 for (size_t x = nprocs; x < 4; x++){ 412 xicu->p_hwi[x] (signal_false); 413 } 414 415 if (io){ 416 xicu->p_hwi[4] (signal_irq_tty0); 417 xicu->p_hwi[5] (signal_irq_tty1); 418 xicu->p_hwi[6] (signal_irq_tty2); 419 xicu->p_hwi[7] (signal_irq_tty3); 420 421 xicu->p_hwi[8] (signal_irq_bdev); 422 } 423 424 // MEMC 425 memc->p_clk (this->p_clk); 426 memc->p_resetn (this->p_resetn); 427 memc->p_vci_ixr (signal_vci_xram); 428 memc->p_vci_tgt (signal_vci_tgt_d_memc); 429 memc->p_vci_ini (signal_vci_ini_c_memc); 430 memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); 431 432 // XRAM 433 xram->p_clk (this->p_clk); 434 xram->p_resetn (this->p_resetn); 435 xram->p_vci (signal_vci_xram); 436 437 // CDMA 438 mdma->p_clk (this->p_clk); 439 mdma->p_resetn (this->p_resetn); 440 mdma->p_vci_target (signal_vci_tgt_d_mdma); 441 mdma->p_vci_initiator (signal_vci_ini_d_mdma); 442 for (size_t p = 0; p < nprocs; p++){ 443 mdma->p_irq[p] (signal_irq_mdma[p]); 444 } 445 446 // Components in IO cluster 447 448 if (io){ 449 // BDEV 450 bdev->p_clk (this->p_clk); 451 bdev->p_resetn (this->p_resetn); 452 bdev->p_irq (signal_irq_bdev); 453 bdev->p_vci_target (signal_vci_tgt_d_bdev); 454 bdev->p_vci_initiator (signal_vci_ini_d_bdev); 455 456 // FBUF 457 fbuf->p_clk (this->p_clk); 458 fbuf->p_resetn (this->p_resetn); 459 fbuf->p_vci (signal_vci_tgt_d_fbuf); 460 461 // BROM 462 brom->p_clk (this->p_clk); 463 brom->p_resetn (this->p_resetn); 464 brom->p_vci (signal_vci_tgt_d_brom); 465 466 // MTTY 467 mtty->p_clk (this->p_clk); 468 mtty->p_resetn (this->p_resetn); 469 mtty->p_vci (signal_vci_tgt_d_mtty); 470 mtty->p_irq[0] (signal_irq_tty0); 471 mtty->p_irq[1] (signal_irq_tty1); 472 mtty->p_irq[2] (signal_irq_tty2); 473 mtty->p_irq[3] (signal_irq_tty3); 474 } 475 } // end constructor 306 vect_names); 307 } 308 309 std::cout << std::endl; 310 311 //////////////////////////////////// 312 // Connections are defined here 313 //////////////////////////////////// 314 315 // CMDROUTER and RSPROUTER 316 cmdrouter->p_clk (this->p_clk); 317 cmdrouter->p_resetn (this->p_resetn); 318 rsprouter->p_clk (this->p_clk); 319 rsprouter->p_resetn (this->p_resetn); 320 for (int x = 0; x < 2; x++) 321 { 322 for(int y = 0; y < 4; y++) 323 { 324 cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); 325 cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); 326 rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); 327 rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); 328 } 329 } 330 331 cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); 332 cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); 333 cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); 334 cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); 335 336 rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); 337 rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); 338 rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); 339 rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); 340 341 std::cout << " - CMD & RSP routers connected" << std::endl; 342 343 // VCI/DSPIN WRAPPERS 344 iniwrapperd->p_clk (this->p_clk); 345 iniwrapperd->p_resetn (this->p_resetn); 346 iniwrapperd->p_vci (signal_vci_l2g_d); 347 iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); 348 iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); 349 350 tgtwrapperd->p_clk (this->p_clk); 351 tgtwrapperd->p_resetn (this->p_resetn); 352 tgtwrapperd->p_vci (signal_vci_g2l_d); 353 tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); 354 tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); 355 356 iniwrapperc->p_clk (this->p_clk); 357 iniwrapperc->p_resetn (this->p_resetn); 358 iniwrapperc->p_vci (signal_vci_l2g_c); 359 iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); 360 iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); 361 362 tgtwrapperc->p_clk (this->p_clk); 363 tgtwrapperc->p_resetn (this->p_resetn); 364 tgtwrapperc->p_vci (signal_vci_g2l_c); 365 tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); 366 tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); 367 368 std::cout << " - VCI/DSPIN wrappers connected" << std::endl; 369 370 // CROSSBAR direct 371 xbard->p_clk (this->p_clk); 372 xbard->p_resetn (this->p_resetn); 373 xbard->p_initiator_to_up (signal_vci_l2g_d); 374 xbard->p_target_to_up (signal_vci_g2l_d); 375 376 xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); 377 xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); 378 xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); 379 380 xbard->p_to_initiator[nb_procs] (signal_vci_ini_d_mdma); 381 382 for (size_t p = 0; p < nb_procs; p++) 383 { 384 xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); 385 } 386 387 if ( io ) 388 { 389 xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); 390 xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); 391 xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); 392 xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); 393 394 xbard->p_to_initiator[nb_procs+1] (signal_vci_ini_d_bdev); 395 } 396 397 std::cout << " - Direct crossbar connected" << std::endl; 398 399 // CROSSBAR coherence 400 xbarc->p_clk (this->p_clk); 401 xbarc->p_resetn (this->p_resetn); 402 xbarc->p_initiator_to_up (signal_vci_l2g_c); 403 xbarc->p_target_to_up (signal_vci_g2l_c); 404 xbarc->p_to_initiator[nb_procs] (signal_vci_ini_c_memc); 405 xbarc->p_to_target[nb_procs] (signal_vci_tgt_c_memc); 406 for (size_t p = 0; p < nb_procs; p++) 407 { 408 xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); 409 xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); 410 } 411 412 std::cout << " - Coherence crossbar connected" << std::endl; 413 414 // Processors 415 for (size_t p = 0; p < nb_procs; p++) 416 { 417 proc[p]->p_clk (this->p_clk); 418 proc[p]->p_resetn (this->p_resetn); 419 proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); 420 proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); 421 proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); 422 proc[p]->p_irq[0] (signal_proc_it[p]); 423 for ( size_t j = 1 ; j < 6 ; j++) 424 { 425 proc[p]->p_irq[j] (signal_false); 426 } 427 } 428 429 std::cout << " - Processors connected" << std::endl; 430 431 // XICU 432 xicu->p_clk (this->p_clk); 433 xicu->p_resetn (this->p_resetn); 434 xicu->p_vci (signal_vci_tgt_d_xicu); 435 for ( size_t p=0 ; p<nb_procs ; p++) 436 { 437 xicu->p_irq[p] (signal_proc_it[p]); 438 } 439 for ( size_t i=0 ; i<32 ; i++) 440 { 441 if ( io ) // I/O cluster 442 { 443 if (i < 8) xicu->p_hwi[i] (signal_false); 444 else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]); 445 else if (i < 16) xicu->p_hwi[i] (signal_false); 446 else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]); 447 else if (i < 31) xicu->p_hwi[i] (signal_false); 448 else xicu->p_hwi[i] (signal_irq_bdev); 449 } 450 else // other clusters 451 { 452 if (i < 8) xicu->p_hwi[i] (signal_false); 453 else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]); 454 else xicu->p_hwi[i] (signal_false); 455 } 456 } 457 458 std::cout << " - XICU connected" << std::endl; 459 460 // MEMC 461 memc->p_clk (this->p_clk); 462 memc->p_resetn (this->p_resetn); 463 memc->p_vci_ixr (signal_vci_xram); 464 memc->p_vci_tgt (signal_vci_tgt_d_memc); 465 memc->p_vci_ini (signal_vci_ini_c_memc); 466 memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); 467 468 std::cout << " - MEMC connected" << std::endl; 469 470 // XRAM 471 xram->p_clk (this->p_clk); 472 xram->p_resetn (this->p_resetn); 473 xram->p_vci (signal_vci_xram); 474 475 std::cout << " - XRAM connected" << std::endl; 476 477 // CDMA 478 mdma->p_clk (this->p_clk); 479 mdma->p_resetn (this->p_resetn); 480 mdma->p_vci_target (signal_vci_tgt_d_mdma); 481 mdma->p_vci_initiator (signal_vci_ini_d_mdma); 482 for (size_t i=0 ; i<nb_dmas ; i++) 483 { 484 mdma->p_irq[i] (signal_irq_mdma[i]); 485 } 486 487 std::cout << " - MDMA connected" << std::endl; 488 489 // Components in I/O cluster 490 491 if ( io ) 492 { 493 // BDEV 494 bdev->p_clk (this->p_clk); 495 bdev->p_resetn (this->p_resetn); 496 bdev->p_irq (signal_irq_bdev); 497 bdev->p_vci_target (signal_vci_tgt_d_bdev); 498 bdev->p_vci_initiator (signal_vci_ini_d_bdev); 499 500 std::cout << " - BDEV connected" << std::endl; 501 502 // FBUF 503 fbuf->p_clk (this->p_clk); 504 fbuf->p_resetn (this->p_resetn); 505 fbuf->p_vci (signal_vci_tgt_d_fbuf); 506 507 std::cout << " - FBUF connected" << std::endl; 508 509 // BROM 510 brom->p_clk (this->p_clk); 511 brom->p_resetn (this->p_resetn); 512 brom->p_vci (signal_vci_tgt_d_brom); 513 514 std::cout << " - BROM connected" << std::endl; 515 516 // MTTY 517 mtty->p_clk (this->p_clk); 518 mtty->p_resetn (this->p_resetn); 519 mtty->p_vci (signal_vci_tgt_d_mtty); 520 for ( size_t i=0 ; i<nb_ttys ; i++ ) 521 { 522 mtty->p_irq[i] (signal_irq_mtty[i]); 523 } 524 525 std::cout << " - MTTY connected" << std::endl; 526 } 527 } // end constructor 476 528 477 529 /////////////////////////////////////////////////////////////////////////// … … 479 531 /////////////////////////////////////////////////////////////////////////// 480 532 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 481 533 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {} 482 534 483 535 }
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