Changeset 351 for branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu

Timestamp:

Apr 4, 2013, 2:36:54 PM (12 years ago)

Author:

joannou

Message:

Got rid of intermediate v5 version. _dspin_coherence versions changed to main version for v5. Changed components names and platforms to fit the new names

Location:

branches/v5/platforms/tsar_generic_mmu

Files:

• . (moved) (moved from branches/v5/platforms/tsar_generic_mmu_dspin_coherence)
• tsar_cluster_mmu/caba/metadata/tsar_cluster_mmu.sd (modified) (1 diff)
• tsar_cluster_mmu/caba/source/include/tsar_cluster_mmu.h (modified) (3 diffs)
• tsar_cluster_mmu/caba/source/src/tsar_cluster_mmu.cpp (modified) (6 diffs)

branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/metadata/tsar_cluster_mmu.sd

@@ -15 +15 @@
                 Uses('common:mapping_table'),
                 Uses('common:iss2'),
-                Uses('caba:vci_cc_vcache_wrapper_dspin_coherence', 
+                Uses('caba:vci_cc_vcache_wrapper', 
                      iss_t = 'common:gdb_iss', 
                      gdb_iss_t = 'common:mips32el'),
-                Uses('caba:vci_mem_cache_dspin_coherence'),
+                Uses('caba:vci_mem_cache'),
                 Uses('caba:vci_simple_ram'),
         Uses('caba:vci_xicu'),

branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/include/tsar_cluster_mmu.h

@@ -32 +32 @@
 #include "vci_framebuffer.h"
 #include "vci_multi_dma.h"
-#include "vci_mem_cache_dspin_coherence.h"
-#include "vci_cc_vcache_wrapper_dspin_coherence.h"
+#include "vci_mem_cache.h"
+#include "vci_cc_vcache_wrapper.h"
 
 namespace soclib {
@@ -128 +128 @@
                      size_t                             cluster,       // y + ymax*x
                      const soclib::common::MappingTable &mtd,          // direct mapping table
-                     const soclib::common::MappingTable &mtc,          // coherence mapping table
                      const soclib::common::MappingTable &mtx,          // xram mapping table
                      size_t                                 x_width,       // x field number of bits
                      size_t                                 y_width,       // y field number of bits
+                     size_t                                 l_width,       // l field number of bits
                      size_t                                 tgtid_memc,
                      size_t                                 tgtid_xicu,
@@ -150 +150 @@
                      size_t                             xfb,           // frame buffer pixels
                      size_t                             yfb,           // frame buffer lines
-                     char*                              disk_name,     // virtual disk name for BDEV
+                     char*                              disk_name,     // virtual disk for BDEV
                      size_t                             block_size,    // block size for BDEV
                      size_t                             nic_channels,  // number of channels

branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/src/tsar_cluster_mmu.cpp

@@ -42 +42 @@
          size_t                             cluster_id,
          const soclib::common::MappingTable &mtd,
-         const soclib::common::MappingTable &mtc, 
          const soclib::common::MappingTable &mtx, 
          size_t                             x_width,
          size_t                             y_width,
+         size_t                             l_width,
          size_t                             tgtid_memc,
          size_t                             tgtid_xicu,
@@ -106 +106 @@
                       cluster_id*nb_procs + p,
                       mtd,                            // Mapping Table Direct
-                      mtc,                            // Mapping Table Coherence
                       IntTab(cluster_id,p),           // SRCID_D
-                      IntTab(cluster_id,p),           // SRCID_C
-                      IntTab(cluster_id,p),           // TGTID_C
+                      (cluster_id << l_width) + p,    // CC_GLOBAL_ID
                       8,                              // ITLB ways
                       8,                              // ITLB sets
@@ -120 +118 @@
                       x_width,
                       y_width,
-                      nb_procs,                       // MEMC local index
                       frozen_cycles,                  // max frozen cycles
                       debug_start_cycle,
@@ -132 +129 @@
     memc = new VciMemCache<vci_param>(
                      smemc.str().c_str(),
-                     mtd, mtc, mtx,
+                     mtd, mtx,
                      IntTab(cluster_id),              // SRCID_X
-                     IntTab(cluster_id, nb_procs),    // SRCID_C
                      IntTab(cluster_id, tgtid_memc),  // TGTID_D
-                     IntTab(cluster_id, nb_procs),    // TGTID_C
+                     (cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
                      memc_ways, memc_sets, 16,        // CACHE SIZE
-                     //4096,                            // HEAP SIZE
+                     3,                                  // MAX NUMBER OF COPIES
                      256,                            // HEAP SIZE
                      8,                               // TRANSACTION TABLE DEPTH
@@ -205 +201 @@
     sc << "ringc_" << x_id << "_" << y_id;
         //ringc = new soclib::caba::DspinLocalRingFastC<vci_param, 40, 33>(sc.str().c_str(),mtc, IntTab(cluster_id), 2, 2, 2, nb_procs + 1, x_width, y_width);
-        ringc = new soclib::caba::DspinLocalRingFastC<vci_param, 40, 33>(sc.str().c_str(),mtc, IntTab(cluster_id), 2, 2, 1, nb_procs, x_width, y_width);
+        //
+   // coherence network
+   // - tgtid_c_proc = srcid_c_proc = local procid
+   // - tgtid_c_memc = srcid_c_memc = NB_PROCS_MAX
+#define address_width         32
+#define srcid_width           14
+#include "../../../../giet_vm/hard_config.h"
+#define cluster(x,y)   (y + CLUSTER_Y*x)
+   MappingTable maptabc(address_width, 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         0x00FF0000);
+
+   for (size_t x = 0; x < CLUSTER_X; x++)
+   {
+      for (size_t y = 0; y < CLUSTER_Y; y++)
+      {
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+         // cleanup requests must be routed to the memory cache
+         std::ostringstream sh;
+         sh << "c_seg_memc_" << x << "_" << y;
+         maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset, 
+                     0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false));
+
+         // update & invalidate requests must be routed to the proper processor
+         for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++) 
+         {
+            std::ostringstream sp;
+            sp << "c_seg_proc_" << x << "_" << y << "_" << p;
+            maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , 
+                         0x10 , IntTab(cluster(x,y), p) , false)); 
+         }
+      }
+   }
+   std::cout << maptabc << std::endl;
+        //
+        //
+        //
+        ringc = new soclib::caba::DspinLocalRingFastC<vci_param, 40, 33>(sc.str().c_str(),maptabc, IntTab(cluster_id), 2, 2, 1, nb_procs, x_width, y_width);
 
     std::cout << "  - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
@@ -405 +440 @@
         proc[p]->p_clk                      (this->p_clk);
         proc[p]->p_resetn                   (this->p_resetn);
-        proc[p]->p_vci_ini_d                (signal_vci_ini_d_proc[p]);
+        proc[p]->p_vci                      (signal_vci_ini_d_proc[p]);
         proc[p]->p_dspin_in                 (signal_dspin_c_to_proc[p]);
         proc[p]->p_dspin_out                (signal_dspin_c_from_proc[p]);