Changeset 477 for branches/RWT

Timestamp:

Jul 26, 2013, 5:03:12 PM (11 years ago)

Author:

lgarcia

Message:

Reintroducing RWT branch merging the last modifications of the
trunk (CLACK channel)
WARNING: bugs remaining (with 1c16p and small caches (L2:16*16; L1:4*4))

Location:

branches/RWT

Files:

• . (added)
• communication (added)
• communication/dspin_dhccp_param (copied) (copied from trunk/communication/dspin_dhccp_param)
• communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h (modified) (5 diffs)
• lib (added)
• lib/generic_cache_tsar (copied) (copied from trunk/lib/generic_cache_tsar)
• lib/generic_cache_tsar/include/generic_cache.h (modified) (30 diffs)
• modules (added)
• modules/vci_cc_vcache_wrapper (copied) (copied from trunk/modules/vci_cc_vcache_wrapper)
• modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (modified) (16 diffs)
• modules/vci_cc_vcache_wrapper/caba/source/src (copied) (copied from trunk/modules/vci_cc_vcache_wrapper/caba/source/src)
• modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (119 diffs)
• modules/vci_mem_cache (copied) (copied from trunk/modules/vci_mem_cache)
• modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (modified) (6 diffs)
• modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (modified) (17 diffs)
• modules/vci_mem_cache/caba/source/include/xram_transaction.h (modified) (1 diff)
• modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (168 diffs)

branches/RWT/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h

@@ -41 +41 @@
  *
  * flit 1
- * ----------------------------------------------------------------------------------------------
- * EOP:0 |    DEST    |   SRCID   | NLINE MSB(2 bits)| X | WAY_INDEX(2 bits) | TYPE:0b1X | BC:0
- *       |  (10 bits) | (14 bits) |                  |   |                   |           |
- * ----------------------------------------------------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------
+ * EOP:0 |    DEST    |   SRCID   | NLINE MSB(2 bits)| CONTAINS_DATA | WAY_INDEX(2 bits) | TYPE:0b1X | BC:0
+ *       |  (10 bits) | (14 bits) |                  |               |                   |           |
+ * --------------------------------------------------------------------------------------------------------
  *                                                                                 | X: 0 DATA  |
  *                                                                                 |    1 INST  |
  * flit 2
  * ----------------------------------------------------------------------------------------------
- * EOP:1 |                                                                         NLINE(32 bits)
+ * EOP:0/1 |                                                                       NLINE(32 bits)
+ * ----------------------------------------------------------------------------------------------
+ *
+ * flit N for data
+ * ----------------------------------------------------------------------------------------------
+ * EOP:0/1 |                                                                       WDATA(32 bits)
  * ----------------------------------------------------------------------------------------------
  *
@@ -175 +180 @@
     static const uint8_t  CLEANUP_NLINE_LSB_SHIFT      = 0;
     static const uint64_t CLEANUP_NLINE_LSB_MASK       = ((1ULL<<32)-1);
+    static const uint8_t  CLEANUP_DATA_UPDT_SHIFT      = 0;
+    static const uint64_t CLEANUP_DATA_UPDT_MASK       = ((1ULL<<32)-1);
+    static const uint8_t  CLEANUP_NCC_SHIFT  = 5;
+    static const uint64_t CLEANUP_NCC_MASK   = 1;
 
     static const uint8_t  MULTI_ACK_DEST_SHIFT         = CLEANUP_DEST_SHIFT;
@@ -277 +286 @@
       CLEANUP_WAY_INDEX,
       CLEANUP_NLINE_LSB,
+      CLEANUP_DATA_UPDT,
+      CLEANUP_NCC,
 
       MULTI_ACK_DEST,
@@ -321 +332 @@
         GET_FIELD(flit,CLEANUP_WAY_INDEX);
         GET_FIELD(flit,CLEANUP_NLINE_LSB);
+        GET_FIELD(flit,CLEANUP_DATA_UPDT);
+        GET_FIELD(flit,CLEANUP_NCC);
         GET_FIELD(flit,MULTI_ACK_DEST);
         GET_FIELD(flit,MULTI_ACK_UPDT_INDEX);
@@ -361 +374 @@
         SET_FIELD(flit,value,CLEANUP_WAY_INDEX);
         SET_FIELD(flit,value,CLEANUP_NLINE_LSB);
+        SET_FIELD(flit,value,CLEANUP_DATA_UPDT);
+        SET_FIELD(flit,value,CLEANUP_NCC);
         SET_FIELD(flit,value,MULTI_ACK_DEST);
         SET_FIELD(flit,value,MULTI_ACK_UPDT_INDEX);

branches/RWT/lib/generic_cache_tsar/include/generic_cache.h

@@ -76 +76 @@
 {
     CACHE_SLOT_STATE_EMPTY,
-    CACHE_SLOT_STATE_VALID,
+    CACHE_SLOT_STATE_VALID_CC,
     CACHE_SLOT_STATE_ZOMBI,
+    CACHE_SLOT_STATE_VALID_NCC,
 };
 
@@ -118 +119 @@
         return r_lru[(way*m_sets)+set];
     }
-
+    
     //////////////////////////////////////////////
     inline int &cache_state(size_t way, size_t set)
@@ -125 +126 @@
     }
 
+    
     /////////////////////////////////////////////////
     inline void cache_set_lru(size_t way, size_t set)
@@ -218 +220 @@
     }
 
+    inline int get_cache_state(int way, int set)
+    {
+        return cache_state(way,set);
+    }
+    
     /////////////////////////////////////////////////////////////////////
     // Read a single 32 bits word.
@@ -233 +240 @@
         {
             if ( (tag == cache_tag(way, set))  
-                   && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) )
+                   && ( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)) )
             {
                 *dt = cache_data(way, set, word);
@@ -262 +269 @@
         {
             if ( (tag == cache_tag(way, set)) and
-                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) )
+                 ( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)))
             {
                 *selway  = way;
@@ -308 +315 @@
             {
 
-                if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID )
+                if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC )
                 {
-                    *state   = CACHE_SLOT_STATE_VALID;
+                    *state   = CACHE_SLOT_STATE_VALID_CC;
+                    *selway  = way;
+                    *selset  = set;
+                    *selword = word;
+                    *dt      = cache_data(way, set, word);
+                    cache_set_lru(way, set);
+                }
+                else if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC )
+                {
+                    *state   = CACHE_SLOT_STATE_VALID_NCC;
                     *selway  = way;
                     *selset  = set;
@@ -347 +363 @@
         {
             if ( (tag == cache_tag(way, set))  
-                   && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) )
+                   && ( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC) ) )
             {
                 *selway  = way;
@@ -382 +398 @@
         {
             if ( (tag == cache_tag(way, set))   
-                   && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+                   &&( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) ) 
             {
                 *dt      = cache_data(way, set, word);
@@ -433 +449 @@
             {
 
-                if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID )
+                if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC )
                 {
-                    *state   = CACHE_SLOT_STATE_VALID;
+                    *state   = CACHE_SLOT_STATE_VALID_CC;
                     *selway  = way;
                     *selset  = set;
@@ -446 +462 @@
                     cache_set_lru(way, set);
                 }
+
+                else if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC )
+                {
+                    *state   = CACHE_SLOT_STATE_VALID_NCC;
+                    *selway  = way;
+                    *selset  = set;
+                    *selword = word;
+                    *dt      = cache_data(way, set, word);
+                    if ( word+1 < m_words) 
+                    {
+                        *dt_next = cache_data(way, set, word+1);
+                    }
+                    cache_set_lru(way, set);
+                }
+
                 else if ( cache_state(way, set) == CACHE_SLOT_STATE_ZOMBI )
                 {
@@ -477 +508 @@
         {
             if ( (tag == cache_tag(way, set)) 
-                   && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+                   && ( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)or(cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC) ) ) 
             {
                 *selway  = way;
@@ -509 +540 @@
         const size_t      ad_set  = m_y[ad];
         const size_t      ad_word = m_x[ad];
-
         for ( size_t _way = 0; _way < m_ways; _way++ ) 
         {
@@ -556 +586 @@
                       data_t    data)
     {
+       /**/ //std::cout << "write cache : way = "<<way<<" | set = "<<set<<" | word = "<<word<<" | data = "<<(uint32_t)data << std::endl;
         cache_data(way, set, word) = data;
         cache_set_lru(way, set);
@@ -584 +615 @@
                       addr_t*   nline)
     {
-        if ( cache_state(way,set) == CACHE_SLOT_STATE_VALID ) 
+        if( (cache_state(way,set) == CACHE_SLOT_STATE_VALID_CC) or  (cache_state(way,set) == CACHE_SLOT_STATE_VALID_NCC))
         {
             cache_state(way,set) = CACHE_SLOT_STATE_EMPTY;
@@ -615 +646 @@
         for ( size_t _way = 0 ; _way < m_ways && !found ; _way++ )
         {
-            if ( cache_state(_way, *set) != CACHE_SLOT_STATE_VALID )  // empty
+            if( ( cache_state(_way, *set) != CACHE_SLOT_STATE_VALID_CC ) and ( cache_state(_way, *set) != CACHE_SLOT_STATE_VALID_NCC ))  // empty
             {
                 found   = true;
@@ -674 +705 @@
             }
         }
+        //////////////////////////////////////////////////////////////
+        /*for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ )
+        {
+            if ( not cache_lru(_way, _set) and 
+                 (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI) and
+                 (cache_state(_way, _set) == CACHE_SLOT_STATE_VALID_NCC) )
+            {
+                *found   = true;
+                *cleanup = true;
+                *way     = _way;
+                *set     = m_y[ad];
+                *victim  = (addr_t)((cache_tag(*way,_set) * m_sets) + _set);
+                return;
+            }
+        }*/
         // Search first not zombi old slot 
         for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ )
@@ -718 +764 @@
 
         cache_tag(way, set)   = tag;
-        cache_state(way, set) = CACHE_SLOT_STATE_VALID;
+        cache_state(way, set) = CACHE_SLOT_STATE_VALID_CC;
         cache_set_lru(way, set);
     }
@@ -733 +779 @@
         addr_t  tag     = m_z[ad];
 
-        assert( ( (state == CACHE_SLOT_STATE_VALID) or 
+        assert( ( (state == CACHE_SLOT_STATE_VALID_CC) or
+                  (state == CACHE_SLOT_STATE_VALID_NCC) or
                   (state == CACHE_SLOT_STATE_ZOMBI) or
                   (state == CACHE_SLOT_STATE_EMPTY) ) and
@@ -747 +794 @@
         cache_state(way, set) = state;
 
-        if ( state == CACHE_SLOT_STATE_VALID ) cache_set_lru(way, set);
+        if ( (state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC) ) cache_set_lru(way, set);
     }
 
@@ -759 +806 @@
                            int      state)
     {
-        assert( ( (state == CACHE_SLOT_STATE_VALID) or 
+        assert( ( (state == CACHE_SLOT_STATE_VALID_CC) or
+                  (state == CACHE_SLOT_STATE_VALID_NCC) or
                   (state == CACHE_SLOT_STATE_ZOMBI) or
                   (state == CACHE_SLOT_STATE_EMPTY) ) and
@@ -772 +820 @@
         cache_state(way, set) = state;
 
-        if ( state == CACHE_SLOT_STATE_VALID ) cache_set_lru(way, set);
+        if ( (state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC) ) cache_set_lru(way, set);
     }
 
@@ -788 +836 @@
 
         cache_tag(way, set)   = tag;
-        cache_state(way, set) = CACHE_SLOT_STATE_VALID;
+        cache_state(way, set) = CACHE_SLOT_STATE_VALID_CC;
         cache_set_lru(way, set);
         for ( size_t word = 0 ; word < m_words ; word++ ) 
@@ -835 +883 @@
                     std::cout << " | " << cache_data(way,set,word) ;
                 }
-                std::cout << std::endl ;
+                std::cout << std::dec << std::endl ;
             }
         }
@@ -853 +901 @@
         {
             if ( (tag == cache_tag(way, set)) and
-                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 
             {
                 hit                   = true;
@@ -878 +926 @@
         {
             if ( (tag == cache_tag(way, set)) and 
-                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 
             {
                 hit                   = true;
@@ -923 +971 @@
         {
             if ( (tag == cache_tag(way, set)) and
-                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 
             {
                 cache_data(way, set, word) = dt;
@@ -948 +996 @@
         {
             if ( (tag == cache_tag(way, set)) and 
-                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 
             {
                 data_t mask = be2mask(be);
@@ -975 +1023 @@
         {
             if ( (tag == cache_tag(way, set)) and
-                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 
             {
                 cache_data(way, set, word) = dt;
@@ -1002 +1050 @@
         {
             if ( (tag == cache_tag(way, set)) and 
-                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 
             {
                 data_t mask = be2mask(be);

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -115 +115 @@
         DCACHE_XTN_IT_INVAL,
         DCACHE_XTN_DC_FLUSH,
+        DCACHE_XTN_DC_FLUSH_DATA,
         DCACHE_XTN_DC_FLUSH_GO,
         DCACHE_XTN_DC_INVAL_VA,
@@ -120 +121 @@
         DCACHE_XTN_DC_INVAL_END,
         DCACHE_XTN_DC_INVAL_GO,
+        DCACHE_XTN_DC_INVAL_DATA,
         DCACHE_XTN_DT_INVAL,
         //handling dirty bit update
@@ -127 +129 @@
         DCACHE_MISS_SELECT,
         DCACHE_MISS_CLEAN,
+        DCACHE_MISS_DATA,
         DCACHE_MISS_WAIT,
         DCACHE_MISS_DATA_UPDT,
@@ -138 +141 @@
         DCACHE_CC_UPDT,
         DCACHE_CC_INVAL,
+        DCACHE_CC_INVAL_DATA,
         // handling TLB inval (after a coherence or XTN request)
         DCACHE_INVAL_TLB_SCAN,
@@ -188 +192 @@
         CC_SEND_CLEANUP_1,
         CC_SEND_CLEANUP_2,
+        CC_SEND_CLEANUP_DATA_UPDT,
         CC_SEND_MULTI_ACK,
     };
@@ -283 +288 @@
         TYPE_INS_MISS     = 0x3,
     };
+
+    //////////////////MODIFIED////////////////
+    enum content_line_cache_status_e
+    {
+        LINE_CACHE_DATA_NOT_DIRTY,
+        LINE_CACHE_DATA_DIRTY,
+        LINE_CACHE_IN_TLB,
+        LINE_CACHE_CONTAINS_PTD,
+    };
+    //////////////////////////////////////////
 
 public:
@@ -390 +405 @@
     // communication between ICACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
-    sc_signal<cc_send_t>    r_icache_cc_send_type;          // ICACHE cc_send request type
+    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
     sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
     sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
@@ -429 +444 @@
     sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
 
+    //RWT: local cas
+    sc_signal<bool>         r_cas_islocal;
+    sc_signal<size_t>       r_cas_local_way;
+    sc_signal<size_t>       r_cas_local_set;
+    sc_signal<size_t>       r_cas_local_word;
+
     // register used for XTN inval
     sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
@@ -447 +468 @@
     sc_signal<size_t>       r_dcache_cc_way;                // selected way for cc update/inval
     sc_signal<size_t>       r_dcache_cc_set;                // selected set for cc update/inval
+    sc_signal<int>          r_dcache_cc_state;          // state of selected cache slot
     sc_signal<size_t>       r_dcache_cc_word;               // word counter for cc update
     sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
+    sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
+    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt;  
 
     // coherence clack handling
@@ -483 +507 @@
     // communication between DCACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
-    sc_signal<cc_send_t>    r_dcache_cc_send_type;          // DCACHE cc_send request type
+    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
     sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
     sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
     sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
-
+    
+    // special registers for ODCCP/RWT
+    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
+    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;          // Register for cleanup with data (wb updt)
+    sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
+    sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
+    sc_signal<bool>         r_dcache_dirty_save;             
+    sc_signal<uint32_t>     r_cc_send_cpt_word;
+    sc_signal<uint32_t>     r_dcache_miss_data_cpt;
+    sc_signal<paddr_t>      r_dcache_miss_data_addr;
+    sc_signal<uint32_t>     r_dcache_xtn_flush_data_cpt;
+    sc_signal<paddr_t>      r_dcache_xtn_flush_addr_data;
+    sc_signal<int>          r_dcache_xtn_state;
+    sc_signal<paddr_t>      r_dcache_xtn_data_addr;
+    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
     // dcache directory extension
-    bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
-    bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
-
+    ///////////////////////////MODIFIED///////////////////////////////////////////////////
+    //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
+    //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
+    int                     *r_dcache_content_state;    // content state of one cache line
+    int                     *r_dcache_dirty_word;    // content state of one cache line
+    //////////////////////////////////////////////////////////////////////////////////////
+
+    //RWT
+    sc_signal<bool>         r_dcache_read_state;
+   
+     ///////////////////////////////////
     // Physical address extension for data access
     sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
@@ -513 +559 @@
     GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;              // response FIFO to ICACHE FSM
     GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;              // response FIFO to DCACHE FSM
+    
+
+    //RWT
+    GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
+
+    GenericFifo<uint32_t>   r_cc_send_data_fifo;   
 
     ///////////////////////////////////
@@ -534 +586 @@
     // communication between CC_RECEIVE FSM and ICACHE FSM
     sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
-    sc_signal<cc_receive_t> r_cc_receive_icache_type;       // cc_receive type of request
+    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
     sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
     sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
@@ -542 +594 @@
     // communication between CC_RECEIVE FSM and DCACHE FSM
     sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
-    sc_signal<cc_receive_t> r_cc_receive_dcache_type;       // cc_receive type of request
+    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
     sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
     sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
@@ -593 +645 @@
     uint32_t m_cpt_data_read;               // total number of read data
     uint32_t m_cpt_data_write;              // total number of write data
+    uint32_t m_cpt_data_write_back;
+    uint32_t m_cpt_data_cleanup;
+    uint32_t m_cpt_data_sc;
     uint32_t m_cpt_data_miss;               // number of read miss
     uint32_t m_cpt_ins_miss;                // number of instruction miss
@@ -608 +663 @@
     uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
     uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_dunc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_ll_transaction;         // number of VCI uncached read transactions
     uint32_t m_cpt_write_transaction;       // number of VCI write transactions
     uint32_t m_cpt_icache_unc_transaction;
@@ -673 +730 @@
     uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
     uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
+    uint32_t m_cpt_cleanup_data_not_dirty;
+    uint32_t m_cpt_cleanup_data_dirty_word;
 
     uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -35 +35 @@
 #define DEBUG_ICACHE            1
 #define DEBUG_CMD               0
+#define INSTRUMENTATION     1
 
 namespace soclib {
@@ -87 +88 @@
         "DCACHE_XTN_IT_INVAL",
         "DCACHE_XTN_DC_FLUSH",
+        "DCACHE_XTN_DC_FLUSH_DATA",
         "DCACHE_XTN_DC_FLUSH_GO",
         "DCACHE_XTN_DC_INVAL_VA",
@@ -92 +94 @@
         "DCACHE_XTN_DC_INVAL_END",
         "DCACHE_XTN_DC_INVAL_GO",
+        "DCACHE_XTN_DC_INVAL_DATA",
         "DCACHE_XTN_DT_INVAL",
 
@@ -99 +102 @@
         "DCACHE_MISS_SELECT",
         "DCACHE_MISS_CLEAN",
+        "DCACHE_MISS_DATA",
         "DCACHE_MISS_WAIT",
         "DCACHE_MISS_DATA_UPDT",
@@ -110 +114 @@
         "DCACHE_CC_UPDT",
         "DCACHE_CC_INVAL",
+        "DCACHE_CC_INVAL_DATA",
 
         "DCACHE_INVAL_TLB_SCAN",
@@ -174 +179 @@
         "CC_SEND_CLEANUP_1",
         "CC_SEND_CLEANUP_2",
+        "CC_SEND_CLEANUP_DATA_UPDT",
         "CC_SEND_MULTI_ACK",
     };
@@ -367 +373 @@
       r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2),        // 2 words depth
       r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2),        // 2 words depth
+      r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2),    // 2 words depth
+      r_cc_send_data_fifo("r_cc_send_data_fifo", 2),
 
       r_cc_send_fsm("r_cc_send_fsm"),
@@ -424 +432 @@
     r_mmu_release = (uint32_t)(1 << 16) | 0x1;
 
-    r_dcache_in_tlb       = new bool[dcache_ways*dcache_sets];
-    r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
+    ////////////////////MODIFIED///////////////////////////////
+    //r_dcache_in_tlb        = new bool[dcache_ways*dcache_sets];
+    //r_dcache_contains_ptd  = new bool[dcache_ways*dcache_sets];
+    r_dcache_content_state = new int [dcache_ways*dcache_sets];
+    r_dcache_dirty_word    = new int [dcache_ways*dcache_sets*dcache_words];
+    ///////////////////////////////////////////////////////////
+
 
     SC_METHOD(transition);
@@ -450 +463 @@
 /////////////////////////////////////
 {
-    delete [] r_dcache_in_tlb;
-    delete [] r_dcache_contains_ptd;
+    ////////////MODIFIED/////////////
+    //delete [] r_dcache_in_tlb;
+    //delete [] r_dcache_contains_ptd;
+    delete [] r_dcache_content_state;
+    delete [] r_dcache_dirty_word;
+    /////////////////////////////////
 }
 
@@ -472 +489 @@
     // b4 : dtlb trace
     // b5 : itlb trace
-
     std::cout << std::dec << "PROC " << name() << std::endl;
 
@@ -479 +495 @@
     std::cout << "  " << m_dreq << std::endl;
     std::cout << "  " << m_drsp << std::endl;
+
+    /**/std::cout << r_iss << std::endl;
 
     std::cout << "  " << icache_fsm_state_str[r_icache_fsm.read()]
@@ -562 +580 @@
 }
 
-/*
+
 ////////////////////////
 tmpl(void)::print_stats()
@@ -569 +587 @@
     float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
     std::cout << name() << std::endl
-        << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl
-        << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl
-        << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
-        << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
-        << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
-        << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
-        << "- DATA MISS COST         = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
-        << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl
-        << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
-        << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
-        << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
-        << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
-        << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
-        << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
-        << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
-        << "- ITLB UPDATE ACC COST   = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
-        << "- DTLB UPDATE ACC COST   = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
-        << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
-        << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
-        << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
-        << "- DCACHE FROZEN BY ITLB  = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
-        << "- DCACHE FOR TLB %       = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
-        << "- NB CC BROADCAST        = " << m_cpt_cc_broadcast << std::endl
-        << "- NB CC UPDATE DATA      = " << m_cpt_cc_update_data << std::endl
-        << "- NB CC INVAL DATA       = " << m_cpt_cc_inval_data << std::endl
-        << "- NB CC INVAL INS        = " << m_cpt_cc_inval_ins << std::endl
-        << "- CC BROADCAST COST      = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
-        << "- CC UPDATE DATA COST    = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
-        << "- CC INVAL DATA COST     = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
-        << "- CC INVAL INS COST      = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
-        << "- NB CC CLEANUP DATA     = " << m_cpt_cc_cleanup_data << std::endl
-        << "- NB CC CLEANUP INS      = " << m_cpt_cc_cleanup_ins << std::endl
-        << "- IMISS TRANSACTION      = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
-        << "- DMISS TRANSACTION      = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
-        << "- UNC TRANSACTION        = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
-        << "- WRITE TRANSACTION      = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
-        << "- WRITE LENGTH           = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
-        << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
-        << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
+        << "- CPI                     = " << std::dec <<(float)m_cpt_total_cycles/run_cycles << std::endl
+        << "- READ RATE               = " << (float)m_cpt_data_read/run_cycles << std::endl
+        << "- WRITE RATE              = " << (float)m_cpt_data_write/run_cycles << std::endl
+        << "- IMISS_RATE              = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
+        << "- DMISS RATE              = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl
+        << "- INS MISS COST           = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
+        << "- DATA MISS COST          = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
+        << "- WRITE COST              = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl
+        << "- UNC COST                = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+        << "- UNCACHED READ RATE      = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl
+        << "- CACHED WRITE RATE       = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl
+        << "- INS TLB MISS RATE       = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+        << "- DATA TLB MISS RATE      = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+        << "- ITLB MISS COST          = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
+        << "- DTLB MISS COST          = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
+        << "- ITLB UPDATE ACC COST    = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
+        << "- DTLB UPDATE ACC COST    = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
+        << "- DTLB UPDATE DIRTY COST  = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
+        << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
+        << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
+        //<< "- DCACHE FROZEN BY ITLB   = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
+        << "- DCACHE FOR TLB %        = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
+        << "- NB CC BROADCAST         = " << m_cpt_cc_broadcast << std::endl
+        << "- NB CC UPDATE DATA       = " << m_cpt_cc_update_dcache << std::endl
+        << "- NB CC INVAL DATA        = " << m_cpt_cc_inval_dcache << std::endl
+        << "- NB CC INVAL INS         = " << m_cpt_cc_inval_icache << std::endl
+        << "- CC BROADCAST COST       = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
+        << "- CC UPDATE DATA COST     = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache << std::endl
+        << "- CC INVAL DATA COST      = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache << std::endl
+        << "- CC INVAL INS COST       = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache << std::endl
+        << "- NB CC CLEANUP DATA      = " << m_cpt_cc_cleanup_data << std::endl
+        << "- NB CC CLEANUP INS       = " << m_cpt_cc_cleanup_ins << std::endl
+        << "- IMISS TRANSACTION       = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+        << "- DMISS TRANSACTION       = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+        << "- UNC TRANSACTION         = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+        << "- WRITE TRANSACTION       = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+        << "- NB WRITE TRANSACTION    = " << m_cpt_write_transaction << std::endl
+        << "- NB WRITE WORDS VCI      = " << m_length_write_transaction << std::endl
+        << "- NB WRITE PROC           = " << m_cpt_data_write << std::endl
+        << "- NB WRITE BACK           = " << m_cpt_data_write_back << std::endl
+        << "- NB WRITE BACK COHERENCE = " << m_cpt_data_cleanup << std::endl
+        << "- NB DATA SC              = " << m_cpt_data_sc << std::endl
+        << "- WRITE LENGTH            = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+        << "- ITLB MISS TRANSACTION   = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+        << "- DTLB MISS TRANSACTION   = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
+
+        << "- DMISS TRANSACTION       = " << m_cpt_dmiss_transaction << std::endl
+        << "- DUNC TRANSACTION        = " << m_cpt_dunc_transaction << std::endl
+        << "- LL TRANSACTION          = " << m_cpt_ll_transaction << std::endl
+        << "- CLEANUP DATA NOT DIRTY  = " << m_cpt_cleanup_data_not_dirty << std::endl
+        << "- CLEANUP DATA DIRTY WORD = " << m_cpt_cleanup_data_dirty_word << std::endl;
 }
 
@@ -624 +654 @@
 
     m_cpt_frz_cycles        = 0;
-    m_cpt_dcache_frz_cycles = 0;
+//    m_cpt_dcache_frz_cycles = 0;
     m_cpt_total_cycles      = 0;
 
-    m_cpt_read         = 0;
-    m_cpt_write        = 0;
+//    m_cpt_read         = 0;
+//    m_cpt_write        = 0;
     m_cpt_data_miss    = 0;
     m_cpt_ins_miss     = 0;
@@ -692 +722 @@
     m_cost_dtlb_sc_dirty_transaction = 0;
 
-    m_cpt_cc_update_data = 0;
-    m_cpt_cc_inval_ins   = 0;
-    m_cpt_cc_inval_data  = 0;
+//    m_cpt_cc_update_data = 0;
+//    m_cpt_cc_inval_ins   = 0;
+//    m_cpt_cc_inval_data  = 0;
     m_cpt_cc_broadcast   = 0;
 
@@ -704 +734 @@
     m_cpt_cc_cleanup_data = 0;
     m_cpt_cc_cleanup_ins  = 0;
+
+    m_cpt_cleanup_data_not_dirty  = 0;
+    m_cpt_cleanup_data_dirty_word = 0;
+
 }
 
-*/
+
 
 /////////////////////////
@@ -734 +768 @@
         for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
         {
-            r_dcache_in_tlb[i]       = false;
-            r_dcache_contains_ptd[i] = false;
+            // MODIFIED
+            //r_dcache_in_tlb[i]        = false;
+            //r_dcache_contains_ptd[i]  = false;
+            r_dcache_content_state[i] = LINE_CACHE_DATA_NOT_DIRTY;
+            r_dcache_dirty_word[i] = 0;
         }
 
@@ -741 +778 @@
         r_vci_rsp_fifo_icache.init();
         r_vci_rsp_fifo_dcache.init();
+        r_cc_send_data_fifo.init();
 
         // ICACHE & DCACHE activated
@@ -805 +843 @@
         m_debug_previous_d_hit     = false;
         m_debug_activated              = false;
+
+        // SPECIAL REGISTERS ODCCP
+        r_dcache_cc_cleanup_updt_data = false;
+        r_dcache_cc_cleanup_line_ncc  = false;
+        r_dcache_miss_victim_no_coherence = false;
+        r_dcache_line_no_coherence = false;
+        r_cc_send_cpt_word = 0;
+        r_dcache_miss_data_cpt = 0;
+        r_dcache_miss_data_addr = 0;
 
         // activity counters
@@ -821 +868 @@
 
         m_cpt_data_miss         = 0;
+        m_cpt_data_write        = 0;
+        m_cpt_data_sc           = 0;
+        m_cpt_data_write_back   = 0;
+        m_cpt_data_cleanup      = 0;
+        m_cpt_cleanup_data_not_dirty = 0; 
         m_cpt_ins_miss          = 0;
         m_cpt_unc_read          = 0;
@@ -879 +931 @@
             m_cpt_cc_cleanup_data = 0;
             m_cpt_cc_cleanup_ins  = 0;
+
+        m_cpt_cleanup_data_not_dirty  = 0;
+        m_cpt_cleanup_data_dirty_word = 0;
 
         m_cpt_itlbmiss_transaction      = 0;
@@ -926 +981 @@
     bool       vci_rsp_fifo_dcache_put   = false;
     uint32_t   vci_rsp_fifo_dcache_data  = 0;
+    bool       vci_rsp_fifo_rpktid_get   = false;
+    bool       vci_rsp_fifo_rpktid_put   = false;
+    bool       vci_rsp_fifo_rpktid       = false;
+
+    // FIFO for cleanup data updt
+    bool       cleanup_data_updt_fifo_dcache_get   = false;
+    bool       cleanup_data_updt_fifo_dcache_put   = false;
+    uint32_t   cleanup_data_updt_fifo_dcache_data  = 0;
 
     // updt fifo
@@ -935 +998 @@
 
 #ifdef INSTRUMENTATION
-    m_cpt_fsm_dcache  [r_dcache_fsm.read() ] ++;
-    m_cpt_fsm_icache  [r_icache_fsm.read() ] ++;
-    m_cpt_fsm_cmd     [r_vci_cmd_fsm.read()] ++;
-    m_cpt_fsm_rsp     [r_vci_rsp_fsm.read()] ++;
-    m_cpt_fsm_tgt     [r_tgt_fsm.read()    ] ++;
-    m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
+    m_cpt_fsm_dcache     [r_dcache_fsm.read()    ] ++;
+    m_cpt_fsm_icache     [r_icache_fsm.read()    ] ++;
+    m_cpt_fsm_cmd        [r_vci_cmd_fsm.read()   ] ++;
+    m_cpt_fsm_rsp        [r_vci_rsp_fsm.read()   ] ++;
+    m_cpt_fsm_cc_send    [r_cc_send_fsm.read()   ] ++;
+    m_cpt_fsm_cc_receive [r_cc_receive_fsm.read()] ++;
 #endif
 
@@ -1069 +1132 @@
                 else
                 {
-                                r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 |
+                                r_icache_vci_paddr = (uint64_t)r_mmu_word_hi.read() << 32 |
                                                          (paddr_t)r_mmu_word_lo.read();
                         }
@@ -1106 +1169 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_itlb_read++;
+m_cpt_ins_tlb_read++;
 #endif
                 tlb_hit = r_itlb.translate( m_ireq.addr,
@@ -1181 +1244 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_itlb_miss++;
+m_cpt_ins_tlb_miss++;
 #endif
                     r_icache_fsm          = ICACHE_TLB_WAIT;
@@ -1199 +1262 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_miss++;
+m_cpt_ins_miss++;
 #endif
                     // we request a VCI transaction
@@ -1340 +1403 @@
                                &state );
 
-            if ( state == CACHE_SLOT_STATE_VALID )    // inval required
+            if ( state == CACHE_SLOT_STATE_VALID_CC )    // inval required
             {
                 // request cleanup
@@ -1421 +1484 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_itlb_read++;
+m_cpt_ins_tlb_read++;
 #endif
             hit = r_itlb.translate(r_dcache_save_wdata.read(),
@@ -1441 +1504 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_itlb_miss++;
+m_cpt_ins_tlb_miss++;
 #endif
             r_icache_tlb_miss_req = true;
@@ -1468 +1531 @@
                           &word);
 
-        if ( state == CACHE_SLOT_STATE_VALID )  // inval to be done
+        if ( state == CACHE_SLOT_STATE_VALID_CC )       // inval to be done
         {
             r_icache_miss_way = way;
@@ -1751 +1814 @@
                                     r_icache_miss_way.read(),
                                     r_icache_miss_set.read(),
-                                    CACHE_SLOT_STATE_VALID );
+                                    CACHE_SLOT_STATE_VALID_CC );
 #if DEBUG_ICACHE
 if ( m_debug_activated )
@@ -1924 +1987 @@
         r_icache_cc_set = set;
 
-        if ( state == CACHE_SLOT_STATE_VALID)            // hit
+        if ( state == CACHE_SLOT_STATE_VALID_CC)            // hit
         {
             // need to update the cache state
@@ -2136 +2199 @@
     m_drsp.error = false;
     m_drsp.rdata = 0;
+    //if(m_cpt_total_cycles % 1000000 == 0 ) r_dcache.printTrace();
 
     switch ( r_dcache_fsm.read() )
@@ -2191 +2255 @@
         bool        wbuf_request       = false;     // request WBUF write in P1 stage
 
+
         // physical address computation : systematic DTLB access if activated)
         if ( m_dreq.valid )
@@ -2203 +2268 @@
                                             &tlb_set );
 #ifdef INSTRUMENTATION
-m_cpt_dtlb_read++;
+m_cpt_data_tlb_read++;
 #endif
             }
@@ -2211 +2276 @@
                 // we take into account the paddr extension
                 if (vci_param::N > 32) 
-                    paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
+                    paddr = paddr | ((uint64_t)(r_dcache_paddr_ext.read()) << 32);
             }
         } // end physical address computation
@@ -2268 +2333 @@
             size_t way = r_dcache_save_cache_way.read();
             size_t set = r_dcache_save_cache_set.read();
-
-            if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
+            // MODIFIED
+            //if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
+            //{
+            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
             {
                 tlb_inval_required       = true;
@@ -2275 +2342 @@
                     r_dcache_tlb_inval_line  = r_dcache_save_paddr.read()>>
                                            (uint32_log2(m_dcache_words<<2));
-                    r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-            }
-            else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
+                // MODIFIED RWT: DIRTY
+                    //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+            }
+            // MODIFIED
+            //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
+            //{
+            else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
             {
                 r_itlb.reset();
                 r_dtlb.reset();
-                    r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+                // MODIFIED
+                    //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             }
 
@@ -2312 +2386 @@
                                          r_dcache_save_wdata.read(),
                                          r_dcache_save_cacheable.read() );
-#ifdef INSTRUMENTATION
+/*#ifdef INSTRUMENTATION
 m_cpt_wbuf_write++;
-#endif
+#endif*/
                 if ( not wok ) // miss if write buffer full
                 {
@@ -2526 +2600 @@
                         else
                         {
-                            r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 |
+                            r_dcache_save_paddr = (uint64_t)r_mmu_word_hi.read() << 32 |
                                                   (paddr_t)r_mmu_word_lo.read();
                         }
@@ -2623 +2697 @@
                         if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
                         else cacheable = tlb_flags.c;
-
                         // access rights checking
                         if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
@@ -2693 +2766 @@
                             {
 #ifdef INSTRUMENTATION
-m_cpt_dcache_miss++;
-#endif
+m_cpt_data_miss++;
+#endif
+                                /*ODCCP*/
+                                //std::cout << "\t\t\t\t\tCACHE MISS NEED READ for : " << name() << std::endl;
                                 // request a VCI DMISS transaction
                                 r_dcache_vci_paddr    = paddr;
@@ -2723 +2798 @@
 m_cpt_data_read++;
 #endif
+                                /*if ((tlb_flags.s == 0) and (r_mmu_mode.read() & DATA_TLB_MASK) and (cache_state == CACHE_SLOT_STATE_VALID_CC))
+                                {
+                                    //ODCCP
+                                    std::cout << "READ NO COHERENCE on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | way = " << cache_way << " | set = " << cache_set << " | at cycle : "<< m_cpt_total_cycles << std::endl;
+                                    r_dcache.write_dir(cache_way,
+                                                       cache_set,
+                                                       CACHE_SLOT_STATE_VALID_NCC);
+                                }*/
                                 // returns data to processor
                                 m_drsp.valid   = true;
@@ -2765 +2848 @@
                         r_dcache_ll_rsp_count = 0;
                         r_dcache_fsm          = DCACHE_LL_WAIT;
+                        /*ODCCP*/
+                        //std::cout << "LL on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | at cycle : " << m_cpt_total_cycles << std::endl;
 
                     }// end LL
@@ -2806 +2891 @@
                             // response to processor
                             m_drsp.valid        = true;
-
                             // activating P1 stage
-                            wbuf_request = true;
-                            updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
+                            if( (cache_state != CACHE_SLOT_STATE_ZOMBI )&&(cache_state != CACHE_SLOT_STATE_EMPTY )&&(cacheable) )
+                            {
+                                wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC); //write to L2 only if CC
+                                updt_request = true;
+                                if (cache_state == CACHE_SLOT_STATE_VALID_NCC) 
+                                {
+                                    if (r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY)
+                                    {
+                                        r_dcache_content_state[cache_way*m_dcache_sets+cache_set] = LINE_CACHE_DATA_DIRTY;
+                                    }
+                                    r_dcache_dirty_word[(cache_way*m_dcache_sets +cache_set)*m_dcache_words+cache_word] = 1;//dirty bit with word granularity (only for stats)
+                                    m_cpt_data_write_back ++;
+                                }
+                            }
+                            else
+                            {
+                               wbuf_request = true;
+                               updt_request = false;
+                            }
                         }
                     } // end WRITE
@@ -2978 +3079 @@
 m_cpt_dcache_dir_read++;
 #endif
-        if ( cache_state == CACHE_SLOT_STATE_VALID )   // hit in dcache
+        /*ODCCP*/
+//        assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE1_GET : IMPOSSIBLE NCC HERE");
+//        if ( cache_state == CACHE_SLOT_STATE_VALID_CC )   // hit in dcache
+        if (( cache_state == CACHE_SLOT_STATE_VALID_NCC ) or ( cache_state == CACHE_SLOT_STATE_VALID_CC ))
         {
             if ( not (entry & PTE_V_MASK) )     // unmapped
@@ -3015 +3119 @@
             {
                 // mark the cache line ac containing a PTD
-                r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
+                //MODIFIED
+                //r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_CONTAINS_PTD;
 
                 // register bypass
@@ -3050 +3156 @@
             else                        //  PTE1 :  we must update the TLB
             {
-                r_dcache_in_tlb[m_icache_sets*way+set] = true;
+                // MODIFIED
+                //r_dcache_in_tlb[m_icache_sets*way+set] = true;
+                r_dcache_content_state[m_icache_sets*way+set] = LINE_CACHE_IN_TLB;
                 r_dcache_tlb_pte_flags  = entry;
                 r_dcache_tlb_cache_way  = way;
@@ -3108 +3216 @@
                            &set );
 #ifdef INSTRUMENTATION
-m_cpt_itlb_read++;
+m_cpt_ins_tlb_read++;
 #endif
         }
@@ -3118 +3226 @@
                            &set );
 #ifdef INSTRUMENTATION
-m_cpt_dtlb_read++;
+m_cpt_data_tlb_read++;
 #endif
         }
@@ -3194 +3302 @@
                               nline );
 #ifdef INSTRUMENTATION
-m_cpt_itlb_write++;
+m_cpt_ins_tlb_update_acc++;
 #endif
 
@@ -3218 +3326 @@
                               nline );
 #ifdef INSTRUMENTATION
-m_cpt_dtlb_write++;
+m_cpt_data_tlb_update_acc++;
 #endif
 
@@ -3268 +3376 @@
         }
 
-        uint32_t        pte_flags;
-        uint32_t        pte_ppn;
-        size_t          way;
-        size_t          set;
-        size_t          word;
-        int         cache_state;
+        uint32_t        pte_flags     = 0;
+        uint32_t        pte_ppn       = 0;
+        size_t          way           = 0;
+        size_t          set           = 0;
+        size_t          word          = 0;
+        int         cache_state   = 0;
 
         r_dcache.read( r_dcache_tlb_paddr.read(),
@@ -3286 +3394 @@
 m_cpt_dcache_dir_read++;
 #endif
-        if ( cache_state == CACHE_SLOT_STATE_VALID )   // hit in dcache
+        /*ODCCP*/
+//        assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE2_GET : IMPOSSIBLE NCC HERE");
+//        if (cache_state == CACHE_SLOT_STATE_VALID_CC)    // hit in dcache
+        if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or (cache_state == CACHE_SLOT_STATE_VALID_NCC))
         {
             if ( not (pte_flags & PTE_V_MASK) ) // unmapped
@@ -3318 +3429 @@
             else                                // mapped : we must update the TLB
             {
-                r_dcache_in_tlb[m_dcache_sets*way+set] = true;
+                // MODIFIED
+                //r_dcache_in_tlb[m_dcache_sets*way+set] = true;
+                r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_IN_TLB;
                 r_dcache_tlb_pte_flags  = pte_flags;
                 r_dcache_tlb_pte_ppn    = pte_ppn;
@@ -3383 +3496 @@
                            &set );
 #ifdef INSTRUMENTATION
-m_cpt_itlb_read++;
+m_cpt_ins_tlb_read++;
 #endif
         }
@@ -3393 +3506 @@
                            &set );
 #ifdef INSTRUMENTATION
-m_cpt_dtlb_read++;
+m_cpt_data_tlb_read++;
 #endif
         }
@@ -3435 +3548 @@
         // As long as this computation is not done, all access are local.
 
+        int  state;
+        size_t way;
+        size_t set;
+        size_t word;
+        r_dcache.read_dir(r_dcache_tlb_paddr.read(),
+                          &state,
+                          &way,
+                          &set,
+                          &word);
+        r_cas_islocal = (state == CACHE_SLOT_STATE_VALID_NCC);//do not check L2 if NCC: the CAS is necessarily a success
+        r_cas_local_way = way;
+        r_cas_local_set = set;
+        r_cas_local_word = word;
+
         if ( local )                                            // local access
         {
@@ -3470 +3597 @@
                               nline );
 #ifdef INSTRUMENTATION
-m_cpt_itlb_write++;
+m_cpt_ins_tlb_update_acc++;
 #endif
 
@@ -3494 +3621 @@
                               nline );
 #ifdef INSTRUMENTATION
-m_cpt_dtlb_write++;
+m_cpt_data_tlb_update_acc++;
 #endif
 
@@ -3528 +3655 @@
     case DCACHE_TLB_LR_UPDT:        // request a CAS transaction to update L/R bit
     {
+        uint32_t way  = r_cas_local_way.read();
+        uint32_t set  = r_cas_local_set.read();
+        uint32_t word = r_cas_local_word.read();
+        paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
 #if DEBUG_DCACHE
 if ( m_debug_activated )
@@ -3535 +3666 @@
 }
 #endif
-        // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
-        r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
-
-        // checking llsc reservation buffer
-        if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
-            r_dcache_llsc_valid = false;
-
-        // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
-        r_dcache_vci_cas_req = true;
-        r_dcache_fsm         = DCACHE_TLB_LR_WAIT;
+
+        if (r_cas_islocal.read())
+        {
+            r_dcache.write(way,
+                           set,
+                           word,
+                           r_dcache_vci_cas_new.read());
+            //compteur dirty
+            r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 1;
+
+            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
+            {
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+                r_dcache_tlb_inval_line  = nline;
+                r_dcache_tlb_inval_set   = 0;
+                r_dcache_fsm_scan_save   = DCACHE_TLB_RETURN;
+                r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+                break;
+            }
+
+            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
+            {
+                r_itlb.reset();
+                r_dtlb.reset();
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+
+#if DEBUG_DCACHE
+                if ( m_debug_activated )
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_LR_UPDT> Flush DTLB & ITLB" << std::endl;
+                }
+#endif
+            }
+
+            r_dcache_fsm = DCACHE_TLB_RETURN; 
+        }
+        else
+        {
+            // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
+          r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
+
+            // checking llsc reservation buffer
+            if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
+                r_dcache_llsc_valid = false;
+
+            // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
+            r_dcache_vci_cas_req = true;
+            r_dcache_fsm         = DCACHE_TLB_LR_WAIT;
+        }
         break;
     }
@@ -3739 +3910 @@
                                &tag,
                                &state );
-
-            if ( state == CACHE_SLOT_STATE_VALID )         // inval required
+            /*ODCCP*/
+
+            if ( state == CACHE_SLOT_STATE_VALID_CC )         // inval required
             {
                 // request cleanup
@@ -3751 +3923 @@
                 r_dcache_miss_way     = way;
                 r_dcache_miss_set     = set;
+                r_dcache_cc_cleanup_line_ncc = false;
+                r_dcache_cc_cleanup_updt_data = false;
                 r_dcache_fsm          = DCACHE_XTN_DC_FLUSH_GO;
+            }
+            else if ( state == CACHE_SLOT_STATE_VALID_NCC)
+            {
+                // request cleanup
+                r_dcache_cc_send_req   = true;
+                r_dcache_cc_send_nline = tag * m_dcache_sets + set;
+                r_dcache_cc_send_way   = way;
+                r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
+
+                // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
+                r_dcache_miss_way     = way;
+                r_dcache_miss_set     = set;
+                r_dcache_cc_cleanup_line_ncc = true;
+                //if (r_dcache_content_state[m_dcache_sets*way+set] != LINE_CACHE_DATA_NOT_DIRTY)//Must send data in the cleanup
+                if (true)//Must send data in the cleanup
+                {
+                    r_dcache_xtn_flush_addr_data = (tag * m_dcache_sets + set) * m_dcache_words * 4;
+                    r_dcache_xtn_flush_data_cpt = 0;
+                    r_dcache_cc_cleanup_updt_data = true;
+                    for (size_t w = 0; w< m_dcache_words; w++)
+                    {
+                        m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
+                    }
+                    r_dcache_fsm          = DCACHE_XTN_DC_FLUSH_DATA;
+                }
+                else
+                {
+                    r_dcache_cc_cleanup_updt_data = false;
+                    r_dcache_fsm          = DCACHE_XTN_DC_FLUSH_GO;
+                }
             }
             else if ( r_dcache_flush_count.read() ==
@@ -3768 +3972 @@
         break;
     }
+
+    ////////////////////////////
+    case DCACHE_XTN_DC_FLUSH_DATA:
+    {
+        uint32_t rdata;
+        size_t   way;
+        size_t   set;
+        size_t   word;
+        r_dcache.read_neutral(r_dcache_xtn_flush_addr_data.read(),
+                              &rdata,
+                              &way,
+                              &set,
+                              &word);
+        if(r_cc_send_data_fifo.wok())
+        {
+            r_dcache_xtn_flush_addr_data = r_dcache_xtn_flush_addr_data.read() + 4;
+
+            cleanup_data_updt_fifo_dcache_put   = true;
+            cleanup_data_updt_fifo_dcache_data  = rdata;
+
+            r_dcache_xtn_flush_data_cpt = r_dcache_xtn_flush_data_cpt + 1;
+            if(r_dcache_xtn_flush_data_cpt.read() == (m_dcache_words - 1))
+            {
+                r_dcache_xtn_flush_data_cpt = 0;
+                r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
+            }
+        }
+        break;
+    }
+
     ////////////////////////////
     case DCACHE_XTN_DC_FLUSH_GO:    // Switch the cache slot to ZOMBI state
@@ -3776 +4010 @@
         size_t set = r_dcache_miss_set.read();
 
-        r_dcache_in_tlb[m_dcache_sets*way+set]       = false;
-        r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
+        // MODIFIED
+        //r_dcache_in_tlb[m_dcache_sets*way+set]       = false;
+        //r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
+        r_dcache_content_state[m_dcache_sets*way+set]  = LINE_CACHE_DATA_DIRTY;
 
 #ifdef INSTRUMENTATION
@@ -3820 +4056 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_dtlb_read++;
+m_cpt_data_tlb_read++;
 #endif
             hit = r_dtlb.translate( r_dcache_save_wdata.read(),
@@ -3840 +4076 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_dtlb_miss++;
+m_cpt_data_tlb_miss++;
 #endif
             r_dcache_tlb_ins    = false;                // dtlb
@@ -3877 +4113 @@
                            &set,
                            &word );
-
-        if ( state == CACHE_SLOT_STATE_VALID )  // inval to be done
-        {
-            r_dcache_xtn_way = way;
-            r_dcache_xtn_set = set;
-            r_dcache_fsm      = DCACHE_XTN_DC_INVAL_GO;
+        /*ODCCP*/
+        //assert((state != CACHE_SLOT_STATE_VALID_NCC) and "NOT YET DONE");
+        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))      // inval to be done
+        {
+            r_dcache_xtn_way       = way;
+            r_dcache_xtn_set       = set;
+            r_dcache_xtn_state     = state;
+            r_dcache_xtn_data_addr = r_dcache_save_paddr.read()&~0x3F;
+            
+            if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) )
+            {
+                m_cpt_cleanup_data_not_dirty ++;
+            }
+            r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
+            
         }
         else            // miss : nothing to do
@@ -3896 +4141 @@
               << " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
               << " / PADDR = " << r_dcache_save_paddr.read() << std::dec
-              << " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
+              << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))
               << " / SET = " << set
               << " / WAY = " << way << std::endl;
+    //r_dcache.printTrace();
 }
 #endif
@@ -3910 +4156 @@
         if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
         {
+            int     state      = r_dcache_xtn_state.read();
             size_t      way        = r_dcache_xtn_way.read();
             size_t      set        = r_dcache_xtn_set.read();
@@ -3917 +4164 @@
 m_cpt_dcache_dir_write++;
 #endif
-            r_dcache.write_dir( way,
-                                set,
-                                CACHE_SLOT_STATE_ZOMBI );
-
-            // request cleanup
-            r_dcache_cc_send_req   = true;
-            r_dcache_cc_send_nline = nline;
-            r_dcache_cc_send_way   = way;
-            r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
+            // MODIFIER POUR DIRTY BIT //
+            if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))// request cleanup
+            {
+                r_dcache_cc_send_req   = true;
+                r_dcache_cc_send_nline = nline;
+                r_dcache_cc_send_way   = way;
+                r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
+                if (state == CACHE_SLOT_STATE_VALID_CC)
+                {
+                    r_dcache_cc_cleanup_line_ncc = false;
+                    r_dcache.write_dir( way,
+                            set,
+                            CACHE_SLOT_STATE_ZOMBI );
+                }
+                else
+                {
+                    r_dcache_cc_cleanup_line_ncc = true;
+                    //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY)) //must send data
+                    if (true) //must send data
+                    {
+                        r_dcache_cc_cleanup_updt_data = true;
+                        for (size_t w = 0; w< m_dcache_words; w++)
+                        {
+                            m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
+                        }
+                        r_dcache_fsm = DCACHE_XTN_DC_INVAL_DATA;
+                        break;
+                    }
+                    else
+                    {
+                        r_dcache_cc_cleanup_updt_data = false;
+                        r_dcache.write_dir( way,
+                                            set,
+                                            CACHE_SLOT_STATE_ZOMBI );
+                    }
+                    if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) )
+                        m_cpt_cleanup_data_not_dirty ++;
+                }
+            }
+            /*ODCCP*/
 
             // possible itlb & dtlb invalidate
-            if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
+            // MODIFIED
+            //if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
+            //{
+            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
             {
                 r_dcache_tlb_inval_line = nline;
@@ -3934 +4215 @@
                 r_dcache_fsm_scan_save  = DCACHE_XTN_DC_INVAL_END;
                 r_dcache_fsm            = DCACHE_INVAL_TLB_SCAN;
-                r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-            }
-            else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
+                // MODIFIED
+                //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+            }
+            // MODIFIED
+            //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
+            //{
+            else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD)
             {
                 r_itlb.reset();
                 r_dtlb.reset();
-                r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+                // MODIFIED
+                //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
                 r_dcache_fsm = DCACHE_IDLE;
                 m_drsp.valid = true;
@@ -3961 +4249 @@
         break;
     }
+
+    /*ODCCP*/
+    //////////////////////////////
+    case DCACHE_XTN_DC_INVAL_DATA:      //A verifier
+    {
+
+        uint32_t rdata;
+        size_t   way;
+        size_t   set;
+        size_t   word;
+        r_dcache.read_neutral(r_dcache_xtn_data_addr.read(),
+                              &rdata,
+                              &way,
+                              &set,
+                              &word);
+        if(r_cc_send_data_fifo.wok())
+        {
+            r_dcache_xtn_data_addr = r_dcache_xtn_data_addr.read() + 4;
+
+            cleanup_data_updt_fifo_dcache_put   = true;
+            cleanup_data_updt_fifo_dcache_data  = rdata;
+
+            r_dcache_xtn_data_cpt = r_dcache_xtn_data_cpt.read() + 1;
+            if(r_dcache_xtn_data_cpt.read() == (m_dcache_words - 1))
+            {
+                r_dcache_xtn_state = CACHE_SLOT_STATE_ZOMBI;
+                r_dcache_xtn_data_cpt = 0;
+                r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
+                r_dcache.write_dir( way,
+                                    set,
+                                    CACHE_SLOT_STATE_ZOMBI );
+            }
+        }
+        break;
+    }
+
     //////////////////////////////
     case DCACHE_XTN_DC_INVAL_END:       // send response to processor XTN request
@@ -4001 +4325 @@
             size_t   set = 0;
             paddr_t  victim = 0;
+            int state;
 
 #ifdef INSTRUMENTATION
@@ -4011 +4336 @@
                                   &found,
                                   &cleanup );
+            state = r_dcache.get_cache_state(way,set);
 
             if ( found )
@@ -4026 +4352 @@
                     r_dcache_cc_send_way   = way;
                     r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
+                    if( (state == CACHE_SLOT_STATE_VALID_NCC) )//and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) )
+                    {
+                        //MODIFIER POUR DIRTY BIT //
+                        r_dcache_cc_cleanup_line_ncc = true;
+                        r_dcache_miss_data_addr = (victim*m_dcache_words)*4;
+                        //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY))//must send data
+                        if (true)//must send data
+                        {
+                            r_dcache_cc_cleanup_updt_data = true;
+                            for (size_t w = 0; w< m_dcache_words; w++)
+                            {
+                                m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
+                            }
+                            r_dcache_fsm = DCACHE_MISS_DATA;
+                        }
+                        else
+                        {
+                            r_dcache_cc_cleanup_updt_data = false;
+                        }
+
+                        if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY)
+                            m_cpt_cleanup_data_not_dirty ++;
+                    }
+                        
+                    else
+                    {
+                        r_dcache_cc_cleanup_line_ncc  = false;
+                        r_dcache_cc_cleanup_updt_data = false;
+                    }
                 }
                 else
@@ -4049 +4404 @@
     }
     ///////////////////////
+    case DCACHE_MISS_DATA:
+    {
+        uint32_t rdata;
+        size_t way;
+        size_t set;
+        size_t word;
+
+        r_dcache.read_neutral(r_dcache_miss_data_addr,
+                              &rdata,
+                              &way,
+                              &set,
+                              &word);
+        if(r_cc_send_data_fifo.wok())
+        {
+            r_dcache_miss_data_addr = r_dcache_miss_data_addr.read() + 4;
+
+            cleanup_data_updt_fifo_dcache_put   = true;
+            cleanup_data_updt_fifo_dcache_data  = rdata;
+
+            r_dcache_miss_data_cpt = r_dcache_miss_data_cpt.read() + 1;
+            if (r_dcache_miss_data_cpt.read() == m_dcache_words-1 )
+            {
+                r_dcache_miss_data_cpt = 0;
+                r_dcache_fsm = DCACHE_MISS_CLEAN;
+            }
+        }
+        break;
+    }
+    ///////////////////////
     case DCACHE_MISS_CLEAN:             // switch the slot to ZOMBI state
                                 // and possibly request itlb or dtlb invalidate
@@ -4074 +4458 @@
         // if selective itlb & dtlb invalidate are required
         // the miss response is not handled before invalidate completed
-        if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
-        {
-            r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+        // MODIFIED
+        //if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
+        //{
+        if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
+        {
+            //MODIFIED
+            //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+            r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             r_dcache_tlb_inval_line  = r_dcache_cc_send_nline;
             r_dcache_tlb_inval_set   = 0;
@@ -4082 +4471 @@
             r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
         }
-        else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
+        // MODIFIED
+        //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
+        //{
+        else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
         {
             r_itlb.reset();
             r_dtlb.reset();
-            r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+            // MODIFIED
+            //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+            r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             r_dcache_fsm = DCACHE_MISS_WAIT;
         }
@@ -4101 +4495 @@
     {
         if ( m_dreq.valid) m_cost_data_miss_frz++;
-
         // coherence clack request (from DSPIN CLACK)
         if ( r_dcache_clack_req.read() )
@@ -4184 +4577 @@
         if ( m_dreq.valid) m_cost_data_miss_frz++;
 
-        if ( r_vci_rsp_fifo_dcache.rok() )      // one word available
+        if ( r_vci_rsp_fifo_dcache.rok() && r_vci_rsp_fifo_rpktid.rok())        // one word available
         {
 #ifdef INSTRUMENTATION
@@ -4205 +4598 @@
 #endif
             vci_rsp_fifo_dcache_get = true;
+
+            r_dcache_read_state = !r_vci_rsp_fifo_rpktid.read();//deduce the state (CC or NCC) from msb of pktid
+            vci_rsp_fifo_rpktid_get = true;
+
+
             r_dcache_miss_word = r_dcache_miss_word.read() + 1;
 
@@ -4253 +4651 @@
                     r_dcache_cc_send_way   = r_dcache_miss_way.read();
                     r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
+                    r_dcache_cc_cleanup_updt_data = false; //the line is evicted at the very moment it arives, so it is not dirty
+                    r_dcache_cc_cleanup_line_ncc = !r_dcache_read_state.read();
 
 #ifdef INSTRUMENTATION
@@ -4279 +4679 @@
 m_cpt_dcache_dir_write++;
 #endif
-                r_dcache.write_dir( r_dcache_save_paddr.read(),
-                                    r_dcache_miss_way.read(),
-                                    r_dcache_miss_set.read(),
-                                    CACHE_SLOT_STATE_VALID );
+
+                size_t way = r_dcache_miss_way.read();
+                size_t set = r_dcache_miss_set.read();
+                if (r_dcache_read_state.read())
+                {
+                  r_dcache.write_dir( r_dcache_save_paddr.read(),
+                                        r_dcache_miss_way.read(),
+                                        r_dcache_miss_set.read(),
+                                        CACHE_SLOT_STATE_VALID_CC );
+
+                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
+                }
+                else
+                {
+                  r_dcache.write_dir( r_dcache_save_paddr.read(),
+                                        r_dcache_miss_way.read(),
+                                        r_dcache_miss_set.read(),
+                                        CACHE_SLOT_STATE_VALID_NCC );
+                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
+                    for (size_t word =0; word < m_dcache_words ; word++)
+                    {
+                        r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 0;
+                    }
+                }
 
 #if DEBUG_DCACHE
@@ -4293 +4713 @@
 #endif
                 // reset directory extension
-                size_t way = r_dcache_miss_way.read();
-                size_t set = r_dcache_miss_set.read();
-                r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-                r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+
+                // MODIFIED
+                //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+                //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
             }
             if      (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
@@ -4467 +4887 @@
                        &state );
 
-        assert( (state == CACHE_SLOT_STATE_VALID) and
+        assert( (state == CACHE_SLOT_STATE_VALID_CC or state == CACHE_SLOT_STATE_VALID_NCC) and
         "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
 
@@ -4479 +4899 @@
 
         // request a CAS CMD and go to DCACHE_DIRTY_WAIT state
-        r_dcache_vci_cas_req = true;
-        r_dcache_vci_paddr   = r_dcache_dirty_paddr.read();
-        r_dcache_vci_cas_old = pte;
-        r_dcache_vci_cas_new = pte | PTE_D_MASK;
-        r_dcache_fsm         = DCACHE_DIRTY_WAIT;
+        if (state == CACHE_SLOT_STATE_VALID_CC)
+        {
+            r_dcache_vci_cas_req = true;
+            r_dcache_vci_paddr   = r_dcache_dirty_paddr.read();
+            r_dcache_vci_cas_old = pte;
+            r_dcache_vci_cas_new = pte | PTE_D_MASK;
+            r_cas_islocal        = false;
+        }
+        else
+        {
+            r_cas_islocal = true;
+            r_cas_local_way = way;
+            r_cas_local_set = set;
+            r_cas_local_word = word;
+            r_dcache_vci_cas_new = pte | PTE_D_MASK;
+        }
+
+
+            r_dcache_fsm         = DCACHE_DIRTY_WAIT;
 
 #if DEBUG_DCACHE
@@ -4506 +4940 @@
                                     // - if the CAS is a failure, we just retry the write.
     {
+        uint32_t way  = r_cas_local_way.read();
+        uint32_t set  = r_cas_local_set.read();
+        uint32_t word = r_cas_local_word.read();
+        paddr_t nline = r_dcache_dirty_paddr.read() / (m_dcache_words<<2);
+
         // coherence clack request (from DSPIN CLACK)
         if ( r_dcache_clack_req.read() )
@@ -4522 +4961 @@
         }
 
-        if ( r_vci_rsp_data_error.read() )      // bus error
-        {
-            std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
-            std::cout << "This should not happen in this state" << std::endl;
-            exit(0);
-        }
-        else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
-        {
-            vci_rsp_fifo_dcache_get = true;
-            r_dcache_fsm            = DCACHE_IDLE;
-
+        if (!r_cas_islocal.read())
+        {
+            if ( r_vci_rsp_data_error.read() )  // bus error
+            {
+                std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
+                std::cout << "This should not happen in this state" << std::endl;
+                exit(0);
+            }
+            else if ( r_vci_rsp_fifo_dcache.rok() )     // response available
+            {
+                vci_rsp_fifo_dcache_get = true;
+                r_dcache_fsm            = DCACHE_IDLE;
 #if DEBUG_DCACHE
 if ( m_debug_activated )
@@ -4540 +4980 @@
 }
 #endif
+            }
+        }
+        else
+        {
+            r_dcache.write(way,
+                           set,
+                           word,
+                           r_dcache_vci_cas_new.read());
+            //std::cout << "CAS local" << std::endl;
+            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
+            {
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+                r_dcache_tlb_inval_line  = nline;
+                r_dcache_tlb_inval_set   = 0;
+                r_dcache_fsm_scan_save   = DCACHE_IDLE;
+                r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+                break;
+            }
+
+            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
+            {
+                r_itlb.reset();
+                r_dtlb.reset();
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+
+#if DEBUG_DCACHE
+                if ( m_debug_activated )
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_DIRTY_WAIT> Flush DTLB & ITLB" << std::endl;
+                }
+#endif
+            }
+            r_dcache_fsm            = DCACHE_IDLE;
         }
         break;
@@ -4674 +5148 @@
                            &word ); // unused
 
+        r_dcache_cc_state = state;
         r_dcache_cc_way = way;
         r_dcache_cc_set = set;
-
-        if ( state == CACHE_SLOT_STATE_VALID) // hit
-        {
-            // need to update the cache state
-            if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
-            {
-                r_dcache_cc_need_write = true;
-                r_dcache_fsm           = DCACHE_CC_UPDT;
-                r_dcache_cc_word       = r_cc_receive_word_idx.read();
-            }
-            else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval
-            {
-                r_dcache_fsm           = DCACHE_CC_INVAL;
+            /*RWT / ODCCP*/
+        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))             // hit
+        {
+          // need to update the cache state
+            r_dcache_cc_need_write = true;
+            r_dcache_cc_cleanup_line_ncc = false;
+            if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)  // hit update
+            {
+                r_dcache_fsm          = DCACHE_CC_UPDT;
+                r_dcache_cc_word      = r_cc_receive_word_idx.read();
+            }
+            else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL)   // hit inval
+            {
+                if (state == CACHE_SLOT_STATE_VALID_NCC)
+                {
+                    r_dcache_cc_inval_addr = (paddr &~0x3F);
+                    r_dcache_cc_inval_data_cpt = 0;
+                }
+                r_dcache_fsm          = DCACHE_CC_INVAL;
+                r_dcache_dirty_save   = false;
             }
         }
@@ -4716 +5198 @@
               << " PADDR = " << std::hex << paddr
               << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
-              << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
+              << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl;
 }
 #endif
@@ -4722 +5204 @@
         break;
     }
+
     /////////////////////
     case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
@@ -4729 +5212 @@
         size_t way    = r_dcache_cc_way.read();
         size_t set    = r_dcache_cc_set.read();
-
-        if ( r_dcache_in_tlb[way*m_dcache_sets+set] )       // selective TLB inval
-        {
-            r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-            r_dcache_tlb_inval_line  = r_cc_receive_dcache_nline.read();
-            r_dcache_tlb_inval_set   = 0;
-            r_dcache_fsm_scan_save   = r_dcache_fsm.read();
-            r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
-            break;
-        }
-
-        if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
-        {
-            r_itlb.reset();
-            r_dtlb.reset();
-            r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
-
+        int      cache_state = r_dcache_cc_state.read();
+        bool     dirty_save = false;
+
+        if (r_dcache_cc_need_write.read())
+        {
+            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
+            {
+                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;//need to remember it was dirty for cleanup
+                dirty_save = true;
+                r_dcache_dirty_save = true;
+                r_dcache_tlb_inval_line  = r_cc_receive_dcache_nline.read();
+                r_dcache_tlb_inval_set   = 0;
+                r_dcache_fsm_scan_save   = r_dcache_fsm.read();
+                r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+                break;
+            }
+            else
+            {
+                if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
+                {
+                    r_itlb.reset();
+                    r_dtlb.reset();
+                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
+                    dirty_save = true;
+                    r_dcache_dirty_save = true;
 #if DEBUG_DCACHE
 if ( m_debug_activated )
@@ -4753 +5244 @@
 }
 #endif
-        }
-
-        assert (not r_dcache_cc_send_req.read() &&
-                "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
-                "must not be set");
-
-        // Switch slot state to ZOMBI and send CLEANUP command 
-        r_dcache.write_dir( 0,
-                            way,
-                            set,
-                            CACHE_SLOT_STATE_ZOMBI );
-
-        // coherence request completed
-        r_cc_receive_dcache_req = false;
-        r_dcache_cc_send_req    = true;
-        r_dcache_cc_send_nline  = r_cc_receive_dcache_nline.read();
-        r_dcache_cc_send_way    = r_dcache_cc_way.read();
-        r_dcache_cc_send_type   = CC_TYPE_CLEANUP;
-        r_dcache_fsm            = r_dcache_fsm_cc_save.read();
-
-#if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-        << " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
-        << " / WAY = " << way
-        << " / SET = " << set << std::endl;
-}
-#endif
+                }
+
+                if (cache_state == CACHE_SLOT_STATE_VALID_CC) 
+                {
+                    r_dcache.write_dir( way,
+                                        set,
+                                        CACHE_SLOT_STATE_ZOMBI );
+                }
+
+                r_dcache_cc_need_write = false;
+            }
+        }
+            assert (not r_dcache_cc_send_req.read() &&
+                    "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
+                    "must not be set");
+            // coherence request completed
+                r_cc_receive_dcache_req = false;
+            // request multicast acknowledgement
+                r_dcache_cc_send_req = true;
+                r_dcache_cc_send_way = way;
+                r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
+                r_dcache_cc_send_type = CC_TYPE_CLEANUP;
+                // MODIFIER POUR DIRTY BIT //
+                if (cache_state == CACHE_SLOT_STATE_VALID_NCC)
+                {
+                    r_dcache_cc_cleanup_line_ncc = true; 
+                    //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data
+                    if (true) //must send data
+                    {
+                        r_dcache_cc_cleanup_updt_data = true;
+                        for (size_t w = 0; w< m_dcache_words; w++)
+                        {
+                            m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
+                        }
+                        r_dcache_fsm          = DCACHE_CC_INVAL_DATA;
+                    }
+                    else
+                    {
+                        r_dcache_cc_cleanup_updt_data = false;
+                        r_dcache_fsm = r_dcache_fsm_cc_save.read();
+                    }
+                }
+                else
+                {
+                    r_dcache_cc_cleanup_updt_data = false;
+                    r_dcache_fsm = r_dcache_fsm_cc_save.read();
+                }
+
+        break;
+    }
+    
+    /////////////////////
+    case DCACHE_CC_INVAL_DATA:
+    {
+
+        uint32_t rdata;
+        size_t   way;
+        size_t   set;
+        size_t   word;
+        r_dcache.read_neutral(r_dcache_cc_inval_addr.read(),
+                              &rdata,
+                              &way,
+                              &set,
+                              &word);
+        if(r_cc_send_data_fifo.wok())
+        {
+            r_dcache_cc_inval_addr = r_dcache_cc_inval_addr.read() + 4;
+
+            cleanup_data_updt_fifo_dcache_put   = true;
+            cleanup_data_updt_fifo_dcache_data  = rdata;
+
+            r_dcache_cc_inval_data_cpt = r_dcache_cc_inval_data_cpt.read() + 1;
+            if(r_dcache_cc_inval_data_cpt.read() == (m_dcache_words - 1))
+            {
+                r_dcache_cc_inval_data_cpt = 0;
+                r_dcache_fsm          = r_dcache_fsm_cc_save.read();
+                r_dcache.write_dir( way,
+                                    set,
+                                    CACHE_SLOT_STATE_ZOMBI );
+            }
+        }
         break;
     }
@@ -4792 +5335 @@
         size_t set        = r_dcache_cc_set.read();
 
-        if ( r_dcache_in_tlb[way*m_dcache_sets+set] )       // selective TLB inval
-        {
-            r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-            r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
-            r_dcache_tlb_inval_set  = 0;
-            r_dcache_fsm_scan_save  = r_dcache_fsm.read();
-            r_dcache_fsm            = DCACHE_INVAL_TLB_SCAN;
-
-            break;
-        }
-
-        if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
-        {
-            r_itlb.reset();
-            r_dtlb.reset();
-            r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+            if (r_dcache_cc_need_write.read())
+            {
+                if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
+                {
+                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
+                    r_dcache_tlb_inval_line  = r_cc_receive_dcache_nline.read();
+                    r_dcache_tlb_inval_set   = 0;
+                    r_dcache_fsm_scan_save   = r_dcache_fsm.read();
+                    r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+                    break;
+                }
+                if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
+                {
+                    r_itlb.reset();
+                    r_dtlb.reset();
+                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
 
 #if DEBUG_DCACHE
@@ -4816 +5359 @@
 }
 #endif
-        }
-
-        assert (not r_dcache_cc_send_req.read() &&
-                "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
-                "must not be set");
+                }
+
+                assert (not r_dcache_cc_send_req.read() &&
+                        "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
+                        "must not be set");
         
-        if ( not r_cc_receive_updt_fifo_be.rok() ) break;
-
-        if (r_dcache_cc_need_write.read())
-        {
-        
+                if ( not r_cc_receive_updt_fifo_be.rok() ) break;
+
 #ifdef INSTRUMENTATION
 m_cpt_dcache_data_write++;
@@ -4855 +5395 @@
             // no need to write in the cache anymore
             r_dcache_cc_need_write = false;
-
             // coherence request completed
             r_cc_receive_dcache_req = false;
@@ -5041 +5580 @@
                         r_dcache_vci_unc_req.read())
                      or r_vci_cmd_imiss_prio.read() );
-
             // 1 - Data Read Miss
             if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
@@ -5048 +5586 @@
                 r_dcache_vci_miss_req = false;
                 r_vci_cmd_imiss_prio  = true;
-//                m_cpt_dmiss_transaction++;
+                m_cpt_dmiss_transaction++;
             }
             // 2 - Data Read Uncachable
@@ -5055 +5593 @@
                 r_vci_cmd_fsm        = CMD_DATA_UNC;
                 r_dcache_vci_unc_req = false;
-//                m_cpt_dunc_transaction++;
+                m_cpt_dunc_transaction++;
             }
             // 3 - Data Linked Load
@@ -5062 +5600 @@
                 r_dcache_vci_ll_req = false;
                 r_vci_cmd_fsm       = CMD_DATA_LL;
-//              m_cpt_ll_transaction++;
+                m_cpt_ll_transaction++;
             }
             // 4 - Instruction Miss
@@ -5070 +5608 @@
                 r_icache_miss_req    = false;
                 r_vci_cmd_imiss_prio = false;
-//                m_cpt_imiss_transaction++;
+                m_cpt_imiss_transaction++;
             }
             // 5 - Instruction Uncachable
@@ -5077 +5615 @@
                 r_vci_cmd_fsm       = CMD_INS_UNC;
                 r_icache_unc_req    = false;
-//                m_cpt_iunc_transaction++;
+                //m_cpt_iunc_transaction++;
             }
             // 6 - Data Write
@@ -5086 +5624 @@
                 r_vci_cmd_min       = wbuf_min;
                 r_vci_cmd_max       = wbuf_max;
-//                m_cpt_write_transaction++;
-//                m_length_write_transaction += (wbuf_max-wbuf_min+1);
+                m_cpt_write_transaction++;
+                m_length_write_transaction += (wbuf_max-wbuf_min+1);
             }
             // 7 - Data Store Conditionnal
@@ -5095 +5633 @@
                 r_vci_cmd_cpt  = 0;
                 r_vci_cmd_fsm  = CMD_DATA_SC;
-//              m_cpt_sc_transaction++;
+                //m_cpt_sc_transaction++;
             }
             // 8 - Compare And Swap
@@ -5103 +5641 @@
                 r_dcache_vci_cas_req = false;
                 r_vci_cmd_cpt        = 0;
-//              m_cpt_cas_transaction++;
+                //m_cpt_cas_transaction++;
             }
 
@@ -5194 +5732 @@
         {
             r_vci_rsp_cpt = 0;
-
+            if (r_dcache_vci_paddr.read() == 0x1f624) std::cout << "Tansaction on barrier, pktid = " <<  p_vci.rpktid.read() << std::endl;
             if      ( (p_vci.rpktid.read() & 0x7) ==  TYPE_READ_DATA_UNC  )
             {
@@ -5311 +5849 @@
                 else                                        // no error reported
                 {
-                    if ( r_vci_rsp_fifo_dcache.wok() )
+
+
+                    if ( r_vci_rsp_fifo_dcache.wok() && r_vci_rsp_fifo_rpktid.wok())
                     {
                         assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
@@ -5319 +5859 @@
                         vci_rsp_fifo_dcache_put       = true,
                         vci_rsp_fifo_dcache_data      = p_vci.rdata.read();
+                        vci_rsp_fifo_rpktid          = (p_vci.rpktid.read() == 0x9);//RWT: interpretation of pktid for state (NCC or CC)
+                        vci_rsp_fifo_rpktid_put      = true;//RWT
+
                         if ( p_vci.reop.read() )
                         {
+                            if (r_vci_rsp_cpt.read() != m_dcache_words - 1) std::cout << "assert on proc " << name() << std::endl;
                             assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
                             "The VCI response packet for data miss is too short");
@@ -5480 +6024 @@
             if (p_dspin_p2m.read.read())
             {
-                if (r_cc_send_last_client.read() == 0) // dcache active request
-                    r_dcache_cc_send_req = false; // reset dcache request
-                else // icache active request
-                    r_icache_cc_send_req = false; // reset icache request
-
-                // go back to idle state
-                r_cc_send_fsm = CC_SEND_IDLE;
+                //std::cout << "CLEANUP send on line " << r_dcache_cc_send_nline.read() << std::endl;
+                if(r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0))//dcache request with data
+               {
+                    r_cc_send_fsm = CC_SEND_CLEANUP_DATA_UPDT;
+                }
+                else
+                {
+                    if (r_cc_send_last_client.read() == 0) // dcache active request
+                    {
+                        r_dcache_cc_send_req = false; // reset dcache request
+                    }
+                    else // icache active request
+                    {
+                        r_icache_cc_send_req = false; // reset icache request
+                    }
+                    // go back to idle state
+                    r_cc_send_fsm = CC_SEND_IDLE;
+                }
+            }
+            break;
+        }
+        ///////////////////////////
+        case CC_SEND_CLEANUP_DATA_UPDT:
+        {
+            if (p_dspin_p2m.read.read())
+            {
+                if(r_cc_send_data_fifo.rok())
+                {
+                    /*ODCCP*///std::cout<<"CLEANUP_DATA_UPDT" << std::endl;
+                    m_cpt_data_cleanup++;
+                    cleanup_data_updt_fifo_dcache_get = true;
+                    r_cc_send_cpt_word = r_cc_send_cpt_word.read() + 1;
+                    if (r_cc_send_cpt_word.read() == m_dcache_words-1)
+                    {
+                        //std::cout << "L1 paddr CLEANUP DATA | paddr = " << std::hex << (r_dcache_cc_send_nline.read()*m_dcache_words)*4 << std::dec << std::endl;
+                        /*ODCCP*/
+                        //std::cout << "CLEANUP with DATA finished by " << name() << std::endl;
+                        r_dcache_cc_send_req = false;
+                        r_dcache_cc_cleanup_updt_data = false;
+                        r_cc_send_cpt_word = 0;
+                        r_cc_send_fsm = CC_SEND_IDLE;
+                    }
+                }
             }
             break;
@@ -5801 +6381 @@
                                  vci_rsp_fifo_dcache_put,
                                  vci_rsp_fifo_dcache_data);
+    //BUG pktid
+    r_vci_rsp_fifo_rpktid.update(vci_rsp_fifo_rpktid_get,
+                                 vci_rsp_fifo_rpktid_put,
+                                 vci_rsp_fifo_rpktid);
+
+    r_cc_send_data_fifo.update(cleanup_data_updt_fifo_dcache_get,
+                               cleanup_data_updt_fifo_dcache_put,
+                               cleanup_data_updt_fifo_dcache_data);
 
     ///////////////// updt FIFO update  //////////////////////
@@ -6011 +6599 @@
                                 >> (m_nline_width - m_x_width - m_y_width) 
                                 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
- 
                 DspinDhccpParam::dspin_set(dspin_send_data,
                                            dest,
@@ -6027 +6614 @@
                                            DspinDhccpParam::TYPE_CLEANUP_DATA,
                                            DspinDhccpParam::P2M_TYPE);
+
+                DspinDhccpParam::dspin_set(dspin_send_data,
+                                           (r_dcache_cc_cleanup_line_ncc.read() and (r_cc_send_last_client.read() == 0)),
+                                           DspinDhccpParam::CLEANUP_NCC);
             }
             else                                // icache active request
@@ -6049 +6640 @@
                                            DspinDhccpParam::TYPE_CLEANUP_INST,
                                            DspinDhccpParam::P2M_TYPE);
+
+                DspinDhccpParam::dspin_set(dspin_send_data,
+                                           0,
+                                           DspinDhccpParam::CLEANUP_NCC);
+
+
             }
             // send flit
@@ -6060 +6657 @@
         {
             // initialize dspin send data
-//            DspinDhccpParam::dspin_set(dspin_send_data,
-//                                       1,
-//                                       DspinDhccpParam::P2M_EOP);
-
             if(r_cc_send_last_client.read() == 0) // dcache active request
             {
@@ -6079 +6672 @@
             p_dspin_p2m.data  = dspin_send_data;
             p_dspin_p2m.write = true;
-            p_dspin_p2m.eop   = true;
+            p_dspin_p2m.eop   = ! (r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0));
+            break;
+        }
+        ///////////////////////
+        case CC_SEND_CLEANUP_DATA_UPDT:
+        {
+            /*if (r_cc_send_cpt_word.read() == m_dcache_words-1)
+            {
+                DspinDhccpParam::dspin_set(dspin_send_data,
+                                           1,
+                                           DspinDhccpParam::FROM_L1_EOP);
+            }
+            else
+            {
+                DspinDhccpParam::dspin_set(dspin_send_data,
+                                           0,
+                                           DspinDhccpParam::FROM_L1_EOP);
+            }*/
+
+            DspinDhccpParam::dspin_set(dspin_send_data,
+                                       r_cc_send_data_fifo.read(),
+                                       DspinDhccpParam::CLEANUP_DATA_UPDT);
+            
+            p_dspin_p2m.data = dspin_send_data;
+            //std::cout << "genmoore CLEANUP DATA UPDT : dspin_send_data = " << std::hex << dspin_send_data << std::dec << std::endl;
+            p_dspin_p2m.write = true;
+            p_dspin_p2m.eop = (r_cc_send_cpt_word.read() == m_dcache_words-1);
             break;
         }

branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h

@@ -96 +96 @@
 
     bool    valid;                  // entry valid
+    bool    cache_coherent;         // WB or WT policy
     bool    is_cnt;                 // directory entry is in counter mode
     bool    dirty;                  // entry dirty
@@ -107 +108 @@
     {
       valid         = false;
+      cache_coherent= false;
       is_cnt        = false;
       dirty         = false;
@@ -123 +125 @@
     {
       valid         = source.valid;
+      cache_coherent= source.cache_coherent;
       is_cnt        = source.is_cnt;
       dirty         = source.dirty;
@@ -138 +141 @@
     {
       valid     = false;
+      cache_coherent = false;
       is_cnt    = false;
       dirty     = false;
@@ -150 +154 @@
     {
       valid         = source.valid;
+      cache_coherent = source.cache_coherent;
       is_cnt    = source.is_cnt;
       dirty         = source.dirty;
@@ -165 +170 @@
     {
       std::cout << "Valid = " << valid 
+                << " ; COHERENCE = " << cache_coherent
                 << " ; IS COUNT = " << is_cnt 
                 << " ; Dirty = " << dirty 

branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -131 +131 @@
         CC_SEND_XRAM_RSP_INVAL_HEADER,
         CC_SEND_XRAM_RSP_INVAL_NLINE,
+        CC_SEND_READ_NCC_INVAL_HEADER,
+        CC_SEND_READ_NCC_INVAL_NLINE,
+        CC_SEND_WRITE_NCC_INVAL_HEADER,
+        CC_SEND_WRITE_NCC_INVAL_NLINE,
         CC_SEND_WRITE_BRDCAST_HEADER,
         CC_SEND_WRITE_BRDCAST_NLINE,
@@ -178 +182 @@
         READ_DIR_REQ,
         READ_DIR_LOCK,
+        READ_IVT_LOCK,
+        READ_WAIT,
         READ_DIR_HIT,
         READ_HEAP_REQ,
@@ -197 +203 @@
         WRITE_DIR_REQ,
         WRITE_DIR_LOCK,
+        WRITE_IVT_LOCK_HIT_WB,
         WRITE_DIR_READ,
         WRITE_DIR_HIT,
@@ -205 +212 @@
         WRITE_UPT_DEC,
         WRITE_RSP,
+        WRITE_MISS_IVT_LOCK,
         WRITE_MISS_TRT_LOCK,
         WRITE_MISS_TRT_DATA,
@@ -253 +261 @@
         IXR_CMD_CAS_IDLE,
         IXR_CMD_XRAM_IDLE,
+        IXR_CMD_CLEANUP_IDLE,
         IXR_CMD_READ,
         IXR_CMD_WRITE,
         IXR_CMD_CAS,
-        IXR_CMD_XRAM
+        IXR_CMD_XRAM,
+        IXR_CMD_CLEANUP_DATA
       };
 
@@ -290 +300 @@
         CLEANUP_IDLE,
         CLEANUP_GET_NLINE,
+        CLEANUP_GET_DATA,
         CLEANUP_DIR_REQ,
         CLEANUP_DIR_LOCK,
         CLEANUP_DIR_WRITE,
+        CLEANUP_IVT_LOCK_DATA,
+        CLEANUP_IVT_CLEAR_DATA,
+        CLEANUP_READ_RSP,
         CLEANUP_HEAP_REQ,
         CLEANUP_HEAP_LOCK,
@@ -302 +316 @@
         CLEANUP_IVT_CLEAR,
         CLEANUP_WRITE_RSP,
+        CLEANUP_IXR_REQ,
+        CLEANUP_WAIT,
         CLEANUP_CONFIG_ACK,
         CLEANUP_SEND_CLACK
@@ -325 +341 @@
         ALLOC_TRT_CAS,
         ALLOC_TRT_XRAM_RSP,
-        ALLOC_TRT_IXR_RSP
+        ALLOC_TRT_IXR_RSP,
+        ALLOC_TRT_CLEANUP
       };
 
@@ -340 +357 @@
       {
         ALLOC_IVT_WRITE,
+        ALLOC_IVT_READ,
         ALLOC_IVT_XRAM_RSP,
         ALLOC_IVT_CLEANUP,
@@ -434 +452 @@
       uint32_t     m_cpt_sc;            // Number of SC transactions
       uint32_t     m_cpt_cas;           // Number of CAS transactions
+      
+      uint32_t     m_cpt_read_fsm_dir_lock;        // wait DIR LOCK
+      uint32_t     m_cpt_read_fsm_n_dir_lock;      // NB DIR LOCK
+      uint32_t     m_cpt_write_fsm_dir_lock;       // wait DIR LOCK
+      uint32_t     m_cpt_write_fsm_n_dir_lock;     // NB DIR LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_dir_lock;    // wait DIR LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_n_dir_lock;  // NB DIR LOCK
+      uint32_t     m_cpt_cas_fsm_dir_lock;         // wait DIR LOCK
+      uint32_t     m_cpt_cas_fsm_n_dir_lock;       // NB DIR LOCK
+      uint32_t     m_cpt_cleanup_fsm_dir_lock;     // wait DIR LOCK
+      uint32_t     m_cpt_cleanup_fsm_n_dir_lock;   // NB DIR LOCK
+      
+      uint32_t     m_cpt_dir_unused;            // NB cycles DIR LOCK unused
+      uint32_t     m_cpt_read_fsm_dir_used;     // NB cycles DIR LOCK used
+      uint32_t     m_cpt_write_fsm_dir_used;    // NB cycles DIR LOCK used
+      uint32_t     m_cpt_cas_fsm_dir_used;      // NB cycles DIR LOCK used
+      uint32_t     m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used
+      uint32_t     m_cpt_cleanup_fsm_dir_used;  // NB cycles DIR LOCK used
+
+      uint32_t     m_cpt_read_fsm_trt_lock;      // wait TRT LOCK
+      uint32_t     m_cpt_write_fsm_trt_lock;     // wait TRT LOCK
+      uint32_t     m_cpt_cas_fsm_trt_lock;       // wait TRT LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_trt_lock;  // wait TRT LOCK
+      uint32_t     m_cpt_ixr_fsm_trt_lock;       // wait TRT LOCK
+      
+      uint32_t     m_cpt_read_fsm_n_trt_lock;      // NB TRT LOCK
+      uint32_t     m_cpt_write_fsm_n_trt_lock;     // NB TRT LOCK
+      uint32_t     m_cpt_cas_fsm_n_trt_lock;       // NB TRT LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_n_trt_lock;  // NB TRT LOCK
+      uint32_t     m_cpt_ixr_fsm_n_trt_lock;       // NB TRT LOCK
+
+      uint32_t     m_cpt_read_fsm_trt_used;      // NB cycles TRT LOCK used
+      uint32_t     m_cpt_write_fsm_trt_used;     // NB cycles TRT LOCK used
+      uint32_t     m_cpt_cas_fsm_trt_used;       // NB cycles TRT LOCK used
+      uint32_t     m_cpt_xram_rsp_fsm_trt_used;  // NB cycles TRT LOCK used
+      uint32_t     m_cpt_ixr_fsm_trt_used;       // NB cycles TRT LOCK used
+      
+      uint32_t     m_cpt_trt_unused;            // NB cycles TRT LOCK unused
+
+      uint32_t     m_cpt_write_fsm_upt_lock;     // wait UPT LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_upt_lock;  // wait UPT LOCK
+      uint32_t     m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK
+      uint32_t     m_cpt_cleanup_fsm_ivt_lock;   // wait UPT LOCK
+      uint32_t     m_cpt_cas_fsm_upt_lock;       // wait UPT LOCK
+      
+      uint32_t     m_cpt_write_fsm_n_upt_lock;     // NB UPT LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_n_upt_lock;  // NB UPT LOCK
+      uint32_t     m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK
+      uint32_t     m_cpt_cleanup_fsm_n_upt_lock;   // NB UPT LOCK
+      uint32_t     m_cpt_cas_fsm_n_upt_lock;       // NB UPT LOCK
+      
+      uint32_t     m_cpt_write_fsm_upt_used;     // NB cycles UPT LOCK used
+      uint32_t     m_cpt_xram_rsp_fsm_upt_used;  // NB cycles UPT LOCK used
+      uint32_t     m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used
+      uint32_t     m_cpt_cleanup_fsm_ivt_used;   // NB cycles UPT LOCK used
+      uint32_t     m_cpt_cas_fsm_upt_used;       // NB cycles UPT LOCK used
+      
+      uint32_t     m_cpt_ivt_unused;            // NB cycles UPT LOCK unused
+      uint32_t     m_cpt_upt_unused;            // NB cycles UPT LOCK unused
+
+      uint32_t     m_cpt_read_fsm_heap_lock;     // wait HEAP LOCK
+      uint32_t     m_cpt_write_fsm_heap_lock;    // wait HEAP LOCK
+      uint32_t     m_cpt_cas_fsm_heap_lock;      // wait HEAP LOCK
+      uint32_t     m_cpt_cleanup_fsm_heap_lock;  // wait HEAP LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK
+      
+      uint32_t     m_cpt_read_fsm_n_heap_lock;     // NB HEAP LOCK
+      uint32_t     m_cpt_write_fsm_n_heap_lock;    // NB HEAP LOCK
+      uint32_t     m_cpt_cas_fsm_n_heap_lock;      // NB HEAP LOCK
+      uint32_t     m_cpt_cleanup_fsm_n_heap_lock;  // NB HEAP LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK
+      
+      uint32_t     m_cpt_read_fsm_heap_used;     // NB cycles HEAP LOCK used
+      uint32_t     m_cpt_write_fsm_heap_used;    // NB cycles HEAP LOCK used
+      uint32_t     m_cpt_cas_fsm_heap_used;      // NB cycles HEAP LOCK used
+      uint32_t     m_cpt_cleanup_fsm_heap_used;  // NB cycles HEAP LOCK used
+      uint32_t     m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
+      
+      uint32_t     m_cpt_heap_unused;            // NB cycles HEAP LOCK unused
+
+      //RWT
+      uint32_t     m_cpt_cleanup_data;   
+      uint32_t     m_cpt_ncc_to_cc_read;         // NB change from NCC to CC caused by a READ
+      uint32_t     m_cpt_ncc_to_cc_write;        // NB change from NCC to CC caused by a WRITE
+      uint32_t     m_cpt_ncc_to_cc;              // NB change from NCC to CC
+
+      uint32_t     m_cpt_read_data_unc;
+      uint32_t     m_cpt_read_data_miss_CC;
+      uint32_t     m_cpt_read_ins_unc;
+      uint32_t     m_cpt_read_ins_miss;
+      uint32_t     m_cpt_read_ll_CC;
+      uint32_t     m_cpt_read_data_miss_NCC;
+      uint32_t     m_cpt_read_ll_NCC;
+      uint32_t     m_cpt_read_WTF;
 
       uint32_t     m_cpt_cleanup_cost;  // Number of (flits * distance) for CLEANUPs
@@ -481 +593 @@
       ~VciMemCache();
 
+      void clear_stats();
       void print_stats();
       void print_trace();
@@ -657 +770 @@
       sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
 
+      //RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
+      sc_signal<bool>     r_read_to_cc_send_req;
+      sc_signal<size_t>   r_read_to_cc_send_dest;
+      sc_signal<addr_t>   r_read_to_cc_send_nline;
+      sc_signal<bool>     r_read_to_cc_send_inst;
+
+      //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) 
+      sc_signal<bool>     r_read_to_cleanup_req;    // valid request
+      sc_signal<addr_t>   r_read_to_cleanup_nline;  // cache line index
+      sc_signal<size_t>   r_read_to_cleanup_srcid;
+      sc_signal<size_t>   r_read_to_cleanup_length;
+      sc_signal<size_t>   r_read_to_cleanup_first_word;
+      sc_signal<bool>     r_read_to_cleanup_cached_read;    
+      sc_signal<bool>     r_read_to_cleanup_is_ll;
+      sc_signal<addr_t>   r_read_to_cleanup_addr;
+      sc_signal<addr_t>   r_read_to_cleanup_ll_key;
+
+      //RWT:
+      sc_signal<bool>     r_read_coherent;          // State of the cache slot after transaction
+      sc_signal<bool>     r_read_ll_done;
+
       ///////////////////////////////////////////////////////////////
       // Registers controlled by the WRITE fsm
@@ -721 +855 @@
       sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
 
+      // RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
+      sc_signal<bool>     r_write_to_cleanup_req;         // valid request
+      sc_signal<addr_t>   r_write_to_cleanup_nline;       // cache line index
+
+      // RWT
+      sc_signal<bool>     r_write_coherent;               // cache slot state after transaction
+
+      //Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
+      sc_signal<bool>     r_write_to_cc_send_req;
+      sc_signal<size_t>   r_write_to_cc_send_dest;
+
+
       /////////////////////////////////////////////////////////
       // Registers controlled by MULTI_ACK fsm
@@ -788 +934 @@
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
+      sc_signal<addr_t>     r_cleanup_to_tgt_rsp_ll_key;
+
+      //RWT
+      sc_signal<size_t>   r_cleanup_read_srcid;
+      sc_signal<size_t>   r_cleanup_read_trdid;
+      sc_signal<size_t>   r_cleanup_read_pktid;
+      sc_signal<bool>     r_cleanup_read_need_rsp;
+      sc_signal<bool>     r_cleanup_to_tgt_rsp_type;
+      sc_signal<data_t> * r_cleanup_to_tgt_rsp_data;
+      sc_signal<size_t>   r_cleanup_to_tgt_rsp_length;
+      sc_signal<size_t>   r_cleanup_to_tgt_rsp_first_word;
 
       ///////////////////////////////////////////////////////
@@ -813 +970 @@
       sc_signal<data_t> * r_cas_data;       // cache line data
 
+      sc_signal<bool>     r_cas_coherent;
+
       // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
       sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
@@ -906 +1065 @@
       sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
 
+      //RWT
+      sc_signal<bool>     r_xram_rsp_victim_coherent;      // victim's cache slot state
+      sc_signal<bool>     r_xram_rsp_coherent;             // coherence of the read
       ////////////////////////////////////////////////////
       // Registers controlled by the IXR_CMD fsm
@@ -966 +1128 @@
       sc_signal<int>      r_alloc_heap_fsm;
       sc_signal<unsigned> r_alloc_heap_reset_cpt;
+
+
+      ////////////////////////////////////////////////////
+      // REGISTERS FOR ODCCP
+      ////////////////////////////////////////////////////
+
+      sc_signal<uint32_t>  r_cleanup_data_index;
+      sc_signal<uint32_t>  r_cleanup_trdid;
+      sc_signal<uint32_t>  r_cleanup_pktid;
+      sc_signal<bool>      r_cleanup_coherent;
+      sc_signal<data_t>    *r_cleanup_data;
+      sc_signal<data_t>    *r_cleanup_old_data;
+      sc_signal<bool>      r_cleanup_contains_data;
+      
+      sc_signal<bool>      r_cleanup_ncc;
+      sc_signal<bool>      r_cleanup_to_ixr_cmd_ncc_l1_dirty;
+      sc_signal<bool>      r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
+      
+      sc_signal<bool>      r_cleanup_to_ixr_cmd_req;
+      sc_signal<data_t>    *r_cleanup_to_ixr_cmd_data;
+      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_srcid;
+      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_trdid;
+      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_pktid;
+      sc_signal<addr_t>    r_cleanup_to_ixr_cmd_nline;
     }; // end class VciMemCache
 

branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h

@@ -294 +294 @@
     }
 
+    ///////////////////////////////////////////////////////////////////////
+    // The hit_write() function looks if an XRAM write transaction exists 
+    // for a given line.
+    // Arguments :
+    // - index : (return argument) the index of the hit entry, if there is
+    // - nline : the index (zy) of the requested line
+    // The function returns true if a write request has already been sent
+    ///////////////////////////////////////////////////////////////////////
+    bool hit_write(const addr_t nline, size_t* index)
+    {
+        for(size_t i=0; i<size_tab; i++){
+            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+                *index = i;
+                return true;    
+            }
+        }
+        return false;
+    }
     /////////////////////////////////////////////////////////////////////
     // The write_data_mask() function writes a vector of data (a line).

branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -107 +107 @@
   "CC_SEND_XRAM_RSP_INVAL_HEADER",
   "CC_SEND_XRAM_RSP_INVAL_NLINE",
+  "CC_SEND_READ_NCC_INVAL_HEADER",
+  "CC_SEND_READ_NCC_INVAL_NLINE",
+  "CC_SEND_WRITE_NCC_INVAL_HEADER",
+  "CC_SEND_WRITE_NCC_INVAL_NLINE",
   "CC_SEND_WRITE_BRDCAST_HEADER",
   "CC_SEND_WRITE_BRDCAST_NLINE",
@@ -148 +152 @@
   "READ_DIR_REQ",
   "READ_DIR_LOCK",
+  "READ_IVT_LOCK",
+  "READ_WAIT",
   "READ_DIR_HIT",
   "READ_HEAP_REQ",
@@ -165 +171 @@
   "WRITE_DIR_REQ",
   "WRITE_DIR_LOCK",
+  "WRITE_IVT_LOCK_HIT_WB",
   "WRITE_DIR_READ",
   "WRITE_DIR_HIT",
@@ -173 +180 @@
   "WRITE_UPT_DEC",
   "WRITE_RSP",
+  "WRITE_MISS_IVT_LOCK",
   "WRITE_MISS_TRT_LOCK",
   "WRITE_MISS_TRT_DATA",
@@ -215 +223 @@
   "IXR_CMD_CAS_IDLE",
   "IXR_CMD_XRAM_IDLE",
+  "IXR_CMD_CLEANUP_IDLE",
   "IXR_CMD_READ",
   "IXR_CMD_WRITE",
   "IXR_CMD_CAS",
-  "IXR_CMD_XRAM"
+  "IXR_CMD_XRAM",
+  "IXR_CMD_CLEANUP_DATA"
 };
 const char *cas_fsm_str[] =
@@ -248 +258 @@
   "CLEANUP_IDLE",
   "CLEANUP_GET_NLINE",
+  "CLEANUP_GET_DATA",
   "CLEANUP_DIR_REQ",
   "CLEANUP_DIR_LOCK",
   "CLEANUP_DIR_WRITE",
+  "CLEANUP_IVT_LOCK_DATA",
+  "CLEANUP_IVT_CLEAR_DATA",
+  "CLEANUP_READ_RSP",
   "CLEANUP_HEAP_REQ",
   "CLEANUP_HEAP_LOCK",
@@ -260 +274 @@
   "CLEANUP_IVT_CLEAR",
   "CLEANUP_WRITE_RSP",
+  "CLEANUP_IXR_REQ",
+  "CLEANUP_WAIT",
   "CLEANUP_CONFIG_ACK",
   "CLEANUP_SEND_CLACK"
@@ -279 +295 @@
   "ALLOC_TRT_CAS",
   "ALLOC_TRT_XRAM_RSP",
-  "ALLOC_TRT_IXR_RSP"
+  "ALLOC_TRT_IXR_RSP",
+  "ALLOC_TRT_CLEANUP"
 };
 const char *alloc_upt_fsm_str[] =
@@ -290 +307 @@
 {
   "ALLOC_IVT_WRITE",
+  "ALLOC_IVT_READ",
   "ALLOC_IVT_XRAM_RSP",
   "ALLOC_IVT_CLEANUP",
@@ -339 +357 @@
   : soclib::caba::BaseModule(name),
 
+    m_monitor_ok(false),
     p_clk( "p_clk" ),
     p_resetn( "p_resetn" ),
@@ -526 +545 @@
     r_cas_data                 = new sc_signal<data_t>[nwords];
     r_cas_rdata                = new sc_signal<data_t>[2];
+
+    // Allocation for ODCCP
+    r_cleanup_data             = new sc_signal<data_t>[nwords];
+    r_cleanup_to_ixr_cmd_data  = new sc_signal<data_t>[nwords];
+    r_cleanup_to_tgt_rsp_data  = new sc_signal<data_t>[nwords];
+    r_cleanup_old_data         = new sc_signal<data_t>[nwords];
 
     // Allocation for debug
@@ -641 +666 @@
 
 /////////////////////////////////////////
+tmpl(void) ::clear_stats()
+/////////////////////////////////////////
+{
+
+    m_cpt_cycles                  = 0;
+    m_cpt_read                    = 0;
+    m_cpt_read_miss               = 0;
+    m_cpt_write                   = 0;
+    m_cpt_write_miss              = 0;
+    m_cpt_write_cells             = 0;
+    m_cpt_write_dirty             = 0;
+    m_cpt_update                  = 0;
+    m_cpt_update_mult             = 0;
+    m_cpt_inval_brdcast           = 0;
+    m_cpt_inval                   = 0;
+    m_cpt_inval_mult              = 0;
+    m_cpt_cleanup                 = 0;
+    m_cpt_ll                      = 0;
+    m_cpt_sc                      = 0;
+    m_cpt_cas                     = 0;
+    m_cpt_trt_full                = 0;
+    m_cpt_trt_rb                  = 0;
+    m_cpt_dir_unused              = 0;
+    m_cpt_ivt_unused              = 0;
+    m_cpt_upt_unused              = 0;
+    m_cpt_heap_unused             = 0;
+    m_cpt_trt_unused              = 0;
+    m_cpt_read_fsm_n_dir_lock     = 0;
+    m_cpt_read_fsm_dir_lock       = 0;
+    m_cpt_read_fsm_dir_used       = 0;
+    m_cpt_read_fsm_trt_lock       = 0;
+    m_cpt_read_fsm_heap_lock      = 0;
+    m_cpt_write_fsm_dir_lock      = 0;
+    m_cpt_write_fsm_n_dir_lock    = 0;
+    m_cpt_write_fsm_upt_lock      = 0;
+    m_cpt_write_fsm_heap_lock     = 0;
+    m_cpt_write_fsm_dir_used      = 0;
+    m_cpt_write_fsm_trt_lock      = 0;
+    m_cpt_cas_fsm_n_dir_lock      = 0;
+    m_cpt_cas_fsm_dir_lock        = 0;
+    m_cpt_cas_fsm_upt_lock        = 0;
+    m_cpt_cas_fsm_heap_lock       = 0;
+    m_cpt_cas_fsm_trt_lock        = 0;
+    m_cpt_cas_fsm_dir_used        = 0;
+    m_cpt_xram_rsp_fsm_n_dir_lock = 0;
+    m_cpt_xram_rsp_fsm_dir_lock   = 0;
+    m_cpt_xram_rsp_fsm_trt_lock   = 0;
+    m_cpt_xram_rsp_fsm_upt_lock   = 0;
+    m_cpt_xram_rsp_fsm_heap_lock  = 0;
+    m_cpt_xram_rsp_fsm_dir_used   = 0;
+    m_cpt_cleanup_fsm_dir_lock    = 0;
+    m_cpt_cleanup_fsm_n_dir_lock  = 0;
+    m_cpt_cleanup_fsm_heap_lock   = 0;
+    m_cpt_cleanup_fsm_ivt_lock    = 0;
+    m_cpt_cleanup_fsm_dir_used    = 0;
+    m_cpt_ixr_fsm_trt_lock        = 0;
+    m_cpt_multi_ack_fsm_upt_lock  = 0;
+    m_cpt_read_data_unc           = 0;   
+    m_cpt_read_data_miss_CC       = 0;   
+    m_cpt_read_ins_unc            = 0;        
+    m_cpt_read_ins_miss           = 0;      
+    m_cpt_read_ll_CC              = 0;       
+    m_cpt_read_data_miss_NCC      = 0;        
+    m_cpt_read_ll_NCC             = 0;    
+    m_cpt_read_WTF                = 0;   
+    m_cpt_cleanup_data            = 0;      
+    m_cpt_ncc_to_cc_read          = 0;      
+    m_cpt_ncc_to_cc_write         = 0;       
+    m_cpt_ncc_to_cc               = 0;        
+}
+
+/////////////////////////////////////////
 tmpl(void) ::print_stats()
 /////////////////////////////////////////
@@ -647 +744 @@
   std::cout
       << "MEM_CACHE " << name() << " / Time = " << m_cpt_cycles << std::endl
-      << "- READ RATE            = " << (double) m_cpt_read/m_cpt_cycles << std::endl
-      << "- READ TOTAL           = " << m_cpt_read << std::endl
-      << "- READ MISS RATE       = " << (double) m_cpt_read_miss/m_cpt_read << std::endl
-      << "- WRITE RATE           = " << (double) m_cpt_write/m_cpt_cycles << std::endl
-      << "- WRITE TOTAL          = " << m_cpt_write << std::endl
-      << "- WRITE MISS RATE      = " << (double) m_cpt_write_miss/m_cpt_write << std::endl
-      << "- WRITE BURST LENGTH   = " << (double) m_cpt_write_cells/m_cpt_write << std::endl
-      << "- WRITE BURST TOTAL    = " << m_cpt_write_cells << std::endl
-      << "- REQUESTS TRT FULL    = " << m_cpt_trt_full << std::endl
-      << "- READ TRT BLOKED HIT  = " << m_cpt_trt_rb << std::endl
-      << "- UPDATE RATE          = " << (double) m_cpt_update/m_cpt_cycles << std::endl
-      << "- UPDATE ARITY         = " << (double) m_cpt_update_mult/m_cpt_update << std::endl
-      << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast) /m_cpt_cycles << std::endl
-      << "- INVAL MULTICAST ARITY= " << (double) m_cpt_inval_mult/ (m_cpt_inval-m_cpt_inval_brdcast) << std::endl
-      << "- INVAL BROADCAST RATE = " << (double) m_cpt_inval_brdcast/m_cpt_cycles << std::endl
-      << "- SAVE DIRTY RATE      = " << (double) m_cpt_write_dirty/m_cpt_cycles << std::endl
-      << "- CLEANUP RATE         = " << (double) m_cpt_cleanup/m_cpt_cycles << std::endl
-      << "- LL RATE              = " << (double) m_cpt_ll/m_cpt_cycles << std::endl
-      << "- SC RATE              = " << (double) m_cpt_sc/m_cpt_cycles << std::endl
-      << "- CAS RATE             = " << (double) m_cpt_cas/m_cpt_cycles << std::endl;
+      << "- READ RATE                              = " << (double) m_cpt_read/m_cpt_cycles << std::endl
+      << "- READ TOTAL                             = " << m_cpt_read << std::endl
+      << "- READ MISS RATE                         = " << (double) m_cpt_read_miss/m_cpt_read << std::endl
+      << "- WRITE RATE                             = " << (double) m_cpt_write/m_cpt_cycles << std::endl
+      << "- WRITE TOTAL                            = " << m_cpt_write << std::endl
+      << "- WRITE MISS RATE                        = " << (double) m_cpt_write_miss/m_cpt_write << std::endl
+      << "- WRITE BURST LENGTH                     = " << (double) m_cpt_write_cells/m_cpt_write << std::endl
+      << "- WRITE BURST TOTAL                      = " << m_cpt_write_cells << std::endl
+      << "- REQUESTS TRT FULL                      = " << m_cpt_trt_full << std::endl
+      << "- READ TRT BLOKED HIT                    = " << m_cpt_trt_rb << std::endl
+      << "- UPDATE RATE                            = " << (double) m_cpt_update/m_cpt_cycles << std::endl
+      << "- UPDATE ARITY                           = " << (double) m_cpt_update_mult/m_cpt_update << std::endl
+      << "- INVAL MULTICAST RATE                   = " << (double)(m_cpt_inval-m_cpt_inval_brdcast) /m_cpt_cycles << std::endl
+      << "- INVAL MULTICAST ARITY                  = " << (double) m_cpt_inval_mult/ (m_cpt_inval-m_cpt_inval_brdcast) << std::endl
+      << "- INVAL BROADCAST RATE                   = " << (double) m_cpt_inval_brdcast/m_cpt_cycles << std::endl
+      << "- SAVE DIRTY RATE                        = " << (double) m_cpt_write_dirty/m_cpt_cycles << std::endl
+      << "- CLEANUP RATE                           = " << (double) m_cpt_cleanup/m_cpt_cycles << std::endl
+      << "- LL RATE                                = " << (double) m_cpt_ll/m_cpt_cycles << std::endl
+      << "- SC RATE                                = " << (double) m_cpt_sc/m_cpt_cycles << std::endl
+      << "- CAS RATE                               = " << (double) m_cpt_cas/m_cpt_cycles << std::endl << std::endl
+
+      << "- WAIT DIR LOCK in READ_FSM              = " << (double) m_cpt_read_fsm_dir_lock/m_cpt_read_fsm_n_dir_lock << std::endl
+      << "- NB CYCLES IN DIR LOCK in READ_FSM      = " << (double) m_cpt_read_fsm_dir_used/m_cpt_read_fsm_n_dir_lock << std::endl
+      << "- WAIT DIR LOCK in WRITE_FSM             = " << (double) m_cpt_write_fsm_dir_lock/m_cpt_write_fsm_n_dir_lock << std::endl
+      << "- NB CYCLES IN DIR LOCK in WRITE_FSM     = " << (double) m_cpt_write_fsm_dir_used/m_cpt_write_fsm_n_dir_lock << std::endl
+      << "- WAIT DIR LOCK in XRAM_FSM              = " << (double) m_cpt_xram_rsp_fsm_dir_lock/m_cpt_xram_rsp_fsm_n_dir_lock << std::endl
+      << "- NB CYCLES IN DIR LOCK in XRAM_FSM      = " << (double) m_cpt_xram_rsp_fsm_dir_used/m_cpt_xram_rsp_fsm_n_dir_lock << std::endl
+      << "- WAIT DIR LOCK in CLEANUP_FSM           = " << (double) m_cpt_cleanup_fsm_dir_lock/m_cpt_cleanup_fsm_n_dir_lock << std::endl
+      << "- NB CYCLES IN DIR LOCK in CLEANUP_FSM   = " << (double) m_cpt_cleanup_fsm_dir_used/m_cpt_cleanup_fsm_n_dir_lock << std::endl
+      << "- WAIT DIR LOCK in CAS_FSM               = " << (double) m_cpt_cas_fsm_dir_lock/m_cpt_cas_fsm_n_dir_lock << std::endl
+      << "- NB CYCLES IN LOCK in CAS_FSM           = " << (double) m_cpt_cas_fsm_dir_used/m_cpt_cas_fsm_n_dir_lock << std::endl
+      << "- DIR UNUSED RATE                        = " << (double) m_cpt_dir_unused/m_cpt_cycles << std::endl << std::endl
+      
+      << "- WAIT TRT LOCK in READ_FSM              = " << (double) m_cpt_read_fsm_trt_lock/m_cpt_read_fsm_n_trt_lock << std::endl
+      << "- NB CYCLES IN TRT LOCK in READ_FSM      = " << (double) m_cpt_read_fsm_trt_used/m_cpt_read_fsm_n_trt_lock << std::endl
+      << "- WAIT TRT LOCK in WRITE_FSM             = " << (double) m_cpt_write_fsm_trt_lock/m_cpt_write_fsm_n_trt_lock << std::endl
+      << "- NB CYCLES IN TRT LOCK in WRITE_FSM     = " << (double) m_cpt_write_fsm_trt_used/m_cpt_write_fsm_n_trt_lock << std::endl
+      << "- WAIT TRT LOCK in CAS_FSM               = " << (double) m_cpt_cas_fsm_trt_lock/m_cpt_cas_fsm_n_trt_lock << std::endl
+      << "- NB CYCLES IN TRT LOCK in CAS_FSM       = " << (double) m_cpt_cas_fsm_trt_used/m_cpt_cas_fsm_n_trt_lock << std::endl
+      << "- WAIT TRT LOCK in XRAM_FSM              = " << (double) m_cpt_xram_rsp_fsm_trt_lock/m_cpt_xram_rsp_fsm_n_trt_lock << std::endl
+      << "- NB CYCLES IN TRT LOCK in XRAM_FSM      = " << (double) m_cpt_xram_rsp_fsm_trt_used/m_cpt_xram_rsp_fsm_n_trt_lock << std::endl
+      << "- WAIT TRT LOCK in IXR_FSM               = " << (double) m_cpt_ixr_fsm_trt_lock/m_cpt_ixr_fsm_n_trt_lock << std::endl
+      << "- NB CYCLES IN TRT LOCK in IXR_FSM       = " << (double) m_cpt_ixr_fsm_trt_used/m_cpt_ixr_fsm_n_trt_lock << std::endl
+      << "- TRT UNUSED RATE                        = " << (double) m_cpt_trt_unused/m_cpt_cycles << std::endl << std::endl
+      
+      << "- WAIT UPT LOCK in WRITE_FSM             = " << (double) m_cpt_write_fsm_upt_lock/m_cpt_write_fsm_n_upt_lock << std::endl
+      << "- NB CYCLES IN UPT LOCK in WRITE_FSM     = " << (double) m_cpt_write_fsm_upt_used/m_cpt_write_fsm_n_upt_lock << std::endl
+      << "- WAIT UPT LOCK in XRAM_FSM              = " << (double) m_cpt_xram_rsp_fsm_upt_lock/m_cpt_xram_rsp_fsm_n_upt_lock << std::endl
+      << "- NB CYCLES IN UPT LOCK in XRAM_FSM      = " << (double) m_cpt_xram_rsp_fsm_upt_used/m_cpt_xram_rsp_fsm_n_upt_lock << std::endl
+      << "- WAIT UPT LOCK in MULTIACK_FSM          = " << (double) m_cpt_multi_ack_fsm_upt_lock/m_cpt_multi_ack_fsm_n_upt_lock << std::endl
+      << "- NB CYCLES IN UPT LOCK in MULTIACK_FSM  = " << (double) m_cpt_multi_ack_fsm_upt_used/m_cpt_multi_ack_fsm_n_upt_lock << std::endl
+      << "- WAIT UPT LOCK in CLEANUP_FSM           = " << (double) m_cpt_cleanup_fsm_ivt_lock/m_cpt_cleanup_fsm_n_upt_lock << std::endl
+      << "- NB CYCLES IN UPT LOCK in CLEANUP_FSM   = " << (double) m_cpt_cleanup_fsm_ivt_used/m_cpt_cleanup_fsm_n_upt_lock << std::endl
+      << "- WAIT UPT LOCK in CAS_FSM               = " << (double) m_cpt_cas_fsm_upt_lock/m_cpt_cas_fsm_n_upt_lock << std::endl
+      << "- NB CYCLES IN UPT LOCK in CAS_FSM       = " << (double) m_cpt_cas_fsm_upt_used/m_cpt_cas_fsm_n_upt_lock << std::endl
+      << "- UPT UNUSED RATE                        = " << (double) m_cpt_upt_unused/m_cpt_cycles << std::endl << std::endl
+      << "- IVT UNUSED RATE                        = " << (double) m_cpt_ivt_unused/m_cpt_cycles << std::endl << std::endl
+      
+      << "- WAIT HEAP LOCK in READ_FSM             = " << (double) m_cpt_read_fsm_heap_lock/m_cpt_read_fsm_n_heap_lock << std::endl
+      << "- NB CYCLES IN HEAP LOCK in READ_FSM     = " << (double) m_cpt_read_fsm_heap_used/m_cpt_read_fsm_n_heap_lock << std::endl
+      << "- WAIT HEAP LOCK in WRITE_FSM            = " << (double) m_cpt_write_fsm_heap_lock/m_cpt_write_fsm_n_heap_lock << std::endl
+      << "- NB CYCLES IN HEAP LOCK in WRITE_FSM    = " << (double) m_cpt_write_fsm_heap_used/m_cpt_write_fsm_n_heap_lock << std::endl
+      << "- WAIT HEAP LOCK in XRAM_FSM             = " << (double) m_cpt_xram_rsp_fsm_heap_lock/m_cpt_xram_rsp_fsm_n_heap_lock << std::endl
+      << "- NB CYCLES IN HEAP LOCK in XRAM_FSM     = " << (double) m_cpt_xram_rsp_fsm_heap_used/m_cpt_xram_rsp_fsm_n_heap_lock << std::endl
+      << "- WAIT HEAP LOCK in CLEANUP_FSM          = " << (double) m_cpt_cleanup_fsm_heap_lock/m_cpt_cleanup_fsm_n_heap_lock << std::endl
+      << "- NB CYCLES IN HEAP LOCK in CLEANUP_FSM  = " << (double) m_cpt_cleanup_fsm_heap_used/m_cpt_cleanup_fsm_n_heap_lock << std::endl
+      << "- WAIT HEAP LOCK in CAS_FSM              = " << (double) m_cpt_cas_fsm_heap_lock/m_cpt_cas_fsm_n_heap_lock << std::endl
+      << "- NB CYCLES IN HEAP LOCK in CAS_FSM      = " << (double) m_cpt_cas_fsm_heap_used/m_cpt_cas_fsm_n_heap_lock << std::endl
+      << "- HEAP UNUSED RATE                       = " << (double) m_cpt_heap_unused/m_cpt_cycles << std::endl
+
+      << "- READ DATA UNC                          = " << (double) m_cpt_read_data_unc << std::endl
+      << "- READ DATA MISS CC                      = " << (double) m_cpt_read_data_miss_CC << std::endl
+      << "- READ INS UNC                           = " << (double) m_cpt_read_ins_unc << std::endl
+      << "- READ INS MISS                          = " << (double) m_cpt_read_ins_miss << std::endl
+      << "- READ LL CC                             = " << (double) m_cpt_read_ll_CC << std::endl
+      << "- READ DATA MISS NCC                     = " << (double) m_cpt_read_data_miss_NCC << std::endl
+      << "- READ LL NCC                            = " << (double) m_cpt_read_ll_NCC << std::endl
+      << "- READ OTHER                             = " << (double) m_cpt_read_WTF << std::endl
+      << "- CLEANUP + DATA                         = " << (double) m_cpt_cleanup_data << std::endl
+      << "- NCC TO CC READ                         = " << (double) m_cpt_ncc_to_cc_read << std::endl
+      << "- NCC TO CC WRITE                        = " << (double) m_cpt_ncc_to_cc_write << std::endl
+      << "- NCC TO CC                              = " << (double) m_cpt_ncc_to_cc << std::endl;
 }
 
@@ -685 +844 @@
   delete [] r_write_be;
   delete [] r_write_to_cc_send_data;
+
+  delete [] r_cleanup_data;
+  delete [] r_cleanup_to_ixr_cmd_data;
+  delete [] r_cleanup_to_tgt_rsp_data;
+  delete [] r_cleanup_old_data;
 }
 
@@ -763 +927 @@
     r_read_to_tgt_rsp_req = false;
     r_read_to_ixr_cmd_req = false;
+    r_read_to_cc_send_req = false;
+    r_read_to_cleanup_req = false;
 
     r_write_to_tgt_rsp_req          = false;
@@ -820 +986 @@
     r_tgt_rsp_key_sent  = false;
 
+    // ODCCP
+    r_cleanup_data_index       = 0;
+    r_cleanup_trdid            = 0;
+    r_cleanup_pktid            = 0;
+    r_cleanup_contains_data    = false;
+    r_cleanup_ncc              = false;
+    r_cleanup_to_ixr_cmd_ncc_l1_dirty    = false;
+    r_xram_rsp_to_ixr_cmd_inval_ncc_pending    = false;
+    r_cleanup_to_ixr_cmd_req   = false;
+    r_cleanup_to_ixr_cmd_srcid = 0;
+    r_cleanup_to_ixr_cmd_trdid = 0;
+    r_cleanup_to_ixr_cmd_pktid = 0;
+    r_cleanup_to_ixr_cmd_nline = 0;
+    for (size_t word = 0; word < m_words; word ++)
+    {
+      r_cleanup_to_ixr_cmd_data[word] = 0;
+      r_cleanup_data[word] = 0;
+    }
+
+
     // Activity counters
-    m_cpt_cycles        = 0;
-    m_cpt_read          = 0;
-    m_cpt_read_miss     = 0;
-    m_cpt_write         = 0;
-    m_cpt_write_miss    = 0;
-    m_cpt_write_cells   = 0;
-    m_cpt_write_dirty   = 0;
-    m_cpt_update        = 0;
-    m_cpt_update_mult   = 0;
-    m_cpt_inval_brdcast = 0;
-    m_cpt_inval         = 0;
-    m_cpt_inval_mult    = 0;
-    m_cpt_cleanup       = 0;
-    m_cpt_ll            = 0;
-    m_cpt_sc            = 0;
-    m_cpt_cas           = 0;
-    m_cpt_trt_full      = 0;
-    m_cpt_trt_rb        = 0;
-
+    m_cpt_cycles                  = 0;
+    m_cpt_read                    = 0;
+    m_cpt_read_miss               = 0;
+    m_cpt_write                   = 0;
+    m_cpt_write_miss              = 0;
+    m_cpt_write_cells             = 0;
+    m_cpt_write_dirty             = 0;
+    m_cpt_update                  = 0;
+    m_cpt_update_mult             = 0;
+    m_cpt_inval_brdcast           = 0;
+    m_cpt_inval                   = 0;
+    m_cpt_inval_mult              = 0;
+    m_cpt_cleanup                 = 0;
+    m_cpt_ll                      = 0;
+    m_cpt_sc                      = 0;
+    m_cpt_cas                     = 0;
+    m_cpt_trt_full                = 0;
+    m_cpt_trt_rb                  = 0;
+    m_cpt_dir_unused              = 0;
+    m_cpt_upt_unused              = 0;
+    m_cpt_ivt_unused              = 0;
+    m_cpt_heap_unused             = 0;
+    m_cpt_trt_unused              = 0;
+    m_cpt_read_fsm_n_dir_lock     = 0;
+    m_cpt_read_fsm_dir_lock       = 0;
+    m_cpt_read_fsm_dir_used       = 0;
+    m_cpt_read_fsm_trt_lock       = 0;
+    m_cpt_read_fsm_heap_lock      = 0;
+    m_cpt_write_fsm_dir_lock      = 0;
+    m_cpt_write_fsm_n_dir_lock    = 0;
+    m_cpt_write_fsm_upt_lock      = 0;
+    m_cpt_write_fsm_heap_lock     = 0;
+    m_cpt_write_fsm_dir_used      = 0;
+    m_cpt_write_fsm_trt_lock      = 0;
+    m_cpt_cas_fsm_n_dir_lock      = 0;
+    m_cpt_cas_fsm_dir_lock        = 0;
+    m_cpt_cas_fsm_upt_lock        = 0;
+    m_cpt_cas_fsm_heap_lock       = 0;
+    m_cpt_cas_fsm_trt_lock        = 0;
+    m_cpt_cas_fsm_dir_used        = 0;
+    m_cpt_xram_rsp_fsm_n_dir_lock = 0;
+    m_cpt_xram_rsp_fsm_dir_lock   = 0;
+    m_cpt_xram_rsp_fsm_trt_lock   = 0;
+    m_cpt_xram_rsp_fsm_upt_lock   = 0;
+    m_cpt_xram_rsp_fsm_heap_lock  = 0;
+    m_cpt_xram_rsp_fsm_dir_used   = 0;
+    m_cpt_cleanup_fsm_dir_lock    = 0;
+    m_cpt_cleanup_fsm_n_dir_lock  = 0;
+    m_cpt_cleanup_fsm_heap_lock   = 0;
+    m_cpt_cleanup_fsm_ivt_lock    = 0;
+    m_cpt_cleanup_fsm_dir_used    = 0;
+    m_cpt_ixr_fsm_trt_lock        = 0;
+    m_cpt_multi_ack_fsm_upt_lock  = 0;
+    m_cpt_read_data_unc           = 0;   
+    m_cpt_read_data_miss_CC       = 0;   
+    m_cpt_read_ins_unc            = 0;        
+    m_cpt_read_ins_miss           = 0;      
+    m_cpt_read_ll_CC              = 0;       
+    m_cpt_read_data_miss_NCC      = 0;        
+    m_cpt_read_ll_NCC             = 0;    
+    m_cpt_read_WTF                = 0;   
+    m_cpt_cleanup_data            = 0;      
+    m_cpt_ncc_to_cc_read          = 0;      
+    m_cpt_ncc_to_cc_write         = 0;       
+    m_cpt_ncc_to_cc               = 0;        
     return;
   }
@@ -946 +1178 @@
     if(p_vci_tgt.cmdval)
     {
+
 
 #if DEBUG_MEMC_TGT_CMD
@@ -1106 +1339 @@
             error            = 0;
             r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) |
-                               ((addr_t)p_vci_tgt.wdata.read())<<32;
+                               ((uint64_t)p_vci_tgt.wdata.read())<<32;
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set buf_lines
@@ -1331 +1564 @@
     case MULTI_ACK_UPT_LOCK:
     {
+        m_cpt_multi_ack_fsm_upt_lock++;
         // get lock to the UPDATE table
-        if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break;
+        if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK)  break;
 
         // decrement the number of expected responses
         size_t count = 0;
         bool valid   = m_upt.decrement(r_multi_ack_upt_index.read(), count);
+
+       /*ODCCP*/ //m_upt.print();
 
         if(not valid)
@@ -1361 +1597 @@
           << " entry = "       << r_multi_ack_upt_index.read()
           << " / rsp_count = " << std::dec << count << std::endl;
+        m_cpt_multi_ack_fsm_n_upt_lock++;
 #endif
         break;
@@ -1875 +2112 @@
             << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
 #endif
+        r_read_coherent = false; //WB by default
+        r_read_ll_done  = false;
         r_read_fsm = READ_DIR_REQ;
       }
@@ -1886 +2125 @@
       {
         r_read_fsm = READ_DIR_LOCK;
+        m_cpt_read_fsm_n_dir_lock++;
       }
 
@@ -1892 +2132 @@
 std::cout << "  <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl;
 #endif
+
+      m_cpt_read_fsm_dir_lock++;
+
       break;
     }
@@ -1903 +2146 @@
         DirectoryEntry entry =
           m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
-        // access the global table ONLY when we have an LL cmd
-        if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)   
-        {
-          r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
+        if(((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and not r_read_ll_done.read())   // access the global table ONLY when we have an LL cmd
+        {
+          addr_t      nline      = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
+          r_read_ll_key   = m_llsc_table.ll(nline);
+          //r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
+          /**//*std::cout << "MEMCACHE : from proc " << m_cmd_read_srcid_fifo.read()
+                        << " | @ " << std::hex << m_cmd_read_addr_fifo.read()
+                        << " | LL" << std::endl;*/
+          r_read_ll_done  = true;
         }
         r_read_is_cnt     = entry.is_cnt;
@@ -1926 +2174 @@
         // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
         bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1);
+
+
         if(entry.valid)    // hit
         {
-          // test if we need to register a new copy in the heap
-          if(entry.is_cnt or (entry.count == 0) or !cached_read)
+          r_read_coherent = entry.cache_coherent;
+          if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) //hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request)
           {
-            r_read_fsm = READ_DIR_HIT;
+            // test if we need to register a new copy in the heap
+            if(entry.is_cnt || (entry.count == 0) || !cached_read)
+            {
+              r_read_fsm = READ_DIR_HIT;
+            }
+            else
+            {
+              //std::cout << "is LL = " << ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) << std::endl;
+              //std::cout << "coherent = " << entry.cache_coherent << " | count = " << std::dec << entry.count << " | cached = " << cached_read << std::endl;
+              r_read_fsm = READ_HEAP_REQ;
+            }
           }
-          else
+          else //hit on a WB line owned by an other proc
           {
-            r_read_fsm = READ_HEAP_REQ;
+            r_read_fsm = READ_IVT_LOCK;
           }
         }
@@ -1950 +2210 @@
           << " / hit = " << std::dec << entry.valid
           << " / count = " <<std::dec << entry.count
-          << " / is_cnt = " << entry.is_cnt;
+          << " / is_cnt = " << entry.is_cnt
+          << " / is_coherent = " << entry.cache_coherent;
 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl;
 else                                                std::cout << std::endl;
@@ -1965 +2226 @@
     }
 
+    ///////////////////
+    case READ_IVT_LOCK:
+    {
+      if (r_alloc_ivt_fsm.read() == ALLOC_IVT_READ)
+      {
+        size_t index;
+        addr_t nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
+        /*std::cout << "nline = " << std::dec <<  nline << std::endl
+                  << "inval en cours sur la ligne = " << m_upt.search_inval(nline, index) << std::endl
+                  << "UPT full = " << m_upt.is_full() << std::endl
+                  << "CC_SEND req = " << r_read_to_cc_send_req.read() << std::endl
+                  << "CLENAUP req = " <<r_read_to_cleanup_req.read() << std::endl;*/
+        if(m_upt.search_inval(nline, index) or m_upt.is_full() or r_read_to_cc_send_req.read() or r_read_to_cleanup_req.read()) //Check pending inval
+        {
+          r_read_fsm = READ_WAIT;
+#if DEBUG_MEMC_READ
+        if(m_debug)
+        {
+          std::cout
+              << "  <MEMC " << name() << " READ_IVT_LOCK>" 
+              << " Wait cleanup completion"
+              << std::endl;
+        }
+#endif
+        }
+        else
+        {
+          r_read_to_cc_send_req = true;
+          r_read_to_cc_send_dest = r_read_copy.read();
+          r_read_to_cc_send_nline = nline;
+          r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 
+          r_read_to_cleanup_req = true;
+          r_read_to_cleanup_nline = nline;
+          r_read_to_cleanup_srcid = m_cmd_read_srcid_fifo.read();
+          r_read_to_cleanup_length  = m_cmd_read_length_fifo.read();
+          r_read_to_cleanup_first_word = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
+          r_read_to_cleanup_cached_read = (m_cmd_read_pktid_fifo.read() & 0x1);
+          r_read_to_cleanup_addr = m_cmd_read_addr_fifo.read();
+          r_read_to_cleanup_is_ll= ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL);
+          r_read_to_cleanup_ll_key = r_read_ll_key.read();
+          //std::cout << "cleanup req (read) on line " << nline << " /on proc " << r_read_copy.read() << std::endl;
+
+          m_upt.set(false,  // it's an inval transaction
+                          false,     // it's not a broadcast
+                          false,     // it needs a read response
+                          false,     // no acknowledge required
+                          m_cmd_read_srcid_fifo.read(),
+                          m_cmd_read_trdid_fifo.read(),
+                          m_cmd_read_pktid_fifo.read(),
+                          nline,
+                          0x1, //Expect only one answer
+                          index);
+
+          cmd_read_fifo_get = true;
+          r_read_fsm = READ_IDLE;
+#if DEBUG_MEMC_READ
+        if(m_debug)
+        {
+          std::cout
+              << "  <MEMC " << name() << " READ_IVT_LOCK>" 
+              << " Inval req on an NCC line"
+              << std::endl;
+        }
+#endif
+        }
+      }
+
+
+      break;
+    }
+
     //////////////////
+        case READ_WAIT://Release the locks
+        {
+            r_read_fsm = READ_DIR_REQ;
+#if DEBUG_MEMC_READ
+        if(m_debug)
+        {
+          std::cout
+              << "  <MEMC " << name() << " READ_WAIT>" << std::endl;
+        }
+#endif
+        break;
+        }
+    ///////////////////                      
     case READ_DIR_HIT:    //  read data in cache & update the directory
                           //  we enter this state in 3 cases:
@@ -1996 +2341 @@
         DirectoryEntry entry;
         entry.valid   = true;
+        entry.cache_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read());
+        r_read_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read());
         entry.is_cnt  = is_cnt;
         entry.dirty   = r_read_dirty.read();
@@ -2001 +2348 @@
         entry.lock    = r_read_lock.read();
         entry.ptr     = r_read_ptr.read();
-
         if(cached_read)   // Cached read => we must update the copies
         {
@@ -2034 +2380 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug)
-          std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
-            << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
-            << " / set = " << std::dec << set
-            << " / way = " << way
-            << " / owner_id = " << std::hex << entry.owner.srcid
-            << " / owner_ins = " << std::dec << entry.owner.inst
-            << " / count = " << entry.count
-            << " / is_cnt = " << entry.is_cnt << std::endl;
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
+          << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / set = " << std::dec << set
+          << " / way = " << way
+          << " / owner_id = " << std::hex << entry.owner.srcid
+          << " / owner_ins = " << std::dec << entry.owner.inst
+          << " / coherent = " << entry.cache_coherent
+          << " / count = " << entry.count
+          << " / is_cnt = " << entry.is_cnt << std::endl;
 #endif
 
@@ -2056 +2403 @@
       {
         r_read_fsm = READ_HEAP_LOCK;
+        m_cpt_read_fsm_n_heap_lock++;
       }
 
@@ -2063 +2411 @@
           << " Requesting HEAP lock " << std::endl;
 #endif
+
+      m_cpt_read_fsm_heap_lock++;
+
       break;
     }
@@ -2075 +2426 @@
         bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full();
 
+        if (!r_read_coherent.read())
+        {
+          std::cout << "Address = " << std::hex << (m_cmd_read_addr_fifo.read()) << std::dec << " |count = " << r_read_count.read() << std::endl;
+        }
+        assert (r_read_coherent.read() && "accÚs au heap sur ncc");
         // read data in the cache
         size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
@@ -2086 +2442 @@
         DirectoryEntry entry;
         entry.valid  = true;
+        entry.cache_coherent = r_read_coherent.read();
         entry.is_cnt = go_cnt;
         entry.dirty  = r_read_dirty.read();
@@ -2272 +2629 @@
         r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
         r_read_to_tgt_rsp_srcid  = m_cmd_read_srcid_fifo.read();
+        /*RWT*/
+        //BUG pktid
+        if (r_read_coherent.read())
+        {
+          r_read_to_tgt_rsp_pktid = 0x0 + m_cmd_read_pktid_fifo.read();
+          //std::cout << "READ RSP COHERENT on word" << std::hex << m_x[(addr_t) m_cmd_read_addr_fifo.read()] << std::dec << std::endl;
+        }
+        else
+        {
+          r_read_to_tgt_rsp_pktid = 0x8 + m_cmd_read_pktid_fifo.read();
+        }
         r_read_to_tgt_rsp_trdid  = m_cmd_read_trdid_fifo.read();
-        r_read_to_tgt_rsp_pktid  = m_cmd_read_pktid_fifo.read();
         r_read_to_tgt_rsp_ll_key = r_read_ll_key.read();
         cmd_read_fifo_get        = true;
@@ -2302 +2669 @@
         if(hit_read or !wok or hit_write)    // missing line already requested or no space
         {
-          if(!wok)      m_cpt_trt_full++;
+          if(!wok)
+          {
+            m_cpt_trt_full++;
+          }
           if(hit_read or hit_write)   m_cpt_trt_rb++;
           r_read_fsm = READ_IDLE;
@@ -2319 +2689 @@
           << " / hit_write = " << hit_write
           << " / full = " << !wok << std::endl;
-#endif
-      }
+        m_cpt_read_fsm_n_trt_lock++;
+#endif
+      }
+
+      m_cpt_read_fsm_trt_lock++;
+
       break;
     }
@@ -2341 +2715 @@
                               std::vector<data_t> (m_words,0),
                               r_read_ll_key.read());
+        
 #if DEBUG_MEMC_READ
 if(m_debug)
@@ -2507 +2882 @@
       {
         ///////////////////////////////////////////////////////////////////////
-        // SC command treatment
+        // SC command handling
         // We test the r_write_pending_sc register to know if we are returning
         // from the WAIT state.
@@ -2513 +2888 @@
         // another time from the FIFO. Also, we don't have to test another
         // time if the SC has succeed
+
+        addr_t nline = m_nline[(addr_t)(r_write_address.read())];
         if(((r_write_pktid.read() & 0x7) == TYPE_SC) and not r_write_pending_sc.read())
         {
           if(not m_cmd_write_addr_fifo.rok()) break;
-
+  
           assert(m_cmd_write_eop_fifo.read() and
                  "Error in VCI_MEM_CACHE : "
                  "invalid packet format for SC command");
-
+          //BUG LLSC
           size_t index    = r_write_word_index.read();
-          bool sc_success = m_llsc_table.sc(r_write_address.read()    ,
+          bool sc_success = m_llsc_table.sc(nline    ,
                                             r_write_data[index].read());
-
+  
+          //bool sc_success = m_llsc_table.sc(r_write_address.read()    ,
+          //                                  r_write_data[index].read());
           // consume a word in the FIFO & write it in the local buffer
           cmd_write_fifo_get  = true;
           r_write_data[index] = m_cmd_write_data_fifo.read();
           r_write_sc_fail     = not sc_success;
+          //WARNING: if the SC is a success, it might still fail at next cycle if the line is NCC
           r_write_pending_sc  = true;
-
+  
           if(not sc_success) r_write_fsm = WRITE_RSP;
           else               r_write_fsm = WRITE_DIR_LOCK;
-
+  
           break;
         }
-
+  
         ///////////////////////////////////////////////////////////////////////
         // WRITE command treatment or SC command returning from the WAIT state
@@ -2542 +2922 @@
         // erase any possible new reservation when we release the lock on the
         // directory
-        m_llsc_table.sw(r_write_address.read());
+        m_llsc_table.sw(nline);
+
+        //m_llsc_table.sw(r_write_address.read());
 
         r_write_fsm = WRITE_DIR_LOCK;
+        m_cpt_write_fsm_n_dir_lock++;
       }
 
@@ -2552 +2935 @@
           << std::endl;
 #endif
+
+      m_cpt_write_fsm_dir_lock++;
 
       break;
@@ -2578 +2963 @@
           r_write_ptr        = entry.ptr;
           r_write_way        = way;
-
-          if(entry.is_cnt and entry.count)
+          
+          r_write_coherent   = entry.cache_coherent;
+
+          if (entry.cache_coherent or (entry.owner.srcid == r_write_srcid.read()) or (entry.count == 0)) // hit WT
           {
-            r_write_fsm = WRITE_DIR_READ;
+            if(entry.is_cnt && entry.count)
+            {
+              r_write_fsm = WRITE_DIR_READ;
+            }
+            else
+            {
+             r_write_fsm = WRITE_DIR_HIT;
+            }
           }
           else
           {
-            r_write_fsm = WRITE_DIR_HIT;
+            if (r_write_to_cleanup_req.read())//inval already sent
+            {
+              r_write_fsm = WRITE_WAIT;
+            }
+            else // hit on a NCC line with a different owner
+            {
+              r_write_fsm = WRITE_IVT_LOCK_HIT_WB;
+              if(r_write_pktid.read() == TYPE_SC)
+              {
+                r_write_sc_fail = true;
+              }
+            }
           }
         }
         else  // miss
         {
-          r_write_fsm = WRITE_MISS_TRT_LOCK;
+          r_write_fsm = WRITE_MISS_IVT_LOCK;
         }
 
@@ -2619 +3024 @@
     }
     ////////////////////
+    case WRITE_IVT_LOCK_HIT_WB:
+    {
+      if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
+      {
+
+        size_t index = 0;
+        bool   match_inval;
+        addr_t nline = m_nline[(addr_t)(r_write_address.read())];
+
+        //std::cout << "WRITE on NCC on line" << std::hex << nline << std::dec << std::endl;
+
+        match_inval = m_upt.search_inval(nline, index);
+        assert ((r_write_count.read() == 1) and "NCC to CC req without copy");
+        if(!match_inval and !r_write_to_cc_send_req.read())
+        {
+          r_write_to_cc_send_req = true;
+          r_write_to_cc_send_dest = r_write_copy;
+          r_write_to_cc_send_nline = nline;
+          r_write_to_cleanup_req = true;
+          r_write_to_cleanup_nline = nline;
+
+          m_upt.set(false,  // it's an inval transaction
+                          false,     // it's not a broadcast
+                          true,      // it needs no read response
+                          false,     // no acknowledge required
+                          m_cmd_write_srcid_fifo.read(), //never read, used for debug
+                          m_cmd_write_trdid_fifo.read(), //never read, used for debug
+                          m_cmd_write_pktid_fifo.read(), //never read, used for debug
+                          nline,
+                          0x1, //Expect only one answer
+                          index);
+        }
+        r_write_fsm = WRITE_WAIT;
+#if DEBUG_MEMC_WRITE
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> get access to the UPT: "
+                    << " Inval requested =  " << (!match_inval and !r_write_to_cc_send_req.read())
+                    << std::endl;
+        }
+#endif
+      }
+#if DEBUG_MEMC_WRITE
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> failed to access to the UPT: "
+                    << std::endl;
+        }
+#endif
+      break;
+    }
+
+
+    ////////////////////
     case WRITE_DIR_READ:  // read the cache and complete the buffer when be!=0xF
     {
@@ -2656 +3115 @@
       DirectoryEntry entry;
       entry.valid          = true;
+      entry.cache_coherent = r_write_coherent.read();
       entry.dirty          = true;
       entry.tag            = r_write_tag.read();
@@ -2683 +3143 @@
       // no_update is true when there is no need for coherence transaction
       // (tests for sc requests)
-      bool no_update = ( (r_write_count.read() == 0) or
-                         (owner and (r_write_count.read() ==1) and 
-                         (r_write_pktid.read() != TYPE_SC)));
+      bool no_update = ((r_write_count.read() ==0) || //no need for coherency
+                        (owner && (r_write_count.read() ==1) && (r_write_pktid.read() != TYPE_SC)) || //writer is owner
+                        ((r_write_pktid.read() == TYPE_SC) && r_write_sc_fail.read())); //SC failed: no data update
 
       // write data in the cache if no coherence transaction
-      if(no_update)
+      if(no_update and ((r_write_pktid.read() != TYPE_SC) or !r_write_sc_fail.read()))
       {
         for(size_t word=0 ; word<m_words ; word++)
@@ -2760 +3220 @@
         size_t      set        = m_y[(addr_t)(r_write_address.read())];
         size_t      way        = r_write_way.read();
+
 
         wok = m_upt.set(true,  // it's an update transaction
@@ -2804 +3265 @@
         if(wok) r_write_fsm = WRITE_UPT_HEAP_LOCK;
         else    r_write_fsm = WRITE_WAIT;
-      }
+        m_cpt_write_fsm_n_upt_lock++;
+      }
+
+      m_cpt_write_fsm_upt_lock++;
+
       break;
     }
@@ -2820 +3285 @@
 #endif
         r_write_fsm = WRITE_UPT_REQ;
-      }
+        m_cpt_write_fsm_n_heap_lock++;
+      }
+
+      m_cpt_write_fsm_heap_lock++;
+
       break;
     }
@@ -2834 +3303 @@
              "transaction in WRITE_UPT_REQ state"
             );
+
 
       r_write_to_cc_send_brdcast_req  = false;
@@ -3070 +3540 @@
       break;
     }
+    ///////////////////////// RWT
+    case WRITE_MISS_IVT_LOCK: // Miss : check UPT 
+    {
+      if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
+      {
+        size_t index;
+        if(m_upt.search_inval(m_nline[(addr_t)(r_write_address.read())], index))
+        {
+          r_write_fsm = WRITE_WAIT;
+        }
+        else
+        {
+          r_write_fsm = WRITE_MISS_TRT_LOCK;
+        }
+      }
+      break;
+    }
 
     /////////////////////////
@@ -3087 +3574 @@
         bool    hit_write = m_trt.hit_write(m_nline[addr]);
         bool    wok       = !m_trt.full(wok_index);
-
+        //std::cout << "MEMCACHE : WRITE MISS at " << std::hex << (uint32_t)addr << std::dec << std::endl;
         if(hit_read)      // register the modified data in TRT
         {
@@ -3105 +3592 @@
           m_cpt_trt_full++;
         }
-      }
+        m_cpt_write_fsm_n_trt_lock++;
+      }
+
+      m_cpt_write_fsm_trt_lock++;
+
       break;
     }
@@ -3224 +3715 @@
           << " : wok = " << wok << " / index = " << wok_index << std::endl;
 #endif
-      }
+        m_cpt_write_fsm_n_trt_lock++;
+      }
+
+      m_cpt_write_fsm_trt_lock++;
+
       break;
     }
@@ -3251 +3746 @@
                         nb_copies,
                         index);
-
+       /*ODCCP*/ //m_upt.print();
 #if DEBUG_MEMC_WRITE
 if( m_debug and wok )
@@ -3261 +3756 @@
         if(wok) r_write_fsm = WRITE_BC_DIR_INVAL;
         else    r_write_fsm = WRITE_WAIT;
-      }
+        m_cpt_write_fsm_n_upt_lock++;
+      }
+
+      m_cpt_write_fsm_upt_lock++;
+
       break;
     }
@@ -3295 +3794 @@
       DirectoryEntry entry;
       entry.valid         = false;
+      entry.cache_coherent= false;
       entry.dirty         = false;
       entry.tag         = 0;
@@ -3394 +3894 @@
     ////////////////////////
     case IXR_CMD_READ_IDLE:
-    {
       if     (r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
       else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
       else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_cleanup_to_ixr_cmd_req)  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
       else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
       break;
-    }
     ////////////////////////
     case IXR_CMD_WRITE_IDLE:
-    {
-      if     (r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      if(r_cas_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CAS;
       else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_cleanup_to_ixr_cmd_req)  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
       else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
       else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
       break;
-    }
     ////////////////////////
     case IXR_CMD_CAS_IDLE:
-    {
-      if     (r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      if(r_xram_rsp_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_cleanup_to_ixr_cmd_req)  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
       else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
       else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
       else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
       break;
-    }
     ////////////////////////
     case IXR_CMD_XRAM_IDLE:
-    {
-      if     (r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
-      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
+      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE;
       else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
       else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
       break;
-    }
+      ////////////////////////
+    case IXR_CMD_CLEANUP_IDLE:
+      /*ODCCP*///std::cout << "IXR_CMD_CLEANUP_IDLE" << std::endl;
+      if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
+      break;      
     //////////////////       // send a get from READ FSM
     case IXR_CMD_READ:
@@ -3553 +4058 @@
       break;
     }
+
+      ////////////////////////
+    case IXR_CMD_CLEANUP_DATA:     // send a put command to XRAM
+      /*ODCCP*///std::cout << "IXR_CMD_CLEANUP_DATA" << std::endl;
+      if(p_vci_ixr.cmdack)
+      {
+        if(r_ixr_cmd_cpt.read() == (m_words - 2))
+        {
+          r_ixr_cmd_cpt = 0;
+          r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE;
+          r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;
+          r_cleanup_to_ixr_cmd_req = false;
+        }
+        else
+        {
+          r_ixr_cmd_cpt = r_ixr_cmd_cpt.read() + 2;
+        }
+
+#if DEBUG_MEMC_IXR_CMD
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA> Send a put request to xram" << std::endl;
+        }
+#endif
+      }
+      break;
 
   } // end switch r_ixr_cmd_fsm
@@ -3631 +4162 @@
           << r_ixr_rsp_trt_index.read() << std::endl;
 #endif
-      }
+      m_cpt_ixr_fsm_n_trt_lock++;
+      }
+
+      m_cpt_ixr_fsm_trt_lock++;
+
       break;
     }
@@ -3667 +4202 @@
           << " / data = " << std::hex << data << std::endl;
 #endif
-      }
+      m_cpt_ixr_fsm_n_trt_lock++;
+      }
+      m_cpt_ixr_fsm_trt_lock++;
       break;
     }
@@ -3740 +4277 @@
           << " Get access to DIR and TRT" << std::endl;
 #endif
-      }
+        m_cpt_xram_rsp_fsm_n_dir_lock++;
+        m_cpt_xram_rsp_fsm_n_trt_lock++;
+      }
+      m_cpt_xram_rsp_fsm_dir_lock++;
+      m_cpt_xram_rsp_fsm_trt_lock++;
       break;
     }
@@ -3756 +4297 @@
         DirectoryEntry victim(m_cache_directory.select(set, way));
 
-        bool inval = (victim.count and victim.valid) ;
+        bool inval = (victim.count && victim.valid) or (!victim.cache_coherent and (victim.count == 1)) ;
+
 
         // copy the victim line in a local buffer
@@ -3766 +4308 @@
         r_xram_rsp_victim_copy_cache= victim.owner.cache_id;
 #endif
+        r_xram_rsp_victim_coherent  = victim.cache_coherent;
         r_xram_rsp_victim_copy_inst = victim.owner.inst;
         r_xram_rsp_victim_count     = victim.count;
@@ -3774 +4317 @@
         r_xram_rsp_victim_is_cnt    = victim.is_cnt;
         r_xram_rsp_victim_inval     = inval ;
-        r_xram_rsp_victim_dirty     = victim.dirty;
+        r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); //a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry
+
 
         if(!r_xram_rsp_trt_buf.rerror)
         {
-          r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
+          if (!victim.cache_coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) //there can not be two L2 invalidation on NCC line at the same time
+          {
+            r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+          }
+          else
+          {
+            r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
+          }
         }
         else
@@ -3808 +4359 @@
       {
         size_t index = 0;
-        if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index))  // pending inval
+        size_t index_victim = 0;
+        if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index) or
+           m_ivt.search_inval(r_xram_rsp_victim_nline.read(), index_victim))
         {
           r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
@@ -3824 +4377 @@
         {
           r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+          m_upt.print();
 
 #if DEBUG_MEMC_XRAM_RSP
@@ -3841 +4395 @@
 #endif
         }
-      }
+        m_cpt_xram_rsp_fsm_n_upt_lock++;
+      }
+
+      m_cpt_xram_rsp_fsm_upt_lock++;
+
       break;
     }
@@ -3891 +4449 @@
       DirectoryEntry entry;
       entry.valid   = true;
+      entry.cache_coherent = (inst_read or (not(cached_read))) and (r_xram_rsp_trt_buf.proc_read);
       entry.is_cnt  = false;
       entry.lock    = false;
@@ -3907 +4466 @@
       else
       {
-        entry.owner.srcid    = 0;
+        entry.owner.srcid    = r_xram_rsp_trt_buf.srcid;
 #if L1_MULTI_CACHE
         entry.owner.cache_id = 0;
@@ -3915 +4474 @@
       }
       m_cache_directory.write(set, way, entry);
-
+      //RWT: keep the coherence information in order to send it to the read_rsp
+      r_xram_rsp_coherent = inst_read or (not(cached_read));
       // request an invalidattion request in IVT for victim line
       if(r_xram_rsp_victim_inval.read())
@@ -3922 +4482 @@
         size_t index        = 0;
         size_t count_copies = r_xram_rsp_victim_count.read();
-
+  
         bool   wok = m_ivt.set(false,      // it's an inval transaction
                                broadcast,  // set broadcast bit
@@ -3935 +4495 @@
 
         r_xram_rsp_ivt_index = index;
-
         if(!wok)
         {
@@ -3943 +4502 @@
         }
       }
-
+      if (!r_xram_rsp_victim_coherent.read())
+      {
+        //m_llsc_table.sw(r_xram_rsp_victim_nline.read()*m_words*4);
+        m_llsc_table.sw(r_xram_rsp_victim_nline.read());
+      }
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
@@ -3962 +4525 @@
 #endif
 
-      // If the victim is not dirty, we don't need another XRAM put transaction,
+      // If the victim is not dirty (RWT: if it is not coherent, we can not know wether it is dirty or not), we don't need another XRAM  put transaction,
       // and we can erase the TRT entry
-      if(!r_xram_rsp_victim_dirty.read())  m_trt.erase(r_xram_rsp_trt_index.read());
+      if(!r_xram_rsp_victim_dirty.read() and (r_xram_rsp_victim_coherent.read() or (r_xram_rsp_victim_count.read() == 0)))  m_trt.erase(r_xram_rsp_trt_index.read());
 
       // Next state
-      if(r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+      if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1)))       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
       else if(r_xram_rsp_trt_buf.proc_read)    r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
       else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
@@ -3974 +4537 @@
     }
     ////////////////////////
-    case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (PUT to XRAM) if the victim is dirty
+    case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (write to XRAM) if the victim is dirty or not coherent (RWT)
     {
       if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)
       {
+
         m_trt.set(r_xram_rsp_trt_index.read(),
                               false,       // write to XRAM
@@ -3999 +4563 @@
         else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
         else                                     r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
-      }
+        m_cpt_xram_rsp_fsm_n_trt_lock++;
+      }
+
+      m_cpt_xram_rsp_fsm_trt_lock++;
+
       break;
     }
@@ -4009 +4577 @@
         r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
         r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
-        r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
+        if (r_xram_rsp_coherent.read())
+        {
+          r_xram_rsp_to_tgt_rsp_pktid = 0x0 + r_xram_rsp_trt_buf.pktid;//RWT CC
+        }
+        else
+        {
+          r_xram_rsp_to_tgt_rsp_pktid = 0x8 + r_xram_rsp_trt_buf.pktid;//RWT NCC
+        }
         for(size_t i=0; i < m_words; i++)
         {
@@ -4019 +4594 @@
         r_xram_rsp_to_tgt_rsp_rerror = false;
         r_xram_rsp_to_tgt_rsp_req    = true;
+      
 
         if(r_xram_rsp_victim_inval)      r_xram_rsp_fsm = XRAM_RSP_INVAL;
@@ -4073 +4649 @@
     case XRAM_RSP_WRITE_DIRTY:  // send a write request to IXR_CMD FSM
     {
-      if(!r_xram_rsp_to_ixr_cmd_req.read())
+      if(!r_xram_rsp_to_ixr_cmd_req.read() and !r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())
       {
         r_xram_rsp_to_ixr_cmd_req = true;
@@ -4081 +4657 @@
         {
             r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+              std::cout << "data L2 = " << std::hex << r_xram_rsp_victim_data[i] << std::dec << std::endl;
         }
         m_cpt_write_dirty++;
+        
+        if ((!r_xram_rsp_victim_coherent.read()) and (r_xram_rsp_victim_count.read() == 1)) //if NCC, we save the data in case of not dirty L1
+        {
+          r_xram_rsp_to_ixr_cmd_req = false;
+          r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true;
+          r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          break;
+        }
 
         bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read();
@@ -4105 +4690 @@
       {
         r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+        m_cpt_xram_rsp_fsm_n_heap_lock++;
       }
 
@@ -4112 +4698 @@
           << " Requesting HEAP lock" << std::endl;
 #endif
+
+      m_cpt_xram_rsp_fsm_heap_lock++;
+
       break;
     }
@@ -4278 +4867 @@
       r_cleanup_inst  = (type == DspinDhccpParam::TYPE_CLEANUP_INST);
       r_cleanup_srcid = srcid;
+      r_cleanup_ncc = 
+        DspinDhccpParam::dspin_get(
+            flit,
+            DspinDhccpParam::CLEANUP_NCC);
+      r_cleanup_contains_data = false;
 
       if(srcid >= m_initiators)
@@ -4294 +4888 @@
 
 #if DEBUG_MEMC_CLEANUP
-if(m_debug)
-std::cout << "  <MEMC "         << name()
-          << " CLEANUP_IDLE> Cleanup request:" << std::hex
-          << " / owner_id = "   << srcid
-          << " / owner_ins = "  << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl;
+      if(m_debug)
+      {
+        std::cout
+            << "  <MEMC "         << name()
+            << " CLEANUP_IDLE> Cleanup request:" << std::hex
+            << " / owner_id = "   << srcid
+            << " / owner_ins = "  << (type == DspinDhccpParam::TYPE_CLEANUP_INST)
+            << " / ncc = " << DspinDhccpParam::dspin_get(
+                                                          flit,
+                                                          DspinDhccpParam::CLEANUP_NCC)
+            << std::endl;
+      }
 #endif
       break;
@@ -4312 +4913 @@
       addr_t nline = r_cleanup_nline.read() |
         DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB);
-
+      
+      //A MODIFIER POUR DIRTY //
+      bool eop =
+        DspinDhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP) == 0x1;
+      if (! eop)
+      {
+        r_cleanup_fsm = CLEANUP_GET_DATA;
+        r_cleanup_data_index = 0;
+        r_cleanup_contains_data = true;
+      }
+      else
+      {
+        r_cleanup_fsm = CLEANUP_DIR_REQ;
+      }
       cc_receive_to_cleanup_fifo_get = true;
-      r_cleanup_nline                = nline;
-      r_cleanup_fsm                  = CLEANUP_DIR_REQ;
+      r_cleanup_nline               = nline;
 
 #if DEBUG_MEMC_CLEANUP
-if(m_debug)
-std::cout << "  <MEMC "         << name()
-          << " CLEANUP_GET_NLINE> Cleanup request:"
-          << " / address = " << std::hex << nline * m_words * 4 << std::endl;
-#endif
-      break;
-    }
-
+      if(m_debug)
+      {
+        std::cout
+            << "  <MEMC "         << name()
+            << " CLEANUP_GET_NLINE> Cleanup request:"
+            << std::hex
+            << " / address = "    << nline * m_words * 4
+            << " / contains data = " << (!eop)
+            << std::endl;
+      }
+#endif
+      break;
+    }
+    /////////////////////
+    case CLEANUP_GET_DATA :
+    {
+      if (m_cc_receive_to_cleanup_fifo.rok())
+      {
+        uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
+  
+        uint32_t data = 
+          DspinDhccpParam::dspin_get (flit, DspinDhccpParam::CLEANUP_DATA_UPDT);
+  
+        r_cleanup_data[r_cleanup_data_index] = data;
+        r_cleanup_data_index = r_cleanup_data_index.read() + 1;
+        assert (r_cleanup_data_index.read() < m_words and "MEM_CACHE in CLEANUP_GET_DATA : too much flits in cleanup data updt");
+        cc_receive_to_cleanup_fifo_get = true;
+        if (r_cleanup_data_index.read() == m_words - 1)
+        {
+          r_cleanup_contains_data = true;
+          m_cpt_cleanup_data ++;
+          r_cleanup_fsm = CLEANUP_DIR_REQ;
+        }
+#if DEBUG_MEMC_CLEANUP
+      if(m_debug)
+      {
+        std::cout
+            << "  <MEMC "         << name()
+            << " CLEANUP_GET_DATA> "
+            << " / word = "    << std::dec << r_cleanup_data_index.read()
+            << " / data = " << std::hex << data
+            << std::endl;
+      }
+#endif
+      }
+      break;
+    }
     /////////////////////
     case CLEANUP_DIR_REQ:   // Get the lock to the directory
     {
+      m_cpt_cleanup_fsm_dir_lock++;
       if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break;
 
       r_cleanup_fsm = CLEANUP_DIR_LOCK;
+      //std::cout << " MEM_CACHE : CLEANUP_DIR_REQ" << std::endl;
 
 #if DEBUG_MEMC_CLEANUP
@@ -4337 +4991 @@
 std::cout << "  <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl;
 #endif
+
+      m_cpt_cleanup_fsm_n_dir_lock++;
+
       break;
     }
@@ -4353 +5010 @@
         exit(0);
       }
+      //std::cout << " MEM_CACHE : CLEANUP_DIR_LOCK" << std::endl;
 
       // Read the directory
@@ -4371 +5029 @@
       r_cleanup_copy_cache   = entry.owner.cache_id;
 #endif
+
+      //RWT
+      size_t set = m_y[(addr_t)(cleanup_address)];
+      m_cache_data.read_line(way, set, r_cleanup_old_data); 
+      r_cleanup_coherent = entry.cache_coherent;
+
+
 
       if(entry.valid)      // hit : the copy must be cleared
@@ -4420 +5085 @@
     case CLEANUP_DIR_WRITE:
     {
+      /*ODCCP*///std::cout << "CLEANUP_DIR_WRITE" << std::endl;
       // Update the directory entry without heap access
       if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP)
@@ -4453 +5119 @@
       }
 
+      /*RWT*/
+      bool   inval_request = (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) // NCC to CC initiated by a read transaction
+                          or (r_write_to_cleanup_req.read() and (r_cleanup_nline.read() == r_write_to_cleanup_nline.read())); //NCC to CC initiated by a wrtie transaction
+
+
+      if (inval_request) m_cpt_ncc_to_cc ++;
+
+      if (r_write_to_cleanup_req.read() and (r_cleanup_nline.read() == r_write_to_cleanup_nline.read()))
+      {
+        r_write_to_cleanup_req = false;
+        m_cpt_ncc_to_cc_write ++;
+      }
+
+
       // update the cache directory (for the copies)
       DirectoryEntry entry;
-      entry.valid       = true;
-      entry.is_cnt      = r_cleanup_is_cnt.read();
-      entry.dirty       = r_cleanup_dirty.read();
-      entry.tag         = r_cleanup_tag.read();
-      entry.lock        = r_cleanup_lock.read();
-      entry.ptr         = r_cleanup_ptr.read();
-      entry.count       = r_cleanup_count.read() - 1;
-      entry.owner.srcid = 0;
-      entry.owner.inst  = 0;
-
+      entry.valid          = true;
+      entry.cache_coherent = inval_request or r_cleanup_coherent.read();
+      entry.is_cnt         = r_cleanup_is_cnt.read();
+      entry.dirty          = r_cleanup_dirty.read() or r_cleanup_contains_data.read();
+      entry.tag            = r_cleanup_tag.read();
+      entry.lock           = r_cleanup_lock.read();
+      entry.ptr            = r_cleanup_ptr.read();
+      if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ 
+      {
+        if (r_read_to_cleanup_cached_read.read())
+        {
+          entry.count          = r_cleanup_count.read();
+          entry.owner.srcid    = r_read_to_cleanup_srcid.read();
+          entry.owner.inst     = 0;
 #if L1_MULTI_CACHE
-      entry.owner.cache_id = 0;
-#endif
+          entry.owner.cache_id = r_cleanup_copy_cache.read();
+#endif
+        }
+        else
+        {
+          entry.count          = r_cleanup_count.read() - 1;
+          entry.owner.srcid    = r_cleanup_copy.read();
+          entry.owner.inst     = r_cleanup_copy_inst.read();
+#if L1_MULTI_CACHE
+          entry.owner.cache_id = r_cleanup_copy_cache.read();
+#endif
+        }
+        if (r_read_to_cleanup_is_ll.read())
+        {
+          r_cleanup_to_tgt_rsp_ll_key = r_read_to_cleanup_ll_key.read();
+        }
+      }
+      else
+      {
+        entry.count          = r_cleanup_count.read() - 1;
+        entry.owner.srcid    = 0;
+        entry.owner.inst     = 0;
+#if L1_MULTI_CACHE
+        entry.owner.cache_id = 0;
+#endif
+      }
+
+
+      if (r_cleanup_contains_data.read())
+      {
+        for (size_t word = 0; word < m_words; word ++)
+        {
+          m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF);
+        }
+        m_llsc_table.sw(r_cleanup_nline.read());
+        //m_llsc_table.sw(r_cleanup_nline.read()*m_words*4);
+      }
+
 
       m_cache_directory.write(set, way, entry);
 
-      r_cleanup_fsm = CLEANUP_SEND_CLACK;
+
+      /*RWT*/
+      if (inval_request)
+      {
+        r_cleanup_fsm = CLEANUP_IVT_LOCK_DATA;
+      }
+      else
+      {
+        r_cleanup_fsm = CLEANUP_SEND_CLACK;
+      }
 
 #if DEBUG_MEMC_CLEANUP
@@ -4485 +5214 @@
             << " / count = "   << entry.count
             << " / is_cnt = "  << entry.is_cnt
+            << " / match_inval = " << inval_request
             << std::endl;
       }
@@ -4491 +5221 @@
       break;
     }
-
+    /////////////////////
+    case CLEANUP_IVT_LOCK_DATA://RWT
+    {
+    //Search for a matching inval in the UPT (there must be one) and check if there is a pending read.
+      if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP)
+      {
+        size_t index = 0;
+        bool   match_inval;
+
+        match_inval = m_upt.search_inval(r_cleanup_nline.read(), index);
+        assert (match_inval && "VCI MEM CACHE ERROR: In CLEANUP_IVT_LOCK_DATA, NO CORRESPONDING INVAL");
+        r_cleanup_read_srcid    = m_upt.srcid(index);
+        r_cleanup_read_trdid    = m_upt.trdid(index);
+        r_cleanup_read_pktid    = 0x0 + m_upt.pktid(index);
+        r_cleanup_read_need_rsp = !m_upt.need_rsp(index);
+        r_cleanup_index         = index;
+
+        r_cleanup_fsm = CLEANUP_IVT_CLEAR_DATA;
+      }
+#if DEBUG_MC_CLEANUP
+      if (m_debug)
+      {
+        std::cout
+            << " <MEMC " << name()
+            << " CLEANUP_IVT_LOCK_DATA> fetch pending inval"
+            << std::endl;
+      }
+#endif
+    break;
+    }
+
+    //////////////////////////
+    case CLEANUP_IVT_CLEAR_DATA://RWT
+    {
+      m_upt.clear(r_cleanup_index.read());
+      assert ((r_cleanup_read_need_rsp.read() == (r_read_to_cleanup_req.read() && (r_cleanup_nline.read() == r_read_to_cleanup_nline.read()))) && "condition pending read");
+      if (r_cleanup_read_need_rsp.read())
+      {
+        r_cleanup_fsm = CLEANUP_READ_RSP;
+      }
+      else
+      {
+        r_cleanup_fsm = CLEANUP_SEND_CLACK;
+      }
+#if DEBUG_MC_CLEANUP
+      if (m_debug)
+      {
+        std::cout
+            << " <MEMC " << name()
+            << " CLEANUP_IVT_CLEAR_DATA> clear UPT entry"
+            << std::endl;
+      }
+#endif
+    break;
+    }
+
+    ////////////////////////
+    case CLEANUP_READ_RSP://RWT
+    {
+      if(r_cleanup_to_tgt_rsp_req.read()) break;
+      
+      r_cleanup_to_tgt_rsp_req     = true;
+      r_cleanup_to_tgt_rsp_srcid   = r_cleanup_read_srcid.read();
+      r_cleanup_to_tgt_rsp_trdid   = r_cleanup_read_trdid.read();
+      r_cleanup_to_tgt_rsp_pktid   = 0x0 + r_cleanup_read_pktid.read();//WT
+      r_cleanup_to_tgt_rsp_type    = 0; //Read instruction
+      r_cleanup_to_tgt_rsp_length  = r_read_to_cleanup_length.read();
+      r_cleanup_to_tgt_rsp_first_word  = r_read_to_cleanup_first_word.read();
+      r_read_to_cleanup_req        = false;
+      m_cpt_ncc_to_cc_read ++;
+      if (r_cleanup_contains_data.read()) //L1 was dirty
+      {
+        for(size_t i = 0; i<m_words; i++)
+        {
+          r_cleanup_to_tgt_rsp_data[i] = r_cleanup_data[i].read();
+        }
+      }
+      else //the L2 data are up to date
+      {
+        for(size_t i = 0; i<m_words; i++)
+        {
+          r_cleanup_to_tgt_rsp_data[i] = r_cleanup_old_data[i].read();
+        }        
+      }
+
+      r_cleanup_fsm                = CLEANUP_SEND_CLACK;
+
+#if DEBUG_MC_CLEANUP
+      if (m_debug)
+      {
+        std::cout
+            << " <MEMC " << name()
+            << " CLEANUP_READ_RSP> answer READ"
+            << std::endl;
+      }
+#endif
+    break;
+    }
     //////////////////////
     case CLEANUP_HEAP_REQ:
@@ -4497 +5324 @@
       // get the lock to the HEAP directory
       if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break;
-
+ 
       r_cleanup_fsm = CLEANUP_HEAP_LOCK;
 
@@ -4509 +5336 @@
       }
 #endif
+      m_cpt_cleanup_fsm_n_heap_lock++;
       break;
     }
@@ -4568 +5396 @@
           << " / r_cleanup_copy_inst = " << r_cleanup_copy_inst.read() << std::endl
           << "heap_entry.owner.srcid = " << heap_entry.owner.srcid
-          << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl;
+          << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl
 /**/
+          << "nline = " << r_cleanup_nline << std::endl;
         exit(0);
       }
@@ -4587 +5416 @@
           << " / r_cleanup_copy_inst = " << r_cleanup_copy_inst.read() << std::endl
           << "heap_entry.owner.srcid = " << heap_entry.owner.srcid
-          << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl;
+          << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl
 /**/
-
+          << "nline = " << r_cleanup_nline << std::endl;
         exit(0);
       }
@@ -4595 +5424 @@
       DirectoryEntry dir_entry;
       dir_entry.valid          = true;
+      dir_entry.cache_coherent = true;
       dir_entry.is_cnt         = r_cleanup_is_cnt.read();
       dir_entry.dirty          = r_cleanup_dirty.read();
@@ -4652 +5482 @@
 
       m_cache_directory.write(set,way,dir_entry);
+
 
 #if DEBUG_MEMC_CLEANUP
@@ -4854 +5685 @@
                              // invalidate transaction matching the cleanup 
     {
+      m_cpt_cleanup_fsm_ivt_lock++;
       if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break;
 
@@ -4860 +5692 @@
 
       match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index);
-
       if ( not match_inval )     // no pending inval
       {
@@ -4874 +5705 @@
           << std::endl;
 #endif
-          break;
+        m_cpt_cleanup_fsm_n_upt_lock++;
+        break;
       }
 
@@ -4914 +5746 @@
       m_ivt.decrement(r_cleanup_index.read(), count);
 
+
       if(count == 0)   // multi inval transaction completed
       {
@@ -4920 +5753 @@
       else             // multi inval transaction not completed
       {
-        r_cleanup_fsm = CLEANUP_SEND_CLACK ;
+        if (r_cleanup_ncc.read()) //need to put data to the XRAM
+        {
+          r_cleanup_fsm = CLEANUP_IXR_REQ;
+        }
+        else
+        {
+          r_cleanup_fsm = CLEANUP_SEND_CLACK;
+        }
       }
 
@@ -4950 +5790 @@
       if      ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP;
       else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK;
+      else if ( r_cleanup_ncc.read()      ) r_cleanup_fsm = CLEANUP_IXR_REQ;
       else                                  r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
@@ -4971 +5812 @@
       r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
       r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
-
-      r_cleanup_fsm                = CLEANUP_SEND_CLACK;
+      r_cleanup_to_tgt_rsp_type    = true;
+
+      if (r_cleanup_ncc.read())
+      {
+        r_cleanup_fsm = CLEANUP_IXR_REQ;//need to put data to the XRAM
+      }
+      else
+      {
+        r_cleanup_fsm = CLEANUP_SEND_CLACK;
+      }
 
 #if DEBUG_MEMC_CLEANUP
@@ -5000 +5849 @@
       break;
     }
+
+    /////////////////////////
+    case CLEANUP_IXR_REQ:
+    {
+    
+      //Send a request to the ixr to write the data in the XRAM using the prereserved TRT entry
+      if (r_alloc_trt_fsm.read() == ALLOC_TRT_CLEANUP)
+      {
+        if(!r_cleanup_to_ixr_cmd_req.read())
+        {
+          size_t index = 0;
+          bool   hit   = m_trt.hit_write(r_cleanup_nline.read(), &index); 
+
+          assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT");
+
+            r_cleanup_to_ixr_cmd_req     = true;
+
+            for(size_t i = 0; i < m_words; i++){
+              r_cleanup_to_ixr_cmd_data[i]   = r_cleanup_data[i];
+            }
+
+            r_cleanup_to_ixr_cmd_srcid   = r_cleanup_srcid.read();
+            r_cleanup_to_ixr_cmd_trdid   = index;
+            r_cleanup_to_ixr_cmd_pktid   = r_cleanup_pktid.read();
+            r_cleanup_to_ixr_cmd_nline   = r_cleanup_nline.read();
+            r_cleanup_to_ixr_cmd_ncc_l1_dirty = r_cleanup_contains_data.read();
+            r_cleanup_fsm = CLEANUP_SEND_CLACK;
+#if DEBUG_MEMC_CLEANUP
+      if(m_debug)
+      {
+        std::cout
+            << "  <MEMC " << name()
+            << " CLEANUP_IXR_REQ>"
+            << " request send to IXR_CMD"
+            << std::endl;
+      }
+#endif
+        }
+        else
+        {
+            r_cleanup_fsm = CLEANUP_WAIT;
+#if DEBUG_MEMC_CLEANUP
+      if(m_debug)
+      {
+        std::cout
+            << "  <MEMC " << name()
+            << " CLEANUP_IXR_REQ>"
+            << " waiting completion of previous request"
+            << std::endl;
+      }
+#endif
+        }
+      }
+      break;
+    }
+
+    /////////////////////
+    case CLEANUP_WAIT :
+    {
+      r_cleanup_fsm = CLEANUP_IXR_REQ;
+      break;
+    }
+
     ////////////////////////
     case CLEANUP_SEND_CLACK:  // acknowledgement to a cleanup command
@@ -5102 +6014 @@
       {
         r_cas_fsm = CAS_DIR_LOCK;
+        m_cpt_cas_fsm_n_dir_lock++;
       }
 
@@ -5112 +6025 @@
       }
 #endif
+
+      m_cpt_cas_fsm_dir_lock++;
+
       break;
     }
@@ -5124 +6040 @@
 
         r_cas_is_cnt     = entry.is_cnt;
+        r_cas_coherent   = entry.cache_coherent;
         r_cas_dirty      = entry.dirty;
         r_cas_tag        = entry.tag;
@@ -5171 +6088 @@
       DirectoryEntry entry;
       entry.valid          = true;
+      entry.cache_coherent = r_cas_coherent.read();
       entry.is_cnt         = r_cas_is_cnt.read();
       entry.dirty          = true;
@@ -5238 +6156 @@
     {
       // The CAS is a success => sw access to the llsc_global_table
-      m_llsc_table.sw(m_cmd_cas_addr_fifo.read());
+      // BUG LLSC
+      addr_t      nline      = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
+      m_llsc_table.sw(nline);
+      //m_llsc_table.sw(m_cmd_cas_addr_fifo.read());
+          /**//*std::cout << "MEMCACHE : from proc " << m_cmd_cas_srcid_fifo.read()
+                        << " | @ " << std::hex << m_cmd_cas_addr_fifo.read()
+                        << " | WRITE (cas triggered)" << std::endl;*/
 
       // test coherence request
@@ -5355 +6279 @@
           << " / count = " << nb_copies << std::endl;
 #endif
-      }
+        m_cpt_cas_fsm_n_upt_lock++;
+      }
+
+      m_cpt_cas_fsm_upt_lock++;
+
       break;
     }
@@ -5386 +6314 @@
 #endif
         r_cas_fsm = CAS_UPT_REQ;
-      }
+        m_cpt_cas_fsm_n_heap_lock++;
+      }
+
+      m_cpt_cas_fsm_heap_lock++;
+
       break;
     }
@@ -5526 +6458 @@
           r_cas_fsm = CAS_WAIT;
         }
-      }
+        m_cpt_cas_fsm_n_trt_lock++;
+      }
+
+      m_cpt_cas_fsm_trt_lock++;
+
       break;
     }
@@ -5591 +6527 @@
           r_cas_fsm = CAS_WAIT;
         }
-      }
+        m_cpt_cas_fsm_n_upt_lock++;
+      }
+
+      m_cpt_cas_fsm_upt_lock++;
+
       break;
     }
@@ -5769 +6709 @@
           r_cas_fsm       = CAS_MISS_TRT_SET;
         }
-      }
+        m_cpt_cas_fsm_n_trt_lock++;
+      }
+
+      m_cpt_cas_fsm_trt_lock++;
+
       break;
     }
@@ -5897 +6841 @@
           break;
         }
+
+        if(r_read_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+          break;
+        }
+
+        if(r_write_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+          break;
+        }
+
+
         // WRITE
+        if(r_read_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+          break;
+        }
+
+        if(r_write_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+          break;
+        }
         if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
@@ -5971 +6940 @@
         }
         // WRITE
+        if(r_read_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+          break;
+        }
+
+        if(r_write_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+          break;
+        }
         if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
@@ -6003 +6983 @@
           break;
         }
+
+        if(r_read_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+          break;
+        }
+
+        if(r_write_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+          break;
+        }
+
+
         // WRITE
+        if(r_read_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+          break;
+        }
+
+        if(r_write_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+          break;
+        }
         if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
@@ -6050 +7055 @@
       case CC_SEND_CAS_IDLE:   // CLEANUP FSM has highest priority
       {
+
+        if(r_read_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+          break;
+        }
+
+        if(r_write_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+          break;
+        }
+
+
         if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
@@ -6208 +7227 @@
         break;
       }
+
+    case CC_SEND_READ_NCC_INVAL_HEADER:
+      {
+        if(not p_dspin_m2p.read) break;
+
+        r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_NLINE;
+        break;
+      }
+
+    case CC_SEND_READ_NCC_INVAL_NLINE:
+      {
+        if(not p_dspin_m2p.read) break;
+
+        r_read_to_cc_send_req = false;
+        r_cc_send_fsm = CC_SEND_WRITE_IDLE;
+
+#if DEBUG_MEMC_CC_SEND
+        if(m_debug)
+        {
+          std::cout
+            << "  <MEMC " << name()
+            << " CC_SEND_READ_NCC_INVAL_HEADER> Inval for line "
+            << r_read_to_cc_send_nline.read()
+            << std::endl;
+        }
+#endif
+        break;
+      }
+
+
+    case CC_SEND_WRITE_NCC_INVAL_HEADER:
+      {
+        if(not p_dspin_m2p.read) break;
+
+        r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_NLINE;
+        break;
+      }
+
+    case CC_SEND_WRITE_NCC_INVAL_NLINE:
+      {
+        if(not p_dspin_m2p.read) break;
+
+        r_write_to_cc_send_req = false;
+        r_cc_send_fsm = CC_SEND_WRITE_IDLE;
+
+#if DEBUG_MEMC_CC_SEND
+        if(m_debug)
+        {
+          std::cout
+            << "  <MEMC " << name()
+            << " CC_SEND_WRITE_NCC_INVAL_HEADER> Inval for line "
+            << r_write_to_cc_send_nline.read()
+            << std::endl;
+        }
+#endif
+        break;
+      }
+
+
       //////////////////////////////////
       case CC_SEND_WRITE_BRDCAST_HEADER:   // send first flit broadcast-inval (from WRITE FSM)
@@ -6417 +7495 @@
           break;
 
-        assert(not p_dspin_p2m.eop.read() and
-            "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
-            "CLEANUP command must have two flits");
-
         cc_receive_to_cleanup_fifo_put = true;
-        r_cc_receive_fsm               = CC_RECEIVE_CLEANUP_EOP;
+        if(p_dspin_p2m.eop.read())
+          r_cc_receive_fsm               = CC_RECEIVE_IDLE;
 
         break;
@@ -6439 +7514 @@
 
         cc_receive_to_cleanup_fifo_put = true;
-        r_cc_receive_fsm               = CC_RECEIVE_IDLE;
-
+        if(p_dspin_p2m.eop.read())
+          r_cc_receive_fsm               = CC_RECEIVE_IDLE;
         break;
       }
@@ -6519 +7594 @@
       }
       else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_cleanup_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+      }
       else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
       else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
@@ -6535 +7614 @@
       }
       else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+      else if(r_cleanup_to_tgt_rsp_req) 
+      {
+        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+      }
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+      else if(r_read_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_READ;
+        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+      }
+      break;
+    }
+    ////////////////////////
+    case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority
+    {
+      if(r_cas_to_tgt_rsp_req)            r_tgt_rsp_fsm = TGT_RSP_CAS;
+      else if(r_xram_rsp_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_XRAM;
+        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+      }
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+      else if(r_cleanup_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+      }
+
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+      else if(r_read_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_READ;
+        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+      }
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      break;
+    }
+    ///////////////////////
+    case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority
+    {
+      if(r_xram_rsp_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_XRAM;
+        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+      }
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
+      else if(r_cleanup_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+      }
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+      else if(r_read_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_READ;
+        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+      }
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+      break;
+    }
+    ///////////////////////
+    case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority
+    {
+
+      if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
+      else if(r_cleanup_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+      }
       else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
       else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
@@ -6543 +7697 @@
         r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
       }
-      break;
-    }
-    ////////////////////////
-    case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority
-    {
-      if(r_cas_to_tgt_rsp_req)            r_tgt_rsp_fsm = TGT_RSP_CAS;
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
       else if(r_xram_rsp_to_tgt_rsp_req)
       {
@@ -6554 +7704 @@
         r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
       }
-      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      break;
+    }
+    ////////////////////////////
+    case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority
+    {
+      if(r_cleanup_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+      }
       else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
       else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
@@ -6564 +7722 @@
       }
       else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      break;
-    }
-    ///////////////////////
-    case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority
-    {
-      if(r_xram_rsp_to_tgt_rsp_req)
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+      else if(r_xram_rsp_to_tgt_rsp_req)
       {
         r_tgt_rsp_fsm = TGT_RSP_XRAM;
         r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
       }
-      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
-      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-      else if(r_read_to_tgt_rsp_req)
-      {
-        r_tgt_rsp_fsm = TGT_RSP_READ;
-        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-      }
-      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
-      break;
-    }
-    ///////////////////////
-    case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority
-    {
-
-      if(r_multi_ack_to_tgt_rsp_req)      r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
-      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+      break;
+    }
+    //////////////////////////
+    case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority
+    {
+      if(r_config_to_tgt_rsp_req)         r_tgt_rsp_fsm = TGT_RSP_CONFIG;
       else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
       else if(r_read_to_tgt_rsp_req)
@@ -6607 +7748 @@
         r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
       }
-      break;
-    }
-    ////////////////////////////
-    case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority
-    {
-      if(r_cleanup_to_tgt_rsp_req)        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-      else if(r_read_to_tgt_rsp_req)
-      {
-        r_tgt_rsp_fsm = TGT_RSP_READ;
-        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-      }
-      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
-      else if(r_xram_rsp_to_tgt_rsp_req)
-      {
-        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-      }
-      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-      break;
-    }
-    //////////////////////////
-    case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority
-    {
-      if(r_config_to_tgt_rsp_req)         r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-      else if(r_read_to_tgt_rsp_req)
-      {
-        r_tgt_rsp_fsm = TGT_RSP_READ;
-        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-      }
-      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
-      else if(r_xram_rsp_to_tgt_rsp_req)
-      {
-        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-      }
       else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
-      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_cleanup_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+      }
       break;
     }
@@ -6716 +7821 @@
 #endif
 
+
         uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() +
                                  r_read_to_tgt_rsp_length.read() - 1;
@@ -6728 +7834 @@
           r_read_to_tgt_rsp_req = false;
           r_tgt_rsp_fsm         = TGT_RSP_READ_IDLE;
+          if (r_read_to_tgt_rsp_pktid.read() == 0x0)
+          {
+            m_cpt_read_data_unc ++;
+          }
+          else if (r_read_to_tgt_rsp_pktid.read() == 0x1)
+          {
+            m_cpt_read_data_miss_CC ++;
+          }
+          else if (r_read_to_tgt_rsp_pktid.read() == 0x2)
+          {
+            m_cpt_read_ins_unc ++;
+          }
+          else if (r_read_to_tgt_rsp_pktid.read() == 0x3)
+          {
+            m_cpt_read_ins_miss ++;
+          }
+          else if (r_read_to_tgt_rsp_pktid.read() == 0x6)
+          {
+            m_cpt_read_ll_CC ++;
+          }
+          else if (r_read_to_tgt_rsp_pktid.read() == 0x9)
+          {
+            m_cpt_read_data_miss_NCC ++;
+          }
+          else if (r_read_to_tgt_rsp_pktid.read() == 0x14)
+          {
+            m_cpt_read_ll_NCC ++;
+          }
+          else
+          {
+            m_cpt_read_WTF ++;
+          }
         }
         else
@@ -6768 +7906 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if(m_debug)
-std::cout << "  <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response"
-          << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read()
-          << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
-          << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl;
-#endif
-        r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
-        r_cleanup_to_tgt_rsp_req = false;
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response"
+                    << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read()
+                    << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
+                    << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl
+                    << " / data = " << std::hex << r_cleanup_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() << std::dec << std::endl;
+        }
+#endif
+
+
+        uint32_t last_word_idx = r_cleanup_to_tgt_rsp_first_word.read() + r_cleanup_to_tgt_rsp_length.read() - 1;
+        bool is_ll = ((r_cleanup_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+
+        if (r_cleanup_to_tgt_rsp_type.read() or ((r_tgt_rsp_cpt.read() == last_word_idx) and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll) )
+        {
+          r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
+          r_cleanup_to_tgt_rsp_req = false;
+          r_tgt_rsp_key_sent = false;
+
+
+          if (r_cleanup_to_tgt_rsp_pktid.read() == 0x0)
+          {
+            m_cpt_read_data_unc ++;
+          }
+          else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x1)
+          {
+            m_cpt_read_data_miss_CC ++;
+          }
+          else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x2)
+          {
+            m_cpt_read_ins_unc ++;
+          }
+          else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x3)
+          {
+            m_cpt_read_ins_miss ++;
+          }
+          else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x6)
+          {
+            m_cpt_read_ll_CC ++;
+          }
+          else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x9)
+          {
+            m_cpt_read_data_miss_NCC ++;
+          }
+          else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x14)
+          {
+            m_cpt_read_ll_NCC ++;
+          }
+          else if (!r_cleanup_to_tgt_rsp_type.read())
+          {
+            m_cpt_read_WTF ++;
+          }
+
+        }
+        else
+        {
+          if (is_ll)
+          {
+            r_tgt_rsp_key_sent = true;
+          }
+          else
+          {
+            r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+          }
+        }
+
       }
       break;
@@ -6825 +8022 @@
           r_xram_rsp_to_tgt_rsp_req = false;
           r_tgt_rsp_fsm             = TGT_RSP_XRAM_IDLE;
+
+
+          if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x0)
+          {
+            m_cpt_read_data_unc ++;
+          }
+          else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x1)
+          {
+            m_cpt_read_data_miss_CC ++;
+          }
+          else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x2)
+          {
+            m_cpt_read_ins_unc ++;
+          }
+          else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x3)
+          {
+            m_cpt_read_ins_miss ++;
+          }
+          else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x6)
+          {
+            m_cpt_read_ll_CC ++;
+          }
+          else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x9)
+          {
+            m_cpt_read_data_miss_NCC ++;
+          }
+          else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x14)
+          {
+            m_cpt_read_ll_NCC ++;
+          }
+          else
+          {
+            m_cpt_read_WTF ++;
+          }
+
         }
         else
@@ -6882 +8114 @@
               else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
                   r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
+            
+              else
+                  m_cpt_upt_unused++;
           }
           break;
@@ -6894 +8129 @@
               else if (r_write_fsm.read() == WRITE_UPT_LOCK)
                   r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+            
+              else
+                  m_cpt_upt_unused++;
           }
           break;
@@ -6907 +8145 @@
               else if (r_cas_fsm.read() == CAS_UPT_LOCK)
                   r_alloc_upt_fsm = ALLOC_UPT_CAS;
+            
+              else
+                  m_cpt_upt_unused++;
           }
           break;
@@ -6930 +8171 @@
       //////////////////////////
       case ALLOC_IVT_WRITE:            // allocated to WRITE FSM
-          if (r_write_fsm.read() != WRITE_BC_IVT_LOCK)
+          if ((r_write_fsm.read() != WRITE_BC_IVT_LOCK) and
+             (r_write_fsm.read() != WRITE_IVT_LOCK_HIT_WB) and
+             (r_write_fsm.read() != WRITE_MISS_IVT_LOCK))
           {
-              if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
-
-              else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
-
-              else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)
+            if(r_read_fsm.read() == READ_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_READ;
+            
+            else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
+
+            else if ((r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) or
+                    (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK_DATA))
+              r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
+              
+            else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)
                   r_alloc_ivt_fsm = ALLOC_IVT_CAS;
-
-              else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
+        
+            else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
+
+            else
+              m_cpt_ivt_unused++;
+          }
+          break;
+
+      //////////////////////////
+      case ALLOC_IVT_READ:            // allocated to READ FSM
+          if (r_read_fsm.read() != READ_IVT_LOCK) 
+          {
+            if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
+
+            else if ((r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) or
+                    (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK_DATA))
+              r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
+              
+            else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)
+                  r_alloc_ivt_fsm = ALLOC_IVT_CAS;
+        
+            else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
+          
+            else if ((r_write_fsm.read() == WRITE_BC_IVT_LOCK) or
+                (r_write_fsm.read() == WRITE_IVT_LOCK_HIT_WB) or
+                (r_write_fsm.read() == WRITE_MISS_IVT_LOCK))
+              r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
+
+            else
+              m_cpt_ivt_unused++;
           }
           break;
@@ -6950 +8227 @@
           if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)
           {
-              if(r_cleanup_fsm.read() == CLEANUP_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
-
-              else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CAS;
-
-              else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
-
-              else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
+            if ((r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) or
+                (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK_DATA))
+              r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
+
+            else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_CAS;
+
+            else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
+
+            else if ((r_write_fsm.read() == WRITE_BC_IVT_LOCK) or
+                    (r_write_fsm.read() == WRITE_IVT_LOCK_HIT_WB) or
+                    (r_write_fsm.read() == WRITE_MISS_IVT_LOCK))
+              r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
+
+            else if(r_read_fsm.read() == READ_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_READ;
+            
+            else
+              m_cpt_ivt_unused++;
           }
           break;
@@ -6967 +8253 @@
       case ALLOC_IVT_CLEANUP:          // allocated to CLEANUP FSM
           if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK     ) and
-              (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT))
+              (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT) and
+              (r_cleanup_fsm.read() != CLEANUP_IVT_LOCK_DATA))
           {
-              if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CAS;
-
-              else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
-
-              else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
-
-              else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
+            if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_CAS;
+
+            else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
+
+            else if ((r_write_fsm.read() == WRITE_BC_IVT_LOCK) or
+                (r_write_fsm.read() == WRITE_IVT_LOCK_HIT_WB) or
+                (r_write_fsm.read() == WRITE_MISS_IVT_LOCK))
+              r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
+
+            else if(r_read_fsm.read() == READ_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_READ;
+
+            else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
+
+            else
+              m_cpt_ivt_unused++;
           }
           break;
@@ -6987 +8282 @@
           if (r_cas_fsm.read() != CAS_BC_IVT_LOCK)
           {
-              if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
-
-              else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
-
-              else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
-
-              else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
+            if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
+
+            else if ((r_write_fsm.read() == WRITE_BC_IVT_LOCK) or
+                (r_write_fsm.read() == WRITE_IVT_LOCK_HIT_WB) or
+                (r_write_fsm.read() == WRITE_MISS_IVT_LOCK))
+              r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
+
+            else if(r_read_fsm.read() == READ_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_READ;
+
+            else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
+
+            else if ((r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) or
+                (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK_DATA))
+              r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
+
+            else
+              m_cpt_ivt_unused++;
           }
           break;
@@ -7005 +8309 @@
           if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK)
           {
-              if (r_write_fsm.read() == WRITE_BC_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
-
-              else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
-
-              else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
-
-              else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)
-                  r_alloc_ivt_fsm = ALLOC_IVT_CAS;
+            if ((r_write_fsm.read() == WRITE_BC_IVT_LOCK) or
+                (r_write_fsm.read() == WRITE_IVT_LOCK_HIT_WB) or
+                (r_write_fsm.read() == WRITE_MISS_IVT_LOCK))
+              r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
+
+            else if(r_read_fsm.read() == READ_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_READ;
+
+            else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
+
+            else if ((r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) or
+                (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK_DATA))
+              r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
+      
+            else if(r_cas_fsm.read() == CAS_BC_IVT_LOCK)
+              r_alloc_ivt_fsm = ALLOC_IVT_CAS;
+
+            else
+              m_cpt_ivt_unused++;
           }
           break;
-
   } // end switch r_alloc_ivt_fsm
-
+  
   ////////////////////////////////////////////////////////////////////////////////////
   //    ALLOC_DIR FSM
@@ -7073 +8385 @@
          (r_read_fsm.read()      != READ_DIR_LOCK)   and
          (r_read_fsm.read()      != READ_TRT_LOCK)   and
-         (r_read_fsm.read()      != READ_HEAP_REQ))
+         (r_read_fsm.read()      != READ_HEAP_REQ)   and
+         (r_read_fsm.read()      != READ_IVT_LOCK))
          or
          ((r_read_fsm.read()       == READ_TRT_LOCK)   and
@@ -7089 +8402 @@
         else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
-
+        
         else if(r_config_fsm.read() == CONFIG_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
-    }
-    break;
-
-    /////////////////////
-    case ALLOC_DIR_WRITE:    // allocated to WRITE FSM
-    if(((r_write_fsm.read()       != WRITE_DIR_REQ)  and
-        (r_write_fsm.read()       != WRITE_DIR_LOCK)  and
-        (r_write_fsm.read()       != WRITE_DIR_READ)  and
-        (r_write_fsm.read()       != WRITE_DIR_HIT)  and
-        (r_write_fsm.read()       != WRITE_BC_TRT_LOCK)  and
-        (r_write_fsm.read()       != WRITE_BC_IVT_LOCK)  and
-        (r_write_fsm.read()       != WRITE_MISS_TRT_LOCK)  and
-        (r_write_fsm.read()       != WRITE_UPT_LOCK)  and
-        (r_write_fsm.read()       != WRITE_UPT_HEAP_LOCK))
-        or
-        ((r_write_fsm.read()      == WRITE_UPT_HEAP_LOCK)  and
-         (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE))
-        or
-        ((r_write_fsm.read()      == WRITE_MISS_TRT_LOCK)  and
-         (r_alloc_trt_fsm.read()  == ALLOC_TRT_WRITE)))
-    {
+
+        else
+          m_cpt_dir_unused++;
+      }
+      else
+        m_cpt_read_fsm_dir_used++;
+      break;
+
+      /////////////////////
+    case ALLOC_DIR_WRITE:
+      if(((r_write_fsm.read()       != WRITE_DIR_REQ)  and
+          (r_write_fsm.read()       != WRITE_DIR_LOCK)  and
+          (r_write_fsm.read()       != WRITE_DIR_READ)  and
+          (r_write_fsm.read()       != WRITE_DIR_HIT)  and
+          (r_write_fsm.read()       != WRITE_BC_TRT_LOCK)  and
+          (r_write_fsm.read()       != WRITE_BC_IVT_LOCK)  and
+          (r_write_fsm.read()       != WRITE_MISS_IVT_LOCK)  and
+          (r_write_fsm.read()       != WRITE_MISS_TRT_LOCK)  and
+          (r_write_fsm.read()       != WRITE_UPT_LOCK)  and
+          (r_write_fsm.read()       != WRITE_UPT_HEAP_LOCK) and
+          (r_write_fsm.read()       != WRITE_IVT_LOCK_HIT_WB))
+          or
+          ((r_write_fsm.read()      == WRITE_UPT_HEAP_LOCK)  and
+           (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE))
+          or
+          ((r_write_fsm.read()      == WRITE_MISS_TRT_LOCK)  and
+           (r_alloc_trt_fsm.read()  == ALLOC_TRT_WRITE)))
+      {
         if(r_cas_fsm.read() == CAS_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CAS;
@@ -7127 +8447 @@
         else if(r_read_fsm.read() == READ_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_READ;
-    }
-    break;
+        
+        else
+          m_cpt_dir_unused++;
+      }
+      else
+        m_cpt_write_fsm_dir_used++;
+      break;
 
     ///////////////////
     case ALLOC_DIR_CAS:    // allocated to CAS FSM
-    if(((r_cas_fsm.read()         != CAS_DIR_REQ)  and
+      if(((r_cas_fsm.read()         != CAS_DIR_REQ)  and
         (r_cas_fsm.read()         != CAS_DIR_LOCK)  and
         (r_cas_fsm.read()         != CAS_DIR_HIT_READ)  and
@@ -7148 +8473 @@
         ((r_cas_fsm.read()        == CAS_MISS_TRT_LOCK)  and
          (r_alloc_trt_fsm.read()  == ALLOC_TRT_CAS)))
-    {
+      {
         if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
@@ -7163 +8488 @@
         else if(r_write_fsm.read() == WRITE_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_WRITE;
-    }
-      break;
-
+        
+        else
+          m_cpt_dir_unused++;
+      }
+      else
+        m_cpt_cas_fsm_dir_used++;
+      break;
+      
     ///////////////////////
     case ALLOC_DIR_CLEANUP:    // allocated to CLEANUP FSM
-    if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and
+      if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and
         (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and
         (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and
-        (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK))
-    {
+        (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and
+        (r_cleanup_fsm.read() != CLEANUP_IVT_LOCK_DATA))
+      {
         if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
@@ -7187 +8518 @@
         else if(r_cas_fsm.read() == CAS_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CAS;
-    }
-    break;
+
+        else
+          m_cpt_dir_unused++;
+      }
+      else
+        m_cpt_cleanup_fsm_dir_used++;
+      break;
 
     ////////////////////////
     case ALLOC_DIR_XRAM_RSP:    // allocated to XRAM_RSP FSM
-    if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and
+      if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and
         (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and
         (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
-    {
+      {
         if(r_config_fsm.read() == CONFIG_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
@@ -7210 +8546 @@
         else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
-    }
-    break;
+
+        else
+          m_cpt_dir_unused++;
+      }
+      else
+        m_cpt_xram_rsp_fsm_dir_used++;
+      break;
 
   } // end switch alloc_dir_fsm
@@ -7245 +8586 @@
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
-      }
+
+        else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+          r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
+
+        else
+          m_cpt_trt_unused++;
+      }
+      else
+        m_cpt_read_fsm_trt_used++;
       break;
 
@@ -7265 +8614 @@
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        
+        else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+          r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
         else if(r_read_fsm.read() == READ_TRT_LOCK)
           r_alloc_trt_fsm = ALLOC_TRT_READ;
-      }
+
+        else
+          m_cpt_trt_unused++;
+      }
+      else
+        m_cpt_write_fsm_trt_used++;
       break;
 
@@ -7284 +8641 @@
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        
+        else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+          r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
         else if(r_read_fsm.read() == READ_TRT_LOCK)
@@ -7291 +8651 @@
                 (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_WRITE;
-      }
+
+        else
+          m_cpt_trt_unused++;
+      }
+      else
+        m_cpt_cas_fsm_trt_used++;
       break;
 
@@ -7305 +8670 @@
             (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        
+        else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+          r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
         else if(r_read_fsm.read() == READ_TRT_LOCK)
@@ -7316 +8684 @@
                 (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
-      }
+
+        else
+          m_cpt_trt_unused++;
+      }
+      else
+        m_cpt_xram_rsp_fsm_trt_used++;
       break;
 
@@ -7324 +8697 @@
           (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ))
       {
+        
+        if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+          r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
+
+        else if(r_read_fsm.read() == READ_TRT_LOCK)
+          r_alloc_trt_fsm = ALLOC_TRT_READ;
+
+        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+                (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
+          r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+
+        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+                (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
+          r_alloc_trt_fsm = ALLOC_TRT_CAS;
+
+        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+                (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
+          r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+        else
+          m_cpt_trt_unused++;
+      }
+      else
+        m_cpt_ixr_fsm_trt_used++;
+      break;
+
+      ////////////////////////
+    case ALLOC_TRT_CLEANUP:
+      /*ODCCP*///std::cout << "TRT ALLOCATED TO CLEANUP" << std::endl;
+      if(r_cleanup_fsm.read() != CLEANUP_IXR_REQ)
+      {
         if(r_read_fsm.read() == READ_TRT_LOCK)
           r_alloc_trt_fsm = ALLOC_TRT_READ;
@@ -7338 +8742 @@
                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+            (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
+          r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
       }
       break;
@@ -7388 +8796 @@
         else if(r_config_fsm.read() == CONFIG_HEAP_REQ)
           r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
-      }
+
+        else
+          m_cpt_heap_unused++;
+      }
+      else
+        m_cpt_read_fsm_heap_used++;
       break;
 
@@ -7411 +8824 @@
         else if(r_read_fsm.read() == READ_HEAP_REQ)
           r_alloc_heap_fsm = ALLOC_HEAP_READ;
-      }
+
+        else
+          m_cpt_heap_unused++;
+      }
+      else
+        m_cpt_write_fsm_heap_used++;
       break;
 
@@ -7434 +8852 @@
         else if(r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
           r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
-      }
+
+        else
+          m_cpt_heap_unused++;
+      }
+      else
+        m_cpt_cas_fsm_heap_used++;
       break;
 
@@ -7458 +8881 @@
         else if(r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
           r_alloc_heap_fsm = ALLOC_HEAP_CAS;
-      }
+
+        else
+          m_cpt_heap_unused++;
+      }
+      else
+        m_cpt_cleanup_fsm_heap_used++;
       break;
 
@@ -7503 +8931 @@
         if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
           r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
-      }
+
+        else
+          m_cpt_heap_unused++;
+      }
+      else
+        m_cpt_xram_rsp_fsm_heap_used++;
       break;
 
@@ -7563 +8996 @@
   ////////////////////////////////////////////////////////////////////////////////////
 
-  m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get,
-                                       cc_receive_to_cleanup_fifo_put, 
-                                       p_dspin_p2m.data.read() );
+  if(cc_receive_to_cleanup_fifo_put)
+  {
+    if(cc_receive_to_cleanup_fifo_get)
+    {
+      m_cc_receive_to_cleanup_fifo.put_and_get( ((uint64_t)(p_dspin_p2m.eop.read()&0x1) << 32) | p_dspin_p2m.data.read() );
+    }
+    else
+    {
+      m_cc_receive_to_cleanup_fifo.simple_put( ((uint64_t)(p_dspin_p2m.eop.read()&0x1) << 32) | p_dspin_p2m.data.read() );
+    }
+  }
+  else
+  {
+    if(cc_receive_to_cleanup_fifo_get)
+    {
+      m_cc_receive_to_cleanup_fifo.simple_get();
+    }
+  }
+  //m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get,
+  //                                     cc_receive_to_cleanup_fifo_put, 
+  //                                     p_dspin_p2m.data.read() );
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -7714 +9165 @@
     p_vci_ixr.trdid     = r_xram_rsp_to_ixr_cmd_trdid.read();
     p_vci_ixr.eop       = (r_ixr_cmd_cpt == (m_words-2));
+  } 
+  else if (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_DATA)
+  {
+    p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
+    p_vci_ixr.cmdval  = true;
+    p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + r_ixr_cmd_cpt.read()) * 4);
+    if (r_cleanup_to_ixr_cmd_ncc_l1_dirty.read()) //if L1 was dirty, the correct data is in the cleanup
+    {
+      p_vci_ixr.wdata   = ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 
+          ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32));
+      if(r_cleanup_to_ixr_cmd_nline.read() == 0x12bb)
+        std::cout << "IXR data dirty = " << std::hex << p_vci_ixr.wdata << std::dec << std::endl;
+    }
+    else //if L1 was not dirty, the data is in the L2
+    {
+      p_vci_ixr.wdata   = ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 
+          ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32));
+      if(r_cleanup_to_ixr_cmd_nline.read() == 0x12bb)
+        std::cout << "IXR data not dirty = " << std::hex << p_vci_ixr.wdata << std::dec << std::endl;
+    }
+    p_vci_ixr.trdid   = r_cleanup_to_ixr_cmd_trdid.read();
+    p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words - 2));
   }
   else
@@ -7857 +9330 @@
 
     case TGT_RSP_CLEANUP:
+    {
+      uint32_t last_word_idx = r_cleanup_to_tgt_rsp_first_word.read() + r_cleanup_to_tgt_rsp_length - 1;
+      bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
+      bool     is_ll         = ((r_cleanup_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+
       p_vci_tgt.rspval   = true;
-      p_vci_tgt.rdata    = 0;
+      if (is_ll and not r_tgt_rsp_key_sent.read())
+      {
+        p_vci_tgt.rdata   = r_cleanup_to_tgt_rsp_ll_key.read();
+      }
+      else if (!r_cleanup_to_tgt_rsp_type.read())
+      {
+        p_vci_tgt.rdata    = r_cleanup_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+      }
+      else  //if the CLEANUP fsm sends a SC_RSP, then it is a success (and it caused an inval)
+      {
+        p_vci_tgt.rdata    = 0;
+      }
       p_vci_tgt.rsrcid   = r_cleanup_to_tgt_rsp_srcid.read();
       p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
       p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
       p_vci_tgt.rerror   = 0; // Can be a CAS rsp
-      p_vci_tgt.reop     = true;
-      break;
+      p_vci_tgt.reop     = r_cleanup_to_tgt_rsp_type.read() or (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll);
+      break;
+    }
 
     case TGT_RSP_CAS:
@@ -7885 +9375 @@
       p_vci_tgt.rspval  = true;
 
-      if( is_ll and not r_tgt_rsp_key_sent.read() ) {
+      if( is_ll and not r_tgt_rsp_key_sent.read() ) 
+      {
         // LL response first flit
         p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read();
       }
-      else {
+      else 
+      {
         // LL response second flit or READ response
         p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
@@ -7900 +9392 @@
       p_vci_tgt.reop    = (((is_last_word or is_error) and not is_ll) or
                             (r_tgt_rsp_key_sent.read() and     is_ll));
+
       break;
     }
@@ -8081 +9574 @@
     }
     /////////////////////////////////
+
+  case CC_SEND_READ_NCC_INVAL_HEADER:
+    {
+      uint64_t flit = 0;
+
+      uint8_t multi_inval_type;
+      if (r_read_to_cc_send_inst.read())
+      {
+        multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST;
+      }
+      else
+      {
+        multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA;
+      }
+
+      DspinDhccpParam::dspin_set(
+          flit,
+          r_read_to_cc_send_dest.read(),
+          DspinDhccpParam::MULTI_INVAL_DEST);
+
+      DspinDhccpParam::dspin_set(
+          flit,
+          m_cc_global_id,
+          DspinDhccpParam::MULTI_INVAL_SRCID);
+
+      DspinDhccpParam::dspin_set(
+          flit,
+          DspinDhccpParam::TYPE_MULTI_INVAL_DATA,
+          DspinDhccpParam::M2P_TYPE);
+
+      p_dspin_m2p.write = true;
+      p_dspin_m2p.data  = flit;
+
+      break;
+
+    }
+
+
+    case CC_SEND_READ_NCC_INVAL_NLINE:
+    {
+      uint64_t flit = 0;
+
+      DspinDhccpParam::dspin_set(
+          flit,
+          r_read_to_cc_send_nline.read(),
+          DspinDhccpParam::MULTI_INVAL_NLINE);
+
+
+      p_dspin_m2p.write = true;
+      p_dspin_m2p.data  = flit;
+      p_dspin_m2p.eop   = true;
+
+      break;
+
+    }
+
+    case CC_SEND_WRITE_NCC_INVAL_HEADER:
+    {
+      uint64_t flit = 0;
+
+      DspinDhccpParam::dspin_set(
+          flit,
+          r_write_to_cc_send_dest.read(),
+          DspinDhccpParam::MULTI_INVAL_DEST);
+
+      DspinDhccpParam::dspin_set(
+          flit,
+          m_cc_global_id,
+          DspinDhccpParam::MULTI_INVAL_SRCID);
+
+      DspinDhccpParam::dspin_set(
+          flit,
+          DspinDhccpParam::TYPE_MULTI_INVAL_DATA,
+          DspinDhccpParam::M2P_TYPE);
+
+      p_dspin_m2p.write = true;
+      p_dspin_m2p.data  = flit;
+
+      break;
+
+    }
+
+    case CC_SEND_WRITE_NCC_INVAL_NLINE:
+    {
+      uint64_t flit = 0;
+
+      DspinDhccpParam::dspin_set(
+          flit,
+          r_write_to_cc_send_nline.read(),
+          DspinDhccpParam::MULTI_INVAL_NLINE);
+
+
+      p_dspin_m2p.write = true;
+      p_dspin_m2p.data  = flit;
+      p_dspin_m2p.eop   = true;
+
+      break;
+
+    }
+
+
     case CC_SEND_WRITE_BRDCAST_NLINE:
     {