Changeset 477 for branches/RWT
- Timestamp:
- Jul 26, 2013, 5:03:12 PM (11 years ago)
- Location:
- branches/RWT
- Files:
-
- 4 added
- 8 edited
- 5 copied
Legend:
- Unmodified
- Added
- Removed
-
branches/RWT/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h
r468 r477 41 41 * 42 42 * flit 1 43 * ---------------------------------------------------------------------------------------------- 44 * EOP:0 | DEST | SRCID | NLINE MSB(2 bits)| X| WAY_INDEX(2 bits) | TYPE:0b1X | BC:045 * | (10 bits) | (14 bits) | | | | |46 * ---------------------------------------------------------------------------------------------- 43 * -------------------------------------------------------------------------------------------------------- 44 * EOP:0 | DEST | SRCID | NLINE MSB(2 bits)| CONTAINS_DATA | WAY_INDEX(2 bits) | TYPE:0b1X | BC:0 45 * | (10 bits) | (14 bits) | | | | | 46 * -------------------------------------------------------------------------------------------------------- 47 47 * | X: 0 DATA | 48 48 * | 1 INST | 49 49 * flit 2 50 50 * ---------------------------------------------------------------------------------------------- 51 * EOP:1 | NLINE(32 bits) 51 * EOP:0/1 | NLINE(32 bits) 52 * ---------------------------------------------------------------------------------------------- 53 * 54 * flit N for data 55 * ---------------------------------------------------------------------------------------------- 56 * EOP:0/1 | WDATA(32 bits) 52 57 * ---------------------------------------------------------------------------------------------- 53 58 * … … 175 180 static const uint8_t CLEANUP_NLINE_LSB_SHIFT = 0; 176 181 static const uint64_t CLEANUP_NLINE_LSB_MASK = ((1ULL<<32)-1); 182 static const uint8_t CLEANUP_DATA_UPDT_SHIFT = 0; 183 static const uint64_t CLEANUP_DATA_UPDT_MASK = ((1ULL<<32)-1); 184 static const uint8_t CLEANUP_NCC_SHIFT = 5; 185 static const uint64_t CLEANUP_NCC_MASK = 1; 177 186 178 187 static const uint8_t MULTI_ACK_DEST_SHIFT = CLEANUP_DEST_SHIFT; … … 277 286 CLEANUP_WAY_INDEX, 278 287 CLEANUP_NLINE_LSB, 288 CLEANUP_DATA_UPDT, 289 CLEANUP_NCC, 279 290 280 291 MULTI_ACK_DEST, … … 321 332 GET_FIELD(flit,CLEANUP_WAY_INDEX); 322 333 GET_FIELD(flit,CLEANUP_NLINE_LSB); 334 GET_FIELD(flit,CLEANUP_DATA_UPDT); 335 GET_FIELD(flit,CLEANUP_NCC); 323 336 GET_FIELD(flit,MULTI_ACK_DEST); 324 337 GET_FIELD(flit,MULTI_ACK_UPDT_INDEX); … … 361 374 SET_FIELD(flit,value,CLEANUP_WAY_INDEX); 362 375 SET_FIELD(flit,value,CLEANUP_NLINE_LSB); 376 SET_FIELD(flit,value,CLEANUP_DATA_UPDT); 377 SET_FIELD(flit,value,CLEANUP_NCC); 363 378 SET_FIELD(flit,value,MULTI_ACK_DEST); 364 379 SET_FIELD(flit,value,MULTI_ACK_UPDT_INDEX); -
branches/RWT/lib/generic_cache_tsar/include/generic_cache.h
r393 r477 76 76 { 77 77 CACHE_SLOT_STATE_EMPTY, 78 CACHE_SLOT_STATE_VALID ,78 CACHE_SLOT_STATE_VALID_CC, 79 79 CACHE_SLOT_STATE_ZOMBI, 80 CACHE_SLOT_STATE_VALID_NCC, 80 81 }; 81 82 … … 118 119 return r_lru[(way*m_sets)+set]; 119 120 } 120 121 121 122 ////////////////////////////////////////////// 122 123 inline int &cache_state(size_t way, size_t set) … … 125 126 } 126 127 128 127 129 ///////////////////////////////////////////////// 128 130 inline void cache_set_lru(size_t way, size_t set) … … 218 220 } 219 221 222 inline int get_cache_state(int way, int set) 223 { 224 return cache_state(way,set); 225 } 226 220 227 ///////////////////////////////////////////////////////////////////// 221 228 // Read a single 32 bits word. … … 233 240 { 234 241 if ( (tag == cache_tag(way, set)) 235 && ( cache_state(way, set) == CACHE_SLOT_STATE_VALID) )242 && ( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)) ) 236 243 { 237 244 *dt = cache_data(way, set, word); … … 262 269 { 263 270 if ( (tag == cache_tag(way, set)) and 264 ( cache_state(way, set) == CACHE_SLOT_STATE_VALID))271 ( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC))) 265 272 { 266 273 *selway = way; … … 308 315 { 309 316 310 if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID )317 if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC ) 311 318 { 312 *state = CACHE_SLOT_STATE_VALID; 319 *state = CACHE_SLOT_STATE_VALID_CC; 320 *selway = way; 321 *selset = set; 322 *selword = word; 323 *dt = cache_data(way, set, word); 324 cache_set_lru(way, set); 325 } 326 else if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC ) 327 { 328 *state = CACHE_SLOT_STATE_VALID_NCC; 313 329 *selway = way; 314 330 *selset = set; … … 347 363 { 348 364 if ( (tag == cache_tag(way, set)) 349 && ( cache_state(way, set) == CACHE_SLOT_STATE_VALID) )365 && ( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC) ) ) 350 366 { 351 367 *selway = way; … … 382 398 { 383 399 if ( (tag == cache_tag(way, set)) 384 && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) )400 &&( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) ) 385 401 { 386 402 *dt = cache_data(way, set, word); … … 433 449 { 434 450 435 if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID )451 if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC ) 436 452 { 437 *state = CACHE_SLOT_STATE_VALID ;453 *state = CACHE_SLOT_STATE_VALID_CC; 438 454 *selway = way; 439 455 *selset = set; … … 446 462 cache_set_lru(way, set); 447 463 } 464 465 else if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC ) 466 { 467 *state = CACHE_SLOT_STATE_VALID_NCC; 468 *selway = way; 469 *selset = set; 470 *selword = word; 471 *dt = cache_data(way, set, word); 472 if ( word+1 < m_words) 473 { 474 *dt_next = cache_data(way, set, word+1); 475 } 476 cache_set_lru(way, set); 477 } 478 448 479 else if ( cache_state(way, set) == CACHE_SLOT_STATE_ZOMBI ) 449 480 { … … 477 508 { 478 509 if ( (tag == cache_tag(way, set)) 479 && ( cache_state(way, set) == CACHE_SLOT_STATE_VALID) )510 && ( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)or(cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC) ) ) 480 511 { 481 512 *selway = way; … … 509 540 const size_t ad_set = m_y[ad]; 510 541 const size_t ad_word = m_x[ad]; 511 512 542 for ( size_t _way = 0; _way < m_ways; _way++ ) 513 543 { … … 556 586 data_t data) 557 587 { 588 /**/ //std::cout << "write cache : way = "<<way<<" | set = "<<set<<" | word = "<<word<<" | data = "<<(uint32_t)data << std::endl; 558 589 cache_data(way, set, word) = data; 559 590 cache_set_lru(way, set); … … 584 615 addr_t* nline) 585 616 { 586 if ( cache_state(way,set) == CACHE_SLOT_STATE_VALID )617 if( (cache_state(way,set) == CACHE_SLOT_STATE_VALID_CC) or (cache_state(way,set) == CACHE_SLOT_STATE_VALID_NCC)) 587 618 { 588 619 cache_state(way,set) = CACHE_SLOT_STATE_EMPTY; … … 615 646 for ( size_t _way = 0 ; _way < m_ways && !found ; _way++ ) 616 647 { 617 if ( cache_state(_way, *set) != CACHE_SLOT_STATE_VALID) // empty648 if( ( cache_state(_way, *set) != CACHE_SLOT_STATE_VALID_CC ) and ( cache_state(_way, *set) != CACHE_SLOT_STATE_VALID_NCC )) // empty 618 649 { 619 650 found = true; … … 674 705 } 675 706 } 707 ////////////////////////////////////////////////////////////// 708 /*for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ ) 709 { 710 if ( not cache_lru(_way, _set) and 711 (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI) and 712 (cache_state(_way, _set) == CACHE_SLOT_STATE_VALID_NCC) ) 713 { 714 *found = true; 715 *cleanup = true; 716 *way = _way; 717 *set = m_y[ad]; 718 *victim = (addr_t)((cache_tag(*way,_set) * m_sets) + _set); 719 return; 720 } 721 }*/ 676 722 // Search first not zombi old slot 677 723 for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ ) … … 718 764 719 765 cache_tag(way, set) = tag; 720 cache_state(way, set) = CACHE_SLOT_STATE_VALID ;766 cache_state(way, set) = CACHE_SLOT_STATE_VALID_CC; 721 767 cache_set_lru(way, set); 722 768 } … … 733 779 addr_t tag = m_z[ad]; 734 780 735 assert( ( (state == CACHE_SLOT_STATE_VALID) or 781 assert( ( (state == CACHE_SLOT_STATE_VALID_CC) or 782 (state == CACHE_SLOT_STATE_VALID_NCC) or 736 783 (state == CACHE_SLOT_STATE_ZOMBI) or 737 784 (state == CACHE_SLOT_STATE_EMPTY) ) and … … 747 794 cache_state(way, set) = state; 748 795 749 if ( state == CACHE_SLOT_STATE_VALID) cache_set_lru(way, set);796 if ( (state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC) ) cache_set_lru(way, set); 750 797 } 751 798 … … 759 806 int state) 760 807 { 761 assert( ( (state == CACHE_SLOT_STATE_VALID) or 808 assert( ( (state == CACHE_SLOT_STATE_VALID_CC) or 809 (state == CACHE_SLOT_STATE_VALID_NCC) or 762 810 (state == CACHE_SLOT_STATE_ZOMBI) or 763 811 (state == CACHE_SLOT_STATE_EMPTY) ) and … … 772 820 cache_state(way, set) = state; 773 821 774 if ( state == CACHE_SLOT_STATE_VALID) cache_set_lru(way, set);822 if ( (state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC) ) cache_set_lru(way, set); 775 823 } 776 824 … … 788 836 789 837 cache_tag(way, set) = tag; 790 cache_state(way, set) = CACHE_SLOT_STATE_VALID ;838 cache_state(way, set) = CACHE_SLOT_STATE_VALID_CC; 791 839 cache_set_lru(way, set); 792 840 for ( size_t word = 0 ; word < m_words ; word++ ) … … 835 883 std::cout << " | " << cache_data(way,set,word) ; 836 884 } 837 std::cout << std:: endl ;885 std::cout << std::dec << std::endl ; 838 886 } 839 887 } … … 853 901 { 854 902 if ( (tag == cache_tag(way, set)) and 855 (cache_state(way, set) == CACHE_SLOT_STATE_VALID ) )903 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 856 904 { 857 905 hit = true; … … 878 926 { 879 927 if ( (tag == cache_tag(way, set)) and 880 (cache_state(way, set) == CACHE_SLOT_STATE_VALID ) )928 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 881 929 { 882 930 hit = true; … … 923 971 { 924 972 if ( (tag == cache_tag(way, set)) and 925 (cache_state(way, set) == CACHE_SLOT_STATE_VALID ) )973 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 926 974 { 927 975 cache_data(way, set, word) = dt; … … 948 996 { 949 997 if ( (tag == cache_tag(way, set)) and 950 (cache_state(way, set) == CACHE_SLOT_STATE_VALID ) )998 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 951 999 { 952 1000 data_t mask = be2mask(be); … … 975 1023 { 976 1024 if ( (tag == cache_tag(way, set)) and 977 (cache_state(way, set) == CACHE_SLOT_STATE_VALID ) )1025 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 978 1026 { 979 1027 cache_data(way, set, word) = dt; … … 1002 1050 { 1003 1051 if ( (tag == cache_tag(way, set)) and 1004 (cache_state(way, set) == CACHE_SLOT_STATE_VALID ) )1052 (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) ) 1005 1053 { 1006 1054 data_t mask = be2mask(be); -
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r468 r477 115 115 DCACHE_XTN_IT_INVAL, 116 116 DCACHE_XTN_DC_FLUSH, 117 DCACHE_XTN_DC_FLUSH_DATA, 117 118 DCACHE_XTN_DC_FLUSH_GO, 118 119 DCACHE_XTN_DC_INVAL_VA, … … 120 121 DCACHE_XTN_DC_INVAL_END, 121 122 DCACHE_XTN_DC_INVAL_GO, 123 DCACHE_XTN_DC_INVAL_DATA, 122 124 DCACHE_XTN_DT_INVAL, 123 125 //handling dirty bit update … … 127 129 DCACHE_MISS_SELECT, 128 130 DCACHE_MISS_CLEAN, 131 DCACHE_MISS_DATA, 129 132 DCACHE_MISS_WAIT, 130 133 DCACHE_MISS_DATA_UPDT, … … 138 141 DCACHE_CC_UPDT, 139 142 DCACHE_CC_INVAL, 143 DCACHE_CC_INVAL_DATA, 140 144 // handling TLB inval (after a coherence or XTN request) 141 145 DCACHE_INVAL_TLB_SCAN, … … 188 192 CC_SEND_CLEANUP_1, 189 193 CC_SEND_CLEANUP_2, 194 CC_SEND_CLEANUP_DATA_UPDT, 190 195 CC_SEND_MULTI_ACK, 191 196 }; … … 283 288 TYPE_INS_MISS = 0x3, 284 289 }; 290 291 //////////////////MODIFIED//////////////// 292 enum content_line_cache_status_e 293 { 294 LINE_CACHE_DATA_NOT_DIRTY, 295 LINE_CACHE_DATA_DIRTY, 296 LINE_CACHE_IN_TLB, 297 LINE_CACHE_CONTAINS_PTD, 298 }; 299 ////////////////////////////////////////// 285 300 286 301 public: … … 390 405 // communication between ICACHE FSM and CC_SEND FSM 391 406 sc_signal<bool> r_icache_cc_send_req; // ICACHE cc_send request 392 sc_signal< cc_send_t>r_icache_cc_send_type; // ICACHE cc_send request type407 sc_signal<int> r_icache_cc_send_type; // ICACHE cc_send request type 393 408 sc_signal<paddr_t> r_icache_cc_send_nline; // ICACHE cc_send nline 394 409 sc_signal<size_t> r_icache_cc_send_way; // ICACHE cc_send way … … 429 444 sc_signal<uint32_t> r_dcache_vci_sc_data; // SC data (command) 430 445 446 //RWT: local cas 447 sc_signal<bool> r_cas_islocal; 448 sc_signal<size_t> r_cas_local_way; 449 sc_signal<size_t> r_cas_local_set; 450 sc_signal<size_t> r_cas_local_word; 451 431 452 // register used for XTN inval 432 453 sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) … … 447 468 sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval 448 469 sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval 470 sc_signal<int> r_dcache_cc_state; // state of selected cache slot 449 471 sc_signal<size_t> r_dcache_cc_word; // word counter for cc update 450 472 sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing 473 sc_signal<paddr_t> r_dcache_cc_inval_addr; // address for a cleanup transaction 474 sc_signal<uint32_t> r_dcache_cc_inval_data_cpt; 451 475 452 476 // coherence clack handling … … 483 507 // communication between DCACHE FSM and CC_SEND FSM 484 508 sc_signal<bool> r_dcache_cc_send_req; // DCACHE cc_send request 485 sc_signal< cc_send_t>r_dcache_cc_send_type; // DCACHE cc_send request type509 sc_signal<int> r_dcache_cc_send_type; // DCACHE cc_send request type 486 510 sc_signal<paddr_t> r_dcache_cc_send_nline; // DCACHE cc_send nline 487 511 sc_signal<size_t> r_dcache_cc_send_way; // DCACHE cc_send way 488 512 sc_signal<size_t> r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index 489 513 514 // special registers for ODCCP/RWT 515 sc_signal<bool> r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt) 516 sc_signal<bool> r_dcache_cc_cleanup_line_ncc; // Register for cleanup with data (wb updt) 517 sc_signal<bool> r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode 518 sc_signal<bool> r_dcache_line_no_coherence; // Register for line current in no coherence mode 519 sc_signal<bool> r_dcache_dirty_save; 520 sc_signal<uint32_t> r_cc_send_cpt_word; 521 sc_signal<uint32_t> r_dcache_miss_data_cpt; 522 sc_signal<paddr_t> r_dcache_miss_data_addr; 523 sc_signal<uint32_t> r_dcache_xtn_flush_data_cpt; 524 sc_signal<paddr_t> r_dcache_xtn_flush_addr_data; 525 sc_signal<int> r_dcache_xtn_state; 526 sc_signal<paddr_t> r_dcache_xtn_data_addr; 527 sc_signal<uint32_t> r_dcache_xtn_data_cpt; 490 528 // dcache directory extension 491 bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 492 bool *r_dcache_contains_ptd; // cache line contains a PTD 493 529 ///////////////////////////MODIFIED/////////////////////////////////////////////////// 530 //bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 531 //bool *r_dcache_contains_ptd; // cache line contains a PTD 532 int *r_dcache_content_state; // content state of one cache line 533 int *r_dcache_dirty_word; // content state of one cache line 534 ////////////////////////////////////////////////////////////////////////////////////// 535 536 //RWT 537 sc_signal<bool> r_dcache_read_state; 538 539 /////////////////////////////////// 494 540 // Physical address extension for data access 495 541 sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32) … … 513 559 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM 514 560 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 561 562 563 //RWT 564 GenericFifo<bool> r_vci_rsp_fifo_rpktid; 565 566 GenericFifo<uint32_t> r_cc_send_data_fifo; 515 567 516 568 /////////////////////////////////// … … 534 586 // communication between CC_RECEIVE FSM and ICACHE FSM 535 587 sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request 536 sc_signal< cc_receive_t>r_cc_receive_icache_type; // cc_receive type of request588 sc_signal<int> r_cc_receive_icache_type; // cc_receive type of request 537 589 sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way 538 590 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set … … 542 594 // communication between CC_RECEIVE FSM and DCACHE FSM 543 595 sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request 544 sc_signal< cc_receive_t>r_cc_receive_dcache_type; // cc_receive type of request596 sc_signal<int> r_cc_receive_dcache_type; // cc_receive type of request 545 597 sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way 546 598 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set … … 593 645 uint32_t m_cpt_data_read; // total number of read data 594 646 uint32_t m_cpt_data_write; // total number of write data 647 uint32_t m_cpt_data_write_back; 648 uint32_t m_cpt_data_cleanup; 649 uint32_t m_cpt_data_sc; 595 650 uint32_t m_cpt_data_miss; // number of read miss 596 651 uint32_t m_cpt_ins_miss; // number of instruction miss … … 608 663 uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions 609 664 uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions 665 uint32_t m_cpt_dunc_transaction; // number of VCI uncached read transactions 666 uint32_t m_cpt_ll_transaction; // number of VCI uncached read transactions 610 667 uint32_t m_cpt_write_transaction; // number of VCI write transactions 611 668 uint32_t m_cpt_icache_unc_transaction; … … 673 730 uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets 674 731 uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets 732 uint32_t m_cpt_cleanup_data_not_dirty; 733 uint32_t m_cpt_cleanup_data_dirty_word; 675 734 676 735 uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions -
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r473 r477 35 35 #define DEBUG_ICACHE 1 36 36 #define DEBUG_CMD 0 37 #define INSTRUMENTATION 1 37 38 38 39 namespace soclib { … … 87 88 "DCACHE_XTN_IT_INVAL", 88 89 "DCACHE_XTN_DC_FLUSH", 90 "DCACHE_XTN_DC_FLUSH_DATA", 89 91 "DCACHE_XTN_DC_FLUSH_GO", 90 92 "DCACHE_XTN_DC_INVAL_VA", … … 92 94 "DCACHE_XTN_DC_INVAL_END", 93 95 "DCACHE_XTN_DC_INVAL_GO", 96 "DCACHE_XTN_DC_INVAL_DATA", 94 97 "DCACHE_XTN_DT_INVAL", 95 98 … … 99 102 "DCACHE_MISS_SELECT", 100 103 "DCACHE_MISS_CLEAN", 104 "DCACHE_MISS_DATA", 101 105 "DCACHE_MISS_WAIT", 102 106 "DCACHE_MISS_DATA_UPDT", … … 110 114 "DCACHE_CC_UPDT", 111 115 "DCACHE_CC_INVAL", 116 "DCACHE_CC_INVAL_DATA", 112 117 113 118 "DCACHE_INVAL_TLB_SCAN", … … 174 179 "CC_SEND_CLEANUP_1", 175 180 "CC_SEND_CLEANUP_2", 181 "CC_SEND_CLEANUP_DATA_UPDT", 176 182 "CC_SEND_MULTI_ACK", 177 183 }; … … 367 373 r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth 368 374 r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth 375 r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth 376 r_cc_send_data_fifo("r_cc_send_data_fifo", 2), 369 377 370 378 r_cc_send_fsm("r_cc_send_fsm"), … … 424 432 r_mmu_release = (uint32_t)(1 << 16) | 0x1; 425 433 426 r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; 427 r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; 434 ////////////////////MODIFIED/////////////////////////////// 435 //r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; 436 //r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; 437 r_dcache_content_state = new int [dcache_ways*dcache_sets]; 438 r_dcache_dirty_word = new int [dcache_ways*dcache_sets*dcache_words]; 439 /////////////////////////////////////////////////////////// 440 428 441 429 442 SC_METHOD(transition); … … 450 463 ///////////////////////////////////// 451 464 { 452 delete [] r_dcache_in_tlb; 453 delete [] r_dcache_contains_ptd; 465 ////////////MODIFIED///////////// 466 //delete [] r_dcache_in_tlb; 467 //delete [] r_dcache_contains_ptd; 468 delete [] r_dcache_content_state; 469 delete [] r_dcache_dirty_word; 470 ///////////////////////////////// 454 471 } 455 472 … … 472 489 // b4 : dtlb trace 473 490 // b5 : itlb trace 474 475 491 std::cout << std::dec << "PROC " << name() << std::endl; 476 492 … … 479 495 std::cout << " " << m_dreq << std::endl; 480 496 std::cout << " " << m_drsp << std::endl; 497 498 /**/std::cout << r_iss << std::endl; 481 499 482 500 std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()] … … 562 580 } 563 581 564 /* 582 565 583 //////////////////////// 566 584 tmpl(void)::print_stats() … … 569 587 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); 570 588 std::cout << name() << std::endl 571 << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl 572 << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl 573 << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl 574 << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl 575 << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 576 << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl 577 << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 578 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl 579 << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl 580 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 581 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 582 << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl 583 << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl 584 << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl 585 << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl 586 << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl 587 << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl 588 << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl 589 << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl 590 << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl 591 << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl 592 << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl 593 << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl 594 << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl 595 << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl 596 << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl 597 << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl 598 << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl 599 << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl 600 << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl 601 << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl 602 << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl 603 << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl 604 << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl 605 << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl 606 << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl 607 << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 608 << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 609 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; 589 << "- CPI = " << std::dec <<(float)m_cpt_total_cycles/run_cycles << std::endl 590 << "- READ RATE = " << (float)m_cpt_data_read/run_cycles << std::endl 591 << "- WRITE RATE = " << (float)m_cpt_data_write/run_cycles << std::endl 592 << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl 593 << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl 594 << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl 595 << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 596 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl 597 << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl 598 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl 599 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl 600 << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl 601 << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl 602 << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl 603 << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl 604 << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl 605 << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl 606 << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl 607 << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl 608 << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl 609 //<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl 610 << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl 611 << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl 612 << "- NB CC UPDATE DATA = " << m_cpt_cc_update_dcache << std::endl 613 << "- NB CC INVAL DATA = " << m_cpt_cc_inval_dcache << std::endl 614 << "- NB CC INVAL INS = " << m_cpt_cc_inval_icache << std::endl 615 << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl 616 << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache << std::endl 617 << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache << std::endl 618 << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache << std::endl 619 << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl 620 << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl 621 << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl 622 << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl 623 << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl 624 << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl 625 << "- NB WRITE TRANSACTION = " << m_cpt_write_transaction << std::endl 626 << "- NB WRITE WORDS VCI = " << m_length_write_transaction << std::endl 627 << "- NB WRITE PROC = " << m_cpt_data_write << std::endl 628 << "- NB WRITE BACK = " << m_cpt_data_write_back << std::endl 629 << "- NB WRITE BACK COHERENCE = " << m_cpt_data_cleanup << std::endl 630 << "- NB DATA SC = " << m_cpt_data_sc << std::endl 631 << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 632 << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 633 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl 634 635 << "- DMISS TRANSACTION = " << m_cpt_dmiss_transaction << std::endl 636 << "- DUNC TRANSACTION = " << m_cpt_dunc_transaction << std::endl 637 << "- LL TRANSACTION = " << m_cpt_ll_transaction << std::endl 638 << "- CLEANUP DATA NOT DIRTY = " << m_cpt_cleanup_data_not_dirty << std::endl 639 << "- CLEANUP DATA DIRTY WORD = " << m_cpt_cleanup_data_dirty_word << std::endl; 610 640 } 611 641 … … 624 654 625 655 m_cpt_frz_cycles = 0; 626 m_cpt_dcache_frz_cycles = 0;656 // m_cpt_dcache_frz_cycles = 0; 627 657 m_cpt_total_cycles = 0; 628 658 629 m_cpt_read = 0;630 m_cpt_write = 0;659 // m_cpt_read = 0; 660 // m_cpt_write = 0; 631 661 m_cpt_data_miss = 0; 632 662 m_cpt_ins_miss = 0; … … 692 722 m_cost_dtlb_sc_dirty_transaction = 0; 693 723 694 m_cpt_cc_update_data = 0;695 m_cpt_cc_inval_ins = 0;696 m_cpt_cc_inval_data = 0;724 // m_cpt_cc_update_data = 0; 725 // m_cpt_cc_inval_ins = 0; 726 // m_cpt_cc_inval_data = 0; 697 727 m_cpt_cc_broadcast = 0; 698 728 … … 704 734 m_cpt_cc_cleanup_data = 0; 705 735 m_cpt_cc_cleanup_ins = 0; 736 737 m_cpt_cleanup_data_not_dirty = 0; 738 m_cpt_cleanup_data_dirty_word = 0; 739 706 740 } 707 741 708 */ 742 709 743 710 744 ///////////////////////// … … 734 768 for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++) 735 769 { 736 r_dcache_in_tlb[i] = false; 737 r_dcache_contains_ptd[i] = false; 770 // MODIFIED 771 //r_dcache_in_tlb[i] = false; 772 //r_dcache_contains_ptd[i] = false; 773 r_dcache_content_state[i] = LINE_CACHE_DATA_NOT_DIRTY; 774 r_dcache_dirty_word[i] = 0; 738 775 } 739 776 … … 741 778 r_vci_rsp_fifo_icache.init(); 742 779 r_vci_rsp_fifo_dcache.init(); 780 r_cc_send_data_fifo.init(); 743 781 744 782 // ICACHE & DCACHE activated … … 805 843 m_debug_previous_d_hit = false; 806 844 m_debug_activated = false; 845 846 // SPECIAL REGISTERS ODCCP 847 r_dcache_cc_cleanup_updt_data = false; 848 r_dcache_cc_cleanup_line_ncc = false; 849 r_dcache_miss_victim_no_coherence = false; 850 r_dcache_line_no_coherence = false; 851 r_cc_send_cpt_word = 0; 852 r_dcache_miss_data_cpt = 0; 853 r_dcache_miss_data_addr = 0; 807 854 808 855 // activity counters … … 821 868 822 869 m_cpt_data_miss = 0; 870 m_cpt_data_write = 0; 871 m_cpt_data_sc = 0; 872 m_cpt_data_write_back = 0; 873 m_cpt_data_cleanup = 0; 874 m_cpt_cleanup_data_not_dirty = 0; 823 875 m_cpt_ins_miss = 0; 824 876 m_cpt_unc_read = 0; … … 879 931 m_cpt_cc_cleanup_data = 0; 880 932 m_cpt_cc_cleanup_ins = 0; 933 934 m_cpt_cleanup_data_not_dirty = 0; 935 m_cpt_cleanup_data_dirty_word = 0; 881 936 882 937 m_cpt_itlbmiss_transaction = 0; … … 926 981 bool vci_rsp_fifo_dcache_put = false; 927 982 uint32_t vci_rsp_fifo_dcache_data = 0; 983 bool vci_rsp_fifo_rpktid_get = false; 984 bool vci_rsp_fifo_rpktid_put = false; 985 bool vci_rsp_fifo_rpktid = false; 986 987 // FIFO for cleanup data updt 988 bool cleanup_data_updt_fifo_dcache_get = false; 989 bool cleanup_data_updt_fifo_dcache_put = false; 990 uint32_t cleanup_data_updt_fifo_dcache_data = 0; 928 991 929 992 // updt fifo … … 935 998 936 999 #ifdef INSTRUMENTATION 937 m_cpt_fsm_dcache [r_dcache_fsm.read()] ++;938 m_cpt_fsm_icache [r_icache_fsm.read()] ++;939 m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;940 m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;941 m_cpt_fsm_ tgt [r_tgt_fsm.read()] ++;942 m_cpt_fsm_c leanup [r_cleanup_cmd_fsm.read()] ++;1000 m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++; 1001 m_cpt_fsm_icache [r_icache_fsm.read() ] ++; 1002 m_cpt_fsm_cmd [r_vci_cmd_fsm.read() ] ++; 1003 m_cpt_fsm_rsp [r_vci_rsp_fsm.read() ] ++; 1004 m_cpt_fsm_cc_send [r_cc_send_fsm.read() ] ++; 1005 m_cpt_fsm_cc_receive [r_cc_receive_fsm.read()] ++; 943 1006 #endif 944 1007 … … 1069 1132 else 1070 1133 { 1071 r_icache_vci_paddr = ( paddr_t)r_mmu_word_hi.read() << 32 |1134 r_icache_vci_paddr = (uint64_t)r_mmu_word_hi.read() << 32 | 1072 1135 (paddr_t)r_mmu_word_lo.read(); 1073 1136 } … … 1106 1169 1107 1170 #ifdef INSTRUMENTATION 1108 m_cpt_i tlb_read++;1171 m_cpt_ins_tlb_read++; 1109 1172 #endif 1110 1173 tlb_hit = r_itlb.translate( m_ireq.addr, … … 1181 1244 1182 1245 #ifdef INSTRUMENTATION 1183 m_cpt_i tlb_miss++;1246 m_cpt_ins_tlb_miss++; 1184 1247 #endif 1185 1248 r_icache_fsm = ICACHE_TLB_WAIT; … … 1199 1262 1200 1263 #ifdef INSTRUMENTATION 1201 m_cpt_i cache_miss++;1264 m_cpt_ins_miss++; 1202 1265 #endif 1203 1266 // we request a VCI transaction … … 1340 1403 &state ); 1341 1404 1342 if ( state == CACHE_SLOT_STATE_VALID ) // inval required1405 if ( state == CACHE_SLOT_STATE_VALID_CC ) // inval required 1343 1406 { 1344 1407 // request cleanup … … 1421 1484 1422 1485 #ifdef INSTRUMENTATION 1423 m_cpt_i tlb_read++;1486 m_cpt_ins_tlb_read++; 1424 1487 #endif 1425 1488 hit = r_itlb.translate(r_dcache_save_wdata.read(), … … 1441 1504 1442 1505 #ifdef INSTRUMENTATION 1443 m_cpt_i tlb_miss++;1506 m_cpt_ins_tlb_miss++; 1444 1507 #endif 1445 1508 r_icache_tlb_miss_req = true; … … 1468 1531 &word); 1469 1532 1470 if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done1533 if ( state == CACHE_SLOT_STATE_VALID_CC ) // inval to be done 1471 1534 { 1472 1535 r_icache_miss_way = way; … … 1751 1814 r_icache_miss_way.read(), 1752 1815 r_icache_miss_set.read(), 1753 CACHE_SLOT_STATE_VALID );1816 CACHE_SLOT_STATE_VALID_CC ); 1754 1817 #if DEBUG_ICACHE 1755 1818 if ( m_debug_activated ) … … 1924 1987 r_icache_cc_set = set; 1925 1988 1926 if ( state == CACHE_SLOT_STATE_VALID ) // hit1989 if ( state == CACHE_SLOT_STATE_VALID_CC) // hit 1927 1990 { 1928 1991 // need to update the cache state … … 2136 2199 m_drsp.error = false; 2137 2200 m_drsp.rdata = 0; 2201 //if(m_cpt_total_cycles % 1000000 == 0 ) r_dcache.printTrace(); 2138 2202 2139 2203 switch ( r_dcache_fsm.read() ) … … 2191 2255 bool wbuf_request = false; // request WBUF write in P1 stage 2192 2256 2257 2193 2258 // physical address computation : systematic DTLB access if activated) 2194 2259 if ( m_dreq.valid ) … … 2203 2268 &tlb_set ); 2204 2269 #ifdef INSTRUMENTATION 2205 m_cpt_d tlb_read++;2270 m_cpt_data_tlb_read++; 2206 2271 #endif 2207 2272 } … … 2211 2276 // we take into account the paddr extension 2212 2277 if (vci_param::N > 32) 2213 paddr = paddr | (( paddr_t)(r_dcache_paddr_ext.read()) << 32);2278 paddr = paddr | ((uint64_t)(r_dcache_paddr_ext.read()) << 32); 2214 2279 } 2215 2280 } // end physical address computation … … 2268 2333 size_t way = r_dcache_save_cache_way.read(); 2269 2334 size_t set = r_dcache_save_cache_set.read(); 2270 2271 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 2335 // MODIFIED 2336 //if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 2337 //{ 2338 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 2272 2339 { 2273 2340 tlb_inval_required = true; … … 2275 2342 r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>> 2276 2343 (uint32_log2(m_dcache_words<<2)); 2277 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 2278 } 2279 else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 2344 // MODIFIED RWT: DIRTY 2345 //r_dcache_in_tlb[way*m_dcache_sets+set] = false; 2346 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 2347 } 2348 // MODIFIED 2349 //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 2350 //{ 2351 else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 2280 2352 { 2281 2353 r_itlb.reset(); 2282 2354 r_dtlb.reset(); 2283 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 2355 // MODIFIED 2356 //r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 2357 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 2284 2358 } 2285 2359 … … 2312 2386 r_dcache_save_wdata.read(), 2313 2387 r_dcache_save_cacheable.read() ); 2314 #ifdef INSTRUMENTATION2388 /*#ifdef INSTRUMENTATION 2315 2389 m_cpt_wbuf_write++; 2316 #endif 2390 #endif*/ 2317 2391 if ( not wok ) // miss if write buffer full 2318 2392 { … … 2526 2600 else 2527 2601 { 2528 r_dcache_save_paddr = ( paddr_t)r_mmu_word_hi.read() << 32 |2602 r_dcache_save_paddr = (uint64_t)r_mmu_word_hi.read() << 32 | 2529 2603 (paddr_t)r_mmu_word_lo.read(); 2530 2604 } … … 2623 2697 if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; 2624 2698 else cacheable = tlb_flags.c; 2625 2626 2699 // access rights checking 2627 2700 if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) … … 2693 2766 { 2694 2767 #ifdef INSTRUMENTATION 2695 m_cpt_dcache_miss++; 2696 #endif 2768 m_cpt_data_miss++; 2769 #endif 2770 /*ODCCP*/ 2771 //std::cout << "\t\t\t\t\tCACHE MISS NEED READ for : " << name() << std::endl; 2697 2772 // request a VCI DMISS transaction 2698 2773 r_dcache_vci_paddr = paddr; … … 2723 2798 m_cpt_data_read++; 2724 2799 #endif 2800 /*if ((tlb_flags.s == 0) and (r_mmu_mode.read() & DATA_TLB_MASK) and (cache_state == CACHE_SLOT_STATE_VALID_CC)) 2801 { 2802 //ODCCP 2803 std::cout << "READ NO COHERENCE on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | way = " << cache_way << " | set = " << cache_set << " | at cycle : "<< m_cpt_total_cycles << std::endl; 2804 r_dcache.write_dir(cache_way, 2805 cache_set, 2806 CACHE_SLOT_STATE_VALID_NCC); 2807 }*/ 2725 2808 // returns data to processor 2726 2809 m_drsp.valid = true; … … 2765 2848 r_dcache_ll_rsp_count = 0; 2766 2849 r_dcache_fsm = DCACHE_LL_WAIT; 2850 /*ODCCP*/ 2851 //std::cout << "LL on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | at cycle : " << m_cpt_total_cycles << std::endl; 2767 2852 2768 2853 }// end LL … … 2806 2891 // response to processor 2807 2892 m_drsp.valid = true; 2808 2809 2893 // activating P1 stage 2810 wbuf_request = true; 2811 updt_request = (cache_state == CACHE_SLOT_STATE_VALID); 2894 if( (cache_state != CACHE_SLOT_STATE_ZOMBI )&&(cache_state != CACHE_SLOT_STATE_EMPTY )&&(cacheable) ) 2895 { 2896 wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC); //write to L2 only if CC 2897 updt_request = true; 2898 if (cache_state == CACHE_SLOT_STATE_VALID_NCC) 2899 { 2900 if (r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY) 2901 { 2902 r_dcache_content_state[cache_way*m_dcache_sets+cache_set] = LINE_CACHE_DATA_DIRTY; 2903 } 2904 r_dcache_dirty_word[(cache_way*m_dcache_sets +cache_set)*m_dcache_words+cache_word] = 1;//dirty bit with word granularity (only for stats) 2905 m_cpt_data_write_back ++; 2906 } 2907 } 2908 else 2909 { 2910 wbuf_request = true; 2911 updt_request = false; 2912 } 2812 2913 } 2813 2914 } // end WRITE … … 2978 3079 m_cpt_dcache_dir_read++; 2979 3080 #endif 2980 if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache 3081 /*ODCCP*/ 3082 // assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE1_GET : IMPOSSIBLE NCC HERE"); 3083 // if ( cache_state == CACHE_SLOT_STATE_VALID_CC ) // hit in dcache 3084 if (( cache_state == CACHE_SLOT_STATE_VALID_NCC ) or ( cache_state == CACHE_SLOT_STATE_VALID_CC )) 2981 3085 { 2982 3086 if ( not (entry & PTE_V_MASK) ) // unmapped … … 3015 3119 { 3016 3120 // mark the cache line ac containing a PTD 3017 r_dcache_contains_ptd[m_dcache_sets*way+set] = true; 3121 //MODIFIED 3122 //r_dcache_contains_ptd[m_dcache_sets*way+set] = true; 3123 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_CONTAINS_PTD; 3018 3124 3019 3125 // register bypass … … 3050 3156 else // PTE1 : we must update the TLB 3051 3157 { 3052 r_dcache_in_tlb[m_icache_sets*way+set] = true; 3158 // MODIFIED 3159 //r_dcache_in_tlb[m_icache_sets*way+set] = true; 3160 r_dcache_content_state[m_icache_sets*way+set] = LINE_CACHE_IN_TLB; 3053 3161 r_dcache_tlb_pte_flags = entry; 3054 3162 r_dcache_tlb_cache_way = way; … … 3108 3216 &set ); 3109 3217 #ifdef INSTRUMENTATION 3110 m_cpt_i tlb_read++;3218 m_cpt_ins_tlb_read++; 3111 3219 #endif 3112 3220 } … … 3118 3226 &set ); 3119 3227 #ifdef INSTRUMENTATION 3120 m_cpt_d tlb_read++;3228 m_cpt_data_tlb_read++; 3121 3229 #endif 3122 3230 } … … 3194 3302 nline ); 3195 3303 #ifdef INSTRUMENTATION 3196 m_cpt_i tlb_write++;3304 m_cpt_ins_tlb_update_acc++; 3197 3305 #endif 3198 3306 … … 3218 3326 nline ); 3219 3327 #ifdef INSTRUMENTATION 3220 m_cpt_d tlb_write++;3328 m_cpt_data_tlb_update_acc++; 3221 3329 #endif 3222 3330 … … 3268 3376 } 3269 3377 3270 uint32_t pte_flags ;3271 uint32_t pte_ppn ;3272 size_t way ;3273 size_t set ;3274 size_t word ;3275 int cache_state ;3378 uint32_t pte_flags = 0; 3379 uint32_t pte_ppn = 0; 3380 size_t way = 0; 3381 size_t set = 0; 3382 size_t word = 0; 3383 int cache_state = 0; 3276 3384 3277 3385 r_dcache.read( r_dcache_tlb_paddr.read(), … … 3286 3394 m_cpt_dcache_dir_read++; 3287 3395 #endif 3288 if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache 3396 /*ODCCP*/ 3397 // assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE2_GET : IMPOSSIBLE NCC HERE"); 3398 // if (cache_state == CACHE_SLOT_STATE_VALID_CC) // hit in dcache 3399 if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or (cache_state == CACHE_SLOT_STATE_VALID_NCC)) 3289 3400 { 3290 3401 if ( not (pte_flags & PTE_V_MASK) ) // unmapped … … 3318 3429 else // mapped : we must update the TLB 3319 3430 { 3320 r_dcache_in_tlb[m_dcache_sets*way+set] = true; 3431 // MODIFIED 3432 //r_dcache_in_tlb[m_dcache_sets*way+set] = true; 3433 r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_IN_TLB; 3321 3434 r_dcache_tlb_pte_flags = pte_flags; 3322 3435 r_dcache_tlb_pte_ppn = pte_ppn; … … 3383 3496 &set ); 3384 3497 #ifdef INSTRUMENTATION 3385 m_cpt_i tlb_read++;3498 m_cpt_ins_tlb_read++; 3386 3499 #endif 3387 3500 } … … 3393 3506 &set ); 3394 3507 #ifdef INSTRUMENTATION 3395 m_cpt_d tlb_read++;3508 m_cpt_data_tlb_read++; 3396 3509 #endif 3397 3510 } … … 3435 3548 // As long as this computation is not done, all access are local. 3436 3549 3550 int state; 3551 size_t way; 3552 size_t set; 3553 size_t word; 3554 r_dcache.read_dir(r_dcache_tlb_paddr.read(), 3555 &state, 3556 &way, 3557 &set, 3558 &word); 3559 r_cas_islocal = (state == CACHE_SLOT_STATE_VALID_NCC);//do not check L2 if NCC: the CAS is necessarily a success 3560 r_cas_local_way = way; 3561 r_cas_local_set = set; 3562 r_cas_local_word = word; 3563 3437 3564 if ( local ) // local access 3438 3565 { … … 3470 3597 nline ); 3471 3598 #ifdef INSTRUMENTATION 3472 m_cpt_i tlb_write++;3599 m_cpt_ins_tlb_update_acc++; 3473 3600 #endif 3474 3601 … … 3494 3621 nline ); 3495 3622 #ifdef INSTRUMENTATION 3496 m_cpt_d tlb_write++;3623 m_cpt_data_tlb_update_acc++; 3497 3624 #endif 3498 3625 … … 3528 3655 case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit 3529 3656 { 3657 uint32_t way = r_cas_local_way.read(); 3658 uint32_t set = r_cas_local_set.read(); 3659 uint32_t word = r_cas_local_word.read(); 3660 paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); 3530 3661 #if DEBUG_DCACHE 3531 3662 if ( m_debug_activated ) … … 3535 3666 } 3536 3667 #endif 3537 // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set 3538 r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); 3539 3540 // checking llsc reservation buffer 3541 if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) 3542 r_dcache_llsc_valid = false; 3543 3544 // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state 3545 r_dcache_vci_cas_req = true; 3546 r_dcache_fsm = DCACHE_TLB_LR_WAIT; 3668 3669 if (r_cas_islocal.read()) 3670 { 3671 r_dcache.write(way, 3672 set, 3673 word, 3674 r_dcache_vci_cas_new.read()); 3675 //compteur dirty 3676 r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 1; 3677 3678 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 3679 { 3680 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 3681 r_dcache_tlb_inval_line = nline; 3682 r_dcache_tlb_inval_set = 0; 3683 r_dcache_fsm_scan_save = DCACHE_TLB_RETURN; 3684 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 3685 break; 3686 } 3687 3688 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 3689 { 3690 r_itlb.reset(); 3691 r_dtlb.reset(); 3692 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 3693 3694 #if DEBUG_DCACHE 3695 if ( m_debug_activated ) 3696 { 3697 std::cout << " <PROC " << name() 3698 << " DCACHE_TLB_LR_UPDT> Flush DTLB & ITLB" << std::endl; 3699 } 3700 #endif 3701 } 3702 3703 r_dcache_fsm = DCACHE_TLB_RETURN; 3704 } 3705 else 3706 { 3707 // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set 3708 r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); 3709 3710 // checking llsc reservation buffer 3711 if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) 3712 r_dcache_llsc_valid = false; 3713 3714 // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state 3715 r_dcache_vci_cas_req = true; 3716 r_dcache_fsm = DCACHE_TLB_LR_WAIT; 3717 } 3547 3718 break; 3548 3719 } … … 3739 3910 &tag, 3740 3911 &state ); 3741 3742 if ( state == CACHE_SLOT_STATE_VALID ) // inval required 3912 /*ODCCP*/ 3913 3914 if ( state == CACHE_SLOT_STATE_VALID_CC ) // inval required 3743 3915 { 3744 3916 // request cleanup … … 3751 3923 r_dcache_miss_way = way; 3752 3924 r_dcache_miss_set = set; 3925 r_dcache_cc_cleanup_line_ncc = false; 3926 r_dcache_cc_cleanup_updt_data = false; 3753 3927 r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; 3928 } 3929 else if ( state == CACHE_SLOT_STATE_VALID_NCC) 3930 { 3931 // request cleanup 3932 r_dcache_cc_send_req = true; 3933 r_dcache_cc_send_nline = tag * m_dcache_sets + set; 3934 r_dcache_cc_send_way = way; 3935 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 3936 3937 // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory 3938 r_dcache_miss_way = way; 3939 r_dcache_miss_set = set; 3940 r_dcache_cc_cleanup_line_ncc = true; 3941 //if (r_dcache_content_state[m_dcache_sets*way+set] != LINE_CACHE_DATA_NOT_DIRTY)//Must send data in the cleanup 3942 if (true)//Must send data in the cleanup 3943 { 3944 r_dcache_xtn_flush_addr_data = (tag * m_dcache_sets + set) * m_dcache_words * 4; 3945 r_dcache_xtn_flush_data_cpt = 0; 3946 r_dcache_cc_cleanup_updt_data = true; 3947 for (size_t w = 0; w< m_dcache_words; w++) 3948 { 3949 m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; 3950 } 3951 r_dcache_fsm = DCACHE_XTN_DC_FLUSH_DATA; 3952 } 3953 else 3954 { 3955 r_dcache_cc_cleanup_updt_data = false; 3956 r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; 3957 } 3754 3958 } 3755 3959 else if ( r_dcache_flush_count.read() == … … 3768 3972 break; 3769 3973 } 3974 3975 //////////////////////////// 3976 case DCACHE_XTN_DC_FLUSH_DATA: 3977 { 3978 uint32_t rdata; 3979 size_t way; 3980 size_t set; 3981 size_t word; 3982 r_dcache.read_neutral(r_dcache_xtn_flush_addr_data.read(), 3983 &rdata, 3984 &way, 3985 &set, 3986 &word); 3987 if(r_cc_send_data_fifo.wok()) 3988 { 3989 r_dcache_xtn_flush_addr_data = r_dcache_xtn_flush_addr_data.read() + 4; 3990 3991 cleanup_data_updt_fifo_dcache_put = true; 3992 cleanup_data_updt_fifo_dcache_data = rdata; 3993 3994 r_dcache_xtn_flush_data_cpt = r_dcache_xtn_flush_data_cpt + 1; 3995 if(r_dcache_xtn_flush_data_cpt.read() == (m_dcache_words - 1)) 3996 { 3997 r_dcache_xtn_flush_data_cpt = 0; 3998 r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; 3999 } 4000 } 4001 break; 4002 } 4003 3770 4004 //////////////////////////// 3771 4005 case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state … … 3776 4010 size_t set = r_dcache_miss_set.read(); 3777 4011 3778 r_dcache_in_tlb[m_dcache_sets*way+set] = false; 3779 r_dcache_contains_ptd[m_dcache_sets*way+set] = false; 4012 // MODIFIED 4013 //r_dcache_in_tlb[m_dcache_sets*way+set] = false; 4014 //r_dcache_contains_ptd[m_dcache_sets*way+set] = false; 4015 r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_DATA_DIRTY; 3780 4016 3781 4017 #ifdef INSTRUMENTATION … … 3820 4056 3821 4057 #ifdef INSTRUMENTATION 3822 m_cpt_d tlb_read++;4058 m_cpt_data_tlb_read++; 3823 4059 #endif 3824 4060 hit = r_dtlb.translate( r_dcache_save_wdata.read(), … … 3840 4076 3841 4077 #ifdef INSTRUMENTATION 3842 m_cpt_d tlb_miss++;4078 m_cpt_data_tlb_miss++; 3843 4079 #endif 3844 4080 r_dcache_tlb_ins = false; // dtlb … … 3877 4113 &set, 3878 4114 &word ); 3879 3880 if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done 3881 { 3882 r_dcache_xtn_way = way; 3883 r_dcache_xtn_set = set; 3884 r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; 4115 /*ODCCP*/ 4116 //assert((state != CACHE_SLOT_STATE_VALID_NCC) and "NOT YET DONE"); 4117 if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // inval to be done 4118 { 4119 r_dcache_xtn_way = way; 4120 r_dcache_xtn_set = set; 4121 r_dcache_xtn_state = state; 4122 r_dcache_xtn_data_addr = r_dcache_save_paddr.read()&~0x3F; 4123 4124 if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) ) 4125 { 4126 m_cpt_cleanup_data_not_dirty ++; 4127 } 4128 r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; 4129 3885 4130 } 3886 4131 else // miss : nothing to do … … 3896 4141 << " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex 3897 4142 << " / PADDR = " << r_dcache_save_paddr.read() << std::dec 3898 << " / HIT = " << ( state == CACHE_SLOT_STATE_VALID)4143 << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) 3899 4144 << " / SET = " << set 3900 4145 << " / WAY = " << way << std::endl; 4146 //r_dcache.printTrace(); 3901 4147 } 3902 4148 #endif … … 3910 4156 if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent 3911 4157 { 4158 int state = r_dcache_xtn_state.read(); 3912 4159 size_t way = r_dcache_xtn_way.read(); 3913 4160 size_t set = r_dcache_xtn_set.read(); … … 3917 4164 m_cpt_dcache_dir_write++; 3918 4165 #endif 3919 r_dcache.write_dir( way, 3920 set, 3921 CACHE_SLOT_STATE_ZOMBI ); 3922 3923 // request cleanup 3924 r_dcache_cc_send_req = true; 3925 r_dcache_cc_send_nline = nline; 3926 r_dcache_cc_send_way = way; 3927 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4166 // MODIFIER POUR DIRTY BIT // 4167 if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))// request cleanup 4168 { 4169 r_dcache_cc_send_req = true; 4170 r_dcache_cc_send_nline = nline; 4171 r_dcache_cc_send_way = way; 4172 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4173 if (state == CACHE_SLOT_STATE_VALID_CC) 4174 { 4175 r_dcache_cc_cleanup_line_ncc = false; 4176 r_dcache.write_dir( way, 4177 set, 4178 CACHE_SLOT_STATE_ZOMBI ); 4179 } 4180 else 4181 { 4182 r_dcache_cc_cleanup_line_ncc = true; 4183 //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY)) //must send data 4184 if (true) //must send data 4185 { 4186 r_dcache_cc_cleanup_updt_data = true; 4187 for (size_t w = 0; w< m_dcache_words; w++) 4188 { 4189 m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; 4190 } 4191 r_dcache_fsm = DCACHE_XTN_DC_INVAL_DATA; 4192 break; 4193 } 4194 else 4195 { 4196 r_dcache_cc_cleanup_updt_data = false; 4197 r_dcache.write_dir( way, 4198 set, 4199 CACHE_SLOT_STATE_ZOMBI ); 4200 } 4201 if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) ) 4202 m_cpt_cleanup_data_not_dirty ++; 4203 } 4204 } 4205 /*ODCCP*/ 3928 4206 3929 4207 // possible itlb & dtlb invalidate 3930 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 4208 // MODIFIED 4209 //if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 4210 //{ 4211 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 3931 4212 { 3932 4213 r_dcache_tlb_inval_line = nline; … … 3934 4215 r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; 3935 4216 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 3936 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 3937 } 3938 else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 4217 // MODIFIED 4218 //r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4219 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 4220 } 4221 // MODIFIED 4222 //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 4223 //{ 4224 else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD) 3939 4225 { 3940 4226 r_itlb.reset(); 3941 4227 r_dtlb.reset(); 3942 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4228 // MODIFIED 4229 //r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4230 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 3943 4231 r_dcache_fsm = DCACHE_IDLE; 3944 4232 m_drsp.valid = true; … … 3961 4249 break; 3962 4250 } 4251 4252 /*ODCCP*/ 4253 ////////////////////////////// 4254 case DCACHE_XTN_DC_INVAL_DATA: //A verifier 4255 { 4256 4257 uint32_t rdata; 4258 size_t way; 4259 size_t set; 4260 size_t word; 4261 r_dcache.read_neutral(r_dcache_xtn_data_addr.read(), 4262 &rdata, 4263 &way, 4264 &set, 4265 &word); 4266 if(r_cc_send_data_fifo.wok()) 4267 { 4268 r_dcache_xtn_data_addr = r_dcache_xtn_data_addr.read() + 4; 4269 4270 cleanup_data_updt_fifo_dcache_put = true; 4271 cleanup_data_updt_fifo_dcache_data = rdata; 4272 4273 r_dcache_xtn_data_cpt = r_dcache_xtn_data_cpt.read() + 1; 4274 if(r_dcache_xtn_data_cpt.read() == (m_dcache_words - 1)) 4275 { 4276 r_dcache_xtn_state = CACHE_SLOT_STATE_ZOMBI; 4277 r_dcache_xtn_data_cpt = 0; 4278 r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; 4279 r_dcache.write_dir( way, 4280 set, 4281 CACHE_SLOT_STATE_ZOMBI ); 4282 } 4283 } 4284 break; 4285 } 4286 3963 4287 ////////////////////////////// 3964 4288 case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request … … 4001 4325 size_t set = 0; 4002 4326 paddr_t victim = 0; 4327 int state; 4003 4328 4004 4329 #ifdef INSTRUMENTATION … … 4011 4336 &found, 4012 4337 &cleanup ); 4338 state = r_dcache.get_cache_state(way,set); 4013 4339 4014 4340 if ( found ) … … 4026 4352 r_dcache_cc_send_way = way; 4027 4353 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4354 if( (state == CACHE_SLOT_STATE_VALID_NCC) )//and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) ) 4355 { 4356 //MODIFIER POUR DIRTY BIT // 4357 r_dcache_cc_cleanup_line_ncc = true; 4358 r_dcache_miss_data_addr = (victim*m_dcache_words)*4; 4359 //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY))//must send data 4360 if (true)//must send data 4361 { 4362 r_dcache_cc_cleanup_updt_data = true; 4363 for (size_t w = 0; w< m_dcache_words; w++) 4364 { 4365 m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; 4366 } 4367 r_dcache_fsm = DCACHE_MISS_DATA; 4368 } 4369 else 4370 { 4371 r_dcache_cc_cleanup_updt_data = false; 4372 } 4373 4374 if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) 4375 m_cpt_cleanup_data_not_dirty ++; 4376 } 4377 4378 else 4379 { 4380 r_dcache_cc_cleanup_line_ncc = false; 4381 r_dcache_cc_cleanup_updt_data = false; 4382 } 4028 4383 } 4029 4384 else … … 4049 4404 } 4050 4405 /////////////////////// 4406 case DCACHE_MISS_DATA: 4407 { 4408 uint32_t rdata; 4409 size_t way; 4410 size_t set; 4411 size_t word; 4412 4413 r_dcache.read_neutral(r_dcache_miss_data_addr, 4414 &rdata, 4415 &way, 4416 &set, 4417 &word); 4418 if(r_cc_send_data_fifo.wok()) 4419 { 4420 r_dcache_miss_data_addr = r_dcache_miss_data_addr.read() + 4; 4421 4422 cleanup_data_updt_fifo_dcache_put = true; 4423 cleanup_data_updt_fifo_dcache_data = rdata; 4424 4425 r_dcache_miss_data_cpt = r_dcache_miss_data_cpt.read() + 1; 4426 if (r_dcache_miss_data_cpt.read() == m_dcache_words-1 ) 4427 { 4428 r_dcache_miss_data_cpt = 0; 4429 r_dcache_fsm = DCACHE_MISS_CLEAN; 4430 } 4431 } 4432 break; 4433 } 4434 /////////////////////// 4051 4435 case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state 4052 4436 // and possibly request itlb or dtlb invalidate … … 4074 4458 // if selective itlb & dtlb invalidate are required 4075 4459 // the miss response is not handled before invalidate completed 4076 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 4077 { 4078 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4460 // MODIFIED 4461 //if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 4462 //{ 4463 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 4464 { 4465 //MODIFIED 4466 //r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4467 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 4079 4468 r_dcache_tlb_inval_line = r_dcache_cc_send_nline; 4080 4469 r_dcache_tlb_inval_set = 0; … … 4082 4471 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4083 4472 } 4084 else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 4473 // MODIFIED 4474 //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 4475 //{ 4476 else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 4085 4477 { 4086 4478 r_itlb.reset(); 4087 4479 r_dtlb.reset(); 4088 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4480 // MODIFIED 4481 //r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4482 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 4089 4483 r_dcache_fsm = DCACHE_MISS_WAIT; 4090 4484 } … … 4101 4495 { 4102 4496 if ( m_dreq.valid) m_cost_data_miss_frz++; 4103 4104 4497 // coherence clack request (from DSPIN CLACK) 4105 4498 if ( r_dcache_clack_req.read() ) … … 4184 4577 if ( m_dreq.valid) m_cost_data_miss_frz++; 4185 4578 4186 if ( r_vci_rsp_fifo_dcache.rok() ) // one word available4579 if ( r_vci_rsp_fifo_dcache.rok() && r_vci_rsp_fifo_rpktid.rok()) // one word available 4187 4580 { 4188 4581 #ifdef INSTRUMENTATION … … 4205 4598 #endif 4206 4599 vci_rsp_fifo_dcache_get = true; 4600 4601 r_dcache_read_state = !r_vci_rsp_fifo_rpktid.read();//deduce the state (CC or NCC) from msb of pktid 4602 vci_rsp_fifo_rpktid_get = true; 4603 4604 4207 4605 r_dcache_miss_word = r_dcache_miss_word.read() + 1; 4208 4606 … … 4253 4651 r_dcache_cc_send_way = r_dcache_miss_way.read(); 4254 4652 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4653 r_dcache_cc_cleanup_updt_data = false; //the line is evicted at the very moment it arives, so it is not dirty 4654 r_dcache_cc_cleanup_line_ncc = !r_dcache_read_state.read(); 4255 4655 4256 4656 #ifdef INSTRUMENTATION … … 4279 4679 m_cpt_dcache_dir_write++; 4280 4680 #endif 4281 r_dcache.write_dir( r_dcache_save_paddr.read(), 4282 r_dcache_miss_way.read(), 4283 r_dcache_miss_set.read(), 4284 CACHE_SLOT_STATE_VALID ); 4681 4682 size_t way = r_dcache_miss_way.read(); 4683 size_t set = r_dcache_miss_set.read(); 4684 if (r_dcache_read_state.read()) 4685 { 4686 r_dcache.write_dir( r_dcache_save_paddr.read(), 4687 r_dcache_miss_way.read(), 4688 r_dcache_miss_set.read(), 4689 CACHE_SLOT_STATE_VALID_CC ); 4690 4691 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 4692 } 4693 else 4694 { 4695 r_dcache.write_dir( r_dcache_save_paddr.read(), 4696 r_dcache_miss_way.read(), 4697 r_dcache_miss_set.read(), 4698 CACHE_SLOT_STATE_VALID_NCC ); 4699 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 4700 for (size_t word =0; word < m_dcache_words ; word++) 4701 { 4702 r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 0; 4703 } 4704 } 4285 4705 4286 4706 #if DEBUG_DCACHE … … 4293 4713 #endif 4294 4714 // reset directory extension 4295 size_t way = r_dcache_miss_way.read(); 4296 size_t set = r_dcache_miss_set.read();4297 r_dcache_in_tlb[way*m_dcache_sets+set] = false;4298 r_dcache_contains_ptd[way*m_dcache_sets+set] = false;4715 4716 // MODIFIED 4717 //r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4718 //r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4299 4719 } 4300 4720 if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; … … 4467 4887 &state ); 4468 4888 4469 assert( (state == CACHE_SLOT_STATE_VALID ) and4889 assert( (state == CACHE_SLOT_STATE_VALID_CC or state == CACHE_SLOT_STATE_VALID_NCC) and 4470 4890 "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" ); 4471 4891 … … 4479 4899 4480 4900 // request a CAS CMD and go to DCACHE_DIRTY_WAIT state 4481 r_dcache_vci_cas_req = true; 4482 r_dcache_vci_paddr = r_dcache_dirty_paddr.read(); 4483 r_dcache_vci_cas_old = pte; 4484 r_dcache_vci_cas_new = pte | PTE_D_MASK; 4485 r_dcache_fsm = DCACHE_DIRTY_WAIT; 4901 if (state == CACHE_SLOT_STATE_VALID_CC) 4902 { 4903 r_dcache_vci_cas_req = true; 4904 r_dcache_vci_paddr = r_dcache_dirty_paddr.read(); 4905 r_dcache_vci_cas_old = pte; 4906 r_dcache_vci_cas_new = pte | PTE_D_MASK; 4907 r_cas_islocal = false; 4908 } 4909 else 4910 { 4911 r_cas_islocal = true; 4912 r_cas_local_way = way; 4913 r_cas_local_set = set; 4914 r_cas_local_word = word; 4915 r_dcache_vci_cas_new = pte | PTE_D_MASK; 4916 } 4917 4918 4919 r_dcache_fsm = DCACHE_DIRTY_WAIT; 4486 4920 4487 4921 #if DEBUG_DCACHE … … 4506 4940 // - if the CAS is a failure, we just retry the write. 4507 4941 { 4942 uint32_t way = r_cas_local_way.read(); 4943 uint32_t set = r_cas_local_set.read(); 4944 uint32_t word = r_cas_local_word.read(); 4945 paddr_t nline = r_dcache_dirty_paddr.read() / (m_dcache_words<<2); 4946 4508 4947 // coherence clack request (from DSPIN CLACK) 4509 4948 if ( r_dcache_clack_req.read() ) … … 4522 4961 } 4523 4962 4524 if ( r_vci_rsp_data_error.read() ) // bus error 4525 { 4526 std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; 4527 std::cout << "This should not happen in this state" << std::endl; 4528 exit(0); 4529 } 4530 else if ( r_vci_rsp_fifo_dcache.rok() ) // response available 4531 { 4532 vci_rsp_fifo_dcache_get = true; 4533 r_dcache_fsm = DCACHE_IDLE; 4534 4963 if (!r_cas_islocal.read()) 4964 { 4965 if ( r_vci_rsp_data_error.read() ) // bus error 4966 { 4967 std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; 4968 std::cout << "This should not happen in this state" << std::endl; 4969 exit(0); 4970 } 4971 else if ( r_vci_rsp_fifo_dcache.rok() ) // response available 4972 { 4973 vci_rsp_fifo_dcache_get = true; 4974 r_dcache_fsm = DCACHE_IDLE; 4535 4975 #if DEBUG_DCACHE 4536 4976 if ( m_debug_activated ) … … 4540 4980 } 4541 4981 #endif 4982 } 4983 } 4984 else 4985 { 4986 r_dcache.write(way, 4987 set, 4988 word, 4989 r_dcache_vci_cas_new.read()); 4990 //std::cout << "CAS local" << std::endl; 4991 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 4992 { 4993 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 4994 r_dcache_tlb_inval_line = nline; 4995 r_dcache_tlb_inval_set = 0; 4996 r_dcache_fsm_scan_save = DCACHE_IDLE; 4997 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4998 break; 4999 } 5000 5001 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5002 { 5003 r_itlb.reset(); 5004 r_dtlb.reset(); 5005 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 5006 5007 #if DEBUG_DCACHE 5008 if ( m_debug_activated ) 5009 { 5010 std::cout << " <PROC " << name() 5011 << " DCACHE_DIRTY_WAIT> Flush DTLB & ITLB" << std::endl; 5012 } 5013 #endif 5014 } 5015 r_dcache_fsm = DCACHE_IDLE; 4542 5016 } 4543 5017 break; … … 4674 5148 &word ); // unused 4675 5149 5150 r_dcache_cc_state = state; 4676 5151 r_dcache_cc_way = way; 4677 5152 r_dcache_cc_set = set; 4678 4679 if ( state == CACHE_SLOT_STATE_VALID) // hit 4680 { 4681 // need to update the cache state 4682 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update 4683 { 4684 r_dcache_cc_need_write = true; 4685 r_dcache_fsm = DCACHE_CC_UPDT; 4686 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4687 } 4688 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval 4689 { 4690 r_dcache_fsm = DCACHE_CC_INVAL; 5153 /*RWT / ODCCP*/ 5154 if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // hit 5155 { 5156 // need to update the cache state 5157 r_dcache_cc_need_write = true; 5158 r_dcache_cc_cleanup_line_ncc = false; 5159 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update 5160 { 5161 r_dcache_fsm = DCACHE_CC_UPDT; 5162 r_dcache_cc_word = r_cc_receive_word_idx.read(); 5163 } 5164 else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval 5165 { 5166 if (state == CACHE_SLOT_STATE_VALID_NCC) 5167 { 5168 r_dcache_cc_inval_addr = (paddr &~0x3F); 5169 r_dcache_cc_inval_data_cpt = 0; 5170 } 5171 r_dcache_fsm = DCACHE_CC_INVAL; 5172 r_dcache_dirty_save = false; 4691 5173 } 4692 5174 } … … 4716 5198 << " PADDR = " << std::hex << paddr 4717 5199 << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() 4718 << " / HIT = " << ( state == CACHE_SLOT_STATE_VALID) << std::endl;5200 << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl; 4719 5201 } 4720 5202 #endif … … 4722 5204 break; 4723 5205 } 5206 4724 5207 ///////////////////// 4725 5208 case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a … … 4729 5212 size_t way = r_dcache_cc_way.read(); 4730 5213 size_t set = r_dcache_cc_set.read(); 4731 4732 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval 4733 { 4734 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4735 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 4736 r_dcache_tlb_inval_set = 0; 4737 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4738 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4739 break; 4740 } 4741 4742 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush 4743 { 4744 r_itlb.reset(); 4745 r_dtlb.reset(); 4746 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4747 5214 int cache_state = r_dcache_cc_state.read(); 5215 bool dirty_save = false; 5216 5217 if (r_dcache_cc_need_write.read()) 5218 { 5219 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 5220 { 5221 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;//need to remember it was dirty for cleanup 5222 dirty_save = true; 5223 r_dcache_dirty_save = true; 5224 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 5225 r_dcache_tlb_inval_set = 0; 5226 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 5227 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 5228 break; 5229 } 5230 else 5231 { 5232 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5233 { 5234 r_itlb.reset(); 5235 r_dtlb.reset(); 5236 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5237 dirty_save = true; 5238 r_dcache_dirty_save = true; 4748 5239 #if DEBUG_DCACHE 4749 5240 if ( m_debug_activated ) … … 4753 5244 } 4754 5245 #endif 4755 } 4756 4757 assert (not r_dcache_cc_send_req.read() && 4758 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " 4759 "must not be set"); 4760 4761 // Switch slot state to ZOMBI and send CLEANUP command 4762 r_dcache.write_dir( 0, 4763 way, 4764 set, 4765 CACHE_SLOT_STATE_ZOMBI ); 4766 4767 // coherence request completed 4768 r_cc_receive_dcache_req = false; 4769 r_dcache_cc_send_req = true; 4770 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4771 r_dcache_cc_send_way = r_dcache_cc_way.read(); 4772 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4773 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4774 4775 #if DEBUG_DCACHE 4776 if ( m_debug_activated ) 4777 { 4778 std::cout << " <PROC " << name() 4779 << " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec 4780 << " / WAY = " << way 4781 << " / SET = " << set << std::endl; 4782 } 4783 #endif 5246 } 5247 5248 if (cache_state == CACHE_SLOT_STATE_VALID_CC) 5249 { 5250 r_dcache.write_dir( way, 5251 set, 5252 CACHE_SLOT_STATE_ZOMBI ); 5253 } 5254 5255 r_dcache_cc_need_write = false; 5256 } 5257 } 5258 assert (not r_dcache_cc_send_req.read() && 5259 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " 5260 "must not be set"); 5261 // coherence request completed 5262 r_cc_receive_dcache_req = false; 5263 // request multicast acknowledgement 5264 r_dcache_cc_send_req = true; 5265 r_dcache_cc_send_way = way; 5266 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 5267 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 5268 // MODIFIER POUR DIRTY BIT // 5269 if (cache_state == CACHE_SLOT_STATE_VALID_NCC) 5270 { 5271 r_dcache_cc_cleanup_line_ncc = true; 5272 //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data 5273 if (true) //must send data 5274 { 5275 r_dcache_cc_cleanup_updt_data = true; 5276 for (size_t w = 0; w< m_dcache_words; w++) 5277 { 5278 m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; 5279 } 5280 r_dcache_fsm = DCACHE_CC_INVAL_DATA; 5281 } 5282 else 5283 { 5284 r_dcache_cc_cleanup_updt_data = false; 5285 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5286 } 5287 } 5288 else 5289 { 5290 r_dcache_cc_cleanup_updt_data = false; 5291 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5292 } 5293 5294 break; 5295 } 5296 5297 ///////////////////// 5298 case DCACHE_CC_INVAL_DATA: 5299 { 5300 5301 uint32_t rdata; 5302 size_t way; 5303 size_t set; 5304 size_t word; 5305 r_dcache.read_neutral(r_dcache_cc_inval_addr.read(), 5306 &rdata, 5307 &way, 5308 &set, 5309 &word); 5310 if(r_cc_send_data_fifo.wok()) 5311 { 5312 r_dcache_cc_inval_addr = r_dcache_cc_inval_addr.read() + 4; 5313 5314 cleanup_data_updt_fifo_dcache_put = true; 5315 cleanup_data_updt_fifo_dcache_data = rdata; 5316 5317 r_dcache_cc_inval_data_cpt = r_dcache_cc_inval_data_cpt.read() + 1; 5318 if(r_dcache_cc_inval_data_cpt.read() == (m_dcache_words - 1)) 5319 { 5320 r_dcache_cc_inval_data_cpt = 0; 5321 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5322 r_dcache.write_dir( way, 5323 set, 5324 CACHE_SLOT_STATE_ZOMBI ); 5325 } 5326 } 4784 5327 break; 4785 5328 } … … 4792 5335 size_t set = r_dcache_cc_set.read(); 4793 5336 4794 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval4795 {4796 r_dcache_in_tlb[way*m_dcache_sets+set] = false;4797 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();4798 r_dcache_tlb_inval_set = 0;4799 r_dcache_fsm_scan_save = r_dcache_fsm.read();4800 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;4801 4802 break;4803 }4804 4805 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush4806 {4807 r_itlb.reset();4808 r_dtlb.reset();4809 r_dcache_contains_ptd[way*m_dcache_sets+set] = false;5337 if (r_dcache_cc_need_write.read()) 5338 { 5339 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 5340 { 5341 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5342 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 5343 r_dcache_tlb_inval_set = 0; 5344 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 5345 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 5346 break; 5347 } 5348 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5349 { 5350 r_itlb.reset(); 5351 r_dtlb.reset(); 5352 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 4810 5353 4811 5354 #if DEBUG_DCACHE … … 4816 5359 } 4817 5360 #endif 4818 }4819 4820 assert (not r_dcache_cc_send_req.read() &&4821 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "4822 "must not be set");5361 } 5362 5363 assert (not r_dcache_cc_send_req.read() && 5364 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " 5365 "must not be set"); 4823 5366 4824 if ( not r_cc_receive_updt_fifo_be.rok() ) break; 4825 4826 if (r_dcache_cc_need_write.read()) 4827 { 4828 5367 if ( not r_cc_receive_updt_fifo_be.rok() ) break; 5368 4829 5369 #ifdef INSTRUMENTATION 4830 5370 m_cpt_dcache_data_write++; … … 4855 5395 // no need to write in the cache anymore 4856 5396 r_dcache_cc_need_write = false; 4857 4858 5397 // coherence request completed 4859 5398 r_cc_receive_dcache_req = false; … … 5041 5580 r_dcache_vci_unc_req.read()) 5042 5581 or r_vci_cmd_imiss_prio.read() ); 5043 5044 5582 // 1 - Data Read Miss 5045 5583 if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) … … 5048 5586 r_dcache_vci_miss_req = false; 5049 5587 r_vci_cmd_imiss_prio = true; 5050 //m_cpt_dmiss_transaction++;5588 m_cpt_dmiss_transaction++; 5051 5589 } 5052 5590 // 2 - Data Read Uncachable … … 5055 5593 r_vci_cmd_fsm = CMD_DATA_UNC; 5056 5594 r_dcache_vci_unc_req = false; 5057 //m_cpt_dunc_transaction++;5595 m_cpt_dunc_transaction++; 5058 5596 } 5059 5597 // 3 - Data Linked Load … … 5062 5600 r_dcache_vci_ll_req = false; 5063 5601 r_vci_cmd_fsm = CMD_DATA_LL; 5064 //m_cpt_ll_transaction++;5602 m_cpt_ll_transaction++; 5065 5603 } 5066 5604 // 4 - Instruction Miss … … 5070 5608 r_icache_miss_req = false; 5071 5609 r_vci_cmd_imiss_prio = false; 5072 //m_cpt_imiss_transaction++;5610 m_cpt_imiss_transaction++; 5073 5611 } 5074 5612 // 5 - Instruction Uncachable … … 5077 5615 r_vci_cmd_fsm = CMD_INS_UNC; 5078 5616 r_icache_unc_req = false; 5079 //m_cpt_iunc_transaction++;5617 //m_cpt_iunc_transaction++; 5080 5618 } 5081 5619 // 6 - Data Write … … 5086 5624 r_vci_cmd_min = wbuf_min; 5087 5625 r_vci_cmd_max = wbuf_max; 5088 //m_cpt_write_transaction++;5089 //m_length_write_transaction += (wbuf_max-wbuf_min+1);5626 m_cpt_write_transaction++; 5627 m_length_write_transaction += (wbuf_max-wbuf_min+1); 5090 5628 } 5091 5629 // 7 - Data Store Conditionnal … … 5095 5633 r_vci_cmd_cpt = 0; 5096 5634 r_vci_cmd_fsm = CMD_DATA_SC; 5097 //m_cpt_sc_transaction++;5635 //m_cpt_sc_transaction++; 5098 5636 } 5099 5637 // 8 - Compare And Swap … … 5103 5641 r_dcache_vci_cas_req = false; 5104 5642 r_vci_cmd_cpt = 0; 5105 //m_cpt_cas_transaction++;5643 //m_cpt_cas_transaction++; 5106 5644 } 5107 5645 … … 5194 5732 { 5195 5733 r_vci_rsp_cpt = 0; 5196 5734 if (r_dcache_vci_paddr.read() == 0x1f624) std::cout << "Tansaction on barrier, pktid = " << p_vci.rpktid.read() << std::endl; 5197 5735 if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC ) 5198 5736 { … … 5311 5849 else // no error reported 5312 5850 { 5313 if ( r_vci_rsp_fifo_dcache.wok() ) 5851 5852 5853 if ( r_vci_rsp_fifo_dcache.wok() && r_vci_rsp_fifo_rpktid.wok()) 5314 5854 { 5315 5855 assert( (r_vci_rsp_cpt.read() < m_dcache_words) and … … 5319 5859 vci_rsp_fifo_dcache_put = true, 5320 5860 vci_rsp_fifo_dcache_data = p_vci.rdata.read(); 5861 vci_rsp_fifo_rpktid = (p_vci.rpktid.read() == 0x9);//RWT: interpretation of pktid for state (NCC or CC) 5862 vci_rsp_fifo_rpktid_put = true;//RWT 5863 5321 5864 if ( p_vci.reop.read() ) 5322 5865 { 5866 if (r_vci_rsp_cpt.read() != m_dcache_words - 1) std::cout << "assert on proc " << name() << std::endl; 5323 5867 assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and 5324 5868 "The VCI response packet for data miss is too short"); … … 5480 6024 if (p_dspin_p2m.read.read()) 5481 6025 { 5482 if (r_cc_send_last_client.read() == 0) // dcache active request 5483 r_dcache_cc_send_req = false; // reset dcache request 5484 else // icache active request 5485 r_icache_cc_send_req = false; // reset icache request 5486 5487 // go back to idle state 5488 r_cc_send_fsm = CC_SEND_IDLE; 6026 //std::cout << "CLEANUP send on line " << r_dcache_cc_send_nline.read() << std::endl; 6027 if(r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0))//dcache request with data 6028 { 6029 r_cc_send_fsm = CC_SEND_CLEANUP_DATA_UPDT; 6030 } 6031 else 6032 { 6033 if (r_cc_send_last_client.read() == 0) // dcache active request 6034 { 6035 r_dcache_cc_send_req = false; // reset dcache request 6036 } 6037 else // icache active request 6038 { 6039 r_icache_cc_send_req = false; // reset icache request 6040 } 6041 // go back to idle state 6042 r_cc_send_fsm = CC_SEND_IDLE; 6043 } 6044 } 6045 break; 6046 } 6047 /////////////////////////// 6048 case CC_SEND_CLEANUP_DATA_UPDT: 6049 { 6050 if (p_dspin_p2m.read.read()) 6051 { 6052 if(r_cc_send_data_fifo.rok()) 6053 { 6054 /*ODCCP*///std::cout<<"CLEANUP_DATA_UPDT" << std::endl; 6055 m_cpt_data_cleanup++; 6056 cleanup_data_updt_fifo_dcache_get = true; 6057 r_cc_send_cpt_word = r_cc_send_cpt_word.read() + 1; 6058 if (r_cc_send_cpt_word.read() == m_dcache_words-1) 6059 { 6060 //std::cout << "L1 paddr CLEANUP DATA | paddr = " << std::hex << (r_dcache_cc_send_nline.read()*m_dcache_words)*4 << std::dec << std::endl; 6061 /*ODCCP*/ 6062 //std::cout << "CLEANUP with DATA finished by " << name() << std::endl; 6063 r_dcache_cc_send_req = false; 6064 r_dcache_cc_cleanup_updt_data = false; 6065 r_cc_send_cpt_word = 0; 6066 r_cc_send_fsm = CC_SEND_IDLE; 6067 } 6068 } 5489 6069 } 5490 6070 break; … … 5801 6381 vci_rsp_fifo_dcache_put, 5802 6382 vci_rsp_fifo_dcache_data); 6383 //BUG pktid 6384 r_vci_rsp_fifo_rpktid.update(vci_rsp_fifo_rpktid_get, 6385 vci_rsp_fifo_rpktid_put, 6386 vci_rsp_fifo_rpktid); 6387 6388 r_cc_send_data_fifo.update(cleanup_data_updt_fifo_dcache_get, 6389 cleanup_data_updt_fifo_dcache_put, 6390 cleanup_data_updt_fifo_dcache_data); 5803 6391 5804 6392 ///////////////// updt FIFO update ////////////////////// … … 6011 6599 >> (m_nline_width - m_x_width - m_y_width) 6012 6600 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6013 6014 6601 DspinDhccpParam::dspin_set(dspin_send_data, 6015 6602 dest, … … 6027 6614 DspinDhccpParam::TYPE_CLEANUP_DATA, 6028 6615 DspinDhccpParam::P2M_TYPE); 6616 6617 DspinDhccpParam::dspin_set(dspin_send_data, 6618 (r_dcache_cc_cleanup_line_ncc.read() and (r_cc_send_last_client.read() == 0)), 6619 DspinDhccpParam::CLEANUP_NCC); 6029 6620 } 6030 6621 else // icache active request … … 6049 6640 DspinDhccpParam::TYPE_CLEANUP_INST, 6050 6641 DspinDhccpParam::P2M_TYPE); 6642 6643 DspinDhccpParam::dspin_set(dspin_send_data, 6644 0, 6645 DspinDhccpParam::CLEANUP_NCC); 6646 6647 6051 6648 } 6052 6649 // send flit … … 6060 6657 { 6061 6658 // initialize dspin send data 6062 // DspinDhccpParam::dspin_set(dspin_send_data,6063 // 1,6064 // DspinDhccpParam::P2M_EOP);6065 6066 6659 if(r_cc_send_last_client.read() == 0) // dcache active request 6067 6660 { … … 6079 6672 p_dspin_p2m.data = dspin_send_data; 6080 6673 p_dspin_p2m.write = true; 6081 p_dspin_p2m.eop = true; 6674 p_dspin_p2m.eop = ! (r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0)); 6675 break; 6676 } 6677 /////////////////////// 6678 case CC_SEND_CLEANUP_DATA_UPDT: 6679 { 6680 /*if (r_cc_send_cpt_word.read() == m_dcache_words-1) 6681 { 6682 DspinDhccpParam::dspin_set(dspin_send_data, 6683 1, 6684 DspinDhccpParam::FROM_L1_EOP); 6685 } 6686 else 6687 { 6688 DspinDhccpParam::dspin_set(dspin_send_data, 6689 0, 6690 DspinDhccpParam::FROM_L1_EOP); 6691 }*/ 6692 6693 DspinDhccpParam::dspin_set(dspin_send_data, 6694 r_cc_send_data_fifo.read(), 6695 DspinDhccpParam::CLEANUP_DATA_UPDT); 6696 6697 p_dspin_p2m.data = dspin_send_data; 6698 //std::cout << "genmoore CLEANUP DATA UPDT : dspin_send_data = " << std::hex << dspin_send_data << std::dec << std::endl; 6699 p_dspin_p2m.write = true; 6700 p_dspin_p2m.eop = (r_cc_send_cpt_word.read() == m_dcache_words-1); 6082 6701 break; 6083 6702 } -
branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
r449 r477 96 96 97 97 bool valid; // entry valid 98 bool cache_coherent; // WB or WT policy 98 99 bool is_cnt; // directory entry is in counter mode 99 100 bool dirty; // entry dirty … … 107 108 { 108 109 valid = false; 110 cache_coherent= false; 109 111 is_cnt = false; 110 112 dirty = false; … … 123 125 { 124 126 valid = source.valid; 127 cache_coherent= source.cache_coherent; 125 128 is_cnt = source.is_cnt; 126 129 dirty = source.dirty; … … 138 141 { 139 142 valid = false; 143 cache_coherent = false; 140 144 is_cnt = false; 141 145 dirty = false; … … 150 154 { 151 155 valid = source.valid; 156 cache_coherent = source.cache_coherent; 152 157 is_cnt = source.is_cnt; 153 158 dirty = source.dirty; … … 165 170 { 166 171 std::cout << "Valid = " << valid 172 << " ; COHERENCE = " << cache_coherent 167 173 << " ; IS COUNT = " << is_cnt 168 174 << " ; Dirty = " << dirty -
branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r468 r477 131 131 CC_SEND_XRAM_RSP_INVAL_HEADER, 132 132 CC_SEND_XRAM_RSP_INVAL_NLINE, 133 CC_SEND_READ_NCC_INVAL_HEADER, 134 CC_SEND_READ_NCC_INVAL_NLINE, 135 CC_SEND_WRITE_NCC_INVAL_HEADER, 136 CC_SEND_WRITE_NCC_INVAL_NLINE, 133 137 CC_SEND_WRITE_BRDCAST_HEADER, 134 138 CC_SEND_WRITE_BRDCAST_NLINE, … … 178 182 READ_DIR_REQ, 179 183 READ_DIR_LOCK, 184 READ_IVT_LOCK, 185 READ_WAIT, 180 186 READ_DIR_HIT, 181 187 READ_HEAP_REQ, … … 197 203 WRITE_DIR_REQ, 198 204 WRITE_DIR_LOCK, 205 WRITE_IVT_LOCK_HIT_WB, 199 206 WRITE_DIR_READ, 200 207 WRITE_DIR_HIT, … … 205 212 WRITE_UPT_DEC, 206 213 WRITE_RSP, 214 WRITE_MISS_IVT_LOCK, 207 215 WRITE_MISS_TRT_LOCK, 208 216 WRITE_MISS_TRT_DATA, … … 253 261 IXR_CMD_CAS_IDLE, 254 262 IXR_CMD_XRAM_IDLE, 263 IXR_CMD_CLEANUP_IDLE, 255 264 IXR_CMD_READ, 256 265 IXR_CMD_WRITE, 257 266 IXR_CMD_CAS, 258 IXR_CMD_XRAM 267 IXR_CMD_XRAM, 268 IXR_CMD_CLEANUP_DATA 259 269 }; 260 270 … … 290 300 CLEANUP_IDLE, 291 301 CLEANUP_GET_NLINE, 302 CLEANUP_GET_DATA, 292 303 CLEANUP_DIR_REQ, 293 304 CLEANUP_DIR_LOCK, 294 305 CLEANUP_DIR_WRITE, 306 CLEANUP_IVT_LOCK_DATA, 307 CLEANUP_IVT_CLEAR_DATA, 308 CLEANUP_READ_RSP, 295 309 CLEANUP_HEAP_REQ, 296 310 CLEANUP_HEAP_LOCK, … … 302 316 CLEANUP_IVT_CLEAR, 303 317 CLEANUP_WRITE_RSP, 318 CLEANUP_IXR_REQ, 319 CLEANUP_WAIT, 304 320 CLEANUP_CONFIG_ACK, 305 321 CLEANUP_SEND_CLACK … … 325 341 ALLOC_TRT_CAS, 326 342 ALLOC_TRT_XRAM_RSP, 327 ALLOC_TRT_IXR_RSP 343 ALLOC_TRT_IXR_RSP, 344 ALLOC_TRT_CLEANUP 328 345 }; 329 346 … … 340 357 { 341 358 ALLOC_IVT_WRITE, 359 ALLOC_IVT_READ, 342 360 ALLOC_IVT_XRAM_RSP, 343 361 ALLOC_IVT_CLEANUP, … … 434 452 uint32_t m_cpt_sc; // Number of SC transactions 435 453 uint32_t m_cpt_cas; // Number of CAS transactions 454 455 uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK 456 uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK 457 uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK 458 uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK 459 uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK 460 uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK 461 uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK 462 uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK 463 uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK 464 uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK 465 466 uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused 467 uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used 468 uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used 469 uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used 470 uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used 471 uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used 472 473 uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK 474 uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK 475 uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK 476 uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK 477 uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK 478 479 uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK 480 uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK 481 uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK 482 uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK 483 uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK 484 485 uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used 486 uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used 487 uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used 488 uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used 489 uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used 490 491 uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused 492 493 uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK 494 uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK 495 uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK 496 uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait UPT LOCK 497 uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK 498 499 uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK 500 uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK 501 uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK 502 uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK 503 uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK 504 505 uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used 506 uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used 507 uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used 508 uint32_t m_cpt_cleanup_fsm_ivt_used; // NB cycles UPT LOCK used 509 uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used 510 511 uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused 512 uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused 513 514 uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK 515 uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK 516 uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK 517 uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK 518 uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK 519 520 uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK 521 uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK 522 uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK 523 uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK 524 uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK 525 526 uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used 527 uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used 528 uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used 529 uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used 530 uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used 531 532 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 533 534 //RWT 535 uint32_t m_cpt_cleanup_data; 536 uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ 537 uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE 538 uint32_t m_cpt_ncc_to_cc; // NB change from NCC to CC 539 540 uint32_t m_cpt_read_data_unc; 541 uint32_t m_cpt_read_data_miss_CC; 542 uint32_t m_cpt_read_ins_unc; 543 uint32_t m_cpt_read_ins_miss; 544 uint32_t m_cpt_read_ll_CC; 545 uint32_t m_cpt_read_data_miss_NCC; 546 uint32_t m_cpt_read_ll_NCC; 547 uint32_t m_cpt_read_WTF; 436 548 437 549 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs … … 481 593 ~VciMemCache(); 482 594 595 void clear_stats(); 483 596 void print_stats(); 484 597 void print_trace(); … … 657 770 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table 658 771 772 //RWT: Buffer between READ fsm and CC_SEND fsm (send inval) 773 sc_signal<bool> r_read_to_cc_send_req; 774 sc_signal<size_t> r_read_to_cc_send_dest; 775 sc_signal<addr_t> r_read_to_cc_send_nline; 776 sc_signal<bool> r_read_to_cc_send_inst; 777 778 //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) 779 sc_signal<bool> r_read_to_cleanup_req; // valid request 780 sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index 781 sc_signal<size_t> r_read_to_cleanup_srcid; 782 sc_signal<size_t> r_read_to_cleanup_length; 783 sc_signal<size_t> r_read_to_cleanup_first_word; 784 sc_signal<bool> r_read_to_cleanup_cached_read; 785 sc_signal<bool> r_read_to_cleanup_is_ll; 786 sc_signal<addr_t> r_read_to_cleanup_addr; 787 sc_signal<addr_t> r_read_to_cleanup_ll_key; 788 789 //RWT: 790 sc_signal<bool> r_read_coherent; // State of the cache slot after transaction 791 sc_signal<bool> r_read_ll_done; 792 659 793 /////////////////////////////////////////////////////////////// 660 794 // Registers controlled by the WRITE fsm … … 721 855 sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table 722 856 857 // RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state) 858 sc_signal<bool> r_write_to_cleanup_req; // valid request 859 sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index 860 861 // RWT 862 sc_signal<bool> r_write_coherent; // cache slot state after transaction 863 864 //Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT) 865 sc_signal<bool> r_write_to_cc_send_req; 866 sc_signal<size_t> r_write_to_cc_send_dest; 867 868 723 869 ///////////////////////////////////////////////////////// 724 870 // Registers controlled by MULTI_ACK fsm … … 788 934 sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid 789 935 sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid 936 sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key; 937 938 //RWT 939 sc_signal<size_t> r_cleanup_read_srcid; 940 sc_signal<size_t> r_cleanup_read_trdid; 941 sc_signal<size_t> r_cleanup_read_pktid; 942 sc_signal<bool> r_cleanup_read_need_rsp; 943 sc_signal<bool> r_cleanup_to_tgt_rsp_type; 944 sc_signal<data_t> * r_cleanup_to_tgt_rsp_data; 945 sc_signal<size_t> r_cleanup_to_tgt_rsp_length; 946 sc_signal<size_t> r_cleanup_to_tgt_rsp_first_word; 790 947 791 948 /////////////////////////////////////////////////////// … … 813 970 sc_signal<data_t> * r_cas_data; // cache line data 814 971 972 sc_signal<bool> r_cas_coherent; 973 815 974 // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) 816 975 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request … … 906 1065 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table 907 1066 1067 //RWT 1068 sc_signal<bool> r_xram_rsp_victim_coherent; // victim's cache slot state 1069 sc_signal<bool> r_xram_rsp_coherent; // coherence of the read 908 1070 //////////////////////////////////////////////////// 909 1071 // Registers controlled by the IXR_CMD fsm … … 966 1128 sc_signal<int> r_alloc_heap_fsm; 967 1129 sc_signal<unsigned> r_alloc_heap_reset_cpt; 1130 1131 1132 //////////////////////////////////////////////////// 1133 // REGISTERS FOR ODCCP 1134 //////////////////////////////////////////////////// 1135 1136 sc_signal<uint32_t> r_cleanup_data_index; 1137 sc_signal<uint32_t> r_cleanup_trdid; 1138 sc_signal<uint32_t> r_cleanup_pktid; 1139 sc_signal<bool> r_cleanup_coherent; 1140 sc_signal<data_t> *r_cleanup_data; 1141 sc_signal<data_t> *r_cleanup_old_data; 1142 sc_signal<bool> r_cleanup_contains_data; 1143 1144 sc_signal<bool> r_cleanup_ncc; 1145 sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty; 1146 sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending; 1147 1148 sc_signal<bool> r_cleanup_to_ixr_cmd_req; 1149 sc_signal<data_t> *r_cleanup_to_ixr_cmd_data; 1150 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid; 1151 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_trdid; 1152 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid; 1153 sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline; 968 1154 }; // end class VciMemCache 969 1155 -
branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h
r422 r477 294 294 } 295 295 296 /////////////////////////////////////////////////////////////////////// 297 // The hit_write() function looks if an XRAM write transaction exists 298 // for a given line. 299 // Arguments : 300 // - index : (return argument) the index of the hit entry, if there is 301 // - nline : the index (zy) of the requested line 302 // The function returns true if a write request has already been sent 303 /////////////////////////////////////////////////////////////////////// 304 bool hit_write(const addr_t nline, size_t* index) 305 { 306 for(size_t i=0; i<size_tab; i++){ 307 if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) { 308 *index = i; 309 return true; 310 } 311 } 312 return false; 313 } 296 314 ///////////////////////////////////////////////////////////////////// 297 315 // The write_data_mask() function writes a vector of data (a line). -
branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r468 r477 107 107 "CC_SEND_XRAM_RSP_INVAL_HEADER", 108 108 "CC_SEND_XRAM_RSP_INVAL_NLINE", 109 "CC_SEND_READ_NCC_INVAL_HEADER", 110 "CC_SEND_READ_NCC_INVAL_NLINE", 111 "CC_SEND_WRITE_NCC_INVAL_HEADER", 112 "CC_SEND_WRITE_NCC_INVAL_NLINE", 109 113 "CC_SEND_WRITE_BRDCAST_HEADER", 110 114 "CC_SEND_WRITE_BRDCAST_NLINE", … … 148 152 "READ_DIR_REQ", 149 153 "READ_DIR_LOCK", 154 "READ_IVT_LOCK", 155 "READ_WAIT", 150 156 "READ_DIR_HIT", 151 157 "READ_HEAP_REQ", … … 165 171 "WRITE_DIR_REQ", 166 172 "WRITE_DIR_LOCK", 173 "WRITE_IVT_LOCK_HIT_WB", 167 174 "WRITE_DIR_READ", 168 175 "WRITE_DIR_HIT", … … 173 180 "WRITE_UPT_DEC", 174 181 "WRITE_RSP", 182 "WRITE_MISS_IVT_LOCK", 175 183 "WRITE_MISS_TRT_LOCK", 176 184 "WRITE_MISS_TRT_DATA", … … 215 223 "IXR_CMD_CAS_IDLE", 216 224 "IXR_CMD_XRAM_IDLE", 225 "IXR_CMD_CLEANUP_IDLE", 217 226 "IXR_CMD_READ", 218 227 "IXR_CMD_WRITE", 219 228 "IXR_CMD_CAS", 220 "IXR_CMD_XRAM" 229 "IXR_CMD_XRAM", 230 "IXR_CMD_CLEANUP_DATA" 221 231 }; 222 232 const char *cas_fsm_str[] = … … 248 258 "CLEANUP_IDLE", 249 259 "CLEANUP_GET_NLINE", 260 "CLEANUP_GET_DATA", 250 261 "CLEANUP_DIR_REQ", 251 262 "CLEANUP_DIR_LOCK", 252 263 "CLEANUP_DIR_WRITE", 264 "CLEANUP_IVT_LOCK_DATA", 265 "CLEANUP_IVT_CLEAR_DATA", 266 "CLEANUP_READ_RSP", 253 267 "CLEANUP_HEAP_REQ", 254 268 "CLEANUP_HEAP_LOCK", … … 260 274 "CLEANUP_IVT_CLEAR", 261 275 "CLEANUP_WRITE_RSP", 276 "CLEANUP_IXR_REQ", 277 "CLEANUP_WAIT", 262 278 "CLEANUP_CONFIG_ACK", 263 279 "CLEANUP_SEND_CLACK" … … 279 295 "ALLOC_TRT_CAS", 280 296 "ALLOC_TRT_XRAM_RSP", 281 "ALLOC_TRT_IXR_RSP" 297 "ALLOC_TRT_IXR_RSP", 298 "ALLOC_TRT_CLEANUP" 282 299 }; 283 300 const char *alloc_upt_fsm_str[] = … … 290 307 { 291 308 "ALLOC_IVT_WRITE", 309 "ALLOC_IVT_READ", 292 310 "ALLOC_IVT_XRAM_RSP", 293 311 "ALLOC_IVT_CLEANUP", … … 339 357 : soclib::caba::BaseModule(name), 340 358 359 m_monitor_ok(false), 341 360 p_clk( "p_clk" ), 342 361 p_resetn( "p_resetn" ), … … 526 545 r_cas_data = new sc_signal<data_t>[nwords]; 527 546 r_cas_rdata = new sc_signal<data_t>[2]; 547 548 // Allocation for ODCCP 549 r_cleanup_data = new sc_signal<data_t>[nwords]; 550 r_cleanup_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 551 r_cleanup_to_tgt_rsp_data = new sc_signal<data_t>[nwords]; 552 r_cleanup_old_data = new sc_signal<data_t>[nwords]; 528 553 529 554 // Allocation for debug … … 641 666 642 667 ///////////////////////////////////////// 668 tmpl(void) ::clear_stats() 669 ///////////////////////////////////////// 670 { 671 672 m_cpt_cycles = 0; 673 m_cpt_read = 0; 674 m_cpt_read_miss = 0; 675 m_cpt_write = 0; 676 m_cpt_write_miss = 0; 677 m_cpt_write_cells = 0; 678 m_cpt_write_dirty = 0; 679 m_cpt_update = 0; 680 m_cpt_update_mult = 0; 681 m_cpt_inval_brdcast = 0; 682 m_cpt_inval = 0; 683 m_cpt_inval_mult = 0; 684 m_cpt_cleanup = 0; 685 m_cpt_ll = 0; 686 m_cpt_sc = 0; 687 m_cpt_cas = 0; 688 m_cpt_trt_full = 0; 689 m_cpt_trt_rb = 0; 690 m_cpt_dir_unused = 0; 691 m_cpt_ivt_unused = 0; 692 m_cpt_upt_unused = 0; 693 m_cpt_heap_unused = 0; 694 m_cpt_trt_unused = 0; 695 m_cpt_read_fsm_n_dir_lock = 0; 696 m_cpt_read_fsm_dir_lock = 0; 697 m_cpt_read_fsm_dir_used = 0; 698 m_cpt_read_fsm_trt_lock = 0; 699 m_cpt_read_fsm_heap_lock = 0; 700 m_cpt_write_fsm_dir_lock = 0; 701 m_cpt_write_fsm_n_dir_lock = 0; 702 m_cpt_write_fsm_upt_lock = 0; 703 m_cpt_write_fsm_heap_lock = 0; 704 m_cpt_write_fsm_dir_used = 0; 705 m_cpt_write_fsm_trt_lock = 0; 706 m_cpt_cas_fsm_n_dir_lock = 0; 707 m_cpt_cas_fsm_dir_lock = 0; 708 m_cpt_cas_fsm_upt_lock = 0; 709 m_cpt_cas_fsm_heap_lock = 0; 710 m_cpt_cas_fsm_trt_lock = 0; 711 m_cpt_cas_fsm_dir_used = 0; 712 m_cpt_xram_rsp_fsm_n_dir_lock = 0; 713 m_cpt_xram_rsp_fsm_dir_lock = 0; 714 m_cpt_xram_rsp_fsm_trt_lock = 0; 715 m_cpt_xram_rsp_fsm_upt_lock = 0; 716 m_cpt_xram_rsp_fsm_heap_lock = 0; 717 m_cpt_xram_rsp_fsm_dir_used = 0; 718 m_cpt_cleanup_fsm_dir_lock = 0; 719 m_cpt_cleanup_fsm_n_dir_lock = 0; 720 m_cpt_cleanup_fsm_heap_lock = 0; 721 m_cpt_cleanup_fsm_ivt_lock = 0; 722 m_cpt_cleanup_fsm_dir_used = 0; 723 m_cpt_ixr_fsm_trt_lock = 0; 724 m_cpt_multi_ack_fsm_upt_lock = 0; 725 m_cpt_read_data_unc = 0; 726 m_cpt_read_data_miss_CC = 0; 727 m_cpt_read_ins_unc = 0; 728 m_cpt_read_ins_miss = 0; 729 m_cpt_read_ll_CC = 0; 730 m_cpt_read_data_miss_NCC = 0; 731 m_cpt_read_ll_NCC = 0; 732 m_cpt_read_WTF = 0; 733 m_cpt_cleanup_data = 0; 734 m_cpt_ncc_to_cc_read = 0; 735 m_cpt_ncc_to_cc_write = 0; 736 m_cpt_ncc_to_cc = 0; 737 } 738 739 ///////////////////////////////////////// 643 740 tmpl(void) ::print_stats() 644 741 ///////////////////////////////////////// … … 647 744 std::cout 648 745 << "MEM_CACHE " << name() << " / Time = " << m_cpt_cycles << std::endl 649 << "- READ RATE = " << (double) m_cpt_read/m_cpt_cycles << std::endl 650 << "- READ TOTAL = " << m_cpt_read << std::endl 651 << "- READ MISS RATE = " << (double) m_cpt_read_miss/m_cpt_read << std::endl 652 << "- WRITE RATE = " << (double) m_cpt_write/m_cpt_cycles << std::endl 653 << "- WRITE TOTAL = " << m_cpt_write << std::endl 654 << "- WRITE MISS RATE = " << (double) m_cpt_write_miss/m_cpt_write << std::endl 655 << "- WRITE BURST LENGTH = " << (double) m_cpt_write_cells/m_cpt_write << std::endl 656 << "- WRITE BURST TOTAL = " << m_cpt_write_cells << std::endl 657 << "- REQUESTS TRT FULL = " << m_cpt_trt_full << std::endl 658 << "- READ TRT BLOKED HIT = " << m_cpt_trt_rb << std::endl 659 << "- UPDATE RATE = " << (double) m_cpt_update/m_cpt_cycles << std::endl 660 << "- UPDATE ARITY = " << (double) m_cpt_update_mult/m_cpt_update << std::endl 661 << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast) /m_cpt_cycles << std::endl 662 << "- INVAL MULTICAST ARITY= " << (double) m_cpt_inval_mult/ (m_cpt_inval-m_cpt_inval_brdcast) << std::endl 663 << "- INVAL BROADCAST RATE = " << (double) m_cpt_inval_brdcast/m_cpt_cycles << std::endl 664 << "- SAVE DIRTY RATE = " << (double) m_cpt_write_dirty/m_cpt_cycles << std::endl 665 << "- CLEANUP RATE = " << (double) m_cpt_cleanup/m_cpt_cycles << std::endl 666 << "- LL RATE = " << (double) m_cpt_ll/m_cpt_cycles << std::endl 667 << "- SC RATE = " << (double) m_cpt_sc/m_cpt_cycles << std::endl 668 << "- CAS RATE = " << (double) m_cpt_cas/m_cpt_cycles << std::endl; 746 << "- READ RATE = " << (double) m_cpt_read/m_cpt_cycles << std::endl 747 << "- READ TOTAL = " << m_cpt_read << std::endl 748 << "- READ MISS RATE = " << (double) m_cpt_read_miss/m_cpt_read << std::endl 749 << "- WRITE RATE = " << (double) m_cpt_write/m_cpt_cycles << std::endl 750 << "- WRITE TOTAL = " << m_cpt_write << std::endl 751 << "- WRITE MISS RATE = " << (double) m_cpt_write_miss/m_cpt_write << std::endl 752 << "- WRITE BURST LENGTH = " << (double) m_cpt_write_cells/m_cpt_write << std::endl 753 << "- WRITE BURST TOTAL = " << m_cpt_write_cells << std::endl 754 << "- REQUESTS TRT FULL = " << m_cpt_trt_full << std::endl 755 << "- READ TRT BLOKED HIT = " << m_cpt_trt_rb << std::endl 756 << "- UPDATE RATE = " << (double) m_cpt_update/m_cpt_cycles << std::endl 757 << "- UPDATE ARITY = " << (double) m_cpt_update_mult/m_cpt_update << std::endl 758 << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast) /m_cpt_cycles << std::endl 759 << "- INVAL MULTICAST ARITY = " << (double) m_cpt_inval_mult/ (m_cpt_inval-m_cpt_inval_brdcast) << std::endl 760 << "- INVAL BROADCAST RATE = " << (double) m_cpt_inval_brdcast/m_cpt_cycles << std::endl 761 << "- SAVE DIRTY RATE = " << (double) m_cpt_write_dirty/m_cpt_cycles << std::endl 762 << "- CLEANUP RATE = " << (double) m_cpt_cleanup/m_cpt_cycles << std::endl 763 << "- LL RATE = " << (double) m_cpt_ll/m_cpt_cycles << std::endl 764 << "- SC RATE = " << (double) m_cpt_sc/m_cpt_cycles << std::endl 765 << "- CAS RATE = " << (double) m_cpt_cas/m_cpt_cycles << std::endl << std::endl 766 767 << "- WAIT DIR LOCK in READ_FSM = " << (double) m_cpt_read_fsm_dir_lock/m_cpt_read_fsm_n_dir_lock << std::endl 768 << "- NB CYCLES IN DIR LOCK in READ_FSM = " << (double) m_cpt_read_fsm_dir_used/m_cpt_read_fsm_n_dir_lock << std::endl 769 << "- WAIT DIR LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_dir_lock/m_cpt_write_fsm_n_dir_lock << std::endl 770 << "- NB CYCLES IN DIR LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_dir_used/m_cpt_write_fsm_n_dir_lock << std::endl 771 << "- WAIT DIR LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_dir_lock/m_cpt_xram_rsp_fsm_n_dir_lock << std::endl 772 << "- NB CYCLES IN DIR LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_dir_used/m_cpt_xram_rsp_fsm_n_dir_lock << std::endl 773 << "- WAIT DIR LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_dir_lock/m_cpt_cleanup_fsm_n_dir_lock << std::endl 774 << "- NB CYCLES IN DIR LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_dir_used/m_cpt_cleanup_fsm_n_dir_lock << std::endl 775 << "- WAIT DIR LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_dir_lock/m_cpt_cas_fsm_n_dir_lock << std::endl 776 << "- NB CYCLES IN LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_dir_used/m_cpt_cas_fsm_n_dir_lock << std::endl 777 << "- DIR UNUSED RATE = " << (double) m_cpt_dir_unused/m_cpt_cycles << std::endl << std::endl 778 779 << "- WAIT TRT LOCK in READ_FSM = " << (double) m_cpt_read_fsm_trt_lock/m_cpt_read_fsm_n_trt_lock << std::endl 780 << "- NB CYCLES IN TRT LOCK in READ_FSM = " << (double) m_cpt_read_fsm_trt_used/m_cpt_read_fsm_n_trt_lock << std::endl 781 << "- WAIT TRT LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_trt_lock/m_cpt_write_fsm_n_trt_lock << std::endl 782 << "- NB CYCLES IN TRT LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_trt_used/m_cpt_write_fsm_n_trt_lock << std::endl 783 << "- WAIT TRT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_trt_lock/m_cpt_cas_fsm_n_trt_lock << std::endl 784 << "- NB CYCLES IN TRT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_trt_used/m_cpt_cas_fsm_n_trt_lock << std::endl 785 << "- WAIT TRT LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_trt_lock/m_cpt_xram_rsp_fsm_n_trt_lock << std::endl 786 << "- NB CYCLES IN TRT LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_trt_used/m_cpt_xram_rsp_fsm_n_trt_lock << std::endl 787 << "- WAIT TRT LOCK in IXR_FSM = " << (double) m_cpt_ixr_fsm_trt_lock/m_cpt_ixr_fsm_n_trt_lock << std::endl 788 << "- NB CYCLES IN TRT LOCK in IXR_FSM = " << (double) m_cpt_ixr_fsm_trt_used/m_cpt_ixr_fsm_n_trt_lock << std::endl 789 << "- TRT UNUSED RATE = " << (double) m_cpt_trt_unused/m_cpt_cycles << std::endl << std::endl 790 791 << "- WAIT UPT LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_upt_lock/m_cpt_write_fsm_n_upt_lock << std::endl 792 << "- NB CYCLES IN UPT LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_upt_used/m_cpt_write_fsm_n_upt_lock << std::endl 793 << "- WAIT UPT LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_upt_lock/m_cpt_xram_rsp_fsm_n_upt_lock << std::endl 794 << "- NB CYCLES IN UPT LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_upt_used/m_cpt_xram_rsp_fsm_n_upt_lock << std::endl 795 << "- WAIT UPT LOCK in MULTIACK_FSM = " << (double) m_cpt_multi_ack_fsm_upt_lock/m_cpt_multi_ack_fsm_n_upt_lock << std::endl 796 << "- NB CYCLES IN UPT LOCK in MULTIACK_FSM = " << (double) m_cpt_multi_ack_fsm_upt_used/m_cpt_multi_ack_fsm_n_upt_lock << std::endl 797 << "- WAIT UPT LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_ivt_lock/m_cpt_cleanup_fsm_n_upt_lock << std::endl 798 << "- NB CYCLES IN UPT LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_ivt_used/m_cpt_cleanup_fsm_n_upt_lock << std::endl 799 << "- WAIT UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_lock/m_cpt_cas_fsm_n_upt_lock << std::endl 800 << "- NB CYCLES IN UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_used/m_cpt_cas_fsm_n_upt_lock << std::endl 801 << "- UPT UNUSED RATE = " << (double) m_cpt_upt_unused/m_cpt_cycles << std::endl << std::endl 802 << "- IVT UNUSED RATE = " << (double) m_cpt_ivt_unused/m_cpt_cycles << std::endl << std::endl 803 804 << "- WAIT HEAP LOCK in READ_FSM = " << (double) m_cpt_read_fsm_heap_lock/m_cpt_read_fsm_n_heap_lock << std::endl 805 << "- NB CYCLES IN HEAP LOCK in READ_FSM = " << (double) m_cpt_read_fsm_heap_used/m_cpt_read_fsm_n_heap_lock << std::endl 806 << "- WAIT HEAP LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_heap_lock/m_cpt_write_fsm_n_heap_lock << std::endl 807 << "- NB CYCLES IN HEAP LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_heap_used/m_cpt_write_fsm_n_heap_lock << std::endl 808 << "- WAIT HEAP LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_heap_lock/m_cpt_xram_rsp_fsm_n_heap_lock << std::endl 809 << "- NB CYCLES IN HEAP LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_heap_used/m_cpt_xram_rsp_fsm_n_heap_lock << std::endl 810 << "- WAIT HEAP LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_heap_lock/m_cpt_cleanup_fsm_n_heap_lock << std::endl 811 << "- NB CYCLES IN HEAP LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_heap_used/m_cpt_cleanup_fsm_n_heap_lock << std::endl 812 << "- WAIT HEAP LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_heap_lock/m_cpt_cas_fsm_n_heap_lock << std::endl 813 << "- NB CYCLES IN HEAP LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_heap_used/m_cpt_cas_fsm_n_heap_lock << std::endl 814 << "- HEAP UNUSED RATE = " << (double) m_cpt_heap_unused/m_cpt_cycles << std::endl 815 816 << "- READ DATA UNC = " << (double) m_cpt_read_data_unc << std::endl 817 << "- READ DATA MISS CC = " << (double) m_cpt_read_data_miss_CC << std::endl 818 << "- READ INS UNC = " << (double) m_cpt_read_ins_unc << std::endl 819 << "- READ INS MISS = " << (double) m_cpt_read_ins_miss << std::endl 820 << "- READ LL CC = " << (double) m_cpt_read_ll_CC << std::endl 821 << "- READ DATA MISS NCC = " << (double) m_cpt_read_data_miss_NCC << std::endl 822 << "- READ LL NCC = " << (double) m_cpt_read_ll_NCC << std::endl 823 << "- READ OTHER = " << (double) m_cpt_read_WTF << std::endl 824 << "- CLEANUP + DATA = " << (double) m_cpt_cleanup_data << std::endl 825 << "- NCC TO CC READ = " << (double) m_cpt_ncc_to_cc_read << std::endl 826 << "- NCC TO CC WRITE = " << (double) m_cpt_ncc_to_cc_write << std::endl 827 << "- NCC TO CC = " << (double) m_cpt_ncc_to_cc << std::endl; 669 828 } 670 829 … … 685 844 delete [] r_write_be; 686 845 delete [] r_write_to_cc_send_data; 846 847 delete [] r_cleanup_data; 848 delete [] r_cleanup_to_ixr_cmd_data; 849 delete [] r_cleanup_to_tgt_rsp_data; 850 delete [] r_cleanup_old_data; 687 851 } 688 852 … … 763 927 r_read_to_tgt_rsp_req = false; 764 928 r_read_to_ixr_cmd_req = false; 929 r_read_to_cc_send_req = false; 930 r_read_to_cleanup_req = false; 765 931 766 932 r_write_to_tgt_rsp_req = false; … … 820 986 r_tgt_rsp_key_sent = false; 821 987 988 // ODCCP 989 r_cleanup_data_index = 0; 990 r_cleanup_trdid = 0; 991 r_cleanup_pktid = 0; 992 r_cleanup_contains_data = false; 993 r_cleanup_ncc = false; 994 r_cleanup_to_ixr_cmd_ncc_l1_dirty = false; 995 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; 996 r_cleanup_to_ixr_cmd_req = false; 997 r_cleanup_to_ixr_cmd_srcid = 0; 998 r_cleanup_to_ixr_cmd_trdid = 0; 999 r_cleanup_to_ixr_cmd_pktid = 0; 1000 r_cleanup_to_ixr_cmd_nline = 0; 1001 for (size_t word = 0; word < m_words; word ++) 1002 { 1003 r_cleanup_to_ixr_cmd_data[word] = 0; 1004 r_cleanup_data[word] = 0; 1005 } 1006 1007 822 1008 // Activity counters 823 m_cpt_cycles = 0; 824 m_cpt_read = 0; 825 m_cpt_read_miss = 0; 826 m_cpt_write = 0; 827 m_cpt_write_miss = 0; 828 m_cpt_write_cells = 0; 829 m_cpt_write_dirty = 0; 830 m_cpt_update = 0; 831 m_cpt_update_mult = 0; 832 m_cpt_inval_brdcast = 0; 833 m_cpt_inval = 0; 834 m_cpt_inval_mult = 0; 835 m_cpt_cleanup = 0; 836 m_cpt_ll = 0; 837 m_cpt_sc = 0; 838 m_cpt_cas = 0; 839 m_cpt_trt_full = 0; 840 m_cpt_trt_rb = 0; 841 1009 m_cpt_cycles = 0; 1010 m_cpt_read = 0; 1011 m_cpt_read_miss = 0; 1012 m_cpt_write = 0; 1013 m_cpt_write_miss = 0; 1014 m_cpt_write_cells = 0; 1015 m_cpt_write_dirty = 0; 1016 m_cpt_update = 0; 1017 m_cpt_update_mult = 0; 1018 m_cpt_inval_brdcast = 0; 1019 m_cpt_inval = 0; 1020 m_cpt_inval_mult = 0; 1021 m_cpt_cleanup = 0; 1022 m_cpt_ll = 0; 1023 m_cpt_sc = 0; 1024 m_cpt_cas = 0; 1025 m_cpt_trt_full = 0; 1026 m_cpt_trt_rb = 0; 1027 m_cpt_dir_unused = 0; 1028 m_cpt_upt_unused = 0; 1029 m_cpt_ivt_unused = 0; 1030 m_cpt_heap_unused = 0; 1031 m_cpt_trt_unused = 0; 1032 m_cpt_read_fsm_n_dir_lock = 0; 1033 m_cpt_read_fsm_dir_lock = 0; 1034 m_cpt_read_fsm_dir_used = 0; 1035 m_cpt_read_fsm_trt_lock = 0; 1036 m_cpt_read_fsm_heap_lock = 0; 1037 m_cpt_write_fsm_dir_lock = 0; 1038 m_cpt_write_fsm_n_dir_lock = 0; 1039 m_cpt_write_fsm_upt_lock = 0; 1040 m_cpt_write_fsm_heap_lock = 0; 1041 m_cpt_write_fsm_dir_used = 0; 1042 m_cpt_write_fsm_trt_lock = 0; 1043 m_cpt_cas_fsm_n_dir_lock = 0; 1044 m_cpt_cas_fsm_dir_lock = 0; 1045 m_cpt_cas_fsm_upt_lock = 0; 1046 m_cpt_cas_fsm_heap_lock = 0; 1047 m_cpt_cas_fsm_trt_lock = 0; 1048 m_cpt_cas_fsm_dir_used = 0; 1049 m_cpt_xram_rsp_fsm_n_dir_lock = 0; 1050 m_cpt_xram_rsp_fsm_dir_lock = 0; 1051 m_cpt_xram_rsp_fsm_trt_lock = 0; 1052 m_cpt_xram_rsp_fsm_upt_lock = 0; 1053 m_cpt_xram_rsp_fsm_heap_lock = 0; 1054 m_cpt_xram_rsp_fsm_dir_used = 0; 1055 m_cpt_cleanup_fsm_dir_lock = 0; 1056 m_cpt_cleanup_fsm_n_dir_lock = 0; 1057 m_cpt_cleanup_fsm_heap_lock = 0; 1058 m_cpt_cleanup_fsm_ivt_lock = 0; 1059 m_cpt_cleanup_fsm_dir_used = 0; 1060 m_cpt_ixr_fsm_trt_lock = 0; 1061 m_cpt_multi_ack_fsm_upt_lock = 0; 1062 m_cpt_read_data_unc = 0; 1063 m_cpt_read_data_miss_CC = 0; 1064 m_cpt_read_ins_unc = 0; 1065 m_cpt_read_ins_miss = 0; 1066 m_cpt_read_ll_CC = 0; 1067 m_cpt_read_data_miss_NCC = 0; 1068 m_cpt_read_ll_NCC = 0; 1069 m_cpt_read_WTF = 0; 1070 m_cpt_cleanup_data = 0; 1071 m_cpt_ncc_to_cc_read = 0; 1072 m_cpt_ncc_to_cc_write = 0; 1073 m_cpt_ncc_to_cc = 0; 842 1074 return; 843 1075 } … … 946 1178 if(p_vci_tgt.cmdval) 947 1179 { 1180 948 1181 949 1182 #if DEBUG_MEMC_TGT_CMD … … 1106 1339 error = 0; 1107 1340 r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | 1108 (( addr_t)p_vci_tgt.wdata.read())<<32;1341 ((uint64_t)p_vci_tgt.wdata.read())<<32; 1109 1342 } 1110 1343 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines … … 1331 1564 case MULTI_ACK_UPT_LOCK: 1332 1565 { 1566 m_cpt_multi_ack_fsm_upt_lock++; 1333 1567 // get lock to the UPDATE table 1334 if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break;1568 if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break; 1335 1569 1336 1570 // decrement the number of expected responses 1337 1571 size_t count = 0; 1338 1572 bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count); 1573 1574 /*ODCCP*/ //m_upt.print(); 1339 1575 1340 1576 if(not valid) … … 1361 1597 << " entry = " << r_multi_ack_upt_index.read() 1362 1598 << " / rsp_count = " << std::dec << count << std::endl; 1599 m_cpt_multi_ack_fsm_n_upt_lock++; 1363 1600 #endif 1364 1601 break; … … 1875 2112 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 1876 2113 #endif 2114 r_read_coherent = false; //WB by default 2115 r_read_ll_done = false; 1877 2116 r_read_fsm = READ_DIR_REQ; 1878 2117 } … … 1886 2125 { 1887 2126 r_read_fsm = READ_DIR_LOCK; 2127 m_cpt_read_fsm_n_dir_lock++; 1888 2128 } 1889 2129 … … 1892 2132 std::cout << " <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl; 1893 2133 #endif 2134 2135 m_cpt_read_fsm_dir_lock++; 2136 1894 2137 break; 1895 2138 } … … 1903 2146 DirectoryEntry entry = 1904 2147 m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); 1905 // access the global table ONLY when we have an LL cmd 1906 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) 1907 { 1908 r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); 2148 if(((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and not r_read_ll_done.read()) // access the global table ONLY when we have an LL cmd 2149 { 2150 addr_t nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())]; 2151 r_read_ll_key = m_llsc_table.ll(nline); 2152 //r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); 2153 /**//*std::cout << "MEMCACHE : from proc " << m_cmd_read_srcid_fifo.read() 2154 << " | @ " << std::hex << m_cmd_read_addr_fifo.read() 2155 << " | LL" << std::endl;*/ 2156 r_read_ll_done = true; 1909 2157 } 1910 2158 r_read_is_cnt = entry.is_cnt; … … 1926 2174 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 1927 2175 bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); 2176 2177 1928 2178 if(entry.valid) // hit 1929 2179 { 1930 // test if we need to register a new copy in the heap1931 if (entry.is_cnt or (entry.count == 0) or !cached_read)2180 r_read_coherent = entry.cache_coherent; 2181 if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) //hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request) 1932 2182 { 1933 r_read_fsm = READ_DIR_HIT; 2183 // test if we need to register a new copy in the heap 2184 if(entry.is_cnt || (entry.count == 0) || !cached_read) 2185 { 2186 r_read_fsm = READ_DIR_HIT; 2187 } 2188 else 2189 { 2190 //std::cout << "is LL = " << ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) << std::endl; 2191 //std::cout << "coherent = " << entry.cache_coherent << " | count = " << std::dec << entry.count << " | cached = " << cached_read << std::endl; 2192 r_read_fsm = READ_HEAP_REQ; 2193 } 1934 2194 } 1935 else 2195 else //hit on a WB line owned by an other proc 1936 2196 { 1937 r_read_fsm = READ_ HEAP_REQ;2197 r_read_fsm = READ_IVT_LOCK; 1938 2198 } 1939 2199 } … … 1950 2210 << " / hit = " << std::dec << entry.valid 1951 2211 << " / count = " <<std::dec << entry.count 1952 << " / is_cnt = " << entry.is_cnt; 2212 << " / is_cnt = " << entry.is_cnt 2213 << " / is_coherent = " << entry.cache_coherent; 1953 2214 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl; 1954 2215 else std::cout << std::endl; … … 1965 2226 } 1966 2227 2228 /////////////////// 2229 case READ_IVT_LOCK: 2230 { 2231 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_READ) 2232 { 2233 size_t index; 2234 addr_t nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())]; 2235 /*std::cout << "nline = " << std::dec << nline << std::endl 2236 << "inval en cours sur la ligne = " << m_upt.search_inval(nline, index) << std::endl 2237 << "UPT full = " << m_upt.is_full() << std::endl 2238 << "CC_SEND req = " << r_read_to_cc_send_req.read() << std::endl 2239 << "CLENAUP req = " <<r_read_to_cleanup_req.read() << std::endl;*/ 2240 if(m_upt.search_inval(nline, index) or m_upt.is_full() or r_read_to_cc_send_req.read() or r_read_to_cleanup_req.read()) //Check pending inval 2241 { 2242 r_read_fsm = READ_WAIT; 2243 #if DEBUG_MEMC_READ 2244 if(m_debug) 2245 { 2246 std::cout 2247 << " <MEMC " << name() << " READ_IVT_LOCK>" 2248 << " Wait cleanup completion" 2249 << std::endl; 2250 } 2251 #endif 2252 } 2253 else 2254 { 2255 r_read_to_cc_send_req = true; 2256 r_read_to_cc_send_dest = r_read_copy.read(); 2257 r_read_to_cc_send_nline = nline; 2258 r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 2259 r_read_to_cleanup_req = true; 2260 r_read_to_cleanup_nline = nline; 2261 r_read_to_cleanup_srcid = m_cmd_read_srcid_fifo.read(); 2262 r_read_to_cleanup_length = m_cmd_read_length_fifo.read(); 2263 r_read_to_cleanup_first_word = m_x[(addr_t) m_cmd_read_addr_fifo.read()]; 2264 r_read_to_cleanup_cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); 2265 r_read_to_cleanup_addr = m_cmd_read_addr_fifo.read(); 2266 r_read_to_cleanup_is_ll= ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL); 2267 r_read_to_cleanup_ll_key = r_read_ll_key.read(); 2268 //std::cout << "cleanup req (read) on line " << nline << " /on proc " << r_read_copy.read() << std::endl; 2269 2270 m_upt.set(false, // it's an inval transaction 2271 false, // it's not a broadcast 2272 false, // it needs a read response 2273 false, // no acknowledge required 2274 m_cmd_read_srcid_fifo.read(), 2275 m_cmd_read_trdid_fifo.read(), 2276 m_cmd_read_pktid_fifo.read(), 2277 nline, 2278 0x1, //Expect only one answer 2279 index); 2280 2281 cmd_read_fifo_get = true; 2282 r_read_fsm = READ_IDLE; 2283 #if DEBUG_MEMC_READ 2284 if(m_debug) 2285 { 2286 std::cout 2287 << " <MEMC " << name() << " READ_IVT_LOCK>" 2288 << " Inval req on an NCC line" 2289 << std::endl; 2290 } 2291 #endif 2292 } 2293 } 2294 2295 2296 break; 2297 } 2298 1967 2299 ////////////////// 2300 case READ_WAIT://Release the locks 2301 { 2302 r_read_fsm = READ_DIR_REQ; 2303 #if DEBUG_MEMC_READ 2304 if(m_debug) 2305 { 2306 std::cout 2307 << " <MEMC " << name() << " READ_WAIT>" << std::endl; 2308 } 2309 #endif 2310 break; 2311 } 2312 /////////////////// 1968 2313 case READ_DIR_HIT: // read data in cache & update the directory 1969 2314 // we enter this state in 3 cases: … … 1996 2341 DirectoryEntry entry; 1997 2342 entry.valid = true; 2343 entry.cache_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read()); 2344 r_read_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read()); 1998 2345 entry.is_cnt = is_cnt; 1999 2346 entry.dirty = r_read_dirty.read(); … … 2001 2348 entry.lock = r_read_lock.read(); 2002 2349 entry.ptr = r_read_ptr.read(); 2003 2004 2350 if(cached_read) // Cached read => we must update the copies 2005 2351 { … … 2034 2380 2035 2381 #if DEBUG_MEMC_READ 2036 if(m_debug) 2037 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 2038 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() 2039 << " / set = " << std::dec << set 2040 << " / way = " << way 2041 << " / owner_id = " << std::hex << entry.owner.srcid 2042 << " / owner_ins = " << std::dec << entry.owner.inst 2043 << " / count = " << entry.count 2044 << " / is_cnt = " << entry.is_cnt << std::endl; 2382 if(m_debug) 2383 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 2384 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() 2385 << " / set = " << std::dec << set 2386 << " / way = " << way 2387 << " / owner_id = " << std::hex << entry.owner.srcid 2388 << " / owner_ins = " << std::dec << entry.owner.inst 2389 << " / coherent = " << entry.cache_coherent 2390 << " / count = " << entry.count 2391 << " / is_cnt = " << entry.is_cnt << std::endl; 2045 2392 #endif 2046 2393 … … 2056 2403 { 2057 2404 r_read_fsm = READ_HEAP_LOCK; 2405 m_cpt_read_fsm_n_heap_lock++; 2058 2406 } 2059 2407 … … 2063 2411 << " Requesting HEAP lock " << std::endl; 2064 2412 #endif 2413 2414 m_cpt_read_fsm_heap_lock++; 2415 2065 2416 break; 2066 2417 } … … 2075 2426 bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); 2076 2427 2428 if (!r_read_coherent.read()) 2429 { 2430 std::cout << "Address = " << std::hex << (m_cmd_read_addr_fifo.read()) << std::dec << " |count = " << r_read_count.read() << std::endl; 2431 } 2432 assert (r_read_coherent.read() && "accÚs au heap sur ncc"); 2077 2433 // read data in the cache 2078 2434 size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; … … 2086 2442 DirectoryEntry entry; 2087 2443 entry.valid = true; 2444 entry.cache_coherent = r_read_coherent.read(); 2088 2445 entry.is_cnt = go_cnt; 2089 2446 entry.dirty = r_read_dirty.read(); … … 2272 2629 r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read(); 2273 2630 r_read_to_tgt_rsp_srcid = m_cmd_read_srcid_fifo.read(); 2631 /*RWT*/ 2632 //BUG pktid 2633 if (r_read_coherent.read()) 2634 { 2635 r_read_to_tgt_rsp_pktid = 0x0 + m_cmd_read_pktid_fifo.read(); 2636 //std::cout << "READ RSP COHERENT on word" << std::hex << m_x[(addr_t) m_cmd_read_addr_fifo.read()] << std::dec << std::endl; 2637 } 2638 else 2639 { 2640 r_read_to_tgt_rsp_pktid = 0x8 + m_cmd_read_pktid_fifo.read(); 2641 } 2274 2642 r_read_to_tgt_rsp_trdid = m_cmd_read_trdid_fifo.read(); 2275 r_read_to_tgt_rsp_pktid = m_cmd_read_pktid_fifo.read();2276 2643 r_read_to_tgt_rsp_ll_key = r_read_ll_key.read(); 2277 2644 cmd_read_fifo_get = true; … … 2302 2669 if(hit_read or !wok or hit_write) // missing line already requested or no space 2303 2670 { 2304 if(!wok) m_cpt_trt_full++; 2671 if(!wok) 2672 { 2673 m_cpt_trt_full++; 2674 } 2305 2675 if(hit_read or hit_write) m_cpt_trt_rb++; 2306 2676 r_read_fsm = READ_IDLE; … … 2319 2689 << " / hit_write = " << hit_write 2320 2690 << " / full = " << !wok << std::endl; 2321 #endif 2322 } 2691 m_cpt_read_fsm_n_trt_lock++; 2692 #endif 2693 } 2694 2695 m_cpt_read_fsm_trt_lock++; 2696 2323 2697 break; 2324 2698 } … … 2341 2715 std::vector<data_t> (m_words,0), 2342 2716 r_read_ll_key.read()); 2717 2343 2718 #if DEBUG_MEMC_READ 2344 2719 if(m_debug) … … 2507 2882 { 2508 2883 /////////////////////////////////////////////////////////////////////// 2509 // SC command treatment2884 // SC command handling 2510 2885 // We test the r_write_pending_sc register to know if we are returning 2511 2886 // from the WAIT state. … … 2513 2888 // another time from the FIFO. Also, we don't have to test another 2514 2889 // time if the SC has succeed 2890 2891 addr_t nline = m_nline[(addr_t)(r_write_address.read())]; 2515 2892 if(((r_write_pktid.read() & 0x7) == TYPE_SC) and not r_write_pending_sc.read()) 2516 2893 { 2517 2894 if(not m_cmd_write_addr_fifo.rok()) break; 2518 2895 2519 2896 assert(m_cmd_write_eop_fifo.read() and 2520 2897 "Error in VCI_MEM_CACHE : " 2521 2898 "invalid packet format for SC command"); 2522 2899 //BUG LLSC 2523 2900 size_t index = r_write_word_index.read(); 2524 bool sc_success = m_llsc_table.sc( r_write_address.read(),2901 bool sc_success = m_llsc_table.sc(nline , 2525 2902 r_write_data[index].read()); 2526 2903 2904 //bool sc_success = m_llsc_table.sc(r_write_address.read() , 2905 // r_write_data[index].read()); 2527 2906 // consume a word in the FIFO & write it in the local buffer 2528 2907 cmd_write_fifo_get = true; 2529 2908 r_write_data[index] = m_cmd_write_data_fifo.read(); 2530 2909 r_write_sc_fail = not sc_success; 2910 //WARNING: if the SC is a success, it might still fail at next cycle if the line is NCC 2531 2911 r_write_pending_sc = true; 2532 2912 2533 2913 if(not sc_success) r_write_fsm = WRITE_RSP; 2534 2914 else r_write_fsm = WRITE_DIR_LOCK; 2535 2915 2536 2916 break; 2537 2917 } 2538 2918 2539 2919 /////////////////////////////////////////////////////////////////////// 2540 2920 // WRITE command treatment or SC command returning from the WAIT state … … 2542 2922 // erase any possible new reservation when we release the lock on the 2543 2923 // directory 2544 m_llsc_table.sw(r_write_address.read()); 2924 m_llsc_table.sw(nline); 2925 2926 //m_llsc_table.sw(r_write_address.read()); 2545 2927 2546 2928 r_write_fsm = WRITE_DIR_LOCK; 2929 m_cpt_write_fsm_n_dir_lock++; 2547 2930 } 2548 2931 … … 2552 2935 << std::endl; 2553 2936 #endif 2937 2938 m_cpt_write_fsm_dir_lock++; 2554 2939 2555 2940 break; … … 2578 2963 r_write_ptr = entry.ptr; 2579 2964 r_write_way = way; 2580 2581 if(entry.is_cnt and entry.count) 2965 2966 r_write_coherent = entry.cache_coherent; 2967 2968 if (entry.cache_coherent or (entry.owner.srcid == r_write_srcid.read()) or (entry.count == 0)) // hit WT 2582 2969 { 2583 r_write_fsm = WRITE_DIR_READ; 2970 if(entry.is_cnt && entry.count) 2971 { 2972 r_write_fsm = WRITE_DIR_READ; 2973 } 2974 else 2975 { 2976 r_write_fsm = WRITE_DIR_HIT; 2977 } 2584 2978 } 2585 2979 else 2586 2980 { 2587 r_write_fsm = WRITE_DIR_HIT; 2981 if (r_write_to_cleanup_req.read())//inval already sent 2982 { 2983 r_write_fsm = WRITE_WAIT; 2984 } 2985 else // hit on a NCC line with a different owner 2986 { 2987 r_write_fsm = WRITE_IVT_LOCK_HIT_WB; 2988 if(r_write_pktid.read() == TYPE_SC) 2989 { 2990 r_write_sc_fail = true; 2991 } 2992 } 2588 2993 } 2589 2994 } 2590 2995 else // miss 2591 2996 { 2592 r_write_fsm = WRITE_MISS_ TRT_LOCK;2997 r_write_fsm = WRITE_MISS_IVT_LOCK; 2593 2998 } 2594 2999 … … 2619 3024 } 2620 3025 //////////////////// 3026 case WRITE_IVT_LOCK_HIT_WB: 3027 { 3028 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) 3029 { 3030 3031 size_t index = 0; 3032 bool match_inval; 3033 addr_t nline = m_nline[(addr_t)(r_write_address.read())]; 3034 3035 //std::cout << "WRITE on NCC on line" << std::hex << nline << std::dec << std::endl; 3036 3037 match_inval = m_upt.search_inval(nline, index); 3038 assert ((r_write_count.read() == 1) and "NCC to CC req without copy"); 3039 if(!match_inval and !r_write_to_cc_send_req.read()) 3040 { 3041 r_write_to_cc_send_req = true; 3042 r_write_to_cc_send_dest = r_write_copy; 3043 r_write_to_cc_send_nline = nline; 3044 r_write_to_cleanup_req = true; 3045 r_write_to_cleanup_nline = nline; 3046 3047 m_upt.set(false, // it's an inval transaction 3048 false, // it's not a broadcast 3049 true, // it needs no read response 3050 false, // no acknowledge required 3051 m_cmd_write_srcid_fifo.read(), //never read, used for debug 3052 m_cmd_write_trdid_fifo.read(), //never read, used for debug 3053 m_cmd_write_pktid_fifo.read(), //never read, used for debug 3054 nline, 3055 0x1, //Expect only one answer 3056 index); 3057 } 3058 r_write_fsm = WRITE_WAIT; 3059 #if DEBUG_MEMC_WRITE 3060 if(m_debug) 3061 { 3062 std::cout << " <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> get access to the UPT: " 3063 << " Inval requested = " << (!match_inval and !r_write_to_cc_send_req.read()) 3064 << std::endl; 3065 } 3066 #endif 3067 } 3068 #if DEBUG_MEMC_WRITE 3069 if(m_debug) 3070 { 3071 std::cout << " <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> failed to access to the UPT: " 3072 << std::endl; 3073 } 3074 #endif 3075 break; 3076 } 3077 3078 3079 //////////////////// 2621 3080 case WRITE_DIR_READ: // read the cache and complete the buffer when be!=0xF 2622 3081 { … … 2656 3115 DirectoryEntry entry; 2657 3116 entry.valid = true; 3117 entry.cache_coherent = r_write_coherent.read(); 2658 3118 entry.dirty = true; 2659 3119 entry.tag = r_write_tag.read(); … … 2683 3143 // no_update is true when there is no need for coherence transaction 2684 3144 // (tests for sc requests) 2685 bool no_update = ( (r_write_count.read() == 0) or2686 (owner and (r_write_count.read() ==1) and2687 (r_write_pktid.read() != TYPE_SC)));3145 bool no_update = ((r_write_count.read() ==0) || //no need for coherency 3146 (owner && (r_write_count.read() ==1) && (r_write_pktid.read() != TYPE_SC)) || //writer is owner 3147 ((r_write_pktid.read() == TYPE_SC) && r_write_sc_fail.read())); //SC failed: no data update 2688 3148 2689 3149 // write data in the cache if no coherence transaction 2690 if(no_update )3150 if(no_update and ((r_write_pktid.read() != TYPE_SC) or !r_write_sc_fail.read())) 2691 3151 { 2692 3152 for(size_t word=0 ; word<m_words ; word++) … … 2760 3220 size_t set = m_y[(addr_t)(r_write_address.read())]; 2761 3221 size_t way = r_write_way.read(); 3222 2762 3223 2763 3224 wok = m_upt.set(true, // it's an update transaction … … 2804 3265 if(wok) r_write_fsm = WRITE_UPT_HEAP_LOCK; 2805 3266 else r_write_fsm = WRITE_WAIT; 2806 } 3267 m_cpt_write_fsm_n_upt_lock++; 3268 } 3269 3270 m_cpt_write_fsm_upt_lock++; 3271 2807 3272 break; 2808 3273 } … … 2820 3285 #endif 2821 3286 r_write_fsm = WRITE_UPT_REQ; 2822 } 3287 m_cpt_write_fsm_n_heap_lock++; 3288 } 3289 3290 m_cpt_write_fsm_heap_lock++; 3291 2823 3292 break; 2824 3293 } … … 2834 3303 "transaction in WRITE_UPT_REQ state" 2835 3304 ); 3305 2836 3306 2837 3307 r_write_to_cc_send_brdcast_req = false; … … 3070 3540 break; 3071 3541 } 3542 ///////////////////////// RWT 3543 case WRITE_MISS_IVT_LOCK: // Miss : check UPT 3544 { 3545 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) 3546 { 3547 size_t index; 3548 if(m_upt.search_inval(m_nline[(addr_t)(r_write_address.read())], index)) 3549 { 3550 r_write_fsm = WRITE_WAIT; 3551 } 3552 else 3553 { 3554 r_write_fsm = WRITE_MISS_TRT_LOCK; 3555 } 3556 } 3557 break; 3558 } 3072 3559 3073 3560 ///////////////////////// … … 3087 3574 bool hit_write = m_trt.hit_write(m_nline[addr]); 3088 3575 bool wok = !m_trt.full(wok_index); 3089 3576 //std::cout << "MEMCACHE : WRITE MISS at " << std::hex << (uint32_t)addr << std::dec << std::endl; 3090 3577 if(hit_read) // register the modified data in TRT 3091 3578 { … … 3105 3592 m_cpt_trt_full++; 3106 3593 } 3107 } 3594 m_cpt_write_fsm_n_trt_lock++; 3595 } 3596 3597 m_cpt_write_fsm_trt_lock++; 3598 3108 3599 break; 3109 3600 } … … 3224 3715 << " : wok = " << wok << " / index = " << wok_index << std::endl; 3225 3716 #endif 3226 } 3717 m_cpt_write_fsm_n_trt_lock++; 3718 } 3719 3720 m_cpt_write_fsm_trt_lock++; 3721 3227 3722 break; 3228 3723 } … … 3251 3746 nb_copies, 3252 3747 index); 3253 3748 /*ODCCP*/ //m_upt.print(); 3254 3749 #if DEBUG_MEMC_WRITE 3255 3750 if( m_debug and wok ) … … 3261 3756 if(wok) r_write_fsm = WRITE_BC_DIR_INVAL; 3262 3757 else r_write_fsm = WRITE_WAIT; 3263 } 3758 m_cpt_write_fsm_n_upt_lock++; 3759 } 3760 3761 m_cpt_write_fsm_upt_lock++; 3762 3264 3763 break; 3265 3764 } … … 3295 3794 DirectoryEntry entry; 3296 3795 entry.valid = false; 3796 entry.cache_coherent= false; 3297 3797 entry.dirty = false; 3298 3798 entry.tag = 0; … … 3394 3894 //////////////////////// 3395 3895 case IXR_CMD_READ_IDLE: 3396 {3397 3896 if (r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3398 3897 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3399 3898 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3899 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3400 3900 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3401 3901 break; 3402 }3403 3902 //////////////////////// 3404 3903 case IXR_CMD_WRITE_IDLE: 3405 { 3406 if (r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3904 if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3407 3905 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3906 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3408 3907 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3409 3908 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3410 3909 break; 3411 }3412 3910 //////////////////////// 3413 3911 case IXR_CMD_CAS_IDLE: 3414 {3415 if (r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;3912 if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3913 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3416 3914 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3417 3915 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3418 3916 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3419 3917 break; 3420 }3421 3918 //////////////////////// 3422 3919 case IXR_CMD_XRAM_IDLE: 3423 {3424 if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ;3425 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE;3920 if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3921 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3922 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3426 3923 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3427 3924 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3428 3925 break; 3429 } 3926 //////////////////////// 3927 case IXR_CMD_CLEANUP_IDLE: 3928 /*ODCCP*///std::cout << "IXR_CMD_CLEANUP_IDLE" << std::endl; 3929 if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3930 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3931 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3932 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3933 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3934 break; 3430 3935 ////////////////// // send a get from READ FSM 3431 3936 case IXR_CMD_READ: … … 3553 4058 break; 3554 4059 } 4060 4061 //////////////////////// 4062 case IXR_CMD_CLEANUP_DATA: // send a put command to XRAM 4063 /*ODCCP*///std::cout << "IXR_CMD_CLEANUP_DATA" << std::endl; 4064 if(p_vci_ixr.cmdack) 4065 { 4066 if(r_ixr_cmd_cpt.read() == (m_words - 2)) 4067 { 4068 r_ixr_cmd_cpt = 0; 4069 r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE; 4070 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; 4071 r_cleanup_to_ixr_cmd_req = false; 4072 } 4073 else 4074 { 4075 r_ixr_cmd_cpt = r_ixr_cmd_cpt.read() + 2; 4076 } 4077 4078 #if DEBUG_MEMC_IXR_CMD 4079 if(m_debug) 4080 { 4081 std::cout << " <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA> Send a put request to xram" << std::endl; 4082 } 4083 #endif 4084 } 4085 break; 3555 4086 3556 4087 } // end switch r_ixr_cmd_fsm … … 3631 4162 << r_ixr_rsp_trt_index.read() << std::endl; 3632 4163 #endif 3633 } 4164 m_cpt_ixr_fsm_n_trt_lock++; 4165 } 4166 4167 m_cpt_ixr_fsm_trt_lock++; 4168 3634 4169 break; 3635 4170 } … … 3667 4202 << " / data = " << std::hex << data << std::endl; 3668 4203 #endif 3669 } 4204 m_cpt_ixr_fsm_n_trt_lock++; 4205 } 4206 m_cpt_ixr_fsm_trt_lock++; 3670 4207 break; 3671 4208 } … … 3740 4277 << " Get access to DIR and TRT" << std::endl; 3741 4278 #endif 3742 } 4279 m_cpt_xram_rsp_fsm_n_dir_lock++; 4280 m_cpt_xram_rsp_fsm_n_trt_lock++; 4281 } 4282 m_cpt_xram_rsp_fsm_dir_lock++; 4283 m_cpt_xram_rsp_fsm_trt_lock++; 3743 4284 break; 3744 4285 } … … 3756 4297 DirectoryEntry victim(m_cache_directory.select(set, way)); 3757 4298 3758 bool inval = (victim.count and victim.valid) ; 4299 bool inval = (victim.count && victim.valid) or (!victim.cache_coherent and (victim.count == 1)) ; 4300 3759 4301 3760 4302 // copy the victim line in a local buffer … … 3766 4308 r_xram_rsp_victim_copy_cache= victim.owner.cache_id; 3767 4309 #endif 4310 r_xram_rsp_victim_coherent = victim.cache_coherent; 3768 4311 r_xram_rsp_victim_copy_inst = victim.owner.inst; 3769 4312 r_xram_rsp_victim_count = victim.count; … … 3774 4317 r_xram_rsp_victim_is_cnt = victim.is_cnt; 3775 4318 r_xram_rsp_victim_inval = inval ; 3776 r_xram_rsp_victim_dirty = victim.dirty; 4319 r_xram_rsp_victim_dirty = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); //a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry 4320 3777 4321 3778 4322 if(!r_xram_rsp_trt_buf.rerror) 3779 4323 { 3780 r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; 4324 if (!victim.cache_coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) //there can not be two L2 invalidation on NCC line at the same time 4325 { 4326 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 4327 } 4328 else 4329 { 4330 r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; 4331 } 3781 4332 } 3782 4333 else … … 3808 4359 { 3809 4360 size_t index = 0; 3810 if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval 4361 size_t index_victim = 0; 4362 if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index) or 4363 m_ivt.search_inval(r_xram_rsp_victim_nline.read(), index_victim)) 3811 4364 { 3812 4365 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 3824 4377 { 3825 4378 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 4379 m_upt.print(); 3826 4380 3827 4381 #if DEBUG_MEMC_XRAM_RSP … … 3841 4395 #endif 3842 4396 } 3843 } 4397 m_cpt_xram_rsp_fsm_n_upt_lock++; 4398 } 4399 4400 m_cpt_xram_rsp_fsm_upt_lock++; 4401 3844 4402 break; 3845 4403 } … … 3891 4449 DirectoryEntry entry; 3892 4450 entry.valid = true; 4451 entry.cache_coherent = (inst_read or (not(cached_read))) and (r_xram_rsp_trt_buf.proc_read); 3893 4452 entry.is_cnt = false; 3894 4453 entry.lock = false; … … 3907 4466 else 3908 4467 { 3909 entry.owner.srcid = 0;4468 entry.owner.srcid = r_xram_rsp_trt_buf.srcid; 3910 4469 #if L1_MULTI_CACHE 3911 4470 entry.owner.cache_id = 0; … … 3915 4474 } 3916 4475 m_cache_directory.write(set, way, entry); 3917 4476 //RWT: keep the coherence information in order to send it to the read_rsp 4477 r_xram_rsp_coherent = inst_read or (not(cached_read)); 3918 4478 // request an invalidattion request in IVT for victim line 3919 4479 if(r_xram_rsp_victim_inval.read()) … … 3922 4482 size_t index = 0; 3923 4483 size_t count_copies = r_xram_rsp_victim_count.read(); 3924 4484 3925 4485 bool wok = m_ivt.set(false, // it's an inval transaction 3926 4486 broadcast, // set broadcast bit … … 3935 4495 3936 4496 r_xram_rsp_ivt_index = index; 3937 3938 4497 if(!wok) 3939 4498 { … … 3943 4502 } 3944 4503 } 3945 4504 if (!r_xram_rsp_victim_coherent.read()) 4505 { 4506 //m_llsc_table.sw(r_xram_rsp_victim_nline.read()*m_words*4); 4507 m_llsc_table.sw(r_xram_rsp_victim_nline.read()); 4508 } 3946 4509 #if DEBUG_MEMC_XRAM_RSP 3947 4510 if(m_debug) … … 3962 4525 #endif 3963 4526 3964 // If the victim is not dirty , we don't need another XRAMput transaction,4527 // If the victim is not dirty (RWT: if it is not coherent, we can not know wether it is dirty or not), we don't need another XRAM put transaction, 3965 4528 // and we can erase the TRT entry 3966 if(!r_xram_rsp_victim_dirty.read() ) m_trt.erase(r_xram_rsp_trt_index.read());4529 if(!r_xram_rsp_victim_dirty.read() and (r_xram_rsp_victim_coherent.read() or (r_xram_rsp_victim_count.read() == 0))) m_trt.erase(r_xram_rsp_trt_index.read()); 3967 4530 3968 4531 // Next state 3969 if(r_xram_rsp_victim_dirty.read() ) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;4532 if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; 3970 4533 else if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 3971 4534 else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; … … 3974 4537 } 3975 4538 //////////////////////// 3976 case XRAM_RSP_TRT_DIRTY: // set the TRT entry ( PUT to XRAM) if the victim is dirty4539 case XRAM_RSP_TRT_DIRTY: // set the TRT entry (write to XRAM) if the victim is dirty or not coherent (RWT) 3977 4540 { 3978 4541 if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) 3979 4542 { 4543 3980 4544 m_trt.set(r_xram_rsp_trt_index.read(), 3981 4545 false, // write to XRAM … … 3999 4563 else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 4000 4564 else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 4001 } 4565 m_cpt_xram_rsp_fsm_n_trt_lock++; 4566 } 4567 4568 m_cpt_xram_rsp_fsm_trt_lock++; 4569 4002 4570 break; 4003 4571 } … … 4009 4577 r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; 4010 4578 r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; 4011 r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; 4579 if (r_xram_rsp_coherent.read()) 4580 { 4581 r_xram_rsp_to_tgt_rsp_pktid = 0x0 + r_xram_rsp_trt_buf.pktid;//RWT CC 4582 } 4583 else 4584 { 4585 r_xram_rsp_to_tgt_rsp_pktid = 0x8 + r_xram_rsp_trt_buf.pktid;//RWT NCC 4586 } 4012 4587 for(size_t i=0; i < m_words; i++) 4013 4588 { … … 4019 4594 r_xram_rsp_to_tgt_rsp_rerror = false; 4020 4595 r_xram_rsp_to_tgt_rsp_req = true; 4596 4021 4597 4022 4598 if(r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL; … … 4073 4649 case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM 4074 4650 { 4075 if(!r_xram_rsp_to_ixr_cmd_req.read() )4651 if(!r_xram_rsp_to_ixr_cmd_req.read() and !r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) 4076 4652 { 4077 4653 r_xram_rsp_to_ixr_cmd_req = true; … … 4081 4657 { 4082 4658 r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i]; 4659 std::cout << "data L2 = " << std::hex << r_xram_rsp_victim_data[i] << std::dec << std::endl; 4083 4660 } 4084 4661 m_cpt_write_dirty++; 4662 4663 if ((!r_xram_rsp_victim_coherent.read()) and (r_xram_rsp_victim_count.read() == 1)) //if NCC, we save the data in case of not dirty L1 4664 { 4665 r_xram_rsp_to_ixr_cmd_req = false; 4666 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true; 4667 r_xram_rsp_fsm = XRAM_RSP_IDLE; 4668 break; 4669 } 4085 4670 4086 4671 bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read(); … … 4105 4690 { 4106 4691 r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; 4692 m_cpt_xram_rsp_fsm_n_heap_lock++; 4107 4693 } 4108 4694 … … 4112 4698 << " Requesting HEAP lock" << std::endl; 4113 4699 #endif 4700 4701 m_cpt_xram_rsp_fsm_heap_lock++; 4702 4114 4703 break; 4115 4704 } … … 4278 4867 r_cleanup_inst = (type == DspinDhccpParam::TYPE_CLEANUP_INST); 4279 4868 r_cleanup_srcid = srcid; 4869 r_cleanup_ncc = 4870 DspinDhccpParam::dspin_get( 4871 flit, 4872 DspinDhccpParam::CLEANUP_NCC); 4873 r_cleanup_contains_data = false; 4280 4874 4281 4875 if(srcid >= m_initiators) … … 4294 4888 4295 4889 #if DEBUG_MEMC_CLEANUP 4296 if(m_debug) 4297 std::cout << " <MEMC " << name() 4298 << " CLEANUP_IDLE> Cleanup request:" << std::hex 4299 << " / owner_id = " << srcid 4300 << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; 4890 if(m_debug) 4891 { 4892 std::cout 4893 << " <MEMC " << name() 4894 << " CLEANUP_IDLE> Cleanup request:" << std::hex 4895 << " / owner_id = " << srcid 4896 << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) 4897 << " / ncc = " << DspinDhccpParam::dspin_get( 4898 flit, 4899 DspinDhccpParam::CLEANUP_NCC) 4900 << std::endl; 4901 } 4301 4902 #endif 4302 4903 break; … … 4312 4913 addr_t nline = r_cleanup_nline.read() | 4313 4914 DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); 4314 4915 4916 //A MODIFIER POUR DIRTY // 4917 bool eop = 4918 DspinDhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP) == 0x1; 4919 if (! eop) 4920 { 4921 r_cleanup_fsm = CLEANUP_GET_DATA; 4922 r_cleanup_data_index = 0; 4923 r_cleanup_contains_data = true; 4924 } 4925 else 4926 { 4927 r_cleanup_fsm = CLEANUP_DIR_REQ; 4928 } 4315 4929 cc_receive_to_cleanup_fifo_get = true; 4316 r_cleanup_nline = nline; 4317 r_cleanup_fsm = CLEANUP_DIR_REQ; 4930 r_cleanup_nline = nline; 4318 4931 4319 4932 #if DEBUG_MEMC_CLEANUP 4320 if(m_debug) 4321 std::cout << " <MEMC " << name() 4322 << " CLEANUP_GET_NLINE> Cleanup request:" 4323 << " / address = " << std::hex << nline * m_words * 4 << std::endl; 4324 #endif 4325 break; 4326 } 4327 4933 if(m_debug) 4934 { 4935 std::cout 4936 << " <MEMC " << name() 4937 << " CLEANUP_GET_NLINE> Cleanup request:" 4938 << std::hex 4939 << " / address = " << nline * m_words * 4 4940 << " / contains data = " << (!eop) 4941 << std::endl; 4942 } 4943 #endif 4944 break; 4945 } 4946 ///////////////////// 4947 case CLEANUP_GET_DATA : 4948 { 4949 if (m_cc_receive_to_cleanup_fifo.rok()) 4950 { 4951 uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); 4952 4953 uint32_t data = 4954 DspinDhccpParam::dspin_get (flit, DspinDhccpParam::CLEANUP_DATA_UPDT); 4955 4956 r_cleanup_data[r_cleanup_data_index] = data; 4957 r_cleanup_data_index = r_cleanup_data_index.read() + 1; 4958 assert (r_cleanup_data_index.read() < m_words and "MEM_CACHE in CLEANUP_GET_DATA : too much flits in cleanup data updt"); 4959 cc_receive_to_cleanup_fifo_get = true; 4960 if (r_cleanup_data_index.read() == m_words - 1) 4961 { 4962 r_cleanup_contains_data = true; 4963 m_cpt_cleanup_data ++; 4964 r_cleanup_fsm = CLEANUP_DIR_REQ; 4965 } 4966 #if DEBUG_MEMC_CLEANUP 4967 if(m_debug) 4968 { 4969 std::cout 4970 << " <MEMC " << name() 4971 << " CLEANUP_GET_DATA> " 4972 << " / word = " << std::dec << r_cleanup_data_index.read() 4973 << " / data = " << std::hex << data 4974 << std::endl; 4975 } 4976 #endif 4977 } 4978 break; 4979 } 4328 4980 ///////////////////// 4329 4981 case CLEANUP_DIR_REQ: // Get the lock to the directory 4330 4982 { 4983 m_cpt_cleanup_fsm_dir_lock++; 4331 4984 if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; 4332 4985 4333 4986 r_cleanup_fsm = CLEANUP_DIR_LOCK; 4987 //std::cout << " MEM_CACHE : CLEANUP_DIR_REQ" << std::endl; 4334 4988 4335 4989 #if DEBUG_MEMC_CLEANUP … … 4337 4991 std::cout << " <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl; 4338 4992 #endif 4993 4994 m_cpt_cleanup_fsm_n_dir_lock++; 4995 4339 4996 break; 4340 4997 } … … 4353 5010 exit(0); 4354 5011 } 5012 //std::cout << " MEM_CACHE : CLEANUP_DIR_LOCK" << std::endl; 4355 5013 4356 5014 // Read the directory … … 4371 5029 r_cleanup_copy_cache = entry.owner.cache_id; 4372 5030 #endif 5031 5032 //RWT 5033 size_t set = m_y[(addr_t)(cleanup_address)]; 5034 m_cache_data.read_line(way, set, r_cleanup_old_data); 5035 r_cleanup_coherent = entry.cache_coherent; 5036 5037 4373 5038 4374 5039 if(entry.valid) // hit : the copy must be cleared … … 4420 5085 case CLEANUP_DIR_WRITE: 4421 5086 { 5087 /*ODCCP*///std::cout << "CLEANUP_DIR_WRITE" << std::endl; 4422 5088 // Update the directory entry without heap access 4423 5089 if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) … … 4453 5119 } 4454 5120 5121 /*RWT*/ 5122 bool inval_request = (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) // NCC to CC initiated by a read transaction 5123 or (r_write_to_cleanup_req.read() and (r_cleanup_nline.read() == r_write_to_cleanup_nline.read())); //NCC to CC initiated by a wrtie transaction 5124 5125 5126 if (inval_request) m_cpt_ncc_to_cc ++; 5127 5128 if (r_write_to_cleanup_req.read() and (r_cleanup_nline.read() == r_write_to_cleanup_nline.read())) 5129 { 5130 r_write_to_cleanup_req = false; 5131 m_cpt_ncc_to_cc_write ++; 5132 } 5133 5134 4455 5135 // update the cache directory (for the copies) 4456 5136 DirectoryEntry entry; 4457 entry.valid = true; 4458 entry.is_cnt = r_cleanup_is_cnt.read(); 4459 entry.dirty = r_cleanup_dirty.read(); 4460 entry.tag = r_cleanup_tag.read(); 4461 entry.lock = r_cleanup_lock.read(); 4462 entry.ptr = r_cleanup_ptr.read(); 4463 entry.count = r_cleanup_count.read() - 1; 4464 entry.owner.srcid = 0; 4465 entry.owner.inst = 0; 4466 5137 entry.valid = true; 5138 entry.cache_coherent = inval_request or r_cleanup_coherent.read(); 5139 entry.is_cnt = r_cleanup_is_cnt.read(); 5140 entry.dirty = r_cleanup_dirty.read() or r_cleanup_contains_data.read(); 5141 entry.tag = r_cleanup_tag.read(); 5142 entry.lock = r_cleanup_lock.read(); 5143 entry.ptr = r_cleanup_ptr.read(); 5144 if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ 5145 { 5146 if (r_read_to_cleanup_cached_read.read()) 5147 { 5148 entry.count = r_cleanup_count.read(); 5149 entry.owner.srcid = r_read_to_cleanup_srcid.read(); 5150 entry.owner.inst = 0; 4467 5151 #if L1_MULTI_CACHE 4468 entry.owner.cache_id = 0; 4469 #endif 5152 entry.owner.cache_id = r_cleanup_copy_cache.read(); 5153 #endif 5154 } 5155 else 5156 { 5157 entry.count = r_cleanup_count.read() - 1; 5158 entry.owner.srcid = r_cleanup_copy.read(); 5159 entry.owner.inst = r_cleanup_copy_inst.read(); 5160 #if L1_MULTI_CACHE 5161 entry.owner.cache_id = r_cleanup_copy_cache.read(); 5162 #endif 5163 } 5164 if (r_read_to_cleanup_is_ll.read()) 5165 { 5166 r_cleanup_to_tgt_rsp_ll_key = r_read_to_cleanup_ll_key.read(); 5167 } 5168 } 5169 else 5170 { 5171 entry.count = r_cleanup_count.read() - 1; 5172 entry.owner.srcid = 0; 5173 entry.owner.inst = 0; 5174 #if L1_MULTI_CACHE 5175 entry.owner.cache_id = 0; 5176 #endif 5177 } 5178 5179 5180 if (r_cleanup_contains_data.read()) 5181 { 5182 for (size_t word = 0; word < m_words; word ++) 5183 { 5184 m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF); 5185 } 5186 m_llsc_table.sw(r_cleanup_nline.read()); 5187 //m_llsc_table.sw(r_cleanup_nline.read()*m_words*4); 5188 } 5189 4470 5190 4471 5191 m_cache_directory.write(set, way, entry); 4472 5192 4473 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5193 5194 /*RWT*/ 5195 if (inval_request) 5196 { 5197 r_cleanup_fsm = CLEANUP_IVT_LOCK_DATA; 5198 } 5199 else 5200 { 5201 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5202 } 4474 5203 4475 5204 #if DEBUG_MEMC_CLEANUP … … 4485 5214 << " / count = " << entry.count 4486 5215 << " / is_cnt = " << entry.is_cnt 5216 << " / match_inval = " << inval_request 4487 5217 << std::endl; 4488 5218 } … … 4491 5221 break; 4492 5222 } 4493 5223 ///////////////////// 5224 case CLEANUP_IVT_LOCK_DATA://RWT 5225 { 5226 //Search for a matching inval in the UPT (there must be one) and check if there is a pending read. 5227 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) 5228 { 5229 size_t index = 0; 5230 bool match_inval; 5231 5232 match_inval = m_upt.search_inval(r_cleanup_nline.read(), index); 5233 assert (match_inval && "VCI MEM CACHE ERROR: In CLEANUP_IVT_LOCK_DATA, NO CORRESPONDING INVAL"); 5234 r_cleanup_read_srcid = m_upt.srcid(index); 5235 r_cleanup_read_trdid = m_upt.trdid(index); 5236 r_cleanup_read_pktid = 0x0 + m_upt.pktid(index); 5237 r_cleanup_read_need_rsp = !m_upt.need_rsp(index); 5238 r_cleanup_index = index; 5239 5240 r_cleanup_fsm = CLEANUP_IVT_CLEAR_DATA; 5241 } 5242 #if DEBUG_MC_CLEANUP 5243 if (m_debug) 5244 { 5245 std::cout 5246 << " <MEMC " << name() 5247 << " CLEANUP_IVT_LOCK_DATA> fetch pending inval" 5248 << std::endl; 5249 } 5250 #endif 5251 break; 5252 } 5253 5254 ////////////////////////// 5255 case CLEANUP_IVT_CLEAR_DATA://RWT 5256 { 5257 m_upt.clear(r_cleanup_index.read()); 5258 assert ((r_cleanup_read_need_rsp.read() == (r_read_to_cleanup_req.read() && (r_cleanup_nline.read() == r_read_to_cleanup_nline.read()))) && "condition pending read"); 5259 if (r_cleanup_read_need_rsp.read()) 5260 { 5261 r_cleanup_fsm = CLEANUP_READ_RSP; 5262 } 5263 else 5264 { 5265 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5266 } 5267 #if DEBUG_MC_CLEANUP 5268 if (m_debug) 5269 { 5270 std::cout 5271 << " <MEMC " << name() 5272 << " CLEANUP_IVT_CLEAR_DATA> clear UPT entry" 5273 << std::endl; 5274 } 5275 #endif 5276 break; 5277 } 5278 5279 //////////////////////// 5280 case CLEANUP_READ_RSP://RWT 5281 { 5282 if(r_cleanup_to_tgt_rsp_req.read()) break; 5283 5284 r_cleanup_to_tgt_rsp_req = true; 5285 r_cleanup_to_tgt_rsp_srcid = r_cleanup_read_srcid.read(); 5286 r_cleanup_to_tgt_rsp_trdid = r_cleanup_read_trdid.read(); 5287 r_cleanup_to_tgt_rsp_pktid = 0x0 + r_cleanup_read_pktid.read();//WT 5288 r_cleanup_to_tgt_rsp_type = 0; //Read instruction 5289 r_cleanup_to_tgt_rsp_length = r_read_to_cleanup_length.read(); 5290 r_cleanup_to_tgt_rsp_first_word = r_read_to_cleanup_first_word.read(); 5291 r_read_to_cleanup_req = false; 5292 m_cpt_ncc_to_cc_read ++; 5293 if (r_cleanup_contains_data.read()) //L1 was dirty 5294 { 5295 for(size_t i = 0; i<m_words; i++) 5296 { 5297 r_cleanup_to_tgt_rsp_data[i] = r_cleanup_data[i].read(); 5298 } 5299 } 5300 else //the L2 data are up to date 5301 { 5302 for(size_t i = 0; i<m_words; i++) 5303 { 5304 r_cleanup_to_tgt_rsp_data[i] = r_cleanup_old_data[i].read(); 5305 } 5306 } 5307 5308 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5309 5310 #if DEBUG_MC_CLEANUP 5311 if (m_debug) 5312 { 5313 std::cout 5314 << " <MEMC " << name() 5315 << " CLEANUP_READ_RSP> answer READ" 5316 << std::endl; 5317 } 5318 #endif 5319 break; 5320 } 4494 5321 ////////////////////// 4495 5322 case CLEANUP_HEAP_REQ: … … 4497 5324 // get the lock to the HEAP directory 4498 5325 if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; 4499 5326 4500 5327 r_cleanup_fsm = CLEANUP_HEAP_LOCK; 4501 5328 … … 4509 5336 } 4510 5337 #endif 5338 m_cpt_cleanup_fsm_n_heap_lock++; 4511 5339 break; 4512 5340 } … … 4568 5396 << " / r_cleanup_copy_inst = " << r_cleanup_copy_inst.read() << std::endl 4569 5397 << "heap_entry.owner.srcid = " << heap_entry.owner.srcid 4570 << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl ;5398 << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl 4571 5399 /**/ 5400 << "nline = " << r_cleanup_nline << std::endl; 4572 5401 exit(0); 4573 5402 } … … 4587 5416 << " / r_cleanup_copy_inst = " << r_cleanup_copy_inst.read() << std::endl 4588 5417 << "heap_entry.owner.srcid = " << heap_entry.owner.srcid 4589 << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl ;5418 << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl 4590 5419 /**/ 4591 5420 << "nline = " << r_cleanup_nline << std::endl; 4592 5421 exit(0); 4593 5422 } … … 4595 5424 DirectoryEntry dir_entry; 4596 5425 dir_entry.valid = true; 5426 dir_entry.cache_coherent = true; 4597 5427 dir_entry.is_cnt = r_cleanup_is_cnt.read(); 4598 5428 dir_entry.dirty = r_cleanup_dirty.read(); … … 4652 5482 4653 5483 m_cache_directory.write(set,way,dir_entry); 5484 4654 5485 4655 5486 #if DEBUG_MEMC_CLEANUP … … 4854 5685 // invalidate transaction matching the cleanup 4855 5686 { 5687 m_cpt_cleanup_fsm_ivt_lock++; 4856 5688 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; 4857 5689 … … 4860 5692 4861 5693 match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); 4862 4863 5694 if ( not match_inval ) // no pending inval 4864 5695 { … … 4874 5705 << std::endl; 4875 5706 #endif 4876 break; 5707 m_cpt_cleanup_fsm_n_upt_lock++; 5708 break; 4877 5709 } 4878 5710 … … 4914 5746 m_ivt.decrement(r_cleanup_index.read(), count); 4915 5747 5748 4916 5749 if(count == 0) // multi inval transaction completed 4917 5750 { … … 4920 5753 else // multi inval transaction not completed 4921 5754 { 4922 r_cleanup_fsm = CLEANUP_SEND_CLACK ; 5755 if (r_cleanup_ncc.read()) //need to put data to the XRAM 5756 { 5757 r_cleanup_fsm = CLEANUP_IXR_REQ; 5758 } 5759 else 5760 { 5761 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5762 } 4923 5763 } 4924 5764 … … 4950 5790 if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; 4951 5791 else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; 5792 else if ( r_cleanup_ncc.read() ) r_cleanup_fsm = CLEANUP_IXR_REQ; 4952 5793 else r_cleanup_fsm = CLEANUP_SEND_CLACK; 4953 5794 … … 4971 5812 r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); 4972 5813 r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); 4973 4974 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5814 r_cleanup_to_tgt_rsp_type = true; 5815 5816 if (r_cleanup_ncc.read()) 5817 { 5818 r_cleanup_fsm = CLEANUP_IXR_REQ;//need to put data to the XRAM 5819 } 5820 else 5821 { 5822 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5823 } 4975 5824 4976 5825 #if DEBUG_MEMC_CLEANUP … … 5000 5849 break; 5001 5850 } 5851 5852 ///////////////////////// 5853 case CLEANUP_IXR_REQ: 5854 { 5855 5856 //Send a request to the ixr to write the data in the XRAM using the prereserved TRT entry 5857 if (r_alloc_trt_fsm.read() == ALLOC_TRT_CLEANUP) 5858 { 5859 if(!r_cleanup_to_ixr_cmd_req.read()) 5860 { 5861 size_t index = 0; 5862 bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); 5863 5864 assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT"); 5865 5866 r_cleanup_to_ixr_cmd_req = true; 5867 5868 for(size_t i = 0; i < m_words; i++){ 5869 r_cleanup_to_ixr_cmd_data[i] = r_cleanup_data[i]; 5870 } 5871 5872 r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); 5873 r_cleanup_to_ixr_cmd_trdid = index; 5874 r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); 5875 r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); 5876 r_cleanup_to_ixr_cmd_ncc_l1_dirty = r_cleanup_contains_data.read(); 5877 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5878 #if DEBUG_MEMC_CLEANUP 5879 if(m_debug) 5880 { 5881 std::cout 5882 << " <MEMC " << name() 5883 << " CLEANUP_IXR_REQ>" 5884 << " request send to IXR_CMD" 5885 << std::endl; 5886 } 5887 #endif 5888 } 5889 else 5890 { 5891 r_cleanup_fsm = CLEANUP_WAIT; 5892 #if DEBUG_MEMC_CLEANUP 5893 if(m_debug) 5894 { 5895 std::cout 5896 << " <MEMC " << name() 5897 << " CLEANUP_IXR_REQ>" 5898 << " waiting completion of previous request" 5899 << std::endl; 5900 } 5901 #endif 5902 } 5903 } 5904 break; 5905 } 5906 5907 ///////////////////// 5908 case CLEANUP_WAIT : 5909 { 5910 r_cleanup_fsm = CLEANUP_IXR_REQ; 5911 break; 5912 } 5913 5002 5914 //////////////////////// 5003 5915 case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command … … 5102 6014 { 5103 6015 r_cas_fsm = CAS_DIR_LOCK; 6016 m_cpt_cas_fsm_n_dir_lock++; 5104 6017 } 5105 6018 … … 5112 6025 } 5113 6026 #endif 6027 6028 m_cpt_cas_fsm_dir_lock++; 6029 5114 6030 break; 5115 6031 } … … 5124 6040 5125 6041 r_cas_is_cnt = entry.is_cnt; 6042 r_cas_coherent = entry.cache_coherent; 5126 6043 r_cas_dirty = entry.dirty; 5127 6044 r_cas_tag = entry.tag; … … 5171 6088 DirectoryEntry entry; 5172 6089 entry.valid = true; 6090 entry.cache_coherent = r_cas_coherent.read(); 5173 6091 entry.is_cnt = r_cas_is_cnt.read(); 5174 6092 entry.dirty = true; … … 5238 6156 { 5239 6157 // The CAS is a success => sw access to the llsc_global_table 5240 m_llsc_table.sw(m_cmd_cas_addr_fifo.read()); 6158 // BUG LLSC 6159 addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; 6160 m_llsc_table.sw(nline); 6161 //m_llsc_table.sw(m_cmd_cas_addr_fifo.read()); 6162 /**//*std::cout << "MEMCACHE : from proc " << m_cmd_cas_srcid_fifo.read() 6163 << " | @ " << std::hex << m_cmd_cas_addr_fifo.read() 6164 << " | WRITE (cas triggered)" << std::endl;*/ 5241 6165 5242 6166 // test coherence request … … 5355 6279 << " / count = " << nb_copies << std::endl; 5356 6280 #endif 5357 } 6281 m_cpt_cas_fsm_n_upt_lock++; 6282 } 6283 6284 m_cpt_cas_fsm_upt_lock++; 6285 5358 6286 break; 5359 6287 } … … 5386 6314 #endif 5387 6315 r_cas_fsm = CAS_UPT_REQ; 5388 } 6316 m_cpt_cas_fsm_n_heap_lock++; 6317 } 6318 6319 m_cpt_cas_fsm_heap_lock++; 6320 5389 6321 break; 5390 6322 } … … 5526 6458 r_cas_fsm = CAS_WAIT; 5527 6459 } 5528 } 6460 m_cpt_cas_fsm_n_trt_lock++; 6461 } 6462 6463 m_cpt_cas_fsm_trt_lock++; 6464 5529 6465 break; 5530 6466 } … … 5591 6527 r_cas_fsm = CAS_WAIT; 5592 6528 } 5593 } 6529 m_cpt_cas_fsm_n_upt_lock++; 6530 } 6531 6532 m_cpt_cas_fsm_upt_lock++; 6533 5594 6534 break; 5595 6535 } … … 5769 6709 r_cas_fsm = CAS_MISS_TRT_SET; 5770 6710 } 5771 } 6711 m_cpt_cas_fsm_n_trt_lock++; 6712 } 6713 6714 m_cpt_cas_fsm_trt_lock++; 6715 5772 6716 break; 5773 6717 } … … 5897 6841 break; 5898 6842 } 6843 6844 if(r_read_to_cc_send_req.read()) 6845 { 6846 r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER; 6847 break; 6848 } 6849 6850 if(r_write_to_cc_send_req.read()) 6851 { 6852 r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER; 6853 break; 6854 } 6855 6856 5899 6857 // WRITE 6858 if(r_read_to_cc_send_req.read()) 6859 { 6860 r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER; 6861 break; 6862 } 6863 6864 if(r_write_to_cc_send_req.read()) 6865 { 6866 r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER; 6867 break; 6868 } 5900 6869 if(m_write_to_cc_send_inst_fifo.rok() or 5901 6870 r_write_to_cc_send_multi_req.read()) … … 5971 6940 } 5972 6941 // WRITE 6942 if(r_read_to_cc_send_req.read()) 6943 { 6944 r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER; 6945 break; 6946 } 6947 6948 if(r_write_to_cc_send_req.read()) 6949 { 6950 r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER; 6951 break; 6952 } 5973 6953 if(m_write_to_cc_send_inst_fifo.rok() or 5974 6954 r_write_to_cc_send_multi_req.read()) … … 6003 6983 break; 6004 6984 } 6985 6986 if(r_read_to_cc_send_req.read()) 6987 { 6988 r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER; 6989 break; 6990 } 6991 6992 if(r_write_to_cc_send_req.read()) 6993 { 6994 r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER; 6995 break; 6996 } 6997 6998 6005 6999 // WRITE 7000 if(r_read_to_cc_send_req.read()) 7001 { 7002 r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER; 7003 break; 7004 } 7005 7006 if(r_write_to_cc_send_req.read()) 7007 { 7008 r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER; 7009 break; 7010 } 6006 7011 if(m_write_to_cc_send_inst_fifo.rok() or 6007 7012 r_write_to_cc_send_multi_req.read()) … … 6050 7055 case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority 6051 7056 { 7057 7058 if(r_read_to_cc_send_req.read()) 7059 { 7060 r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER; 7061 break; 7062 } 7063 7064 if(r_write_to_cc_send_req.read()) 7065 { 7066 r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER; 7067 break; 7068 } 7069 7070 6052 7071 if(m_write_to_cc_send_inst_fifo.rok() or 6053 7072 r_write_to_cc_send_multi_req.read()) … … 6208 7227 break; 6209 7228 } 7229 7230 case CC_SEND_READ_NCC_INVAL_HEADER: 7231 { 7232 if(not p_dspin_m2p.read) break; 7233 7234 r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_NLINE; 7235 break; 7236 } 7237 7238 case CC_SEND_READ_NCC_INVAL_NLINE: 7239 { 7240 if(not p_dspin_m2p.read) break; 7241 7242 r_read_to_cc_send_req = false; 7243 r_cc_send_fsm = CC_SEND_WRITE_IDLE; 7244 7245 #if DEBUG_MEMC_CC_SEND 7246 if(m_debug) 7247 { 7248 std::cout 7249 << " <MEMC " << name() 7250 << " CC_SEND_READ_NCC_INVAL_HEADER> Inval for line " 7251 << r_read_to_cc_send_nline.read() 7252 << std::endl; 7253 } 7254 #endif 7255 break; 7256 } 7257 7258 7259 case CC_SEND_WRITE_NCC_INVAL_HEADER: 7260 { 7261 if(not p_dspin_m2p.read) break; 7262 7263 r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_NLINE; 7264 break; 7265 } 7266 7267 case CC_SEND_WRITE_NCC_INVAL_NLINE: 7268 { 7269 if(not p_dspin_m2p.read) break; 7270 7271 r_write_to_cc_send_req = false; 7272 r_cc_send_fsm = CC_SEND_WRITE_IDLE; 7273 7274 #if DEBUG_MEMC_CC_SEND 7275 if(m_debug) 7276 { 7277 std::cout 7278 << " <MEMC " << name() 7279 << " CC_SEND_WRITE_NCC_INVAL_HEADER> Inval for line " 7280 << r_write_to_cc_send_nline.read() 7281 << std::endl; 7282 } 7283 #endif 7284 break; 7285 } 7286 7287 6210 7288 ////////////////////////////////// 6211 7289 case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) … … 6417 7495 break; 6418 7496 6419 assert(not p_dspin_p2m.eop.read() and6420 "VCI_MEM_CACHE ERROR in CC_RECEIVE : "6421 "CLEANUP command must have two flits");6422 6423 7497 cc_receive_to_cleanup_fifo_put = true; 6424 r_cc_receive_fsm = CC_RECEIVE_CLEANUP_EOP; 7498 if(p_dspin_p2m.eop.read()) 7499 r_cc_receive_fsm = CC_RECEIVE_IDLE; 6425 7500 6426 7501 break; … …