Changeset 495 for branches/RWT/modules/vci_mem_cache/caba/source/include

Timestamp:

Aug 22, 2013, 6:45:38 PM (11 years ago)

Author:

haoliu

Message:

This version for RWT has merged with the lastest version of classic tsar.
It pass the test with giet_vm.

Location:

branches/RWT/modules/vci_mem_cache/caba/source/include

Files:

• . (modified) (1 prop)
• mem_cache_directory.h (modified) (12 diffs)
• update_tab.h (modified) (1 prop)
• vci_mem_cache.h (modified) (25 diffs, 1 prop)
• xram_transaction.h (modified) (25 diffs)

branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h

@@ -6 +6 @@
 #include <cassert>
 #include "arithmetics.h"
-
-// !!!
-// The L1_MULTI_CACHE mechanism does no longer work with the new pktid encoding
-// of TSAR. Turning the define below to a non null value will cause the memcache
-// to behave in an unpredicted way.
-// TODO Either remove the mechanism from the mem cache or update its behaviour.
-
-#define L1_MULTI_CACHE 0
 
 //#define RANDOM_EVICTION
@@ -46 +38 @@
       bool      inst;       // Is the owner an ICache ?
       size_t    srcid;      // The SRCID of the owner
-#if L1_MULTI_CACHE
-      size_t    cache_id;   // In multi_cache configuration
-#endif
 
     ////////////////////////
     // Constructors
     ////////////////////////
-      Owner(bool   i_inst
-            ,size_t i_srcid
-#if L1_MULTI_CACHE
-            ,size_t i_cache_id
-#endif
-            ){
+      Owner(bool   i_inst,
+            size_t i_srcid)
+      {
         inst    = i_inst;
         srcid   = i_srcid;
-#if L1_MULTI_CACHE
-        cache_id= i_cache_id;
-#endif
-      }
-
-      Owner(const Owner &a){
+      }
+
+      Owner(const Owner &a)
+      {
         inst    = a.inst;
         srcid   = a.srcid;
-#if L1_MULTI_CACHE
-        cache_id= a.cache_id;
-#endif
-      }
-
-      Owner(){
+      }
+
+      Owner()
+      {
         inst    = false;
         srcid   = 0;
-#if L1_MULTI_CACHE
-        cache_id= 0;
-#endif
       }
       // end constructors
@@ -116 +95 @@
       owner.inst    = 0;
       owner.srcid   = 0;
-#if L1_MULTI_CACHE
-      owner.cache_id= 0;
-#endif
       ptr           = 0;
     }
@@ -177 +153 @@
                 << " ; Count = " << count 
                 << " ; Owner = " << owner.srcid 
-#if L1_MULTI_CACHE
-                << "." << owner.cache_id 
-#endif
                 << " " << owner.inst 
                 << " ; Pointer = " << ptr << std::endl;
@@ -328 +301 @@
     // - entry : the entry value
     /////////////////////////////////////////////////////////////////////
-    void write(const size_t &set, const size_t &way, const DirectoryEntry &entry)
+    void write( const size_t         &set, 
+                const size_t         &way, 
+                const DirectoryEntry &entry)
     {
       assert( (set<m_sets) 
@@ -374 +349 @@
     DirectoryEntry select(const size_t &set, size_t &way)
     {
-      assert( (set < m_sets) 
+        assert( (set < m_sets) 
           && "Cache Directory : (select) The set index is invalid");
 
-      for(size_t i=0; i<m_ways; i++){
-        if(!m_dir_tab[set][i].valid){
-          way=i;
-          return DirectoryEntry(m_dir_tab[set][way]);
+        // looking for an empty slot
+        for(size_t i=0; i<m_ways; i++)
+        {
+            if( not m_dir_tab[set][i].valid )
+            {
+                way=i;
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         }
-      }
 
 #ifdef RANDOM_EVICTION
-      lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001);
-      way = lfsr % m_ways;
-      return DirectoryEntry(m_dir_tab[set][way]);
+        lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001);
+        way = lfsr % m_ways;
+        return DirectoryEntry(m_dir_tab[set][way]);
 #endif
 
-      for(size_t i=0; i<m_ways; i++){
-        if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
-          way=i;
-          return DirectoryEntry(m_dir_tab[set][way]);
+        // looking for a not locked and not recently used entry
+        for(size_t i=0; i<m_ways; i++)
+        {
+            if((not m_lru_tab[set][i].recent) && (not m_dir_tab[set][i].lock) )
+            {
+                way=i;
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         }
-      }
-      for(size_t i=0; i<m_ways; i++){
-        if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
-          way=i;
-          return DirectoryEntry(m_dir_tab[set][way]);
+
+        // looking for a locked not recently used entry
+        for(size_t i=0; i<m_ways; i++)
+        {
+            if( (not m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock))
+            {
+                way=i;
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         }
-      }
-      for(size_t i=0; i<m_ways; i++){
-        if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
-          way=i;
-          return DirectoryEntry(m_dir_tab[set][way]);
+
+        // looking for a recently used entry not locked
+        for(size_t i=0; i<m_ways; i++)
+        {
+            if( (m_lru_tab[set][i].recent) && (not m_dir_tab[set][i].lock))
+            {
+                way=i;
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         }
-      }
-      way = 0;
-      return DirectoryEntry(m_dir_tab[set][0]);
+
+        // select way 0 (even if entry is locked and recently used)
+        way = 0;
+        return DirectoryEntry(m_dir_tab[set][0]);
     } // end select()
 
@@ -443 +434 @@
     ////////////////////////
       HeapEntry()
-      :owner(false,0
-#if L1_MULTI_CACHE
-             ,0
-#endif
-             )
+      :owner(false,0)
       {
         next = 0;
@@ -455 +442 @@
     // Constructor
     ////////////////////////
-      HeapEntry(const HeapEntry &entry){
+      HeapEntry(const HeapEntry &entry)
+      {
         owner.inst  = entry.owner.inst;
         owner.srcid = entry.owner.srcid;
-#if L1_MULTI_CACHE
-        owner.cache_id = entry.owner.cache_id;
-#endif        
         next           = entry.next;
       } // end constructor
@@ -467 +452 @@
     // The copy() function copies an existing source entry to a target 
     /////////////////////////////////////////////////////////////////////
-      void copy(const HeapEntry &entry){
+      void copy(const HeapEntry &entry)
+      {
         owner.inst     = entry.owner.inst;
         owner.srcid    = entry.owner.srcid;
-#if L1_MULTI_CACHE
-        owner.cache_id = entry.owner.cache_id;
-#endif
         next           = entry.next;
       } // end copy()
@@ -483 +466 @@
         << " -- owner.inst     : " << std::dec << owner.inst << std::endl
         << " -- owner.srcid    : " << std::dec << owner.srcid << std::endl
-#if L1_MULTI_CACHE
-        << " -- owner.cache_id : " << std::dec << owner.cache_id << std::endl
-#endif
         << " -- next           : " << std::dec << next << std::endl;
 
@@ -646 +626 @@
   //                        Cache Data 
   ////////////////////////////////////////////////////////////////////////
-  class CacheData {
+  class CacheData 
+  {
     private:
       const uint32_t m_sets;
@@ -656 +637 @@
     public:
 
+      ///////////////////////////////////////////////////////
       CacheData(uint32_t ways, uint32_t sets, uint32_t words)
-        : m_sets(sets), m_ways(ways), m_words(words) {
-
+        : m_sets(sets), m_ways(ways), m_words(words) 
+      {
           m_cache_data = new uint32_t ** [ways];
-          for ( size_t i=0 ; i < ways ; i++ ) {
-            m_cache_data[i] = new uint32_t * [sets];
+          for ( size_t i=0 ; i < ways ; i++ ) 
+          {
+              m_cache_data[i] = new uint32_t * [sets];
           }
-          for ( size_t i=0; i<ways; i++ ) {
-            for ( size_t j=0; j<sets; j++ ) {
-              m_cache_data[i][j] = new uint32_t [words];
-            }
+          for ( size_t i=0; i<ways; i++ ) 
+          {
+              for ( size_t j=0; j<sets; j++ ) 
+              {
+                  m_cache_data[i][j] = new uint32_t [words];
+              }
           }
-        }
-
-      ~CacheData() {
-          for(size_t i=0; i<m_ways ; i++){
-              for(size_t j=0; j<m_sets ; j++){
+      }
+      ////////////
+      ~CacheData() 
+      {
+          for(size_t i=0; i<m_ways ; i++)
+          {
+              for(size_t j=0; j<m_sets ; j++)
+              {
                   delete [] m_cache_data[i][j];
               }
           }
-          for(size_t i=0; i<m_ways ; i++){
+          for(size_t i=0; i<m_ways ; i++)
+          {
               delete [] m_cache_data[i];
           }
           delete [] m_cache_data;
       }
-
-      uint32_t read (
-          const uint32_t &way,
-          const uint32_t &set,
-          const uint32_t &word) const {
-
-        assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set" );
-        assert((way  < m_ways ) && "Cache data error: Trying to read a wrong way" );
-        assert((word < m_words) && "Cache data error: Trying to read a wrong word");
-
-        return m_cache_data[way][set][word];
-      }
-
-      void read_line(
-          const uint32_t &way,
-          const uint32_t &set,
-          sc_core::sc_signal<uint32_t> * cache_line)
-      {
-        assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
-        assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
-
-        for (uint32_t word=0; word<m_words; word++)
-          cache_line[word].write(m_cache_data[way][set][word]);
-      }
-
-      void write (
-          const uint32_t &way,
-          const uint32_t &set,
-          const uint32_t &word,
-          const uint32_t &data,
-          const uint32_t &be = 0xF) {
-
-        assert((set  < m_sets ) && "Cache data error: Trying to write a wrong set" );
-        assert((way  < m_ways ) && "Cache data error: Trying to write a wrong way" );
-        assert((word < m_words) && "Cache data error: Trying to write a wrong word");
-        assert((be  <= 0xF    ) && "Cache data error: Trying to write a wrong word cell");
-
-        if (be == 0x0) return;
-
-        if (be == 0xF) {
-            m_cache_data[way][set][word] = data; 
-            return;
-        }
-
-        uint32_t mask = 0;
-        if  (be & 0x1) mask = mask | 0x000000FF;
-        if  (be & 0x2) mask = mask | 0x0000FF00;
-        if  (be & 0x4) mask = mask | 0x00FF0000;
-        if  (be & 0x8) mask = mask | 0xFF000000;
-
-        m_cache_data[way][set][word] = 
-          (data & mask) | (m_cache_data[way][set][word] & ~mask);
+      //////////////////////////////////////////
+      uint32_t read ( const uint32_t &way,
+                      const uint32_t &set,
+                      const uint32_t &word) const 
+      {
+          assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set" );
+          assert((way  < m_ways ) && "Cache data error: Trying to read a wrong way" );
+          assert((word < m_words) && "Cache data error: Trying to read a wrong word");
+
+          return m_cache_data[way][set][word];
+      }
+      //////////////////////////////////////////
+      void read_line( const uint32_t &way,
+                      const uint32_t &set,
+                      sc_core::sc_signal<uint32_t> * cache_line)
+      {
+          assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
+          assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
+
+          for (uint32_t word=0; word<m_words; word++)
+              cache_line[word].write(m_cache_data[way][set][word]);
+      }
+      /////////////////////////////////////////
+      void write ( const uint32_t &way,
+                   const uint32_t &set,
+                   const uint32_t &word,
+                   const uint32_t &data,
+                   const uint32_t &be = 0xF) 
+      {
+
+          assert((set  < m_sets ) && "Cache data error: Trying to write a wrong set" );
+          assert((way  < m_ways ) && "Cache data error: Trying to write a wrong way" );
+          assert((word < m_words) && "Cache data error: Trying to write a wrong word");
+          assert((be  <= 0xF    ) && "Cache data error: Trying to write a wrong be");
+
+          if (be == 0x0) return;
+
+          if (be == 0xF) 
+          {
+              m_cache_data[way][set][word] = data; 
+              return;
+          }
+
+          uint32_t mask = 0;
+          if  (be & 0x1) mask = mask | 0x000000FF;
+          if  (be & 0x2) mask = mask | 0x0000FF00;
+          if  (be & 0x4) mask = mask | 0x00FF0000;
+          if  (be & 0x8) mask = mask | 0xFF000000;
+
+          m_cache_data[way][set][word] = 
+              (data & mask) | (m_cache_data[way][set][word] & ~mask);
       }
   }; // end class CacheData

branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -25 +25 @@
  * SOCLIB_LGPL_HEADER_END
  *
- * Maintainers: alain eric.guthmuller@polytechnique.edu
+ * Maintainers: alain.greiner@lip6.fr 
+ *              eric.guthmuller@polytechnique.edu
  *              cesar.fuguet-tortolero@lip6.fr
  *              alexandre.joannou@lip6.fr
@@ -154 +155 @@
         MULTI_ACK_UPT_LOCK,
         MULTI_ACK_UPT_CLEAR,
-        MULTI_ACK_WRITE_RSP,
-        MULTI_ACK_CONFIG_ACK
+        MULTI_ACK_WRITE_RSP
       };
 
@@ -163 +163 @@
         CONFIG_IDLE,
         CONFIG_LOOP,
+        CONFIG_WAIT,
         CONFIG_RSP,
         CONFIG_DIR_REQ,
         CONFIG_DIR_ACCESS,
-        CONFIG_DIR_IVT_LOCK,
+        CONFIG_IVT_LOCK,
         CONFIG_BC_SEND,
-        CONFIG_BC_WAIT,
-        CONFIG_INV_SEND,
+        CONFIG_INVAL_SEND,
         CONFIG_HEAP_REQ,
         CONFIG_HEAP_SCAN,
         CONFIG_HEAP_LAST,
-        CONFIG_INV_WAIT
+        CONFIG_TRT_LOCK,
+        CONFIG_TRT_SET,
+        CONFIG_PUT_REQ
       };
 
@@ -204 +206 @@
         WRITE_DIR_LOCK,
         WRITE_IVT_LOCK_HIT_WB,
-        WRITE_DIR_READ,
         WRITE_DIR_HIT,
         WRITE_UPT_LOCK,
@@ -217 +218 @@
         WRITE_MISS_TRT_SET,
         WRITE_MISS_XRAM_REQ,
+        WRITE_BC_DIR_READ,
         WRITE_BC_TRT_LOCK,
         WRITE_BC_IVT_LOCK,
@@ -243 +245 @@
         XRAM_RSP_DIR_UPDT,
         XRAM_RSP_DIR_RSP,
-        XRAM_RSP_INVAL_LOCK,
+        XRAM_RSP_IVT_LOCK,
         XRAM_RSP_INVAL_WAIT,
         XRAM_RSP_INVAL,
@@ -262 +264 @@
         IXR_CMD_XRAM_IDLE,
         IXR_CMD_CLEANUP_IDLE,
-        IXR_CMD_READ,
-        IXR_CMD_WRITE,
-        IXR_CMD_CAS,
-        IXR_CMD_XRAM,
-        IXR_CMD_CLEANUP_DATA
+        IXR_CMD_CONFIG_IDLE,
+        IXR_CMD_READ_TRT,
+        IXR_CMD_WRITE_TRT,
+        IXR_CMD_CAS_TRT,
+        IXR_CMD_XRAM_TRT,
+        IXR_CMD_CLEANUP_TRT,
+        IXR_CMD_CONFIG_TRT,
+        IXR_CMD_READ_SEND,
+        IXR_CMD_WRITE_SEND,
+        IXR_CMD_CAS_SEND,
+        IXR_CMD_XRAM_SEND,
+        IXR_CMD_CLEANUP_DATA_SEND,
+        IXR_CMD_CONFIG_SEND
       };
 
@@ -318 +328 @@
         CLEANUP_IXR_REQ,
         CLEANUP_WAIT,
-        CLEANUP_CONFIG_ACK,
         CLEANUP_SEND_CLACK
       };
@@ -342 +351 @@
         ALLOC_TRT_XRAM_RSP,
         ALLOC_TRT_IXR_RSP,
-        ALLOC_TRT_CLEANUP
+        ALLOC_TRT_CLEANUP,
+        ALLOC_TRT_IXR_CMD,
+        ALLOC_TRT_CONFIG
       };
 
@@ -404 +415 @@
       };
 
-      /* Configuration commands */
-      enum cmd_config_type_e
-      {
-          CMD_CONFIG_INVAL = 0,
-          CMD_CONFIG_SYNC  = 1
-      };
-
-      // debug variables (for each FSM)
+      // debug variables 
       bool                 m_debug;
       bool                 m_debug_previous_valid;
       size_t               m_debug_previous_count;
       bool                 m_debug_previous_dirty;
-      sc_signal<data_t>*   m_debug_previous_data;
-      sc_signal<data_t>*   m_debug_data;
-
-      bool         m_monitor_ok;
-      addr_t       m_monitor_base;
-      addr_t       m_monitor_length;
+      data_t *             m_debug_previous_data;
+      data_t *             m_debug_data;
 
       // instrumentation counters
@@ -644 +644 @@
       uint32_t                           m_broadcast_boundaries;
 
-      //////////////////////////////////////////////////
-      // Registers controlled by the TGT_CMD fsm
-      //////////////////////////////////////////////////
-
-      sc_signal<int>         r_tgt_cmd_fsm;
-
       // Fifo between TGT_CMD fsm and READ fsm
       GenericFifo<addr_t>    m_cmd_read_addr_fifo;
@@ -693 +687 @@
       sc_signal<size_t>   r_tgt_cmd_config_cmd;
 
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+      sc_signal<size_t>      r_tgt_cmd_srcid;           // srcid for response to config
+      sc_signal<size_t>      r_tgt_cmd_trdid;           // trdid for response to config
+      sc_signal<size_t>      r_tgt_cmd_pktid;           // pktid for response to config
+
       ///////////////////////////////////////////////////////
       // Registers controlled by the CONFIG fsm
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_config_fsm;            // FSM state
-      sc_signal<bool>     r_config_lock;           // lock protecting exclusive access
-      sc_signal<int>      r_config_cmd;            // config request status
-      sc_signal<addr_t>   r_config_address;        // target buffer physical address
-      sc_signal<size_t>   r_config_srcid;          // config request srcid
-      sc_signal<size_t>   r_config_trdid;          // config request trdid
-      sc_signal<size_t>   r_config_pktid;          // config request pktid
-      sc_signal<size_t>   r_config_nlines;         // number of lines covering the buffer
-      sc_signal<size_t>   r_config_dir_way;        // DIR: selected way
-      sc_signal<size_t>   r_config_dir_count;      // DIR: number of copies
-      sc_signal<bool>     r_config_dir_is_cnt;     // DIR: counter mode (broadcast required)
-      sc_signal<size_t>   r_config_dir_copy_srcid; // DIR: first copy SRCID
-      sc_signal<bool>     r_config_dir_copy_inst;  // DIR: first copy L1 type
-      sc_signal<size_t>   r_config_dir_next_ptr;   // DIR: index of next copy in HEAP
-      sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
-
-      sc_signal<size_t>   r_config_ivt_index;      // IVT index
+      sc_signal<int>      r_config_fsm;               // FSM state
+      sc_signal<bool>     r_config_lock;              // lock protecting exclusive access
+      sc_signal<int>      r_config_cmd;               // config request type  
+      sc_signal<addr_t>   r_config_address;           // target buffer physical address
+      sc_signal<size_t>   r_config_srcid;             // config request srcid
+      sc_signal<size_t>   r_config_trdid;             // config request trdid
+      sc_signal<size_t>   r_config_pktid;             // config request pktid
+      sc_signal<size_t>   r_config_cmd_lines;         // number of lines to be handled
+      sc_signal<size_t>   r_config_rsp_lines;         // number of lines not completed
+      sc_signal<size_t>   r_config_dir_way;           // DIR: selected way
+      sc_signal<bool>     r_config_dir_lock;          // DIR: locked entry
+      sc_signal<size_t>   r_config_dir_count;         // DIR: number of copies
+      sc_signal<bool>     r_config_dir_is_cnt;        // DIR: counter mode (broadcast)
+      sc_signal<size_t>   r_config_dir_copy_srcid;    // DIR: first copy SRCID
+      sc_signal<bool>     r_config_dir_copy_inst;     // DIR: first copy L1 type
+      sc_signal<size_t>   r_config_dir_ptr;           // DIR: index of next copy in HEAP
+      sc_signal<size_t>   r_config_heap_next;         // current pointer to scan HEAP
+      sc_signal<size_t>   r_config_trt_index;         // selected entry in TRT
+      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT 
+
+      // Buffer between CONFIG fsm and IXR_CMD fsm
+      sc_signal<bool>     r_config_to_ixr_cmd_req;    // valid request
+      sc_signal<size_t>   r_config_to_ixr_cmd_index;  // TRT index
+
 
       // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
@@ -730 +740 @@
       GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
-#endif
-
       ///////////////////////////////////////////////////////
       // Registers controlled by the READ fsm
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_read_fsm;          // FSM state
-      sc_signal<size_t>   r_read_copy;         // Srcid of the first copy
-      sc_signal<size_t>   r_read_copy_cache;   // Srcid of the first copy
-      sc_signal<bool>     r_read_copy_inst;    // Type of the first copy
-      sc_signal<tag_t>    r_read_tag;          // cache line tag (in directory)
-      sc_signal<bool>     r_read_is_cnt;       // is_cnt bit (in directory)
-      sc_signal<bool>     r_read_lock;         // lock bit (in directory)
-      sc_signal<bool>     r_read_dirty;        // dirty bit (in directory)
-      sc_signal<size_t>   r_read_count;        // number of copies
-      sc_signal<size_t>   r_read_ptr;          // pointer to the heap
-      sc_signal<data_t> * r_read_data;         // data (one cache line)
-      sc_signal<size_t>   r_read_way;          // associative way (in cache)
-      sc_signal<size_t>   r_read_trt_index;    // Transaction Table index
-      sc_signal<size_t>   r_read_next_ptr;     // Next entry to point to
-      sc_signal<bool>     r_read_last_free;    // Last free entry
-      sc_signal<addr_t>   r_read_ll_key;       // LL key from the llsc_global_table
-
-      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
-      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
-      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
-      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
+      sc_signal<int>      r_read_fsm;                 // FSM state
+      sc_signal<size_t>   r_read_copy;                // Srcid of the first copy
+      sc_signal<size_t>   r_read_copy_cache;          // Srcid of the first copy
+      sc_signal<bool>     r_read_copy_inst;           // Type of the first copy
+      sc_signal<tag_t>    r_read_tag;                 // cache line tag (in directory)
+      sc_signal<bool>     r_read_is_cnt;              // is_cnt bit (in directory)
+      sc_signal<bool>     r_read_lock;                // lock bit (in directory)
+      sc_signal<bool>     r_read_dirty;               // dirty bit (in directory)
+      sc_signal<size_t>   r_read_count;               // number of copies
+      sc_signal<size_t>   r_read_ptr;                 // pointer to the heap
+      sc_signal<data_t> * r_read_data;                // data (one cache line)
+      sc_signal<size_t>   r_read_way;                 // associative way (in cache)
+      sc_signal<size_t>   r_read_trt_index;           // Transaction Table index
+      sc_signal<size_t>   r_read_next_ptr;            // Next entry to point to
+      sc_signal<bool>     r_read_last_free;           // Last free entry
+      sc_signal<addr_t>   r_read_ll_key;              // LL key from llsc_global_table
+
+      // Buffer between READ fsm and IXR_CMD fsm 
+      sc_signal<bool>     r_read_to_ixr_cmd_req;      // valid request
+      sc_signal<size_t>   r_read_to_ixr_cmd_index;    // TRT index
 
       // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
-      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
-      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
-      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
-      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
-      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
-      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
-      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
-      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
+      sc_signal<bool>     r_read_to_tgt_rsp_req;      // valid request
+      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;    // Transaction srcid
+      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;    // Transaction trdid
+      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;    // Transaction pktid
+      sc_signal<data_t> * r_read_to_tgt_rsp_data;     // data (one cache line)
+      sc_signal<size_t>   r_read_to_tgt_rsp_word;     // first word of the response
+      sc_signal<size_t>   r_read_to_tgt_rsp_length;   // length of the response
+      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key;   // LL key from llsc_global_table
 
       //RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
@@ -795 +800 @@
       ///////////////////////////////////////////////////////////////
 
-      sc_signal<int>      r_write_fsm;        // FSM state
-      sc_signal<addr_t>   r_write_address;    // first word address
-      sc_signal<size_t>   r_write_word_index; // first word index in line
-      sc_signal<size_t>   r_write_word_count; // number of words in line
-      sc_signal<size_t>   r_write_srcid;      // transaction srcid
-      sc_signal<size_t>   r_write_trdid;      // transaction trdid
-      sc_signal<size_t>   r_write_pktid;      // transaction pktid
-      sc_signal<data_t> * r_write_data;       // data (one cache line)
-      sc_signal<be_t>   * r_write_be;         // one byte enable per word
-      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
-      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
-      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
-      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
-      sc_signal<size_t>   r_write_copy;       // first owner of the line
-      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
-      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
-      sc_signal<size_t>   r_write_count;      // number of copies
-      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
-      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
-      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
-      sc_signal<size_t>   r_write_way;        // way of the line
-      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
-      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
-      sc_signal<bool>     r_write_sc_fail;    // sc command failed
-      sc_signal<bool>     r_write_pending_sc; // sc command pending
+      sc_signal<int>      r_write_fsm;                // FSM state
+      sc_signal<addr_t>   r_write_address;            // first word address
+      sc_signal<size_t>   r_write_word_index;         // first word index in line
+      sc_signal<size_t>   r_write_word_count;         // number of words in line
+      sc_signal<size_t>   r_write_srcid;              // transaction srcid
+      sc_signal<size_t>   r_write_trdid;              // transaction trdid
+      sc_signal<size_t>   r_write_pktid;              // transaction pktid
+      sc_signal<data_t> * r_write_data;               // data (one cache line)
+      sc_signal<be_t>   * r_write_be;                 // one byte enable per word
+      sc_signal<bool>     r_write_byte;               // (BE != 0X0) and (BE != 0xF)
+      sc_signal<bool>     r_write_is_cnt;             // is_cnt bit (in directory)
+      sc_signal<bool>     r_write_lock;               // lock bit (in directory)
+      sc_signal<tag_t>    r_write_tag;                // cache line tag (in directory)
+      sc_signal<size_t>   r_write_copy;               // first owner of the line
+      sc_signal<size_t>   r_write_copy_cache;         // first owner of the line
+      sc_signal<bool>     r_write_copy_inst;          // is this owner a ICache ?
+      sc_signal<size_t>   r_write_count;              // number of copies
+      sc_signal<size_t>   r_write_ptr;                // pointer to the heap
+      sc_signal<size_t>   r_write_next_ptr;           // next pointer to the heap
+      sc_signal<bool>     r_write_to_dec;             // need to decrement update counter
+      sc_signal<size_t>   r_write_way;                // way of the line
+      sc_signal<size_t>   r_write_trt_index;          // index in Transaction Table
+      sc_signal<size_t>   r_write_upt_index;          // index in Update Table
+      sc_signal<bool>     r_write_sc_fail;            // sc command failed
+      sc_signal<bool>     r_write_pending_sc;         // sc command pending
 
       // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
@@ -828 +833 @@
       sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
 
-      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
-      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
-      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
-      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
-      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
-      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
+      // Buffer between WRITE fsm and IXR_CMD fsm 
+      sc_signal<bool>     r_write_to_ixr_cmd_req;     // valid request
+      sc_signal<bool>     r_write_to_ixr_cmd_put;     // request type (GET/PUT)
+      sc_signal<size_t>   r_write_to_ixr_cmd_index;   // TRT index 
 
       // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
@@ -847 +850 @@
       GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
-#endif
-
       // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
       sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
@@ -878 +877 @@
       sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
 
-      // signaling completion of multi-inval to CONFIG fsm
-      sc_signal<bool>     r_multi_ack_to_config_ack; 
-
       // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
       sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
@@ -897 +893 @@
       sc_signal<addr_t>   r_cleanup_nline;         // cache line index
 
-#if L1_MULTI_CACHE
-      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
-#endif
 
       sc_signal<copy_t>   r_cleanup_copy;          // first copy
@@ -926 +919 @@
       sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
 
-      // signaling completion of broadcast-inval to CONFIG fsm
-      sc_signal<bool>     r_cleanup_to_config_ack;  
-       
       // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
       sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
@@ -950 +940 @@
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_cas_fsm;        // FSM state
-      sc_signal<data_t>   r_cas_wdata;      // write data word
-      sc_signal<data_t> * r_cas_rdata;      // read data word
-      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
-      sc_signal<size_t>   r_cas_cpt;        // size of command
-      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
-      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
-      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
-      sc_signal<size_t>   r_cas_count;      // number of copies
-      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
-      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
-      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
-      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
-      sc_signal<size_t>   r_cas_way;        // way in directory
-      sc_signal<size_t>   r_cas_set;        // set in directory
-      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
-      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
-      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
-      sc_signal<data_t> * r_cas_data;       // cache line data
+      sc_signal<int>      r_cas_fsm;              // FSM state
+      sc_signal<data_t>   r_cas_wdata;            // write data word
+      sc_signal<data_t> * r_cas_rdata;            // read data word
+      sc_signal<uint32_t> r_cas_lfsr;             // lfsr for random introducing
+      sc_signal<size_t>   r_cas_cpt;              // size of command
+      sc_signal<copy_t>   r_cas_copy;             // Srcid of the first copy
+      sc_signal<copy_t>   r_cas_copy_cache;       // Srcid of the first copy
+      sc_signal<bool>     r_cas_copy_inst;        // Type of the first copy
+      sc_signal<size_t>   r_cas_count;            // number of copies
+      sc_signal<size_t>   r_cas_ptr;              // pointer to the heap
+      sc_signal<size_t>   r_cas_next_ptr;         // next pointer to the heap
+      sc_signal<bool>     r_cas_is_cnt;           // is_cnt bit (in directory)
+      sc_signal<bool>     r_cas_dirty;            // dirty bit (in directory)
+      sc_signal<size_t>   r_cas_way;              // way in directory
+      sc_signal<size_t>   r_cas_set;              // set in directory
+      sc_signal<data_t>   r_cas_tag;              // cache line tag (in directory)
+      sc_signal<size_t>   r_cas_trt_index;        // Transaction Table index
+      sc_signal<size_t>   r_cas_upt_index;        // Update Table index
+      sc_signal<data_t> * r_cas_data;             // cache line data
 
       sc_signal<bool>     r_cas_coherent;
@@ -974 +964 @@
       // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
       sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
-      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
-      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
-      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
-      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
-
+      sc_signal<bool>     r_cas_to_ixr_cmd_put;   // request type (GET/PUT)
+      sc_signal<size_t>   r_cas_to_ixr_cmd_index; // TRT index 
 
       // Buffer between CAS fsm and TGT_RSP fsm
@@ -999 +986 @@
       GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
-#endif
-
       ////////////////////////////////////////////////////
       // Registers controlled by the IXR_RSP fsm
       ////////////////////////////////////////////////////
 
-      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
-      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
-      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
+      sc_signal<int>      r_ixr_rsp_fsm;                // FSM state
+      sc_signal<size_t>   r_ixr_rsp_trt_index;          // TRT entry index
+      sc_signal<size_t>   r_ixr_rsp_cpt;                // word counter
+
+      // Buffer between IXR_RSP fsm and CONFIG fsm  (response from the XRAM)
+      sc_signal<bool>     r_ixr_rsp_to_config_ack;      // one single bit   
 
       // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
-      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
+      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok;    // one bit per TRT entry
 
       ////////////////////////////////////////////////////
@@ -1055 +1041 @@
       GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
-#endif
-
-      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm 
       sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
-      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
-      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
-      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
+      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_index; // TRT index 
 
       //RWT
@@ -1073 +1053 @@
 
       sc_signal<int>      r_ixr_cmd_fsm;
-      sc_signal<size_t>   r_ixr_cmd_cpt;
+      sc_signal<size_t>   r_ixr_cmd_word;              // word index for a put
+      sc_signal<size_t>   r_ixr_cmd_trdid;             // TRT index value     
+      sc_signal<addr_t>   r_ixr_cmd_address;           // address to XRAM
+      sc_signal<data_t> * r_ixr_cmd_wdata;             // cache line buffer
+      sc_signal<bool>     r_ixr_cmd_get;               // transaction type (PUT/GET)
 
       ////////////////////////////////////////////////////
@@ -1149 +1133 @@
       sc_signal<data_t>    *r_cleanup_to_ixr_cmd_data;
       sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_srcid;
-      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_trdid;
+      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_index;
       sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_pktid;
       sc_signal<addr_t>    r_cleanup_to_ixr_cmd_nline;

branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h

@@ -34 +34 @@
     bool                rerror;         // error returned by xram
     data_t              ll_key;         // LL key returned by the llsc_global_table
+    bool                config;         // transaction required by CONFIG FSM
 
     /////////////////////////////////////////////////////////////////////
@@ -42 +43 @@
         valid           = false;
         rerror      = false;
+        config      = false;
     }
 
@@ -80 +82 @@
         rerror      = source.rerror;
         ll_key      = source.ll_key;
+        config      = source.config;
     }
 
@@ -87 +90 @@
     void print()
     {
+        std::cout << "------- TRT entry -------" << std::endl;
         std::cout << "valid       = " << valid        << std::endl;
         std::cout << "xram_read   = " << xram_read    << std::endl;
@@ -96 +100 @@
         std::cout << "read_length = " << read_length  << std::endl;
         std::cout << "word_index  = " << word_index   << std::endl; 
-        for(size_t i=0; i<wdata_be.size() ; i++){
-            std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
-        }
-        for(size_t i=0; i<wdata.size() ; i++){
-            std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
-        }
+        for(size_t i=0; i<wdata_be.size() ; i++)
+        {
+            std::cout << "wdata_be[" << std::dec << i << "] = " 
+                      << std::hex << wdata_be[i] << std::endl;
+        }
+        for(size_t i=0; i<wdata.size() ; i++)
+        {
+            std::cout << "wdata[" << std::dec << i << "] = " 
+                      << std::hex << wdata[i] << std::endl;
+        }
+        std::cout << "rerror      = " << rerror       << std::endl;
+        std::cout << "ll_key      = " << ll_key       << std::endl;
+        std::cout << "config      = " << config       << std::endl;
         std::cout << std::endl;
-        std::cout << "rerror      = " << rerror       << std::endl;
     }
 
@@ -114 +124 @@
         wdata_be.clear();
         wdata.clear();
-        valid=false;
-        rerror=false;
-    }
-
-    TransactionTabEntry(const TransactionTabEntry &source){
+        valid  = false;
+        rerror = false;
+        config = false;
+    }
+
+    TransactionTabEntry(const TransactionTabEntry &source)
+    {
         valid       = source.valid;
         xram_read       = source.xram_read;
@@ -132 +144 @@
         rerror      = source.rerror;
         ll_key      = source.ll_key;
+        config      = source.config;
     }
 
@@ -197 +210 @@
         delete [] tab;
     }
-
     /////////////////////////////////////////////////////////////////////
     // The size() function returns the size of the tab
@@ -205 +217 @@
         return size_tab;
     }
-
     /////////////////////////////////////////////////////////////////////
     // The init() function initializes the transaction tab entries
@@ -211 +222 @@
     void init()
     {
-        for ( size_t i=0; i<size_tab; i++) {
+        for ( size_t i=0; i<size_tab; i++) 
+        {
             tab[i].init();
         }
     }
-
     /////////////////////////////////////////////////////////////////////
     // The print() function prints a transaction tab entry
@@ -223 +234 @@
     void print(const size_t index)
     {
-        assert( (index < size_tab) 
-                && "Invalid Transaction Tab Entry");
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()");
+
         tab[index].print();
         return;
     }
-
     /////////////////////////////////////////////////////////////////////
     // The read() function returns a transaction tab entry.
@@ -236 +247 @@
     TransactionTabEntry read(const size_t index)
     {
-        assert( (index < size_tab) 
-                && "Invalid Transaction Tab Entry");
+        assert( (index < size_tab) and 
+        "MEMC ERROR: Invalid Transaction Tab Entry");
+
         return tab[index];
     }
-
     /////////////////////////////////////////////////////////////////////
     // The full() function returns the state of the transaction tab
@@ -249 +260 @@
     bool full(size_t &index)
     {
-        for(size_t i=0; i<size_tab; i++){
-            if(!tab[i].valid){
+        for(size_t i=0; i<size_tab; i++)
+        {
+            if(!tab[i].valid)
+            {
                 index=i;
                 return false;   
@@ -257 +270 @@
         return true;
     }
-
     /////////////////////////////////////////////////////////////////////
     // The hit_read() function checks if an XRAM read transaction exists 
@@ -268 +280 @@
     bool hit_read(const addr_t nline,size_t &index)
     {
-        for(size_t i=0; i<size_tab; i++){
-            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
+        for(size_t i=0; i<size_tab; i++)
+        {
+            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) 
+            {
                 index=i;
                 return true;    
@@ -276 +290 @@
         return false;
     }
-
     ///////////////////////////////////////////////////////////////////////
     // The hit_write() function looks if an XRAM write transaction exists 
@@ -286 +299 @@
     bool hit_write(const addr_t nline)
     {
-        for(size_t i=0; i<size_tab; i++){
-            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+        for(size_t i=0; i<size_tab; i++)
+        {
+            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) 
+            {
                 return true;    
             }
@@ -325 +340 @@
             const std::vector<data_t> &data) 
     {
-        assert( (index < size_tab) 
-                && "Invalid Transaction Tab Entry");
-        assert(be.size()==tab[index].wdata_be.size() 
-                && "Bad data mask in write_data_mask in TransactionTab");
-        assert(data.size()==tab[index].wdata.size() 
-                && "Bad data in write_data_mask in TransactionTab");
-
-        for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()");
+
+        assert( (be.size()==tab[index].wdata_be.size()) and
+        "MEMC ERROR: Bad be size in TRT write_data_mask()");
+
+        assert( (data.size()==tab[index].wdata.size()) and
+        "MEMC ERROR: Bad data size in TRT write_data_mask()");
+
+        for(size_t i=0; i<tab[index].wdata_be.size() ; i++) 
+        {
             tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
             data_t mask = be_to_mask(be[i]);
@@ -338 +356 @@
         }
     }
-
     /////////////////////////////////////////////////////////////////////
     // The set() function registers a transaction (read or write)
@@ -355 +372 @@
     // - data_be : the mask of the data to write (in case of write)
     // - ll_key  : the ll key (if any) returned by the llsc_global_table
+    // - config  : transaction required by config FSM
     /////////////////////////////////////////////////////////////////////
     void set(const size_t index,
@@ -367 +385 @@
             const std::vector<be_t> &data_be,
             const std::vector<data_t> &data, 
-            const data_t ll_key = 0) 
-    {
-        assert( (index < size_tab) 
-                && "The selected entry is out of range in set() Transaction Tab");
-        assert(data_be.size()==tab[index].wdata_be.size() 
-                && "Bad data_be argument in set() TransactionTab");
-        assert(data.size()==tab[index].wdata.size() 
-                && "Bad data argument in set() TransactionTab");
+            const data_t ll_key = 0,
+            const bool config = false) 
+    {
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT set()");
+
+        assert( (data_be.size()==tab[index].wdata_be.size()) and 
+        "MEMC ERROR: Bad data_be argument in TRT set()");
+
+        assert( (data.size()==tab[index].wdata.size()) and 
+        "MEMC ERROR: Bad data argument in TRT set()");
 
         tab[index].valid                = true;
@@ -386 +407 @@
         tab[index].word_index       = word_index;
         tab[index].ll_key           = ll_key;
+        tab[index].config           = config;
         for(size_t i=0; i<tab[index].wdata.size(); i++) 
         {
@@ -398 +420 @@
     // The BE field in TRT is taken into account.
     // Arguments :
-    // - index : the index of the transaction in the transaction tab
-    // - word_index : the index of the data in the line
-    // - data : a 64 bits value
-    // - error : invalid data
+    // - index : index of the entry in TRT
+    // - word  : index of the 32 bits word in the line
+    // - data  : 64 bits value (first data right)
     /////////////////////////////////////////////////////////////////////
     void write_rsp(const size_t      index,
                    const size_t      word,
-                   const wide_data_t data,
-                   const bool        rerror)
+                   const wide_data_t data)
     {
         data_t  value;
         data_t  mask;
 
-        if ( index >= size_tab )
-        { 
-            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
-                      <<  " TRT entry  out of range in write_rsp()" << std::endl;
-            exit(0);
-        }
-        if ( word > tab[index].wdata_be.size() ) 
-        { 
-            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
-                      <<  " Bad word_index in write_rsp() in TRT" << std::endl;
-            exit(0);
-        }
-        if ( not tab[index].valid )
-        { 
-            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
-                      <<  " TRT Entry invalid in write_rsp()" << std::endl;
-            exit(0);
-        }
-        if ( not tab[index].xram_read )
-        { 
-            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
-                      <<  " TRT entry is not an XRAM GET in write_rsp()" << std::endl;
-            exit(0);
-        }
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT write_rsp()");
+
+        assert( (word < tab[index].wdata_be.size()) and 
+        "MEMC ERROR: Bad word index in TRT write_rsp()");
+
+        assert( (tab[index].valid) and
+        "MEMC ERROR: TRT entry not valid in TRT write_rsp()");
+
+        assert( (tab[index].xram_read ) and
+        "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()");
 
         // first 32 bits word
@@ -445 +452 @@
         mask  = be_to_mask(tab[index].wdata_be[word+1]);
         tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask);
-
-        // error update
-        tab[index].rerror |= rerror;
-    }
-
+    }
     /////////////////////////////////////////////////////////////////////
     // The erase() function erases an entry in the transaction tab.
@@ -457 +460 @@
     void erase(const size_t index)
     {
-        assert( (index < size_tab) 
-                && "The selected entry is out of range in erase() Transaction Tab");
+        assert( (index < size_tab) and 
+        "MEMC ERROR: The selected entry is out of range in TRT erase()");
+
         tab[index].valid        = false;
         tab[index].rerror   = false;
+    }
+    /////////////////////////////////////////////////////////////////////
+    // The is_config() function returns the config flag value.
+    // Arguments :
+    // - index : the index of the entry in the transaction tab
+    /////////////////////////////////////////////////////////////////////
+    bool is_config(const size_t index)
+    {
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT is_config()");
+
+        return tab[index].config;
     }
 }; // end class TransactionTab