Changeset 477 for branches/RWT/modules/vci_mem_cache/caba/source/include
- Timestamp:
- Jul 26, 2013, 5:03:12 PM (11 years ago)
- Location:
- branches/RWT
- Files:
-
- 2 added
- 3 edited
- 1 copied
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. (added)
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modules (added)
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modules/vci_mem_cache (copied) (copied from trunk/modules/vci_mem_cache)
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modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (modified) (6 diffs)
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modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (modified) (17 diffs)
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modules/vci_mem_cache/caba/source/include/xram_transaction.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
r449 r477 96 96 97 97 bool valid; // entry valid 98 bool cache_coherent; // WB or WT policy 98 99 bool is_cnt; // directory entry is in counter mode 99 100 bool dirty; // entry dirty … … 107 108 { 108 109 valid = false; 110 cache_coherent= false; 109 111 is_cnt = false; 110 112 dirty = false; … … 123 125 { 124 126 valid = source.valid; 127 cache_coherent= source.cache_coherent; 125 128 is_cnt = source.is_cnt; 126 129 dirty = source.dirty; … … 138 141 { 139 142 valid = false; 143 cache_coherent = false; 140 144 is_cnt = false; 141 145 dirty = false; … … 150 154 { 151 155 valid = source.valid; 156 cache_coherent = source.cache_coherent; 152 157 is_cnt = source.is_cnt; 153 158 dirty = source.dirty; … … 165 170 { 166 171 std::cout << "Valid = " << valid 172 << " ; COHERENCE = " << cache_coherent 167 173 << " ; IS COUNT = " << is_cnt 168 174 << " ; Dirty = " << dirty -
branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r468 r477 131 131 CC_SEND_XRAM_RSP_INVAL_HEADER, 132 132 CC_SEND_XRAM_RSP_INVAL_NLINE, 133 CC_SEND_READ_NCC_INVAL_HEADER, 134 CC_SEND_READ_NCC_INVAL_NLINE, 135 CC_SEND_WRITE_NCC_INVAL_HEADER, 136 CC_SEND_WRITE_NCC_INVAL_NLINE, 133 137 CC_SEND_WRITE_BRDCAST_HEADER, 134 138 CC_SEND_WRITE_BRDCAST_NLINE, … … 178 182 READ_DIR_REQ, 179 183 READ_DIR_LOCK, 184 READ_IVT_LOCK, 185 READ_WAIT, 180 186 READ_DIR_HIT, 181 187 READ_HEAP_REQ, … … 197 203 WRITE_DIR_REQ, 198 204 WRITE_DIR_LOCK, 205 WRITE_IVT_LOCK_HIT_WB, 199 206 WRITE_DIR_READ, 200 207 WRITE_DIR_HIT, … … 205 212 WRITE_UPT_DEC, 206 213 WRITE_RSP, 214 WRITE_MISS_IVT_LOCK, 207 215 WRITE_MISS_TRT_LOCK, 208 216 WRITE_MISS_TRT_DATA, … … 253 261 IXR_CMD_CAS_IDLE, 254 262 IXR_CMD_XRAM_IDLE, 263 IXR_CMD_CLEANUP_IDLE, 255 264 IXR_CMD_READ, 256 265 IXR_CMD_WRITE, 257 266 IXR_CMD_CAS, 258 IXR_CMD_XRAM 267 IXR_CMD_XRAM, 268 IXR_CMD_CLEANUP_DATA 259 269 }; 260 270 … … 290 300 CLEANUP_IDLE, 291 301 CLEANUP_GET_NLINE, 302 CLEANUP_GET_DATA, 292 303 CLEANUP_DIR_REQ, 293 304 CLEANUP_DIR_LOCK, 294 305 CLEANUP_DIR_WRITE, 306 CLEANUP_IVT_LOCK_DATA, 307 CLEANUP_IVT_CLEAR_DATA, 308 CLEANUP_READ_RSP, 295 309 CLEANUP_HEAP_REQ, 296 310 CLEANUP_HEAP_LOCK, … … 302 316 CLEANUP_IVT_CLEAR, 303 317 CLEANUP_WRITE_RSP, 318 CLEANUP_IXR_REQ, 319 CLEANUP_WAIT, 304 320 CLEANUP_CONFIG_ACK, 305 321 CLEANUP_SEND_CLACK … … 325 341 ALLOC_TRT_CAS, 326 342 ALLOC_TRT_XRAM_RSP, 327 ALLOC_TRT_IXR_RSP 343 ALLOC_TRT_IXR_RSP, 344 ALLOC_TRT_CLEANUP 328 345 }; 329 346 … … 340 357 { 341 358 ALLOC_IVT_WRITE, 359 ALLOC_IVT_READ, 342 360 ALLOC_IVT_XRAM_RSP, 343 361 ALLOC_IVT_CLEANUP, … … 434 452 uint32_t m_cpt_sc; // Number of SC transactions 435 453 uint32_t m_cpt_cas; // Number of CAS transactions 454 455 uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK 456 uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK 457 uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK 458 uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK 459 uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK 460 uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK 461 uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK 462 uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK 463 uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK 464 uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK 465 466 uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused 467 uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used 468 uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used 469 uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used 470 uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used 471 uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used 472 473 uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK 474 uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK 475 uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK 476 uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK 477 uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK 478 479 uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK 480 uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK 481 uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK 482 uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK 483 uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK 484 485 uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used 486 uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used 487 uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used 488 uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used 489 uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used 490 491 uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused 492 493 uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK 494 uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK 495 uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK 496 uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait UPT LOCK 497 uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK 498 499 uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK 500 uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK 501 uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK 502 uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK 503 uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK 504 505 uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used 506 uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used 507 uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used 508 uint32_t m_cpt_cleanup_fsm_ivt_used; // NB cycles UPT LOCK used 509 uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used 510 511 uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused 512 uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused 513 514 uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK 515 uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK 516 uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK 517 uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK 518 uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK 519 520 uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK 521 uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK 522 uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK 523 uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK 524 uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK 525 526 uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used 527 uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used 528 uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used 529 uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used 530 uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used 531 532 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 533 534 //RWT 535 uint32_t m_cpt_cleanup_data; 536 uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ 537 uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE 538 uint32_t m_cpt_ncc_to_cc; // NB change from NCC to CC 539 540 uint32_t m_cpt_read_data_unc; 541 uint32_t m_cpt_read_data_miss_CC; 542 uint32_t m_cpt_read_ins_unc; 543 uint32_t m_cpt_read_ins_miss; 544 uint32_t m_cpt_read_ll_CC; 545 uint32_t m_cpt_read_data_miss_NCC; 546 uint32_t m_cpt_read_ll_NCC; 547 uint32_t m_cpt_read_WTF; 436 548 437 549 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs … … 481 593 ~VciMemCache(); 482 594 595 void clear_stats(); 483 596 void print_stats(); 484 597 void print_trace(); … … 657 770 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table 658 771 772 //RWT: Buffer between READ fsm and CC_SEND fsm (send inval) 773 sc_signal<bool> r_read_to_cc_send_req; 774 sc_signal<size_t> r_read_to_cc_send_dest; 775 sc_signal<addr_t> r_read_to_cc_send_nline; 776 sc_signal<bool> r_read_to_cc_send_inst; 777 778 //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) 779 sc_signal<bool> r_read_to_cleanup_req; // valid request 780 sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index 781 sc_signal<size_t> r_read_to_cleanup_srcid; 782 sc_signal<size_t> r_read_to_cleanup_length; 783 sc_signal<size_t> r_read_to_cleanup_first_word; 784 sc_signal<bool> r_read_to_cleanup_cached_read; 785 sc_signal<bool> r_read_to_cleanup_is_ll; 786 sc_signal<addr_t> r_read_to_cleanup_addr; 787 sc_signal<addr_t> r_read_to_cleanup_ll_key; 788 789 //RWT: 790 sc_signal<bool> r_read_coherent; // State of the cache slot after transaction 791 sc_signal<bool> r_read_ll_done; 792 659 793 /////////////////////////////////////////////////////////////// 660 794 // Registers controlled by the WRITE fsm … … 721 855 sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table 722 856 857 // RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state) 858 sc_signal<bool> r_write_to_cleanup_req; // valid request 859 sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index 860 861 // RWT 862 sc_signal<bool> r_write_coherent; // cache slot state after transaction 863 864 //Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT) 865 sc_signal<bool> r_write_to_cc_send_req; 866 sc_signal<size_t> r_write_to_cc_send_dest; 867 868 723 869 ///////////////////////////////////////////////////////// 724 870 // Registers controlled by MULTI_ACK fsm … … 788 934 sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid 789 935 sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid 936 sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key; 937 938 //RWT 939 sc_signal<size_t> r_cleanup_read_srcid; 940 sc_signal<size_t> r_cleanup_read_trdid; 941 sc_signal<size_t> r_cleanup_read_pktid; 942 sc_signal<bool> r_cleanup_read_need_rsp; 943 sc_signal<bool> r_cleanup_to_tgt_rsp_type; 944 sc_signal<data_t> * r_cleanup_to_tgt_rsp_data; 945 sc_signal<size_t> r_cleanup_to_tgt_rsp_length; 946 sc_signal<size_t> r_cleanup_to_tgt_rsp_first_word; 790 947 791 948 /////////////////////////////////////////////////////// … … 813 970 sc_signal<data_t> * r_cas_data; // cache line data 814 971 972 sc_signal<bool> r_cas_coherent; 973 815 974 // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) 816 975 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request … … 906 1065 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table 907 1066 1067 //RWT 1068 sc_signal<bool> r_xram_rsp_victim_coherent; // victim's cache slot state 1069 sc_signal<bool> r_xram_rsp_coherent; // coherence of the read 908 1070 //////////////////////////////////////////////////// 909 1071 // Registers controlled by the IXR_CMD fsm … … 966 1128 sc_signal<int> r_alloc_heap_fsm; 967 1129 sc_signal<unsigned> r_alloc_heap_reset_cpt; 1130 1131 1132 //////////////////////////////////////////////////// 1133 // REGISTERS FOR ODCCP 1134 //////////////////////////////////////////////////// 1135 1136 sc_signal<uint32_t> r_cleanup_data_index; 1137 sc_signal<uint32_t> r_cleanup_trdid; 1138 sc_signal<uint32_t> r_cleanup_pktid; 1139 sc_signal<bool> r_cleanup_coherent; 1140 sc_signal<data_t> *r_cleanup_data; 1141 sc_signal<data_t> *r_cleanup_old_data; 1142 sc_signal<bool> r_cleanup_contains_data; 1143 1144 sc_signal<bool> r_cleanup_ncc; 1145 sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty; 1146 sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending; 1147 1148 sc_signal<bool> r_cleanup_to_ixr_cmd_req; 1149 sc_signal<data_t> *r_cleanup_to_ixr_cmd_data; 1150 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid; 1151 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_trdid; 1152 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid; 1153 sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline; 968 1154 }; // end class VciMemCache 969 1155 -
branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h
r422 r477 294 294 } 295 295 296 /////////////////////////////////////////////////////////////////////// 297 // The hit_write() function looks if an XRAM write transaction exists 298 // for a given line. 299 // Arguments : 300 // - index : (return argument) the index of the hit entry, if there is 301 // - nline : the index (zy) of the requested line 302 // The function returns true if a write request has already been sent 303 /////////////////////////////////////////////////////////////////////// 304 bool hit_write(const addr_t nline, size_t* index) 305 { 306 for(size_t i=0; i<size_tab; i++){ 307 if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) { 308 *index = i; 309 return true; 310 } 311 } 312 return false; 313 } 296 314 ///////////////////////////////////////////////////////////////////// 297 315 // The write_data_mask() function writes a vector of data (a line).
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