Changeset 568 for trunk/softs/tsar_boot

Timestamp:

Oct 30, 2013, 11:19:23 AM (11 years ago)

Author:

cfuguet

Message:

Adding support for TSAR platforms using the vci_io_bridge component.

In this case (USE_IOB=1), when a block is read from the disk controller,
the buffer containing the read data must be invalidated in the Memory
Cache as the transfer is done between the disk controller and the RAM.

Location:

trunk/softs/tsar_boot

Files:

• README.txt (modified) (3 diffs)
• conf/platform_fpga_de2-115/defs_platform.h (modified) (2 diffs)
• conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h (modified) (2 diffs)
• conf/platform_vgsb_xicu_mmu/defs_platform.h (modified) (2 diffs)
• include/boot_ioc.h (modified) (1 diff)
• include/mcc.h (added)
• src/boot_ioc.c (modified) (4 diffs)

trunk/softs/tsar_boot/README.txt

@@ -15 +15 @@
              This file is mandatory. This file defines the
              NB_PROCS per cluster, the NB_CLUSTERS and the base address of
-             the TTY, IOC and XICU devices.
+             the TTY, IOC, XICU and MEMC (config) devices.
              It defines also:
+
+              -> USE_IOB
+                 This constant is used by the boot_ioc_read function to know
+                 if the buffer used to store the blocks from the
+                 block_device must be invalidated in the memory cache after
+                 the transfert has finished.
 
               -> CACHE_COHERENCE
@@ -25 +31 @@
 
               -> CACHE_LINE_SIZE
-                 This constant is mandatory if CACHE_COHERENCE=0
+                 This constant is mandatory if CACHE_COHERENCE=0 or USE_IOB=1
                  This constant defines the size in bytes of a cache line.
 
@@ -55 +61 @@
                 seg_stack_base: Base address of the stack used by processor 0
                 during the boot process. read-write data and bss will also
-                be there.
+                be there.
 
                 seg_boot_base: Base address of the code and read-only data
-                defined for this loader
+                defined for this loader
             
 Makefile    Makefile for compile the boot loader.

trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h

@@ -4 +4 @@
 #define IRQ_PER_PROC    1
 
+#define USE_IOB         0
 #define CACHE_COHERENCE 1
 #define CACHE_LINE_SIZE 64//bytes
@@ -13 +14 @@
 #define TTY_BASE        0xFC000000
 #define ICU_BASE        0xFD000000
+#define MCC_BASE        0xFFFFFFFF // not used
 
 /* Mandatory argument only for FPGA platforms */ 

trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h

@@ -4 +4 @@
 #define IRQ_PER_PROC    1
 
+#define USE_IOB         0
 #define CACHE_COHERENCE 1
 #define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word)
@@ -13 +14 @@
 #define ICU_BASE        0x30000000
 #define IOC_BASE        0x40000000
+#define MCC_BASE        0xFFFFFFFF // not used

trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h

@@ -4 +4 @@
 #define IRQ_PER_PROC    1
 
+#define USE_IOB         0
 #define CACHE_COHERENCE 0
 #define CACHE_LINE_SIZE 16//bytes
@@ -13 +14 @@
 #define IOC_BASE        0x00F10000
 #define TTY_BASE        0x00F20000
+#define MCC_BASE        0xFFFFFFFF //not used

trunk/softs/tsar_boot/include/boot_ioc.h

@@ -7 +7 @@
 #else
 #include <block_device.h>
+#include <mcc.h>
 #endif
 

trunk/softs/tsar_boot/src/boot_ioc.c

@@ -145 +145 @@
 // SOCLIB version of the boot_ioc_read function
 
+void boot_buf_invalidate (
+        const void * buffer,
+        unsigned int line_size,
+        unsigned int size);
+
+void boot_mcc_invalidate (
+        const void * buffer,
+        unsigned int size);
+
 int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count)
 {
@@ -179 +188 @@
     _boot_ioc_completed();
 
-#if (CACHE_COHERENCE == 0)
-    boot_dbuf_invalidate(buffer, CACHE_LINE_SIZE, count * 512);
+#if (CACHE_COHERENCE == 0) || (USE_IOB == 1)
+    boot_buf_invalidate(buffer, CACHE_LINE_SIZE, count * 512);
+#endif
+
+#if (USE_IOB == 1)
+    boot_mcc_invalidate(buffer, count * 512);
 #endif
 
@@ -252 +265 @@
  * buffer (identified by an address and a size).
  */
-#if (CACHE_COHERENCE == 0)
-void boot_dbuf_invalidate (
+#if (CACHE_COHERENCE == 0) || (USE_IOB == 1)
+void boot_buf_invalidate (
         const void * buffer,
         unsigned int line_size,
@@ -271 +284 @@
 #endif
 
+/**
+ * boot_mcc_inval()
+ *
+ * Invalidate all data cache lines corresponding to a memory
+ * buffer (identified by an address and a size).
+ */
+#if (USE_IOB == 1)
+void boot_mcc_invalidate (
+        const void * buffer,
+        unsigned int size)
+{
+    unsigned int * mcc_address = (unsigned int *)MCC_BASE;
+
+    // get the hard lock assuring exclusive access to MEMC
+    while (ioread32(&mcc_address[MCC_LOCK]));
+
+    // write invalidate paremeters on the memory cache
+    // this preloader use only the cluster 0 and then the HI bits are not used
+    
+    iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer);
+    iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0);
+    iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size);
+    iowrite32(&mcc_address[MCC_CMD]    , (unsigned int) MCC_CMD_INVAL);
+
+    // release the lock protecting MEMC
+    iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0);
+}
+#endif
+
 /*
  * vim: tabstop=4 : shiftwidth=4 : expandtab