Changeset 823 for branches/RWT

Timestamp:

Sep 30, 2014, 3:32:13 PM (10 years ago)

Author:

devigne

Message:

RWT Commit : Cosmetic

Location:

branches/RWT

Files:

• lib/generic_cache_tsar/include/generic_cache.h (modified) (32 diffs)
• modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (modified) (4 diffs)
• modules/vci_mem_cache/caba/source/include/update_tab.h (modified) (2 diffs)
• modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (modified) (19 diffs)
• modules/vci_mem_cache/caba/source/include/xram_transaction.h (modified) (18 diffs)
• modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (137 diffs)

branches/RWT/lib/generic_cache_tsar/include/generic_cache.h

@@ -89 +89 @@
     typedef uint32_t be_t;
 
-    data_t           *r_data ;
-    addr_t           *r_tag ;
-    int              *r_state;
-    bool             *r_lru ;
-
-    size_t           m_ways;
-    size_t           m_sets;
-    size_t           m_words;
+    data_t *r_data ;
+    addr_t *r_tag ;
+    int    *r_state;
+    bool   *r_lru ;
+
+    size_t m_ways;
+    size_t m_sets;
+    size_t m_words;
 
     const soclib::common::AddressMaskingTable<addr_t> m_x ;
@@ -105 +105 @@
     inline data_t &cache_data(size_t way, size_t set, size_t word)
     {
-        return r_data[(way*m_sets*m_words)+(set*m_words)+word];
+        return r_data[(way * m_sets * m_words) + (set * m_words) + word];
     }
 
@@ -111 +111 @@
     inline addr_t &cache_tag(size_t way, size_t set)
     {
-        return r_tag[(way*m_sets)+set];
+        return r_tag[(way * m_sets) + set];
     }
 
@@ -117 +117 @@
     inline bool &cache_lru(size_t way, size_t set)
     {
-        return r_lru[(way*m_sets)+set];
+        return r_lru[(way * m_sets) + set];
     }
 
@@ -123 +123 @@
     inline int &cache_state(size_t way, size_t set)
     {
-        return r_state[(way*m_sets)+set];
+        return r_state[(way * m_sets) + set];
     }
 
@@ -149 +149 @@
     {
         data_t mask = 0;
-        if ( (be & 0x1) == 0x1 ) mask = mask | 0x000000FF;
-        if ( (be & 0x2) == 0x2 ) mask = mask | 0x0000FF00;
-        if ( (be & 0x4) == 0x4 ) mask = mask | 0x00FF0000;
-        if ( (be & 0x8) == 0x8 ) mask = mask | 0xFF000000;
+        if ((be & 0x1) == 0x1) mask = mask | 0x000000FF;
+        if ((be & 0x2) == 0x2) mask = mask | 0x0000FF00;
+        if ((be & 0x4) == 0x4) mask = mask | 0x00FF0000;
+        if ((be & 0x8) == 0x8) mask = mask | 0xFF000000;
         return mask;
     }
@@ -160 +160 @@
     //////////////////////////////////////////
     GenericCache(const std::string &name,
-                    size_t            nways,
-                    size_t            nsets,
-                    size_t            nwords)
+                 size_t            nways,
+                 size_t            nsets,
+                 size_t            nwords)
         : m_ways(nways),
           m_sets(nsets),
@@ -169 +169 @@
 #define l2 soclib::common::uint32_log2
 
-          m_x( l2(nwords), l2(sizeof(data_t))),
-          m_y( l2(nsets), l2(nwords) + l2(sizeof(data_t))),
-          m_z( 8*sizeof(addr_t) - l2(nsets) - l2(nwords) - l2(sizeof(data_t)),
-               l2(nsets) + l2(nwords) + l2(sizeof(data_t)))
+          m_x(l2(nwords), l2(sizeof(data_t))),
+          m_y(l2(nsets), l2(nwords) + l2(sizeof(data_t))),
+          m_z(8*sizeof(addr_t) - l2(nsets) - l2(nwords) - l2(sizeof(data_t)),
+              l2(nsets) + l2(nwords) + l2(sizeof(data_t)))
 #undef l2
     {
@@ -196 +196 @@
 #endif
 
-        r_data  = new data_t[nways*nsets*nwords];
-        r_tag   = new addr_t[nways*nsets];
-        r_state = new int[nways*nsets];
-        r_lru   = new bool[nways*nsets];
+        r_data  = new data_t[nways * nsets * nwords];
+        r_tag   = new addr_t[nways * nsets];
+        r_state = new int[nways * nsets];
+        r_lru   = new bool[nways * nsets];
     }
 
@@ -214 +214 @@
     inline void reset()
     {
-        std::memset(r_data, 0, sizeof(*r_data)*m_ways*m_sets*m_words);
-        std::memset(r_tag, 0, sizeof(*r_tag)*m_ways*m_sets);
-        std::memset(r_state, CACHE_SLOT_STATE_EMPTY, sizeof(*r_state)*m_ways*m_sets);
-        std::memset(r_lru, 0, sizeof(*r_lru)*m_ways*m_sets);
+        std::memset(r_data, 0, sizeof(*r_data) * m_ways * m_sets * m_words);
+        std::memset(r_tag, 0, sizeof(*r_tag) * m_ways * m_sets);
+        std::memset(r_state, CACHE_SLOT_STATE_EMPTY, sizeof(*r_state) * m_ways * m_sets);
+        std::memset(r_lru, 0, sizeof(*r_lru) * m_ways * m_sets);
     }
 
@@ -239 +239 @@
         for (size_t way = 0; way < m_ways; way++)
         {
-            if ((tag == cache_tag(way, set))
-                   && ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)) )
+            if ((tag == cache_tag(way, set)) and
+                   ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or
+                    (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)))
             {
                 *dt = cache_data(way, set, word);
@@ -269 +270 @@
         {
             if ((tag == cache_tag(way, set)) and
-                 ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)))
+                 ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or
+                  (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)))
             {
                 *selway  = way;
@@ -314 +316 @@
             if (tag == cache_tag(way, set))  // matching tag
             {
-
                 if (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)
                 {
@@ -362 +363 @@
         for (size_t way = 0; way < m_ways; way++)
         {
-            if ((tag == cache_tag(way, set))
-                   && ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC) ))
+            if ((tag == cache_tag(way, set)) and
+                   ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or
+                    (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)))
             {
                 *selway  = way;
                 *selset  = set;
                 *selword = word;
-                *dt = cache_data(way, set, word);
+                *dt      = cache_data(way, set, word);
                 return true;
             }
@@ -384 +386 @@
     // This function is used by the cc_vcache to get a 64 bits page table entry.
     /////////////////////////////////////////////////////////////////////////////
-    inline bool read( addr_t  ad,
-                      data_t* dt,
-                      data_t* dt_next,
-                      size_t* selway,
-                      size_t* selset,
-                      size_t* selword)
+    inline bool read(addr_t  ad,
+                     data_t* dt,
+                     data_t* dt_next,
+                     size_t* selway,
+                     size_t* selset,
+                     size_t* selword)
     {
         const addr_t tag  = m_z[ad];
@@ -397 +399 @@
         for (size_t way = 0; way < m_ways; way++)
         {
-            if ((tag == cache_tag(way, set))
-                   &&( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)))
+            if ((tag == cache_tag(way, set)) and
+                   ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)))
             {
                 *dt = cache_data(way, set, word);
@@ -507 +509 @@
         for (size_t way = 0; way < m_ways; way++)
         {
-            if ((tag == cache_tag(way, set))
-                   && ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)or(cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)))
+            if ((tag == cache_tag(way, set)) and
+                   ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or
+                    (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)))
             {
                 *selway  = way;
@@ -614 +617 @@
                       addr_t* nline)
     {
-        if ((cache_state(way,set) == CACHE_SLOT_STATE_VALID_CC) or  (cache_state(way,set) == CACHE_SLOT_STATE_VALID_NCC))
+        if ((cache_state(way,set) == CACHE_SLOT_STATE_VALID_CC) or
+                (cache_state(way,set) == CACHE_SLOT_STATE_VALID_NCC))
         {
             cache_state(way,set) = CACHE_SLOT_STATE_EMPTY;
-            *nline = (data_t)cache_tag(way,set)* m_sets + set;
+            *nline = (data_t) cache_tag(way, set) * m_sets + set;
             return true;
         }
@@ -643 +647 @@
 
         // Search first empty slot
-        for (size_t _way = 0 ; _way < m_ways && !found ; _way++)
-        {
-            if ((cache_state(_way, *set) != CACHE_SLOT_STATE_VALID_CC) and (cache_state(_way, *set) != CACHE_SLOT_STATE_VALID_NCC ))  // empty
+        for (size_t _way = 0; _way < m_ways && !found; _way++)
+        {
+            // empty
+            if ((cache_state(_way, *set) != CACHE_SLOT_STATE_VALID_CC) and
+                    (cache_state(_way, *set) != CACHE_SLOT_STATE_VALID_NCC))
             {
                 found   = true;
@@ -656 +662 @@
         if (!found)
         {
-            for (size_t _way = 0 ; _way < m_ways && !found ; _way++)
+            for (size_t _way = 0; _way < m_ways && !found; _way++)
             {
                 if (not cache_lru(_way, *set))
@@ -668 +674 @@
 
         assert(found && "all ways can't be new at the same time");
-        *victim = (addr_t) ((cache_tag(*way,*set) * m_sets) + *set);
+        *victim = (addr_t) ((cache_tag(*way, *set) * m_sets) + *set);
         return cleanup;
     }
@@ -693 +699 @@
 
         // Search first empty slot
-        for (size_t _way = 0 ; _way < m_ways && !(*found) ; _way++)
+        for (size_t _way = 0; _way < m_ways && !(*found); _way++)
         {
             if (cache_state(_way, _set) == CACHE_SLOT_STATE_EMPTY)
@@ -706 +712 @@
 
         // Search first not zombi old slot
-        for (size_t _way = 0 ; _way < m_ways && !(*found) ; _way++)
+        for (size_t _way = 0; _way < m_ways && !(*found); _way++)
         {
             if (not cache_lru(_way, _set) and
-                 (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI))
+               (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI))
             {
                 *found   = true;
@@ -720 +726 @@
         }
         // Search first not zombi slot
-        for (size_t _way = 0 ; _way < m_ways && !(*found) ; _way++)
+        for (size_t _way = 0; _way < m_ways && !(*found); _way++)
         {
             if (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI)
@@ -746 +752 @@
                                   size_t set)
     {
-        addr_t  tag     = m_z[ad];
-
-        cache_tag(way, set)   = tag;
+        addr_t tag = m_z[ad];
+
+        cache_tag(way, set) = tag;
         cache_state(way, set) = CACHE_SLOT_STATE_VALID_CC;
         cache_set_lru(way, set);
@@ -764 +770 @@
         addr_t tag = m_z[ad];
 
-        assert( ( (state == CACHE_SLOT_STATE_VALID_CC) or
-                  (state == CACHE_SLOT_STATE_VALID_NCC) or
-                  (state == CACHE_SLOT_STATE_ZOMBI) or
-                  (state == CACHE_SLOT_STATE_EMPTY) ) and
+        assert(((state == CACHE_SLOT_STATE_VALID_CC) or
+                (state == CACHE_SLOT_STATE_VALID_NCC) or
+                (state == CACHE_SLOT_STATE_ZOMBI) or
+                (state == CACHE_SLOT_STATE_EMPTY)) and
         "illegal slot state argument in Generic Cache write_dir()");
 
-        assert( (way < m_ways) and
+        assert((way < m_ways) and
         "too large way index argument in Generic Cache write_dir()");
 
-        assert( (set < m_sets) and
+        assert((set < m_sets) and
         "too large set index argument in Generic Cache write_dir()");
 
@@ -779 +785 @@
         cache_state(way, set) = state;
 
-        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) cache_set_lru(way, set);
+        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))
+            cache_set_lru(way, set);
     }
 
@@ -791 +798 @@
                           int    state)
     {
-        assert( ( (state == CACHE_SLOT_STATE_VALID_CC) or
-                  (state == CACHE_SLOT_STATE_VALID_NCC) or
-                  (state == CACHE_SLOT_STATE_ZOMBI) or
-                  (state == CACHE_SLOT_STATE_EMPTY) ) and
+        assert(((state == CACHE_SLOT_STATE_VALID_CC) or
+                (state == CACHE_SLOT_STATE_VALID_NCC) or
+                (state == CACHE_SLOT_STATE_ZOMBI) or
+                (state == CACHE_SLOT_STATE_EMPTY) ) and
         "illegal slot state argument in Generic Cache write_dir()");
 
-        assert( (way < m_ways) and
+        assert((way < m_ways) and
         "too large way index argument in Generic Cache write_dir()");
 
-        assert( (set < m_sets) and
+        assert((set < m_sets) and
         "too large set index argument in Generic Cache write_dir()");
 
         cache_state(way, set) = state;
 
-        if ( (state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC) ) cache_set_lru(way, set);
+        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))
+            cache_set_lru(way, set);
     }
 
@@ -820 +828 @@
         addr_t tag = m_z[ad];
 
-        cache_tag(way, set)   = tag;
+        cache_tag(way, set) = tag;
         cache_state(way, set) = CACHE_SLOT_STATE_VALID_CC;
         cache_set_lru(way, set);
-        for (size_t word = 0 ; word < m_words ; word++)
-        {
-            cache_data(way, set, word) = buf[word] ;
+        for (size_t word = 0; word < m_words; word++)
+        {
+            cache_data(way, set, word) = buf[word];
         }
     }
@@ -832 +840 @@
     void fileTrace(FILE* file)
     {
-        for (size_t nway = 0 ; nway < m_ways ; nway++)
-        {
-            for (size_t nset = 0 ; nset < m_sets ; nset++)
-            {
-                fprintf(file, "%d / ", (int)cache_state(nway, nset));
-                fprintf(file, "way %d / ", (int)nway);
-                fprintf(file, "set %d / ", (int)nset);
+        for (size_t nway = 0; nway < m_ways; nway++)
+        {
+            for (size_t nset = 0; nset < m_sets; nset++)
+            {
+                fprintf(file, "%d / ", (int) cache_state(nway, nset));
+                fprintf(file, "way %d / ", (int) nway);
+                fprintf(file, "set %d / ", (int) nset);
                 fprintf(file, "@ = %08zX / ",
                         ((cache_tag(nway, nset) * m_sets + nset) * m_words * 4));
-                for (size_t nword = m_words ; nword > 0 ; nword--)
+                for (size_t nword = m_words; nword > 0; nword--)
                 {
                     unsigned int data = cache_data(nway, nset, nword - 1);
@@ -854 +862 @@
     inline void printTrace()
     {
-        for (size_t way = 0; way < m_ways ; way++)
-        {
-            for (size_t set = 0 ; set < m_sets ; set++)
-            {
-                addr_t addr = (((addr_t)cache_tag(way,set))*m_words*m_sets+m_words*set)*4;
+        for (size_t way = 0; way < m_ways; way++)
+        {
+            for (size_t set = 0; set < m_sets; set++)
+            {
+                addr_t addr = (((addr_t) cache_tag(way, set)) * m_words * m_sets + m_words * set) * 4;
                 std::cout << std::dec << cache_state(way, set)
                           << " | way " << way
@@ -864 +872 @@
                           << std::hex << " | @ " << addr;
 
-                for (size_t word = 0 ; word < m_words ; word++)
-                {
-                    std::cout << " | " << cache_data(way,set,word) ;
+                for (size_t word = 0; word < m_words; word++)
+                {
+                    std::cout << " | " << cache_data(way, set, word) ;
                 }
                 std::cout << std::dec << std::endl ;

branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h

@@ -18 +18 @@
   class LruEntry {
 
-    public:
-
-      bool recent;
-
+      public:
+
+          bool recent;
+
+          void init()
+          {
+              recent=false;
+          }
+
+  }; // end class LruEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    An Owner
+  ////////////////////////////////////////////////////////////////////////
+  class Owner{
+
+      public:
+
+          // Fields
+          bool   inst;  // Is the owner an ICache ?
+          size_t srcid; // The SRCID of the owner
+
+          ////////////////////////
+          // Constructors
+          ////////////////////////
+          Owner(bool   i_inst,
+                size_t i_srcid)
+          {
+              inst  = i_inst;
+              srcid = i_srcid;
+          }
+
+          Owner(const Owner &a)
+          {
+              inst  = a.inst;
+              srcid = a.srcid;
+          }
+
+          Owner()
+          {
+              inst  = false;
+              srcid = 0;
+          }
+          // end constructors
+
+  }; // end class Owner
+
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A directory entry
+  ////////////////////////////////////////////////////////////////////////
+  class DirectoryEntry {
+
+      typedef uint32_t tag_t;
+
+      public:
+
+      bool   valid;          // entry valid
+      bool   cache_coherent; // WB or WT policy
+      bool   is_cnt;         // directory entry is in counter mode
+      bool   dirty;          // entry dirty
+      bool   lock;           // entry locked
+      tag_t  tag;            // tag of the entry
+      size_t count;          // number of copies
+      Owner  owner;          // an owner of the line
+      size_t ptr;            // pointer to the next owner
+
+      DirectoryEntry()
+      {
+          valid          = false;
+          cache_coherent = false;
+          is_cnt         = false;
+          dirty          = false;
+          lock           = false;
+          tag            = 0;
+          count          = 0;
+          owner.inst     = 0;
+          owner.srcid    = 0;
+          ptr            = 0;
+      }
+
+      DirectoryEntry(const DirectoryEntry &source)
+      {
+          valid          = source.valid;
+          cache_coherent = source.cache_coherent;
+          is_cnt         = source.is_cnt;
+          dirty          = source.dirty;
+          lock           = source.lock;
+          tag            = source.tag;
+          count          = source.count;
+          owner          = source.owner;
+          ptr            = source.ptr;
+      }
+
+      /////////////////////////////////////////////////////////////////////
+      // The init() function initializes the entry
+      /////////////////////////////////////////////////////////////////////
       void init()
       {
-        recent=false;
+          valid          = false;
+          cache_coherent = false;
+          is_cnt         = false;
+          dirty          = false;
+          lock           = false;
+          count          = 0;
       }
 
-  }; // end class LruEntry
-
-  ////////////////////////////////////////////////////////////////////////
-  //                    An Owner
-  ////////////////////////////////////////////////////////////////////////
-  class Owner{
-
-    public:
-    // Fields
-      bool      inst;       // Is the owner an ICache ?
-      size_t    srcid;      // The SRCID of the owner
-
-    ////////////////////////
-    // Constructors
-    ////////////////////////
-      Owner(bool   i_inst,
-            size_t i_srcid)
-      {
-        inst    = i_inst;
-        srcid   = i_srcid;
+      /////////////////////////////////////////////////////////////////////
+      // The copy() function copies an existing source entry to a target
+      /////////////////////////////////////////////////////////////////////
+      void copy(const DirectoryEntry &source)
+      {
+          valid          = source.valid;
+          cache_coherent = source.cache_coherent;
+          is_cnt         = source.is_cnt;
+          dirty          = source.dirty;
+          lock           = source.lock;
+          tag            = source.tag;
+          count          = source.count;
+          owner          = source.owner;
+          ptr            = source.ptr;
       }
 
-      Owner(const Owner &a)
-      {
-        inst    = a.inst;
-        srcid   = a.srcid;
+      ////////////////////////////////////////////////////////////////////
+      // The print() function prints the entry
+      ////////////////////////////////////////////////////////////////////
+      void print()
+      {
+          std::cout << "Valid = " << valid
+              << " ; COHERENCE = " << cache_coherent
+              << " ; IS COUNT = " << is_cnt
+              << " ; Dirty = " << dirty
+              << " ; Lock = " << lock
+              << " ; Tag = " << std::hex << tag << std::dec
+              << " ; Count = " << count
+              << " ; Owner = " << owner.srcid
+              << " " << owner.inst
+              << " ; Pointer = " << ptr << std::endl;
       }
 
-      Owner()
-      {
-        inst    = false;
-        srcid   = 0;
+  }; // end class DirectoryEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                       The directory
+  ////////////////////////////////////////////////////////////////////////
+  class CacheDirectory {
+
+      typedef sc_dt::sc_uint<40> addr_t;
+      typedef uint32_t data_t;
+      typedef uint32_t tag_t;
+
+      private:
+
+      // Directory constants
+      size_t   m_ways;
+      size_t   m_sets;
+      size_t   m_words;
+      size_t   m_width;
+      uint32_t lfsr;
+
+      // the directory & lru tables
+      DirectoryEntry **m_dir_tab;
+      LruEntry       **m_lru_tab;
+
+      public:
+
+      ////////////////////////
+      // Constructor
+      ////////////////////////
+      CacheDirectory(size_t ways, size_t sets, size_t words, size_t address_width)
+      {
+          m_ways  = ways;
+          m_sets  = sets;
+          m_words = words;
+          m_width = address_width;
+          lfsr    = -1;
+
+          m_dir_tab = new DirectoryEntry*[sets];
+          for (size_t i = 0; i < sets; i++) {
+              m_dir_tab[i] = new DirectoryEntry[ways];
+              for (size_t j = 0; j < ways; j++) {
+                  m_dir_tab[i][j].init();
+              }
+          }
+
+          m_lru_tab = new LruEntry*[sets];
+          for (size_t i = 0; i < sets; i++) {
+              m_lru_tab[i] = new LruEntry[ways];
+              for (size_t j = 0; j < ways; j++) {
+                  m_lru_tab[i][j].init();
+              }
+          }
+      } // end constructor
+
+      /////////////////
+      // Destructor
+      /////////////////
+      ~CacheDirectory()
+      {
+          for (size_t i = 0; i < m_sets; i++) {
+              delete [] m_dir_tab[i];
+              delete [] m_lru_tab[i];
+          }
+          delete [] m_dir_tab;
+          delete [] m_lru_tab;
+      } // end destructor
+
+      /////////////////////////////////////////////////////////////////////
+      // The read() function reads a directory entry. In case of hit, the
+      // LRU is updated.
+      // Arguments :
+      // - address : the address of the entry
+      // - way : (return argument) the way of the entry in case of hit
+      // The function returns a copy of a (valid or invalid) entry
+      /////////////////////////////////////////////////////////////////////
+      DirectoryEntry read(const addr_t &address, size_t &way)
+      {
+
+#define L2 soclib::common::uint32_log2
+          const size_t set = (size_t) (address >> (L2(m_words) + 2)) & (m_sets - 1);
+          const tag_t  tag = (tag_t) (address >> (L2(m_sets) + L2(m_words) + 2));
+#undef L2
+
+          bool hit = false;
+
+          for (size_t i = 0; i < m_ways; i++) {
+              bool equal = (m_dir_tab[set][i].tag == tag);
+              bool valid = m_dir_tab[set][i].valid;
+              hit = equal && valid;
+              if (hit) {
+                  way = i;
+                  break;
+              }
+          }
+          if (hit) {
+              m_lru_tab[set][way].recent = true;
+              return DirectoryEntry(m_dir_tab[set][way]);
+          } else {
+              return DirectoryEntry();
+          }
+      } // end read()
+
+      /////////////////////////////////////////////////////////////////////
+      // The inval function invalidate an entry defined by the set and
+      // way arguments.
+      /////////////////////////////////////////////////////////////////////
+      void inval( const size_t &way, const size_t &set )
+      {
+          m_dir_tab[set][way].init();
       }
-      // end constructors
-
-  }; // end class Owner
-
-
-  ////////////////////////////////////////////////////////////////////////
-  //                    A directory entry
-  ////////////////////////////////////////////////////////////////////////
-  class DirectoryEntry {
-
-    typedef uint32_t tag_t;
-
-    public:
-
-    bool    valid;                  // entry valid
-    bool    cache_coherent;         // WB or WT policy
-    bool    is_cnt;                 // directory entry is in counter mode
-    bool    dirty;                  // entry dirty
-    bool    lock;                   // entry locked
-    tag_t   tag;                    // tag of the entry
-    size_t  count;                  // number of copies
-    Owner   owner;                  // an owner of the line
-    size_t  ptr;                    // pointer to the next owner
-
-    DirectoryEntry()
-    {
-      valid         = false;
-      cache_coherent= false;
-      is_cnt        = false;
-      dirty         = false;
-      lock          = false;
-      tag           = 0;
-      count         = 0;
-      owner.inst    = 0;
-      owner.srcid   = 0;
-      ptr           = 0;
-    }
-
-    DirectoryEntry(const DirectoryEntry &source)
-    {
-      valid         = source.valid;
-      cache_coherent= source.cache_coherent;
-      is_cnt        = source.is_cnt;
-      dirty         = source.dirty;
-      lock          = source.lock;
-      tag           = source.tag;
-      count         = source.count;
-      owner         = source.owner;
-      ptr           = source.ptr;
-    }
-
-    /////////////////////////////////////////////////////////////////////
-    // The init() function initializes the entry
-    /////////////////////////////////////////////////////////////////////
-    void init()
-    {
-      valid     = false;
-      cache_coherent = false;
-      is_cnt    = false;
-      dirty     = false;
-      lock      = false;
-      count     = 0;
-    }
-
-    /////////////////////////////////////////////////////////////////////
-    // The copy() function copies an existing source entry to a target
-    /////////////////////////////////////////////////////////////////////
-    void copy(const DirectoryEntry &source)
-    {
-      valid     = source.valid;
-      cache_coherent = source.cache_coherent;
-      is_cnt    = source.is_cnt;
-      dirty     = source.dirty;
-      lock      = source.lock;
-      tag       = source.tag;
-      count     = source.count;
-      owner     = source.owner;
-      ptr       = source.ptr;
-    }
-
-    ////////////////////////////////////////////////////////////////////
-    // The print() function prints the entry
-    ////////////////////////////////////////////////////////////////////
-    void print()
-    {
-      std::cout << "Valid = " << valid
-                << " ; COHERENCE = " << cache_coherent
-                << " ; IS COUNT = " << is_cnt
-                << " ; Dirty = " << dirty
-                << " ; Lock = " << lock
-                << " ; Tag = " << std::hex << tag << std::dec
-                << " ; Count = " << count
-                << " ; Owner = " << owner.srcid
-                << " " << owner.inst
-                << " ; Pointer = " << ptr << std::endl;
-    }
-
-  }; // end class DirectoryEntry
-
-  ////////////////////////////////////////////////////////////////////////
-  //                       The directory
-  ////////////////////////////////////////////////////////////////////////
-  class CacheDirectory {
-
-    typedef sc_dt::sc_uint<40> addr_t;
-    typedef uint32_t data_t;
-    typedef uint32_t tag_t;
-
-    private:
-
-    // Directory constants
-    size_t   m_ways;
-    size_t   m_sets;
-    size_t   m_words;
-    size_t   m_width;
-    uint32_t lfsr;
-
-    // the directory & lru tables
-    DirectoryEntry **m_dir_tab;
-    LruEntry       **m_lru_tab;
-
-    public:
-
-    ////////////////////////
-    // Constructor
-    ////////////////////////
-    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)
-    {
-      m_ways  = ways;
-      m_sets  = sets;
-      m_words = words;
-      m_width = address_width;
-      lfsr = -1;
-
-      m_dir_tab = new DirectoryEntry*[sets];
-      for ( size_t i=0; i<sets; i++ ) {
-        m_dir_tab[i] = new DirectoryEntry[ways];
-        for ( size_t j=0 ; j<ways ; j++) m_dir_tab[i][j].init();
-      }
-      m_lru_tab = new LruEntry*[sets];
-      for ( size_t i=0; i<sets; i++ ) {
-        m_lru_tab[i] = new LruEntry[ways];
-        for ( size_t j=0 ; j<ways ; j++) m_lru_tab[i][j].init();
-      }
-    } // end constructor
-
-    /////////////////
-    // Destructor
-    /////////////////
-    ~CacheDirectory()
-    {
-      for(size_t i=0 ; i<m_sets ; i++){
-        delete [] m_dir_tab[i];
-        delete [] m_lru_tab[i];
-      }
-      delete [] m_dir_tab;
-      delete [] m_lru_tab;
-    } // end destructor
-
-    /////////////////////////////////////////////////////////////////////
-    // The read() function reads a directory entry. In case of hit, the
-    // LRU is updated.
-    // Arguments :
-    // - address : the address of the entry
-    // - way : (return argument) the way of the entry in case of hit
-    // The function returns a copy of a (valid or invalid) entry
-    /////////////////////////////////////////////////////////////////////
-    DirectoryEntry read(const addr_t &address, size_t &way)
-    {
+
+      /////////////////////////////////////////////////////////////////////
+      // The read_neutral() function reads a directory entry, without
+      // changing the LRU
+      // Arguments :
+      // - address : the address of the entry
+      // The function returns a copy of a (valid or invalid) entry
+      /////////////////////////////////////////////////////////////////////
+      DirectoryEntry read_neutral(const addr_t &address,
+                                  size_t*      ret_way,
+                                  size_t*      ret_set)
+      {
 
 #define L2 soclib::common::uint32_log2
-      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
-      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+          size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+          tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
 #undef L2
 
-      bool hit       = false;
-      for ( size_t i=0 ; i<m_ways ; i++ ) {
-        bool equal = ( m_dir_tab[set][i].tag == tag );
-        bool valid = m_dir_tab[set][i].valid;
-        hit = equal && valid;
-        if ( hit ) {
-          way = i;
-          break;
-        }
-      }
-      if ( hit ) {
-        m_lru_tab[set][way].recent = true;
-        return DirectoryEntry(m_dir_tab[set][way]);
-      } else {
-        return DirectoryEntry();
-      }
-    } // end read()
-
-    /////////////////////////////////////////////////////////////////////
-    // The inval function invalidate an entry defined by the set and
-    // way arguments.
-    /////////////////////////////////////////////////////////////////////
-    void inval( const size_t &way, const size_t &set )
-    {
-        m_dir_tab[set][way].init();
-    }
-
-    /////////////////////////////////////////////////////////////////////
-    // The read_neutral() function reads a directory entry, without
-    // changing the LRU
-    // Arguments :
-    // - address : the address of the entry
-    // The function returns a copy of a (valid or invalid) entry
-    /////////////////////////////////////////////////////////////////////
-    DirectoryEntry read_neutral( const addr_t &address,
-                                 size_t*      ret_way,
-                                 size_t*      ret_set )
-    {
-
-#define L2 soclib::common::uint32_log2
-        size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
-        tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
-#undef L2
-
-        for ( size_t way = 0 ; way < m_ways ; way++ )
-        {
-            bool equal = ( m_dir_tab[set][way].tag == tag );
-            bool valid = m_dir_tab[set][way].valid;
-            if ( equal and valid )
-            {
-                *ret_set = set;
-                *ret_way = way;
-                return DirectoryEntry(m_dir_tab[set][way]);
-            }
-        }
-        return DirectoryEntry();
-    } // end read_neutral()
-
-    /////////////////////////////////////////////////////////////////////
-    // The write function writes a new entry,
-    // and updates the LRU bits if necessary.
-    // Arguments :
-    // - set : the set of the entry
-    // - way : the way of the entry
-    // - entry : the entry value
-    /////////////////////////////////////////////////////////////////////
-    void write( const size_t         &set,
-                const size_t         &way,
-                const DirectoryEntry &entry)
-    {
-      assert( (set<m_sets)
-          && "Cache Directory write : The set index is invalid");
-      assert( (way<m_ways)
-          && "Cache Directory write : The way index is invalid");
-
-      // update Directory
-      m_dir_tab[set][way].copy(entry);
-
-      // update LRU bits
-      bool all_recent = true;
-      for ( size_t i=0 ; i<m_ways ; i++ )
-      {
-          if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
-      }
-      if ( all_recent )
-      {
-          for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
-      }
-      else
-      {
-          m_lru_tab[set][way].recent = true;
-      }
-    } // end write()
-
-    /////////////////////////////////////////////////////////////////////
-    // The print() function prints a selected directory entry
-    // Arguments :
-    // - set : the set of the entry to print
-    // - way : the way of the entry to print
-    /////////////////////////////////////////////////////////////////////
-    void print(const size_t &set, const size_t &way)
-    {
-      std::cout << std::dec << " set : " << set << " ; way : " << way << " ; " ;
-      m_dir_tab[set][way].print();
-    } // end print()
-
-    /////////////////////////////////////////////////////////////////////
-    // The select() function selects a directory entry to evince.
-    // Arguments :
-    // - set   : (input argument) the set to modify
-    // - way   : (return argument) the way to evince
-    /////////////////////////////////////////////////////////////////////
-    DirectoryEntry select(const size_t &set, size_t &way)
-    {
-        assert( (set < m_sets)
-          && "Cache Directory : (select) The set index is invalid");
-
-        // looking for an empty slot
-        for(size_t i=0; i<m_ways; i++)
-        {
-            if( not m_dir_tab[set][i].valid )
-            {
-                way=i;
-                return DirectoryEntry(m_dir_tab[set][way]);
-            }
-        }
+          for (size_t way = 0; way < m_ways; way++)
+          {
+              bool equal = (m_dir_tab[set][way].tag == tag);
+              bool valid = m_dir_tab[set][way].valid;
+              if (equal and valid)
+              {
+                  *ret_set = set;
+                  *ret_way = way;
+                  return DirectoryEntry(m_dir_tab[set][way]);
+              }
+          }
+          return DirectoryEntry();
+      } // end read_neutral()
+
+      /////////////////////////////////////////////////////////////////////
+      // The write function writes a new entry,
+      // and updates the LRU bits if necessary.
+      // Arguments :
+      // - set : the set of the entry
+      // - way : the way of the entry
+      // - entry : the entry value
+      /////////////////////////////////////////////////////////////////////
+      void write(const size_t         &set,
+                 const size_t         &way,
+                 const DirectoryEntry &entry)
+      {
+          assert((set<m_sets)
+                  && "Cache Directory write : The set index is invalid");
+          assert((way<m_ways)
+                  && "Cache Directory write : The way index is invalid");
+
+          // update Directory
+          m_dir_tab[set][way].copy(entry);
+
+          // update LRU bits
+          bool all_recent = true;
+          for (size_t i = 0; i < m_ways; i++)
+          {
+              if (i != way)
+              {
+                  all_recent = m_lru_tab[set][i].recent && all_recent;
+              }
+          }
+          if (all_recent)
+          {
+              for (size_t i = 0; i < m_ways; i++)
+              {
+                  m_lru_tab[set][i].recent = false;
+              }
+          }
+          else
+          {
+              m_lru_tab[set][way].recent = true;
+          }
+      } // end write()
+
+      /////////////////////////////////////////////////////////////////////
+      // The print() function prints a selected directory entry
+      // Arguments :
+      // - set : the set of the entry to print
+      // - way : the way of the entry to print
+      /////////////////////////////////////////////////////////////////////
+      void print(const size_t &set, const size_t &way)
+      {
+          std::cout << std::dec << " set : " << set << " ; way : " << way << " ; ";
+          m_dir_tab[set][way].print();
+      } // end print()
+
+      /////////////////////////////////////////////////////////////////////
+      // The select() function selects a directory entry to evince.
+      // Arguments :
+      // - set   : (input argument) the set to modify
+      // - way   : (return argument) the way to evince
+      /////////////////////////////////////////////////////////////////////
+      DirectoryEntry select(const size_t &set, size_t &way)
+      {
+          assert((set < m_sets)
+                  && "Cache Directory : (select) The set index is invalid");
+
+          // looking for an empty slot
+          for (size_t i = 0; i < m_ways; i++)
+          {
+              if (not m_dir_tab[set][i].valid)
+              {
+                  way = i;
+                  return DirectoryEntry(m_dir_tab[set][way]);
+              }
+          }
 
 #ifdef RANDOM_EVICTION
-        lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001);
-        way = lfsr % m_ways;
-        return DirectoryEntry(m_dir_tab[set][way]);
+          lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001);
+          way = lfsr % m_ways;
+          return DirectoryEntry(m_dir_tab[set][way]);
 #endif
 
-        // looking for a not locked and not recently used entry
-        for(size_t i=0; i<m_ways; i++)
-        {
-            if((not m_lru_tab[set][i].recent) && (not m_dir_tab[set][i].lock) )
-            {
-                way=i;
-                return DirectoryEntry(m_dir_tab[set][way]);
-            }
-        }
-
-        // looking for a locked not recently used entry
-        for(size_t i=0; i<m_ways; i++)
-        {
-            if( (not m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock))
-            {
-                way=i;
-                return DirectoryEntry(m_dir_tab[set][way]);
-            }
-        }
-
-        // looking for a recently used entry not locked
-        for(size_t i=0; i<m_ways; i++)
-        {
-            if( (m_lru_tab[set][i].recent) && (not m_dir_tab[set][i].lock))
-            {
-                way=i;
-                return DirectoryEntry(m_dir_tab[set][way]);
-            }
-        }
-
-        // select way 0 (even if entry is locked and recently used)
-        way = 0;
-        return DirectoryEntry(m_dir_tab[set][0]);
-    } // end select()
-
-    /////////////////////////////////////////////////////////////////////
-    //               Global initialisation function
-    /////////////////////////////////////////////////////////////////////
-    void init()
-    {
-      for ( size_t set=0 ; set<m_sets ; set++ )
-      {
-        for ( size_t way=0 ; way<m_ways ; way++ )
-        {
-          m_dir_tab[set][way].init();
-          m_lru_tab[set][way].init();
-        }
-      }
-    } // end init()
+          // looking for a not locked and not recently used entry
+          for (size_t i = 0; i < m_ways; i++)
+          {
+              if ((not m_lru_tab[set][i].recent) and (not m_dir_tab[set][i].lock))
+              {
+                  way = i;
+                  return DirectoryEntry(m_dir_tab[set][way]);
+              }
+          }
+
+          // looking for a locked not recently used entry
+          for (size_t i = 0; i < m_ways; i++)
+          {
+              if ((not m_lru_tab[set][i].recent) and (m_dir_tab[set][i].lock))
+              {
+                  way = i;
+                  return DirectoryEntry(m_dir_tab[set][way]);
+              }
+          }
+
+          // looking for a recently used entry not locked
+          for (size_t i = 0; i < m_ways; i++)
+          {
+              if ((m_lru_tab[set][i].recent) and (not m_dir_tab[set][i].lock))
+              {
+                  way = i;
+                  return DirectoryEntry(m_dir_tab[set][way]);
+              }
+          }
+
+          // select way 0 (even if entry is locked and recently used)
+          way = 0;
+          return DirectoryEntry(m_dir_tab[set][0]);
+      } // end select()
+
+      /////////////////////////////////////////////////////////////////////
+      //               Global initialisation function
+      /////////////////////////////////////////////////////////////////////
+      void init()
+      {
+          for (size_t set = 0; set < m_sets; set++)
+          {
+              for (size_t way = 0; way < m_ways; way++)
+              {
+                  m_dir_tab[set][way].init();
+                  m_lru_tab[set][way].init();
+              }
+          }
+      } // end init()
 
   }; // end class CacheDirectory
@@ -425 +438 @@
   class HeapEntry{
 
-    public:
-    // Fields of the entry
-      Owner     owner;
-      size_t    next;
-
-    ////////////////////////
-    // Constructor
-    ////////////////////////
-      HeapEntry()
-      :owner(false,0)
-      {
-        next = 0;
-      } // end constructor
-
-    ////////////////////////
-    // Constructor
-    ////////////////////////
-      HeapEntry(const HeapEntry &entry)
-      {
-        owner.inst  = entry.owner.inst;
-        owner.srcid = entry.owner.srcid;
-        next        = entry.next;
-      } // end constructor
-
-    /////////////////////////////////////////////////////////////////////
-    // The copy() function copies an existing source entry to a target
-    /////////////////////////////////////////////////////////////////////
-      void copy(const HeapEntry &entry)
-      {
-        owner.inst  = entry.owner.inst;
-        owner.srcid = entry.owner.srcid;
-        next        = entry.next;
-      } // end copy()
-
-    ////////////////////////////////////////////////////////////////////
-    // The print() function prints the entry
-    ////////////////////////////////////////////////////////////////////
-      void print(){
-        std::cout
-        << " -- owner.inst     : " << std::dec << owner.inst << std::endl
-        << " -- owner.srcid    : " << std::dec << owner.srcid << std::endl
-        << " -- next           : " << std::dec << next << std::endl;
-
-      } // end print()
+      public:
+          // Fields of the entry
+          Owner  owner;
+          size_t next;
+
+          ////////////////////////
+          // Constructor
+          ////////////////////////
+          HeapEntry()
+              :owner(false, 0)
+          {
+              next = 0;
+          } // end constructor
+
+          ////////////////////////
+          // Constructor
+          ////////////////////////
+          HeapEntry(const HeapEntry &entry)
+          {
+              owner.inst  = entry.owner.inst;
+              owner.srcid = entry.owner.srcid;
+              next        = entry.next;
+          } // end constructor
+
+          /////////////////////////////////////////////////////////////////////
+          // The copy() function copies an existing source entry to a target
+          /////////////////////////////////////////////////////////////////////
+          void copy(const HeapEntry &entry)
+          {
+              owner.inst  = entry.owner.inst;
+              owner.srcid = entry.owner.srcid;
+              next        = entry.next;
+          } // end copy()
+
+          ////////////////////////////////////////////////////////////////////
+          // The print() function prints the entry
+          ////////////////////////////////////////////////////////////////////
+          void print()
+          {
+              std::cout
+                  << " -- owner.inst     : " << std::dec << owner.inst << std::endl
+                  << " -- owner.srcid    : " << std::dec << owner.srcid << std::endl
+                  << " -- next           : " << std::dec << next << std::endl;
+
+          } // end print()
 
   }; // end class HeapEntry
@@ -477 +491 @@
   class HeapDirectory{
 
-    private:
-    // Registers and the heap
-      size_t    ptr_free;
-      bool      full;
-      HeapEntry *m_heap_tab;
-
-    // Constants for debugging purpose
-      size_t    tab_size;
-
-    public:
-    ////////////////////////
-    // Constructor
-    ////////////////////////
-      HeapDirectory(uint32_t size){
-        assert(size>0 && "Memory Cache, HeapDirectory constructor : invalid size");
-        ptr_free    = 0;
-        full        = false;
-        m_heap_tab  = new HeapEntry[size];
-        tab_size    = size;
-      } // end constructor
-
-    /////////////////
-    // Destructor
-    /////////////////
-      ~HeapDirectory(){
-        delete [] m_heap_tab;
-      } // end destructor
-
-    /////////////////////////////////////////////////////////////////////
-    //              Global initialisation function
-    /////////////////////////////////////////////////////////////////////
-      void init(){
-        ptr_free=0;
-        full=false;
-        for(size_t i=0; i< tab_size-1;i++){
-          m_heap_tab[i].next = i+1;
-        }
-        m_heap_tab[tab_size-1].next = tab_size-1;
-        return;
-      }
-
-    /////////////////////////////////////////////////////////////////////
-    // The print() function prints a selected directory entry
-    // Arguments :
-    // - ptr : the pointer to the entry to print
-    /////////////////////////////////////////////////////////////////////
-      void print(const size_t &ptr){
-        std::cout << "Heap, printing the entry : " << std::dec << ptr << std::endl;
-        m_heap_tab[ptr].print();
-      } // end print()
-
-    /////////////////////////////////////////////////////////////////////
-    // The print_list() function prints a list from selected directory entry
-    // Arguments :
-    // - ptr : the pointer to the first entry to print
-    /////////////////////////////////////////////////////////////////////
-      void print_list(const size_t &ptr){
-        bool end = false;
-        size_t ptr_temp = ptr;
-        std::cout << "Heap, printing the list from : " << std::dec << ptr << std::endl;
-        while(!end){
-            m_heap_tab[ptr_temp].print();
-            if(ptr_temp == m_heap_tab[ptr_temp].next) end = true;
-            ptr_temp = m_heap_tab[ptr_temp].next;
-        }
-      } // end print_list()
-
-    /////////////////////////////////////////////////////////////////////
-    // The is_full() function return true if the heap is full.
-    /////////////////////////////////////////////////////////////////////
-      bool is_full(){
-        return full;
-      } // end is_full()
-
-    /////////////////////////////////////////////////////////////////////
-    // The next_free_ptr() function returns the pointer
-    // to the next free entry.
-    /////////////////////////////////////////////////////////////////////
-      size_t next_free_ptr(){
-        return ptr_free;
-      } // end next_free_ptr()
-
-    /////////////////////////////////////////////////////////////////////
-    // The next_free_entry() function returns
-    // a copy of the next free entry.
-    /////////////////////////////////////////////////////////////////////
-      HeapEntry next_free_entry(){
-        return HeapEntry(m_heap_tab[ptr_free]);
-      } // end next_free_entry()
-
-    /////////////////////////////////////////////////////////////////////
-    // The write_free_entry() function modify the next free entry.
-    // Arguments :
-    // - entry : the entry to write
-    /////////////////////////////////////////////////////////////////////
-      void write_free_entry(const HeapEntry &entry){
-        m_heap_tab[ptr_free].copy(entry);
-      } // end write_free_entry()
-
-    /////////////////////////////////////////////////////////////////////
-    // The write_free_ptr() function writes the pointer
-    // to the next free entry
-    /////////////////////////////////////////////////////////////////////
-      void write_free_ptr(const size_t &ptr){
-        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
-        ptr_free = ptr;
-      } // end write_free_ptr()
-
-    /////////////////////////////////////////////////////////////////////
-    // The set_full() function sets the full bit (to true).
-    /////////////////////////////////////////////////////////////////////
-      void set_full(){
-        full = true;
-      } // end set_full()
-
-    /////////////////////////////////////////////////////////////////////
-    // The unset_full() function unsets the full bit (to false).
-    /////////////////////////////////////////////////////////////////////
-      void unset_full(){
-        full = false;
-      } // end unset_full()
-
-    /////////////////////////////////////////////////////////////////////
-    // The read() function returns a copy of
-    // the entry pointed by the argument
-    // Arguments :
-    //  - ptr : the pointer to the entry to read
-    /////////////////////////////////////////////////////////////////////
-      HeapEntry read(const size_t &ptr){
-        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
-        return HeapEntry(m_heap_tab[ptr]);
-      } // end read()
-
-    /////////////////////////////////////////////////////////////////////
-    // The write() function writes an entry in the heap
-    // Arguments :
-    //  - ptr : the pointer to the entry to replace
-    //  - entry : the entry to write
-    /////////////////////////////////////////////////////////////////////
-      void write(const size_t &ptr, const HeapEntry &entry){
-        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
-        m_heap_tab[ptr].copy(entry);
-      } // end write()
+      private:
+          // Registers and the heap
+          size_t    ptr_free;
+          bool      full;
+          HeapEntry *m_heap_tab;
+
+          // Constants for debugging purpose
+          size_t    tab_size;
+
+      public:
+          ////////////////////////
+          // Constructor
+          ////////////////////////
+          HeapDirectory(uint32_t size)
+          {
+              assert(size > 0 && "Memory Cache, HeapDirectory constructor : invalid size");
+              ptr_free    = 0;
+              full        = false;
+              m_heap_tab  = new HeapEntry[size];
+              tab_size    = size;
+          } // end constructor
+
+          /////////////////
+          // Destructor
+          /////////////////
+          ~HeapDirectory()
+          {
+              delete [] m_heap_tab;
+          } // end destructor
+
+          /////////////////////////////////////////////////////////////////////
+          //              Global initialisation function
+          /////////////////////////////////////////////////////////////////////
+          void init()
+          {
+              ptr_free = 0;
+              full = false;
+              for (size_t i = 0; i < tab_size - 1; i++) {
+                  m_heap_tab[i].next = i + 1;
+              }
+              m_heap_tab[tab_size - 1].next = tab_size - 1;
+              return;
+          }
+
+          /////////////////////////////////////////////////////////////////////
+          // The print() function prints a selected directory entry
+          // Arguments :
+          // - ptr : the pointer to the entry to print
+          /////////////////////////////////////////////////////////////////////
+          void print(const size_t &ptr)
+          {
+              std::cout << "Heap, printing the entry : " << std::dec << ptr << std::endl;
+              m_heap_tab[ptr].print();
+          } // end print()
+
+          /////////////////////////////////////////////////////////////////////
+          // The print_list() function prints a list from selected directory entry
+          // Arguments :
+          // - ptr : the pointer to the first entry to print
+          /////////////////////////////////////////////////////////////////////
+          void print_list(const size_t &ptr)
+          {
+              bool end = false;
+              size_t ptr_temp = ptr;
+              std::cout << "Heap, printing the list from : " << std::dec << ptr << std::endl;
+              while (!end) {
+                  m_heap_tab[ptr_temp].print();
+                  if (ptr_temp == m_heap_tab[ptr_temp].next) {
+                      end = true;
+                  }
+                  ptr_temp = m_heap_tab[ptr_temp].next;
+              }
+          } // end print_list()
+
+          /////////////////////////////////////////////////////////////////////
+          // The is_full() function return true if the heap is full.
+          /////////////////////////////////////////////////////////////////////
+          bool is_full()
+          {
+              return full;
+          } // end is_full()
+
+          /////////////////////////////////////////////////////////////////////
+          // The next_free_ptr() function returns the pointer
+          // to the next free entry.
+          /////////////////////////////////////////////////////////////////////
+          size_t next_free_ptr()
+          {
+              return ptr_free;
+          } // end next_free_ptr()
+
+          /////////////////////////////////////////////////////////////////////
+          // The next_free_entry() function returns
+          // a copy of the next free entry.
+          /////////////////////////////////////////////////////////////////////
+          HeapEntry next_free_entry()
+          {
+              return HeapEntry(m_heap_tab[ptr_free]);
+          } // end next_free_entry()
+
+          /////////////////////////////////////////////////////////////////////
+          // The write_free_entry() function modify the next free entry.
+          // Arguments :
+          // - entry : the entry to write
+          /////////////////////////////////////////////////////////////////////
+          void write_free_entry(const HeapEntry &entry)
+          {
+              m_heap_tab[ptr_free].copy(entry);
+          } // end write_free_entry()
+
+          /////////////////////////////////////////////////////////////////////
+          // The write_free_ptr() function writes the pointer
+          // to the next free entry
+          /////////////////////////////////////////////////////////////////////
+          void write_free_ptr(const size_t &ptr)
+          {
+              assert((ptr < tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+              ptr_free = ptr;
+          } // end write_free_ptr()
+
+          /////////////////////////////////////////////////////////////////////
+          // The set_full() function sets the full bit (to true).
+          /////////////////////////////////////////////////////////////////////
+          void set_full()
+          {
+              full = true;
+          } // end set_full()
+
+          /////////////////////////////////////////////////////////////////////
+          // The unset_full() function unsets the full bit (to false).
+          /////////////////////////////////////////////////////////////////////
+          void unset_full()
+          {
+              full = false;
+          } // end unset_full()
+
+          /////////////////////////////////////////////////////////////////////
+          // The read() function returns a copy of
+          // the entry pointed by the argument
+          // Arguments :
+          //  - ptr : the pointer to the entry to read
+          /////////////////////////////////////////////////////////////////////
+          HeapEntry read(const size_t &ptr)
+          {
+              assert((ptr < tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+              return HeapEntry(m_heap_tab[ptr]);
+          } // end read()
+
+          /////////////////////////////////////////////////////////////////////
+          // The write() function writes an entry in the heap
+          // Arguments :
+          //  - ptr : the pointer to the entry to replace
+          //  - entry : the entry to write
+          /////////////////////////////////////////////////////////////////////
+          void write(const size_t &ptr, const HeapEntry &entry)
+          {
+              assert((ptr < tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+              m_heap_tab[ptr].copy(entry);
+          } // end write()
 
   }; // end class HeapDirectory
@@ -628 +658 @@
   class CacheData
   {
-    private:
-      const uint32_t m_sets;
-      const uint32_t m_ways;
-      const uint32_t m_words;
-
-      uint32_t *** m_cache_data;
-
-    public:
-
-      ///////////////////////////////////////////////////////
-      CacheData(uint32_t ways, uint32_t sets, uint32_t words)
-        : m_sets(sets), m_ways(ways), m_words(words)
-      {
-          m_cache_data = new uint32_t ** [ways];
-          for ( size_t i=0 ; i < ways ; i++ )
-          {
-              m_cache_data[i] = new uint32_t * [sets];
-          }
-          for ( size_t i=0; i<ways; i++ )
-          {
-              for ( size_t j=0; j<sets; j++ )
-              {
-                  m_cache_data[i][j] = new uint32_t [words];
-              }
-          }
-      }
-      ////////////
-      ~CacheData()
-      {
-          for(size_t i=0; i<m_ways ; i++)
-          {
-              for(size_t j=0; j<m_sets ; j++)
-              {
-                  delete [] m_cache_data[i][j];
-              }
-          }
-          for(size_t i=0; i<m_ways ; i++)
-          {
-              delete [] m_cache_data[i];
-          }
-          delete [] m_cache_data;
-      }
-      //////////////////////////////////////////
-      uint32_t read ( const uint32_t &way,
-                      const uint32_t &set,
-                      const uint32_t &word) const
-      {
-          assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set" );
-          assert((way  < m_ways ) && "Cache data error: Trying to read a wrong way" );
-          assert((word < m_words) && "Cache data error: Trying to read a wrong word");
-
-          return m_cache_data[way][set][word];
-      }
-      //////////////////////////////////////////
-      void read_line( const uint32_t &way,
-                      const uint32_t &set,
-                      sc_core::sc_signal<uint32_t> * cache_line)
-      {
-          assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
-          assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
-
-          for (uint32_t word=0; word<m_words; word++)
-              cache_line[word].write(m_cache_data[way][set][word]);
-      }
-      /////////////////////////////////////////
-      void write ( const uint32_t &way,
-                   const uint32_t &set,
-                   const uint32_t &word,
-                   const uint32_t &data,
-                   const uint32_t &be = 0xF)
-      {
-
-          assert((set  < m_sets ) && "Cache data error: Trying to write a wrong set" );
-          assert((way  < m_ways ) && "Cache data error: Trying to write a wrong way" );
-          assert((word < m_words) && "Cache data error: Trying to write a wrong word");
-          assert((be  <= 0xF    ) && "Cache data error: Trying to write a wrong be");
-
-          if (be == 0x0) return;
-
-          if (be == 0xF)
-          {
-              m_cache_data[way][set][word] = data;
-              return;
-          }
-
-          uint32_t mask = 0;
-          if  (be & 0x1) mask = mask | 0x000000FF;
-          if  (be & 0x2) mask = mask | 0x0000FF00;
-          if  (be & 0x4) mask = mask | 0x00FF0000;
-          if  (be & 0x8) mask = mask | 0xFF000000;
-
-          m_cache_data[way][set][word] =
-              (data & mask) | (m_cache_data[way][set][word] & ~mask);
-      }
+      private:
+          const uint32_t m_sets;
+          const uint32_t m_ways;
+          const uint32_t m_words;
+
+          uint32_t *** m_cache_data;
+
+      public:
+
+          ///////////////////////////////////////////////////////
+          CacheData(uint32_t ways, uint32_t sets, uint32_t words)
+              : m_sets(sets), m_ways(ways), m_words(words)
+          {
+              m_cache_data = new uint32_t ** [ways];
+              for (size_t i = 0; i < ways; i++)
+              {
+                  m_cache_data[i] = new uint32_t * [sets];
+              }
+              for (size_t i = 0; i < ways; i++)
+              {
+                  for (size_t j = 0; j < sets; j++)
+                  {
+                      m_cache_data[i][j] = new uint32_t [words];
+                  }
+              }
+          }
+          ////////////
+          ~CacheData()
+          {
+              for (size_t i = 0; i < m_ways; i++)
+              {
+                  for (size_t j = 0; j < m_sets; j++)
+                  {
+                      delete [] m_cache_data[i][j];
+                  }
+              }
+              for (size_t i = 0; i < m_ways; i++)
+              {
+                  delete [] m_cache_data[i];
+              }
+              delete [] m_cache_data;
+          }
+          //////////////////////////////////////////
+          uint32_t read(const uint32_t &way,
+                        const uint32_t &set,
+                        const uint32_t &word) const
+          {
+              assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set");
+              assert((way  < m_ways ) && "Cache data error: Trying to read a wrong way");
+              assert((word < m_words) && "Cache data error: Trying to read a wrong word");
+
+              return m_cache_data[way][set][word];
+          }
+          //////////////////////////////////////////
+          void read_line(const uint32_t &way,
+                         const uint32_t &set,
+                         sc_core::sc_signal<uint32_t> * cache_line)
+          {
+              assert((set < m_sets) && "Cache data error: Trying to read a wrong set");
+              assert((way < m_ways) && "Cache data error: Trying to read a wrong way");
+
+              for (uint32_t word = 0; word < m_words; word++) {
+                  cache_line[word].write(m_cache_data[way][set][word]);
+              }
+          }
+          /////////////////////////////////////////
+          void write(const uint32_t &way,
+                     const uint32_t &set,
+                     const uint32_t &word,
+                     const uint32_t &data,
+                     const uint32_t &be = 0xF)
+          {
+              assert((set  < m_sets ) && "Cache data error: Trying to write a wrong set");
+              assert((way  < m_ways ) && "Cache data error: Trying to write a wrong way");
+              assert((word < m_words) && "Cache data error: Trying to write a wrong word");
+              assert((be  <= 0xF    ) && "Cache data error: Trying to write a wrong be");
+
+              if (be == 0x0) return;
+
+              if (be == 0xF)
+              {
+                  m_cache_data[way][set][word] = data;
+                  return;
+              }
+
+              uint32_t mask = 0;
+              if (be & 0x1) mask = mask | 0x000000FF;
+              if (be & 0x2) mask = mask | 0x0000FF00;
+              if (be & 0x4) mask = mask | 0x00FF0000;
+              if (be & 0x8) mask = mask | 0xFF000000;
+
+              m_cache_data[way][set][word] =
+                  (data & mask) | (m_cache_data[way][set][word] & ~mask);
+          }
   }; // end class CacheData
 

branches/RWT/modules/vci_mem_cache/caba/source/include/update_tab.h

@@ -12 +12 @@
 class UpdateTabEntry {
 
-  typedef uint32_t size_t;
-  typedef sc_dt::sc_uint<40> addr_t;
-
-  public:
-
-  bool   valid;   // It is a valid pending transaction
-  bool   update;  // It is an update transaction
-  bool   brdcast; // It is a broadcast invalidate
-  bool   rsp;     // Response to the initiator required
-  bool   ack;     // Acknowledge to the CONFIG FSM required
-  size_t srcid;   // The srcid of the initiator which wrote the data
-  size_t trdid;   // The trdid of the initiator which wrote the data
-  size_t pktid;   // The pktid of the initiator which wrote the data
-  addr_t nline;   // The identifier of the cache line
-  size_t count;   // The number of acknowledge responses to receive
-
-  UpdateTabEntry()
-  {
-    valid   = false;
-    update  = false;
-    brdcast = false;
-    rsp     = false;
-    ack     = false;
-    srcid   = 0;
-    trdid   = 0;
-    pktid   = 0;
-    nline   = 0;
-    count   = 0;
-  }
-
-  UpdateTabEntry(bool   i_valid,
-                 bool   i_update,
-                 bool   i_brdcast,
-                 bool   i_rsp,
-                 bool   i_ack,
-                 size_t i_srcid,
-                 size_t i_trdid,
-                 size_t i_pktid,
-                 addr_t i_nline,
-                 size_t i_count)
-  {
-    valid   = i_valid;
-    update  = i_update;
-    brdcast = i_brdcast;
-    rsp     = i_rsp;
-    ack     = i_ack;
-    srcid   = i_srcid;
-    trdid   = i_trdid;
-    pktid   = i_pktid;
-    nline   = i_nline;
-    count   = i_count;
-  }
-
-  UpdateTabEntry(const UpdateTabEntry &source)
-  {
-    valid   = source.valid;
-    update  = source.update;
-    brdcast = source.brdcast;
-    rsp     = source.rsp;
-    ack     = source.ack;
-    srcid   = source.srcid;
-    trdid   = source.trdid;
-    pktid   = source.pktid;
-    nline   = source.nline;
-    count   = source.count;
-  }
-
-  ////////////////////////////////////////////////////
-  // The init() function initializes the entry
-  ///////////////////////////////////////////////////
-  void init()
-  {
-    valid   = false;
-    update  = false;
-    brdcast = false;
-    rsp     = false;
-    ack     = false;
-    srcid   = 0;
-    trdid   = 0;
-    pktid   = 0;
-    nline   = 0;
-    count   = 0;
-  }
-
-  ////////////////////////////////////////////////////////////////////
-  // The copy() function copies an existing entry
-  // Its arguments are :
-  // - source : the update tab entry to copy
-  ////////////////////////////////////////////////////////////////////
-  void copy(const UpdateTabEntry &source)
-  {
-    valid  = source.valid;
-    update = source.update;
-    brdcast= source.brdcast;
-    rsp    = source.rsp;
-    ack    = source.ack  ;
-    srcid  = source.srcid;
-    trdid  = source.trdid;
-    pktid  = source.pktid;
-    nline  = source.nline;
-    count  = source.count;
-  }
-
-  ////////////////////////////////////////////////////////////////////
-  // The print() function prints the entry
-  ////////////////////////////////////////////////////////////////////
-  void print()
-  {
-    std::cout << " val = " << std::dec << valid
-              << " / updt = " << update
-              << " / bc = " << brdcast
-              << " / rsp = " << rsp
-              << " / ack = " << ack
-              << " / count = " << count
-              << " / srcid = " << std::hex << srcid
-              << " / trdid = " << trdid
-              << " / pktid = " << pktid
-              << " / nline = " << nline  << std::endl;
-  }
+    typedef uint32_t size_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+
+    public:
+
+    bool   valid;   // It is a valid pending transaction
+    bool   update;  // It is an update transaction
+    bool   brdcast; // It is a broadcast invalidate
+    bool   rsp;     // Response to the initiator required
+    bool   ack;     // Acknowledge to the CONFIG FSM required
+    size_t srcid;   // The srcid of the initiator which wrote the data
+    size_t trdid;   // The trdid of the initiator which wrote the data
+    size_t pktid;   // The pktid of the initiator which wrote the data
+    addr_t nline;   // The identifier of the cache line
+    size_t count;   // The number of acknowledge responses to receive
+
+    UpdateTabEntry()
+    {
+        valid   = false;
+        update  = false;
+        brdcast = false;
+        rsp     = false;
+        ack     = false;
+        srcid   = 0;
+        trdid   = 0;
+        pktid   = 0;
+        nline   = 0;
+        count   = 0;
+    }
+
+    UpdateTabEntry(bool   i_valid,
+                   bool   i_update,
+                   bool   i_brdcast,
+                   bool   i_rsp,
+                   bool   i_ack,
+                   size_t i_srcid,
+                   size_t i_trdid,
+                   size_t i_pktid,
+                   addr_t i_nline,
+                   size_t i_count)
+    {
+        valid   = i_valid;
+        update  = i_update;
+        brdcast = i_brdcast;
+        rsp     = i_rsp;
+        ack     = i_ack;
+        srcid   = i_srcid;
+        trdid   = i_trdid;
+        pktid   = i_pktid;
+        nline   = i_nline;
+        count   = i_count;
+    }
+
+    UpdateTabEntry(const UpdateTabEntry &source)
+    {
+        valid   = source.valid;
+        update  = source.update;
+        brdcast = source.brdcast;
+        rsp     = source.rsp;
+        ack     = source.ack;
+        srcid   = source.srcid;
+        trdid   = source.trdid;
+        pktid   = source.pktid;
+        nline   = source.nline;
+        count   = source.count;
+    }
+
+    ////////////////////////////////////////////////////
+    // The init() function initializes the entry
+    ///////////////////////////////////////////////////
+    void init()
+    {
+        valid   = false;
+        update  = false;
+        brdcast = false;
+        rsp     = false;
+        ack     = false;
+        srcid   = 0;
+        trdid   = 0;
+        pktid   = 0;
+        nline   = 0;
+        count   = 0;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing entry
+    // Its arguments are :
+    // - source : the update tab entry to copy
+    ////////////////////////////////////////////////////////////////////
+    void copy(const UpdateTabEntry &source)
+    {
+        valid   = source.valid;
+        update  = source.update;
+        brdcast = source.brdcast;
+        rsp     = source.rsp;
+        ack     = source.ack;
+        srcid   = source.srcid;
+        trdid   = source.trdid;
+        pktid   = source.pktid;
+        nline   = source.nline;
+        count   = source.count;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry
+    ////////////////////////////////////////////////////////////////////
+    void print()
+    {
+        std::cout << " val = " << std::dec << valid
+                  << " / updt = " << update
+                  << " / bc = " << brdcast
+                  << " / rsp = " << rsp
+                  << " / ack = " << ack
+                  << " / count = " << count
+                  << " / srcid = " << std::hex << srcid
+                  << " / trdid = " << trdid
+                  << " / pktid = " << pktid
+                  << " / nline = " << nline << std::endl;
+    }
 };
 
@@ -138 +138 @@
 class UpdateTab{
 
-  typedef uint64_t addr_t;
-
-  private:
-  size_t                      size_tab;
-  std::vector<UpdateTabEntry> tab;
-
-  public:
-
-  UpdateTab()
-    : tab(0)
-  {
-    size_tab=0;
-  }
-
-  UpdateTab(size_t size_tab_i)
-    : tab(size_tab_i)
-  {
-    size_tab=size_tab_i;
-  }
-
-  ////////////////////////////////////////////////////////////////////
-  // The size() function returns the size of the tab
-  ////////////////////////////////////////////////////////////////////
-  const size_t size()
-  {
-    return size_tab;
-  }
-
-  ////////////////////////////////////////////////////////////////////
-  // The print() function diplays the tab content
-  ////////////////////////////////////////////////////////////////////
-  void print()
-  {
-    std::cout << "UPDATE TABLE Content" << std::endl;
-    for(size_t i=0; i<size_tab; i++)
-    {
-      std::cout << "[" << std::dec << i << "] ";
-      tab[i].print();
-    }
-    return;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The init() function initializes the tab
-  /////////////////////////////////////////////////////////////////////
-  void init()
-  {
-    for ( size_t i=0; i<size_tab; i++) tab[i].init();
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The reads() function reads an entry
-  // Arguments :
-  // - entry : the entry to read
-  // This function returns a copy of the entry.
-  /////////////////////////////////////////////////////////////////////
-  UpdateTabEntry read (size_t entry)
-  {
-    assert(entry<size_tab && "Bad Update Tab Entry");
-    return UpdateTabEntry(tab[entry]);
-  }
-
-  ///////////////////////////////////////////////////////////////////////////
-  // The set() function writes an entry in the Update Table
-  // Arguments :
-  // - update : transaction type (bool)
-  // - srcid : srcid of the initiator
-  // - trdid : trdid of the initiator
-  // - pktid : pktid of the initiator
-  // - count : number of expected responses
-  // - index : (return argument) index of the selected entry
-  // This function returns true if the write successed (an entry was empty).
-  ///////////////////////////////////////////////////////////////////////////
-  bool set(const bool   update,
-           const bool   brdcast,
-           const bool   rsp,
-           const bool   ack,
-           const size_t srcid,
-           const size_t trdid,
-           const size_t pktid,
-           const addr_t nline,
-           const size_t count,
-           size_t       &index)
-  {
-    for ( size_t i=0 ; i<size_tab ; i++ )
-    {
-      if( !tab[i].valid )
-      {
-        tab[i].valid   = true;
-        tab[i].update  = update;
-        tab[i].brdcast = brdcast;
-        tab[i].rsp     = rsp;
-        tab[i].ack     = ack;
-        tab[i].srcid   = (size_t) srcid;
-        tab[i].trdid   = (size_t) trdid;
-        tab[i].pktid   = (size_t) pktid;
-        tab[i].nline   = (addr_t) nline;
-        tab[i].count   = (size_t) count;
-        index          = i;
+    typedef uint64_t addr_t;
+
+    private:
+    size_t size_tab;
+    std::vector<UpdateTabEntry> tab;
+
+    public:
+
+    UpdateTab()
+        : tab(0)
+    {
+        size_tab = 0;
+    }
+
+    UpdateTab(size_t size_tab_i)
+        : tab(size_tab_i)
+    {
+        size_tab = size_tab_i;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The size() function returns the size of the tab
+    ////////////////////////////////////////////////////////////////////
+    const size_t size()
+    {
+        return size_tab;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function diplays the tab content
+    ////////////////////////////////////////////////////////////////////
+    void print()
+    {
+        std::cout << "UPDATE TABLE Content" << std::endl;
+        for (size_t i = 0; i < size_tab; i++)
+        {
+            std::cout << "[" << std::dec << i << "] ";
+            tab[i].print();
+        }
+        return;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the tab
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+        for (size_t i = 0; i < size_tab; i++)
+        {
+            tab[i].init();
+        }
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The reads() function reads an entry
+    // Arguments :
+    // - entry : the entry to read
+    // This function returns a copy of the entry.
+    /////////////////////////////////////////////////////////////////////
+    UpdateTabEntry read(size_t entry)
+    {
+        assert(entry < size_tab && "Bad Update Tab Entry");
+        return UpdateTabEntry(tab[entry]);
+    }
+
+    ///////////////////////////////////////////////////////////////////////////
+    // The set() function writes an entry in the Update Table
+    // Arguments :
+    // - update : transaction type (bool)
+    // - srcid : srcid of the initiator
+    // - trdid : trdid of the initiator
+    // - pktid : pktid of the initiator
+    // - count : number of expected responses
+    // - index : (return argument) index of the selected entry
+    // This function returns true if the write successed (an entry was empty).
+    ///////////////////////////////////////////////////////////////////////////
+    bool set(const bool   update,
+             const bool   brdcast,
+             const bool   rsp,
+             const bool   ack,
+             const size_t srcid,
+             const size_t trdid,
+             const size_t pktid,
+             const addr_t nline,
+             const size_t count,
+             size_t       &index)
+    {
+        for (size_t i = 0; i < size_tab; i++)
+        {
+            if (!tab[i].valid)
+            {
+                tab[i].valid   = true;
+                tab[i].update  = update;
+                tab[i].brdcast = brdcast;
+                tab[i].rsp     = rsp;
+                tab[i].ack     = ack;
+                tab[i].srcid   = (size_t) srcid;
+                tab[i].trdid   = (size_t) trdid;
+                tab[i].pktid   = (size_t) pktid;
+                tab[i].nline   = (addr_t) nline;
+                tab[i].count   = (size_t) count;
+                index          = i;
+                return true;
+            }
+        }
+        return false;
+    } // end set()
+
+    /////////////////////////////////////////////////////////////////////
+    // The decrement() function decrements the counter for a given entry.
+    // Arguments :
+    // - index   : the index of the entry
+    // - counter : (return argument) value of the counter after decrement
+    // This function returns true if the entry is valid.
+    /////////////////////////////////////////////////////////////////////
+    bool decrement(const size_t index,
+                   size_t       &counter)
+    {
+        assert((index < size_tab) && "Bad Update Tab Entry");
+        if (tab[index].valid)
+        {
+            tab[index].count--;
+            counter = tab[index].count;
+            return true;
+        }
+        else
+        {
+            return false;
+        }
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The is_full() function returns true if the table is full
+    /////////////////////////////////////////////////////////////////////
+    bool is_full()
+    {
+        for (size_t i = 0; i < size_tab; i++)
+        {
+            if (!tab[i].valid)
+            {
+                return false;
+            }
+        }
         return true;
-      }
-    }
-    return false;
-  } // end set()
-
-  /////////////////////////////////////////////////////////////////////
-  // The decrement() function decrements the counter for a given entry.
-  // Arguments :
-  // - index   : the index of the entry
-  // - counter : (return argument) value of the counter after decrement
-  // This function returns true if the entry is valid.
-  /////////////////////////////////////////////////////////////////////
-  bool decrement( const size_t index,
-                  size_t &counter )
-  {
-    assert((index<size_tab) && "Bad Update Tab Entry");
-    if ( tab[index].valid )
-    {
-      tab[index].count--;
-      counter = tab[index].count;
-      return true;
-    }
-    else
-    {
-      return false;
-    }
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The is_full() function returns true if the table is full
-  /////////////////////////////////////////////////////////////////////
-  bool is_full()
-  {
-    for(size_t i = 0 ; i < size_tab ; i++)
-    {
-      if(!tab[i].valid) return false;
-    }
-    return true;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The is_not_empty() function returns true if the table is not empty
-  /////////////////////////////////////////////////////////////////////
-  bool is_not_empty()
-  {
-    for(size_t i = 0 ; i < size_tab ; i++)
-    {
-      if(tab[i].valid) return true;
-    }
-    return false;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The need_rsp() function returns the need of a response
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  bool need_rsp(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].rsp;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The need_ack() function returns the need of an acknowledge
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  bool need_ack(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].ack;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The is_brdcast() function returns the transaction type
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  bool is_brdcast(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].brdcast;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The is_update() function returns the transaction type
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  bool is_update(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].update;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The srcid() function returns the srcid value
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  size_t srcid(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].srcid;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The trdid() function returns the trdid value
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  size_t trdid(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].trdid;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The pktid() function returns the pktid value
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  size_t pktid(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].pktid;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The nline() function returns the nline value
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  addr_t nline(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].nline;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The search_inval() function returns the index of the entry in UPT
-  // Arguments :
-  // - nline : the line number of the entry in the directory
-  /////////////////////////////////////////////////////////////////////
-  bool search_inval(const addr_t nline,size_t &index)
-  {
-    size_t i ;
-
-    for (i = 0 ; i < size_tab ; i++)
-    {
-      if ( (tab[i].nline == nline) and tab[i].valid and not tab[i].update )
-      {
-        index = i ;
-        return true;
-      }
-    }
-    return false;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The read_nline() function returns the index of the entry in UPT
-  // Arguments :
-  // - nline : the line number of the entry in the directory
-  /////////////////////////////////////////////////////////////////////
-  bool read_nline(const addr_t nline,size_t &index)
-  {
-    size_t i ;
-
-    for (i = 0 ; i < size_tab ; i++)
-    {
-      if ( (tab[i].nline == nline) and tab[i].valid )
-      {
-        index = i ;
-        return true;
-      }
-    }
-    return false;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The clear() function erases an entry of the tab
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  void clear(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    tab[index].valid=false;
-    return;
-  }
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The is_not_empty() function returns true if the table is not empty
+    /////////////////////////////////////////////////////////////////////
+    bool is_not_empty()
+    {
+        for (size_t i = 0; i < size_tab; i++)
+        {
+            if (tab[i].valid)
+            {
+                return true;
+            }
+        }
+        return false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The need_rsp() function returns the need of a response
+    // Arguments :
+    // - index : the index of the entry
+    /////////////////////////////////////////////////////////////////////
+    bool need_rsp(const size_t index)
+    {
+        assert(index < size_tab && "Bad Update Tab Entry");
+        return tab[index].rsp;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The need_ack() function returns the need of an acknowledge
+    // Arguments :
+    // - index : the index of the entry
+    /////////////////////////////////////////////////////////////////////
+    bool need_ack(const size_t index)
+    {
+        assert(index < size_tab && "Bad Update Tab Entry");
+        return tab[index].ack;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The is_brdcast() function returns the transaction type
+    // Arguments :
+    // - index : the index of the entry
+    /////////////////////////////////////////////////////////////////////
+    bool is_brdcast(const size_t index)
+    {
+        assert(index < size_tab && "Bad Update Tab Entry");
+        return tab[index].brdcast;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The is_update() function returns the transaction type
+    // Arguments :
+    // - index : the index of the entry
+    /////////////////////////////////////////////////////////////////////
+    bool is_update(const size_t index)
+    {
+        assert(index < size_tab && "Bad Update Tab Entry");
+        return tab[index].update;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The srcid() function returns the srcid value
+    // Arguments :
+    // - index : the index of the entry
+    /////////////////////////////////////////////////////////////////////
+    size_t srcid(const size_t index)
+    {
+        assert(index < size_tab && "Bad Update Tab Entry");
+        return tab[index].srcid;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The trdid() function returns the trdid value
+    // Arguments :
+    // - index : the index of the entry
+    /////////////////////////////////////////////////////////////////////
+    size_t trdid(const size_t index)
+    {
+        assert(index < size_tab && "Bad Update Tab Entry");
+        return tab[index].trdid;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The pktid() function returns the pktid value
+    // Arguments :
+    // - index : the index of the entry
+    /////////////////////////////////////////////////////////////////////
+    size_t pktid(const size_t index)
+    {
+        assert(index < size_tab && "Bad Update Tab Entry");
+        return tab[index].pktid;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The nline() function returns the nline value
+    // Arguments :
+    // - index : the index of the entry
+    /////////////////////////////////////////////////////////////////////
+    addr_t nline(const size_t index)
+    {
+        assert(index < size_tab && "Bad Update Tab Entry");
+        return tab[index].nline;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The search_inval() function returns the index of the entry in UPT
+    // Arguments :
+    // - nline : the line number of the entry in the directory
+    /////////////////////////////////////////////////////////////////////
+    bool search_inval(const addr_t nline, size_t &index)
+    {
+        size_t i;
+
+        for (i = 0; i < size_tab; i++)
+        {
+            if ((tab[i].nline == nline) and tab[i].valid and not tab[i].update)
+            {
+                index = i;
+                return true;
+            }
+        }
+        return false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The read_nline() function returns the index of the entry in UPT
+    // Arguments :
+    // - nline : the line number of the entry in the directory
+    /////////////////////////////////////////////////////////////////////
+    bool read_nline(const addr_t nline, size_t &index)
+    {
+        size_t i;
+
+        for (i = 0; i < size_tab; i++)
+        {
+            if ((tab[i].nline == nline) and tab[i].valid)
+            {
+                index = i;
+                return true;
+            }
+        }
+        return false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The clear() function erases an entry of the tab
+    // Arguments :
+    // - index : the index of the entry
+    /////////////////////////////////////////////////////////////////////
+    void clear(const size_t index)
+    {
+        assert(index < size_tab && "Bad Update Tab Entry");
+        tab[index].valid = false;
+        return;
+    }
 
 };

branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -69 +69 @@
     : public soclib::caba::BaseModule
     {
-      typedef typename vci_param_int::fast_addr_t  addr_t;
-      typedef typename sc_dt::sc_uint<64>          wide_data_t;
-      typedef uint32_t                             data_t;
-      typedef uint32_t                             tag_t;
-      typedef uint32_t                             be_t;
-      typedef uint32_t                             copy_t;
+      typedef typename vci_param_int::fast_addr_t addr_t;
+      typedef typename sc_dt::sc_uint<64>         wide_data_t;
+      typedef uint32_t                            data_t;
+      typedef uint32_t                            tag_t;
+      typedef uint32_t                            be_t;
+      typedef uint32_t                            copy_t;
 
       /* States of the TGT_CMD fsm */
@@ -113 +113 @@
         CC_RECEIVE_IDLE,
         CC_RECEIVE_CLEANUP,
-        CC_RECEIVE_CLEANUP_EOP,
         CC_RECEIVE_MULTI_ACK
       };
@@ -232 +231 @@
       {
         IXR_RSP_IDLE,
-        IXR_RSP_ACK,
         IXR_RSP_TRT_ERASE,
         IXR_RSP_TRT_READ
@@ -399 +397 @@
           //  b1 accÚs table llsc type SW / other
           //  b2 WRITE/CAS/LL/SC
-          TYPE_READ_DATA_UNC   = 0x0,
-          TYPE_READ_DATA_MISS  = 0x1,
-          TYPE_READ_INS_UNC    = 0x2,
-          TYPE_READ_INS_MISS   = 0x3,
-          TYPE_WRITE           = 0x4,
-          TYPE_CAS             = 0x5,
-          TYPE_LL              = 0x6,
-          TYPE_SC              = 0x7
+          TYPE_READ_DATA_UNC  = 0x0,
+          TYPE_READ_DATA_MISS = 0x1,
+          TYPE_READ_INS_UNC   = 0x2,
+          TYPE_READ_INS_MISS  = 0x3,
+          TYPE_WRITE          = 0x4,
+          TYPE_CAS            = 0x5,
+          TYPE_LL             = 0x6,
+          TYPE_SC             = 0x7
       };
 
@@ -425 +423 @@
 
       // instrumentation counters
-      uint32_t m_cpt_cycles;        // Counter of cycles
+      uint32_t m_cpt_cycles;                  // Counter of cycles
 
       // Counters accessible in software (not yet but eventually) and tagged
-      uint32_t m_cpt_reset_count;    // Last cycle at which counters have been reset
-      uint32_t m_cpt_read_local;     // Number of local READ transactions
-      uint32_t m_cpt_read_remote;    // number of remote READ transactions
-      uint32_t m_cpt_read_cost;      // Number of (flits * distance) for READs
-
-      uint32_t m_cpt_write_local;    // Number of local WRITE transactions
-      uint32_t m_cpt_write_remote;   // number of remote WRITE transactions
-      uint32_t m_cpt_write_flits_local;  // number of flits for local WRITEs
-      uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs
-      uint32_t m_cpt_write_cost;     // Number of (flits * distance) for WRITEs
-      uint32_t m_cpt_write_ncc_miss;   // Number of write on ncc line
-
-      uint32_t m_cpt_ll_local;       // Number of local LL transactions
-      uint32_t m_cpt_ll_remote;      // number of remote LL transactions
-      uint32_t m_cpt_ll_cost;        // Number of (flits * distance) for LLs
-
-      uint32_t m_cpt_sc_local;       // Number of local SC transactions
-      uint32_t m_cpt_sc_remote;      // number of remote SC transactions
-      uint32_t m_cpt_sc_cost;        // Number of (flits * distance) for SCs
-
-      uint32_t m_cpt_cas_local;      // Number of local SC transactions
-      uint32_t m_cpt_cas_remote;     // number of remote SC transactions
-      uint32_t m_cpt_cas_cost;       // Number of (flits * distance) for SCs
-
-      uint32_t m_cpt_update;         // Number of requests causing an UPDATE
-      uint32_t m_cpt_update_local;   // Number of local UPDATE transactions
-      uint32_t m_cpt_update_remote;  // Number of remote UPDATE transactions
-      uint32_t m_cpt_update_cost;    // Number of (flits * distance) for UPDT
-
-      uint32_t m_cpt_minval;         // Number of requests causing M_INV
-      uint32_t m_cpt_minval_local;   // Number of local M_INV transactions
-      uint32_t m_cpt_minval_remote;  // Number of remote M_INV transactions
-      uint32_t m_cpt_minval_cost;    // Number of (flits * distance) for M_INV
-
-      uint32_t m_cpt_binval;         // Number of BROADCAST INVAL
-
-      uint32_t m_cpt_cleanup_local;  // Number of local CLEANUP transactions (all cleanup types)
-      uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions (all cleanup types)
-      uint32_t m_cpt_cleanup_cost;   // Number of (flits * distance) for CLEANUPs (all types)
+      uint32_t m_cpt_reset_count;             // Last cycle at which counters have been reset
+      uint32_t m_cpt_read_local;              // Number of local READ transactions
+      uint32_t m_cpt_read_remote;             // number of remote READ transactions
+      uint32_t m_cpt_read_cost;               // Number of (flits * distance) for READs
+
+      uint32_t m_cpt_write_local;             // Number of local WRITE transactions
+      uint32_t m_cpt_write_remote;            // number of remote WRITE transactions
+      uint32_t m_cpt_write_flits_local;       // number of flits for local WRITEs
+      uint32_t m_cpt_write_flits_remote;      // number of flits for remote WRITEs
+      uint32_t m_cpt_write_cost;              // Number of (flits * distance) for WRITEs
+      uint32_t m_cpt_write_ncc_miss;          // Number of write on ncc line
+
+      uint32_t m_cpt_ll_local;                // Number of local LL transactions
+      uint32_t m_cpt_ll_remote;               // number of remote LL transactions
+      uint32_t m_cpt_ll_cost;                 // Number of (flits * distance) for LLs
+
+      uint32_t m_cpt_sc_local;                // Number of local SC transactions
+      uint32_t m_cpt_sc_remote;               // number of remote SC transactions
+      uint32_t m_cpt_sc_cost;                 // Number of (flits * distance) for SCs
+
+      uint32_t m_cpt_cas_local;               // Number of local SC transactions
+      uint32_t m_cpt_cas_remote;              // number of remote SC transactions
+      uint32_t m_cpt_cas_cost;                // Number of (flits * distance) for SCs
+
+      uint32_t m_cpt_update;                  // Number of requests causing an UPDATE
+      uint32_t m_cpt_update_local;            // Number of local UPDATE transactions
+      uint32_t m_cpt_update_remote;           // Number of remote UPDATE transactions
+      uint32_t m_cpt_update_cost;             // Number of (flits * distance) for UPDT
+
+      uint32_t m_cpt_minval;                  // Number of requests causing M_INV
+      uint32_t m_cpt_minval_local;            // Number of local M_INV transactions
+      uint32_t m_cpt_minval_remote;           // Number of remote M_INV transactions
+      uint32_t m_cpt_minval_cost;             // Number of (flits * distance) for M_INV
+
+      uint32_t m_cpt_binval;                  // Number of BROADCAST INVAL
+
+      uint32_t m_cpt_cleanup_local;           // Number of local CLEANUP transactions (all cleanup types)
+      uint32_t m_cpt_cleanup_remote;          // Number of remote CLEANUP transactions (all cleanup types)
+      uint32_t m_cpt_cleanup_cost;            // Number of (flits * distance) for CLEANUPs (all types)
 
       // Counters not accessible by software, but tagged
-      uint32_t m_cpt_read_miss;       // Number of MISS READ
-      uint32_t m_cpt_write_miss;      // Number of MISS WRITE
-      uint32_t m_cpt_write_dirty;     // Cumulated length for WRITE transactions
-      uint32_t m_cpt_write_broadcast; // Number of BROADCAST INVAL because write
-
-      uint32_t m_cpt_trt_rb;          // Read blocked by a hit in trt
-      uint32_t m_cpt_trt_full;        // Transaction blocked due to a full trt
+      uint32_t m_cpt_read_miss;               // Number of MISS READ
+      uint32_t m_cpt_write_miss;              // Number of MISS WRITE
+      uint32_t m_cpt_write_dirty;             // Cumulated length for WRITE transactions
+      uint32_t m_cpt_write_broadcast;         // Number of BROADCAST INVAL because write
+
+      uint32_t m_cpt_trt_rb;                  // Read blocked by a hit in trt
+      uint32_t m_cpt_trt_full;                // Transaction blocked due to a full trt
 
       uint32_t m_cpt_heap_unused;             // NB cycles HEAP LOCK unused
@@ -481 +479 @@
       uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available
 
-      uint32_t m_cpt_ncc_to_cc_read;         // NB change from NCC to CC caused by a READ
-      uint32_t m_cpt_ncc_to_cc_write;        // NB change from NCC to CC caused by a WRITE
-
-      uint32_t m_cpt_cleanup_data_local;  // Number of local cleanups with data
-      uint32_t m_cpt_cleanup_data_remote; // Number of remote cleanups with data
-      uint32_t m_cpt_cleanup_data_cost;   // Cost for cleanups with data
-
-      uint32_t m_cpt_update_flits;  // Number of flits for UPDATEs
-      uint32_t m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
+      uint32_t m_cpt_ncc_to_cc_read;          // NB change from NCC to CC caused by a READ
+      uint32_t m_cpt_ncc_to_cc_write;         // NB change from NCC to CC caused by a WRITE
+
+      uint32_t m_cpt_cleanup_data_local;      // Number of local cleanups with data
+      uint32_t m_cpt_cleanup_data_remote;     // Number of remote cleanups with data
+      uint32_t m_cpt_cleanup_data_cost;       // Cost for cleanups with data
+
+      uint32_t m_cpt_update_flits;            // Number of flits for UPDATEs
+      uint32_t m_cpt_inval_cost;              // Number of (flits * distance) for INVALs
 
       uint32_t m_cpt_get;
@@ -499 +497 @@
       uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused
 
-      // Unused
-      uint32_t m_cpt_read_data_unc;
-      uint32_t m_cpt_read_data_miss_CC;
-      uint32_t m_cpt_read_ins_unc;
-      uint32_t m_cpt_read_ins_miss;
-      uint32_t m_cpt_read_ll_CC;
-      uint32_t m_cpt_read_data_miss_NCC;
-      uint32_t m_cpt_read_ll_NCC;
-
       size_t   m_prev_count;
 
@@ -515 +504 @@
 
       public:
-      sc_in<bool>                                 p_clk;
-      sc_in<bool>                                 p_resetn;
-      sc_out<bool>                                p_irq;
-      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
-      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
-      soclib::caba::DspinInput<dspin_in_width>    p_dspin_p2m;
-      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_m2p;
-      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_clack;
+      sc_in<bool>                                p_clk;
+      sc_in<bool>                                p_resetn;
+      sc_out<bool>                               p_irq;
+      soclib::caba::VciTarget<vci_param_int>     p_vci_tgt;
+      soclib::caba::VciInitiator<vci_param_ext>  p_vci_ixr;
+      soclib::caba::DspinInput<dspin_in_width>   p_dspin_p2m;
+      soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p;
+      soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack;
 
 #if MONITOR_MEMCACHE_FSM == 1
@@ -557 +546 @@
           const size_t                       nwords,          // Number of words per line
           const size_t                       max_copies,      // max number of copies
-          const size_t                       heap_size=HEAP_ENTRIES,
-          const size_t                       trt_lines=TRT_ENTRIES,
-          const size_t                       upt_lines=UPT_ENTRIES,
-          const size_t                       ivt_lines=IVT_ENTRIES,
-          const size_t                       debug_start_cycle=0,
-          const bool                         debug_ok=false );
+          const size_t                       heap_size = HEAP_ENTRIES,
+          const size_t                       trt_lines = TRT_ENTRIES,
+          const size_t                       upt_lines = UPT_ENTRIES,
+          const size_t                       ivt_lines = IVT_ENTRIES,
+          const size_t                       debug_start_cycle = 0,
+          const bool                         debug_ok = false );
 
       ~VciMemCache();
@@ -568 +557 @@
       void reset_counters();
       void print_stats(bool activity_counters = true, bool stats = false);
-      void print_trace( size_t detailled = 0 );
+      void print_trace(size_t detailled = 0);
       void cache_monitor(addr_t addr);
       void start_monitor(addr_t addr, addr_t length);
@@ -581 +570 @@
       uint32_t min_value(uint32_t old_value, uint32_t new_value);
       bool is_local_req(uint32_t req_srcid);
-      int  read_instrumentation(uint32_t regr, uint32_t & rdata);
+      int read_instrumentation(uint32_t regr, uint32_t & rdata);
 
       // Component attributes
@@ -616 +605 @@
 
       // adress masks
-      const soclib::common::AddressMaskingTable<addr_t>   m_x;
-      const soclib::common::AddressMaskingTable<addr_t>   m_y;
-      const soclib::common::AddressMaskingTable<addr_t>   m_z;
-      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
+      const soclib::common::AddressMaskingTable<addr_t> m_x;
+      const soclib::common::AddressMaskingTable<addr_t> m_y;
+      const soclib::common::AddressMaskingTable<addr_t> m_z;
+      const soclib::common::AddressMaskingTable<addr_t> m_nline;
 
       // broadcast address
-      uint32_t                           m_broadcast_boundaries;
+      uint32_t m_broadcast_boundaries;
 
       // configuration interface constants
@@ -632 +621 @@
 
       // Fifo between TGT_CMD fsm and READ fsm
-      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
-      GenericFifo<size_t>    m_cmd_read_length_fifo;
-      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
-      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
-      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
+      GenericFifo<addr_t> m_cmd_read_addr_fifo;
+      GenericFifo<size_t> m_cmd_read_length_fifo;
+      GenericFifo<size_t> m_cmd_read_srcid_fifo;
+      GenericFifo<size_t> m_cmd_read_trdid_fifo;
+      GenericFifo<size_t> m_cmd_read_pktid_fifo;
 
       // Fifo between TGT_CMD fsm and WRITE fsm
-      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
-      GenericFifo<bool>      m_cmd_write_eop_fifo;
-      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
-      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
-      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
-      GenericFifo<data_t>    m_cmd_write_data_fifo;
-      GenericFifo<be_t>      m_cmd_write_be_fifo;
+      GenericFifo<addr_t> m_cmd_write_addr_fifo;
+      GenericFifo<bool>   m_cmd_write_eop_fifo;
+      GenericFifo<size_t> m_cmd_write_srcid_fifo;
+      GenericFifo<size_t> m_cmd_write_trdid_fifo;
+      GenericFifo<size_t> m_cmd_write_pktid_fifo;
+      GenericFifo<data_t> m_cmd_write_data_fifo;
+      GenericFifo<be_t>   m_cmd_write_be_fifo;
 
       // Fifo between TGT_CMD fsm and CAS fsm
-      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
-      GenericFifo<bool>      m_cmd_cas_eop_fifo;
-      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
-      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
-      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
-      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
+      GenericFifo<addr_t> m_cmd_cas_addr_fifo;
+      GenericFifo<bool>   m_cmd_cas_eop_fifo;
+      GenericFifo<size_t> m_cmd_cas_srcid_fifo;
+      GenericFifo<size_t> m_cmd_cas_trdid_fifo;
+      GenericFifo<size_t> m_cmd_cas_pktid_fifo;
+      GenericFifo<data_t> m_cmd_cas_wdata_fifo;
 
       // Fifo between CC_RECEIVE fsm and CLEANUP fsm
-      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
+      GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
 
       // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
-      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
+      GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
 
       // Buffer between TGT_CMD fsm and TGT_RSP fsm
@@ -678 +667 @@
       //////////////////////////////////////////////////
 
-      sc_signal<int>         r_tgt_cmd_fsm;
+      sc_signal<int> r_tgt_cmd_fsm;
 
       ///////////////////////////////////////////////////////
@@ -684 +673 @@
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_config_fsm;               // FSM state
-      sc_signal<bool>     r_config_lock;              // lock protecting exclusive access
-      sc_signal<int>      r_config_cmd;               // config request type
-      sc_signal<addr_t>   r_config_address;           // target buffer physical address
-      sc_signal<size_t>   r_config_srcid;             // config request srcid
-      sc_signal<size_t>   r_config_trdid;             // config request trdid
-      sc_signal<size_t>   r_config_pktid;             // config request pktid
-      sc_signal<size_t>   r_config_cmd_lines;         // number of lines to be handled
-      sc_signal<size_t>   r_config_rsp_lines;         // number of lines not completed
-      sc_signal<size_t>   r_config_dir_way;           // DIR: selected way
-      sc_signal<bool>     r_config_dir_lock;          // DIR: locked entry
-      sc_signal<size_t>   r_config_dir_count;         // DIR: number of copies
-      sc_signal<bool>     r_config_dir_is_cnt;        // DIR: counter mode (broadcast)
-      sc_signal<size_t>   r_config_dir_copy_srcid;    // DIR: first copy SRCID
-      sc_signal<bool>     r_config_dir_copy_inst;     // DIR: first copy L1 type
-      sc_signal<size_t>   r_config_dir_ptr;           // DIR: index of next copy in HEAP
-      sc_signal<size_t>   r_config_heap_next;         // current pointer to scan HEAP
-      sc_signal<size_t>   r_config_trt_index;         // selected entry in TRT
-      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT
+      sc_signal<int>    r_config_fsm;            // FSM state
+      sc_signal<bool>   r_config_lock;           // lock protecting exclusive access
+      sc_signal<int>    r_config_cmd;            // config request type
+      sc_signal<addr_t> r_config_address;        // target buffer physical address
+      sc_signal<size_t> r_config_srcid;          // config request srcid
+      sc_signal<size_t> r_config_trdid;          // config request trdid
+      sc_signal<size_t> r_config_pktid;          // config request pktid
+      sc_signal<size_t> r_config_cmd_lines;      // number of lines to be handled
+      sc_signal<size_t> r_config_rsp_lines;      // number of lines not completed
+      sc_signal<size_t> r_config_dir_way;        // DIR: selected way
+      sc_signal<bool>   r_config_dir_lock;       // DIR: locked entry
+      sc_signal<size_t> r_config_dir_count;      // DIR: number of copies
+      sc_signal<bool>   r_config_dir_is_cnt;     // DIR: counter mode (broadcast)
+      sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
+      sc_signal<bool>   r_config_dir_copy_inst;  // DIR: first copy L1 type
+      sc_signal<size_t> r_config_dir_ptr;        // DIR: index of next copy in HEAP
+      sc_signal<size_t> r_config_heap_next;      // current pointer to scan HEAP
+      sc_signal<size_t> r_config_trt_index;      // selected entry in TRT
+      sc_signal<size_t> r_config_ivt_index;      // selected entry in IVT
 
       // Buffer between CONFIG fsm and IXR_CMD fsm
-      sc_signal<bool>     r_config_to_ixr_cmd_req;    // valid request
-      sc_signal<size_t>   r_config_to_ixr_cmd_index;  // TRT index
+      sc_signal<bool>   r_config_to_ixr_cmd_req;   // valid request
+      sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index
 
       // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
-      sc_signal<bool>     r_config_to_tgt_rsp_req;    // valid request
-      sc_signal<bool>     r_config_to_tgt_rsp_error;  // error response
-      sc_signal<size_t>   r_config_to_tgt_rsp_srcid;  // Transaction srcid
-      sc_signal<size_t>   r_config_to_tgt_rsp_trdid;  // Transaction trdid
-      sc_signal<size_t>   r_config_to_tgt_rsp_pktid;  // Transaction pktid
+      sc_signal<bool>   r_config_to_tgt_rsp_req;   // valid request
+      sc_signal<bool>   r_config_to_tgt_rsp_error; // error response
+      sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
 
       // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
-      sc_signal<bool>     r_config_to_cc_send_multi_req;    // multi-inval request
-      sc_signal<bool>     r_config_to_cc_send_brdcast_req;  // broadcast-inval request
-      sc_signal<addr_t>   r_config_to_cc_send_nline;        // line index
-      sc_signal<size_t>   r_config_to_cc_send_trdid;        // UPT index
-      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;    // fifo for the L1 type
-      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
+      sc_signal<bool>     r_config_to_cc_send_multi_req;   // multi-inval request
+      sc_signal<bool>     r_config_to_cc_send_brdcast_req; // broadcast-inval request
+      sc_signal<addr_t>   r_config_to_cc_send_nline;       // line index
+      sc_signal<size_t>   r_config_to_cc_send_trdid;       // UPT index
+      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;   // fifo for the L1 type
+      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;  // fifo for owners srcid
 
       ///////////////////////////////////////////////////////
@@ -727 +716 @@
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_read_fsm;                 // FSM state
-      sc_signal<size_t>   r_read_copy;                // Srcid of the first copy
-      sc_signal<size_t>   r_read_copy_cache;          // Srcid of the first copy
-      sc_signal<bool>     r_read_copy_inst;           // Type of the first copy
-      sc_signal<tag_t>    r_read_tag;                 // cache line tag (in directory)
-      sc_signal<bool>     r_read_is_cnt;              // is_cnt bit (in directory)
-      sc_signal<bool>     r_read_lock;                // lock bit (in directory)
-      sc_signal<bool>     r_read_dirty;               // dirty bit (in directory)
-      sc_signal<size_t>   r_read_count;               // number of copies
-      sc_signal<size_t>   r_read_ptr;                 // pointer to the heap
-      sc_signal<data_t> * r_read_data;                // data (one cache line)
-      sc_signal<size_t>   r_read_way;                 // associative way (in cache)
-      sc_signal<size_t>   r_read_trt_index;           // Transaction Table index
-      sc_signal<size_t>   r_read_next_ptr;            // Next entry to point to
-      sc_signal<bool>     r_read_last_free;           // Last free entry
-      sc_signal<addr_t>   r_read_ll_key;              // LL key from llsc_global_table
+      sc_signal<int>      r_read_fsm;        // FSM state
+      sc_signal<size_t>   r_read_copy;       // Srcid of the first copy
+      sc_signal<size_t>   r_read_copy_cache; // Srcid of the first copy
+      sc_signal<bool>     r_read_copy_inst;  // Type of the first copy
+      sc_signal<tag_t>    r_read_tag;        // cache line tag (in directory)
+      sc_signal<bool>     r_read_is_cnt;     // is_cnt bit (in directory)
+      sc_signal<bool>     r_read_lock;       // lock bit (in directory)
+      sc_signal<bool>     r_read_dirty;      // dirty bit (in directory)
+      sc_signal<size_t>   r_read_count;      // number of copies
+      sc_signal<size_t>   r_read_ptr;        // pointer to the heap
+      sc_signal<data_t> * r_read_data;       // data (one cache line)
+      sc_signal<size_t>   r_read_way;        // associative way (in cache)
+      sc_signal<size_t>   r_read_trt_index;  // Transaction Table index
+      sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
+      sc_signal<bool>     r_read_last_free;  // Last free entry
+      sc_signal<addr_t>   r_read_ll_key;     // LL key from llsc_global_table
 
       // Buffer between READ fsm and IXR_CMD fsm
-      sc_signal<bool>     r_read_to_ixr_cmd_req;      // valid request
-      sc_signal<size_t>   r_read_to_ixr_cmd_index;    // TRT index
+      sc_signal<bool>     r_read_to_ixr_cmd_req;   // valid request
+      sc_signal<size_t>   r_read_to_ixr_cmd_index; // TRT index
 
       // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
-      sc_signal<bool>     r_read_to_tgt_rsp_req;      // valid request
-      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;    // Transaction srcid
-      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;    // Transaction trdid
-      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;    // Transaction pktid
-      sc_signal<data_t> * r_read_to_tgt_rsp_data;     // data (one cache line)
-      sc_signal<size_t>   r_read_to_tgt_rsp_word;     // first word of the response
-      sc_signal<size_t>   r_read_to_tgt_rsp_length;   // length of the response
-      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key;   // LL key from llsc_global_table
+      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
+      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
+      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
+      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
+      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
+      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
+      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
+      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table
 
       //RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
@@ -777 +766 @@
 
       //RWT:
-      sc_signal<bool>     r_read_coherent;          // State of the cache slot after transaction
+      sc_signal<bool>     r_read_coherent; // State of the cache slot after transaction
       sc_signal<bool>     r_read_ll_done;
 
@@ -839 +828 @@
 
       // RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
-      sc_signal<bool>     r_write_to_cleanup_req;         // valid request
-      sc_signal<addr_t>   r_write_to_cleanup_nline;       // cache line index
+      sc_signal<bool>     r_write_to_cleanup_req;    // valid request
+      sc_signal<addr_t>   r_write_to_cleanup_nline;  // cache line index
 
       // RWT
-      sc_signal<bool>     r_write_coherent;               // cache slot state after transaction
+      sc_signal<bool>     r_write_coherent;          // cache slot state after transaction
 
       //Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
@@ -1114 +1103 @@
 
       sc_signal<bool>      r_cleanup_ncc;
-      sc_signal<bool>      r_cleanup_to_ixr_cmd_ncc_l1_dirty;
-      sc_signal<bool>      r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
 
       sc_signal<bool>      r_cleanup_to_ixr_cmd_req;

branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h

@@ -15 +15 @@
 class TransactionTabEntry
 {
-    typedef sc_dt::sc_uint<64>    wide_data_t;
-    typedef sc_dt::sc_uint<40>    addr_t;
-    typedef uint32_t              data_t;
-    typedef uint32_t              be_t;
+    typedef sc_dt::sc_uint<64> wide_data_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t           data_t;
+    typedef uint32_t           be_t;
 
     public:
@@ -154 +154 @@
 class TransactionTab
 {
-    typedef sc_dt::sc_uint<64>    wide_data_t;
-    typedef sc_dt::sc_uint<40>    addr_t;
-    typedef uint32_t              data_t;
-    typedef uint32_t              be_t;
+    typedef sc_dt::sc_uint<64> wide_data_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t           data_t;
+    typedef uint32_t           be_t;
 
     private:
-    const std::string tab_name;                // the name for logs
-    size_t            size_tab;                // the size of the tab
+    const std::string tab_name; // the name for logs
+    size_t            size_tab; // the size of the tab
 
     data_t be_to_mask(be_t be)
     {
         data_t ret = 0;
-        if ( be&0x1 ) {
+        if (be & 0x1) {
             ret = ret | 0x000000FF;
         }
-        if ( be&0x2 ) {
+        if (be & 0x2) {
             ret = ret | 0x0000FF00;
         }
-        if ( be&0x4 ) {
+        if (be & 0x4) {
             ret = ret | 0x00FF0000;
         }
-        if ( be&0x8 ) {
+        if (be & 0x8) {
             ret = ret | 0xFF000000;
         }
@@ -189 +189 @@
     TransactionTab()
     {
-        size_tab=0;
-        tab=NULL;
+        size_tab = 0;
+        tab = NULL;
     }
 
@@ -196 +196 @@
                    size_t            n_entries,
                    size_t            n_words )
-    : tab_name( name ),
-      size_tab( n_entries )
+    : tab_name(name),
+      size_tab(n_entries)
     {
         tab = new TransactionTabEntry[size_tab];
-        for ( size_t i=0; i<size_tab; i++)
+        for (size_t i = 0; i < size_tab; i++)
         {
             tab[i].alloc(n_words);
@@ -222 +222 @@
     void init()
     {
-        for ( size_t i=0; i<size_tab; i++)
+        for (size_t i = 0; i < size_tab; i++)
         {
             tab[i].init();
@@ -234 +234 @@
     void print(const size_t index)
     {
-        assert( (index < size_tab) and
+        assert((index < size_tab) and
         "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()");
 
@@ -247 +247 @@
     TransactionTabEntry read(const size_t index)
     {
-        assert( (index < size_tab) and
+        assert((index < size_tab) and
         "MEMC ERROR: Invalid Transaction Tab Entry");
 
@@ -260 +260 @@
     bool full(size_t &index)
     {
-        for(size_t i=0; i<size_tab; i++)
-        {
-            if(!tab[i].valid)
+        for (size_t i = 0; i < size_tab; i++)
+        {
+            if (!tab[i].valid)
             {
-                index=i;
+                index = i;
                 return false;
             }
@@ -278 +278 @@
     // The function returns true if a read request has already been sent
     //////////////////////////////////////////////////////////////////////
-    bool hit_read(const addr_t nline,size_t &index)
-    {
-        for(size_t i=0; i<size_tab; i++)
-        {
-            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read))
+    bool hit_read(const addr_t nline, size_t &index)
+    {
+        for (size_t i = 0; i < size_tab; i++)
+        {
+            if ((tab[i].valid && (nline == tab[i].nline)) && (tab[i].xram_read))
             {
-                index=i;
+                index = i;
                 return true;
             }
@@ -299 +299 @@
     bool hit_write(const addr_t nline)
     {
-        for(size_t i=0; i<size_tab; i++)
-        {
-            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read))
+        for (size_t i = 0; i < size_tab; i++)
+        {
+            if(tab[i].valid && (nline == tab[i].nline) && !(tab[i].xram_read))
             {
                 return true;
@@ -319 +319 @@
     bool hit_write(const addr_t nline, size_t* index)
     {
-        for(size_t i=0; i<size_tab; i++){
-            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+        for (size_t i = 0; i < size_tab; i++){
+            if (tab[i].valid && (nline == tab[i].nline) && !(tab[i].xram_read)) {
                 *index = i;
                 return true;
@@ -337 +337 @@
     /////////////////////////////////////////////////////////////////////
     void write_data_mask(const size_t index,
-            const std::vector<be_t> &be,
-            const std::vector<data_t> &data)
-    {
-        assert( (index < size_tab) and
+                         const std::vector<be_t> &be,
+                         const std::vector<data_t> &data)
+    {
+        assert((index < size_tab) and
         "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()");
 
-        assert( (be.size()==tab[index].wdata_be.size()) and
+        assert((be.size() == tab[index].wdata_be.size()) and
         "MEMC ERROR: Bad be size in TRT write_data_mask()");
 
-        assert( (data.size()==tab[index].wdata.size()) and
+        assert((data.size() == tab[index].wdata.size()) and
         "MEMC ERROR: Bad data size in TRT write_data_mask()");
 
-        for(size_t i=0; i<tab[index].wdata_be.size() ; i++)
+        for (size_t i = 0; i < tab[index].wdata_be.size(); i++)
         {
             tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
@@ -375 +375 @@
     /////////////////////////////////////////////////////////////////////
     void set(const size_t index,
-            const bool xram_read,
-            const addr_t nline,
-            const size_t srcid,
-            const size_t trdid,
-            const size_t pktid,
-            const bool proc_read,
-            const size_t read_length,
-            const size_t word_index,
-            const std::vector<be_t> &data_be,
-            const std::vector<data_t> &data,
-            const data_t ll_key = 0,
-            const bool config = false)
-    {
-        assert( (index < size_tab) and
+             const bool xram_read,
+             const addr_t nline,
+             const size_t srcid,
+             const size_t trdid,
+             const size_t pktid,
+             const bool proc_read,
+             const size_t read_length,
+             const size_t word_index,
+             const std::vector<be_t> &data_be,
+             const std::vector<data_t> &data,
+             const data_t ll_key = 0,
+             const bool config = false)
+    {
+        assert((index < size_tab) and
         "MEMC ERROR: The selected entry is out of range in TRT set()");
 
-        assert( (data_be.size()==tab[index].wdata_be.size()) and
+        assert((data_be.size() == tab[index].wdata_be.size()) and
         "MEMC ERROR: Bad data_be argument in TRT set()");
 
-        assert( (data.size()==tab[index].wdata.size()) and
+        assert((data.size() == tab[index].wdata.size()) and
         "MEMC ERROR: Bad data argument in TRT set()");
 
@@ -408 +408 @@
         tab[index].ll_key      = ll_key;
         tab[index].config      = config;
-        for(size_t i=0; i<tab[index].wdata.size(); i++)
-        {
-            tab[index].wdata_be[i]    = data_be[i];
-            tab[index].wdata[i]       = data[i];
+        for (size_t i = 0; i < tab[index].wdata.size(); i++)
+        {
+            tab[index].wdata_be[i] = data_be[i];
+            tab[index].wdata[i]    = data[i];
         }
     }
@@ -429 +429 @@
                    const bool        rerror)
     {
-        data_t  value;
-        data_t  mask;
-
-        assert( (index < size_tab) and
+        data_t value;
+        data_t mask;
+
+        assert((index < size_tab) and
         "MEMC ERROR: The selected entry is out of range in TRT write_rsp()");
 
-        assert( (word < tab[index].wdata_be.size()) and
+        assert((word < tab[index].wdata_be.size()) and
         "MEMC ERROR: Bad word index in TRT write_rsp()");
 
-        assert( (tab[index].valid) and
+        assert((tab[index].valid) and
         "MEMC ERROR: TRT entry not valid in TRT write_rsp()");
 
-        assert( (tab[index].xram_read ) and
+        assert((tab[index].xram_read ) and
         "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()");
 
-        if ( rerror )
+        if (rerror)
         {
             tab[index].rerror = true;
@@ -456 +456 @@
 
         // second 32 bits word
-        value = (data_t)(data>>32);
-        mask  = be_to_mask(tab[index].wdata_be[word+1]);
-        tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask);
+        value = (data_t)(data >> 32);
+        mask  = be_to_mask(tab[index].wdata_be[word + 1]);
+        tab[index].wdata[word + 1] = (tab[index].wdata[word + 1] & mask) | (value & ~mask);
     }
     /////////////////////////////////////////////////////////////////////
@@ -467 +467 @@
     void erase(const size_t index)
     {
-        assert( (index < size_tab) and
+        assert((index < size_tab) and
         "MEMC ERROR: The selected entry is out of range in TRT erase()");
 
@@ -480 +480 @@
     bool is_config(const size_t index)
     {
-        assert( (index < size_tab) and
+        assert((index < size_tab) and
         "MEMC ERROR: The selected entry is out of range in TRT is_config()");
 

branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -1 +1 @@
 /* -*- c++ -*-
-*
-* File       : vci_mem_cache.cpp
-* Date       : 30/10/2008
-* Copyright  : UPMC / LIP6
-* Authors    : Alain Greiner / Eric Guthmuller
-*
-* SOCLIB_LGPL_HEADER_BEGIN
-*
-* This file is part of SoCLib, GNU LGPLv2.1.
-*
-* SoCLib is free software; you can redistribute it and/or modify it
-* under the terms of the GNU Lesser General Public License as published
-* by the Free Software Foundation; version 2.1 of the License.
-*
-* SoCLib is distributed in the hope that it will be useful, but
-* WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-* Lesser General Public License for more details.
-*
-* You should have received a copy of the GNU Lesser General Public
-* License along with SoCLib; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
-* 02110-1301 USA
-*
-* SOCLIB_LGPL_HEADER_END
-*
-* Maintainers: alain.greiner@lip6.fr
-*              eric.guthmuller@polytechnique.edu
-*              cesar.fuguet-tortolero@lip6.fr
-*              alexandre.joannou@lip6.fr
-*/
+ *
+ * File       : vci_mem_cache.cpp
+ * Date       : 30/10/2008
+ * Copyright  : UPMC / LIP6
+ * Authors    : Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain.greiner@lip6.fr
+ *              eric.guthmuller@polytechnique.edu
+ *              cesar.fuguet-tortolero@lip6.fr
+ *              alexandre.joannou@lip6.fr
+ */
+
 
 #include "../include/vci_mem_cache.h"
+#include "mem_cache.h"
 
 //////   debug services   /////////////////////////////////////////////////////////////
@@ -96 +98 @@
         "CC_RECEIVE_IDLE",
         "CC_RECEIVE_CLEANUP",
-        "CC_RECEIVE_CLEANUP_EOP",
         "CC_RECEIVE_MULTI_ACK"
     };
@@ -203 +204 @@
     {
         "IXR_RSP_IDLE",
-        "IXR_RSP_ACK",
         "IXR_RSP_TRT_ERASE",
         "IXR_RSP_TRT_READ"
@@ -355 +355 @@
 
     tmpl(/**/) ::VciMemCache(
-            sc_module_name      name,
-            const MappingTable  &mtp,              // mapping table for direct network
-            const MappingTable  &mtx,              // mapping table for external network
-            const IntTab        &srcid_x,          // global index on external network
-            const IntTab        &tgtid_d,          // global index on direct network
-            const size_t        x_width,           // number of x bits in platform
-            const size_t        y_width,           // number of x bits in platform
-            const size_t        nways,             // number of ways per set
-            const size_t        nsets,             // number of associative sets
-            const size_t        nwords,            // number of words in cache line
-            const size_t        max_copies,        // max number of copies in heap
-            const size_t        heap_size,         // number of heap entries
-            const size_t        trt_lines,         // number of TRT entries
-            const size_t        upt_lines,         // number of UPT entries
-            const size_t        ivt_lines,         // number of IVT entries
-            const size_t        debug_start_cycle,
-            const bool          debug_ok)
+            sc_module_name     name,
+            const MappingTable &mtp,       // mapping table for direct network
+            const MappingTable &mtx,       // mapping table for external network
+            const IntTab       &srcid_x,   // global index on external network
+            const IntTab       &tgtid_d,   // global index on direct network
+            const size_t       x_width,    // number of x bits in platform
+            const size_t       y_width,    // number of x bits in platform
+            const size_t       nways,      // number of ways per set
+            const size_t       nsets,      // number of associative sets
+            const size_t       nwords,     // number of words in cache line
+            const size_t       max_copies, // max number of copies in heap
+            const size_t       heap_size,  // number of heap entries
+            const size_t       trt_lines,  // number of TRT entries
+            const size_t       upt_lines,  // number of UPT entries
+            const size_t       ivt_lines,  // number of IVT entries
+            const size_t       debug_start_cycle,
+            const bool         debug_ok)
 
         : soclib::caba::BaseModule(name),
 
-        p_clk( "p_clk" ),
-        p_resetn( "p_resetn" ),
-        p_irq( "p_irq" ),
-        p_vci_tgt( "p_vci_tgt" ),
-        p_vci_ixr( "p_vci_ixr" ),
-        p_dspin_p2m( "p_dspin_p2m" ),
-        p_dspin_m2p( "p_dspin_m2p" ),
-        p_dspin_clack( "p_dspin_clack" ),
+        p_clk("p_clk"),
+        p_resetn("p_resetn"),
+        p_irq("p_irq"),
+        p_vci_tgt("p_vci_tgt"),
+        p_vci_ixr("p_vci_ixr"),
+        p_dspin_p2m("p_dspin_p2m"),
+        p_dspin_m2p("p_dspin_m2p"),
+        p_dspin_clack("p_dspin_clack"),
 
         m_seglist(mtp.getSegmentList(tgtid_d)),
         m_nseg(0),
-        m_srcid_x( mtx.indexForId(srcid_x)),
+        m_srcid_x(mtx.indexForId(srcid_x)),
         m_initiators(1 << vci_param_int::S),
         m_heap_size(heap_size),
@@ -394 +394 @@
         m_x_width(x_width),
         m_y_width(y_width),
-        m_debug_start_cycle( debug_start_cycle ),
-        m_debug_ok( debug_ok ),
+        m_debug_start_cycle(debug_start_cycle),
+        m_debug_ok(debug_ok),
         m_trt_lines(trt_lines),
         m_trt(this->name(), trt_lines, nwords),
@@ -404 +404 @@
         m_cache_data(nways, nsets, nwords),
         m_heap(m_heap_size),
-        m_max_copies( max_copies ),
+        m_max_copies(max_copies),
         m_llsc_table(),
 
@@ -419 +419 @@
 
         // CONFIG interface
-        m_config_addr_mask((1<<12)-1),
+        m_config_addr_mask((1 << 12) - 1),
 
         m_config_regr_width(7),
         m_config_func_width(3),
-        m_config_regr_idx_mask((1<<m_config_regr_width)-1),
-        m_config_func_idx_mask((1<<m_config_func_width)-1),
+        m_config_regr_idx_mask((1 << m_config_regr_width) - 1),
+        m_config_func_idx_mask((1 << m_config_func_width) - 1),
 
         //  FIFOs
@@ -453 +453 @@
         r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
 
-        r_config_fsm( "r_config_fsm" ),
-
-        m_config_to_cc_send_inst_fifo( "m_config_to_cc_send_inst_fifo", 8 ),
-        m_config_to_cc_send_srcid_fifo( "m_config_to_cc_send_srcid_fifo", 8 ),
-
-        r_read_fsm( "r_read_fsm" ),
-
-        r_write_fsm( "r_write_fsm" ),
+        r_config_fsm("r_config_fsm"),
+
+        m_config_to_cc_send_inst_fifo("m_config_to_cc_send_inst_fifo", 8),
+        m_config_to_cc_send_srcid_fifo("m_config_to_cc_send_srcid_fifo", 8),
+
+        r_read_fsm("r_read_fsm"),
+
+        r_write_fsm("r_write_fsm"),
 
         m_write_to_cc_send_inst_fifo("m_write_to_cc_send_inst_fifo",8),
@@ -495 +495 @@
         r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt")
 #if MONITOR_MEMCACHE_FSM == 1
-            ,
+        ,
         p_read_fsm("p_read_fsm"),
         p_write_fsm("p_write_fsm"),
@@ -530 +530 @@
 
             // check internal and external data width
-            assert( (vci_param_int::B == 4 ) and
+            assert((vci_param_int::B == 4) and
                     "MEMC ERROR : VCI internal data width must be 32 bits");
 
-            assert( (vci_param_ext::B == 8) and
+            assert((vci_param_ext::B == 8) and
                     "MEMC ERROR : VCI external data width must be 64 bits");
 
             // Check coherence between internal & external addresses
-            assert( (vci_param_int::N == vci_param_ext::N) and
+            assert((vci_param_int::N == vci_param_ext::N) and
                     "MEMC ERROR : VCI internal & external addresses must have the same width");
 
@@ -544 +544 @@
             size_t i = 0;
 
-            for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++)
+            for (seg = m_seglist.begin(); seg != m_seglist.end(); seg++)
             {
                 std::cout << "    => segment " << seg->name()
@@ -552 +552 @@
             }
 
-            assert( (m_nseg > 0) and
+            assert((m_nseg > 0) and
                     "MEMC ERROR : At least one segment must be mapped to this component");
 
             m_seg = new soclib::common::Segment*[m_nseg];
 
-            for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++)
-            {
-                if ( seg->special() ) m_seg_config = i;
+            for (seg = m_seglist.begin(); seg != m_seglist.end(); seg++)
+            {
+                if (seg->special()) m_seg_config = i;
                 m_seg[i] = & (*seg);
                 i++;
@@ -574 +574 @@
             r_xram_rsp_victim_data     = new sc_signal<data_t>[nwords];
             r_xram_rsp_to_tgt_rsp_data = new sc_signal<data_t>[nwords];
-            //r_xram_rsp_to_ixr_cmd_data = new sc_signal<data_t>[nwords];
 
             // Allocation for READ FSM
@@ -585 +584 @@
             r_write_to_cc_send_data    = new sc_signal<data_t>[nwords];
             r_write_to_cc_send_be      = new sc_signal<be_t>[nwords];
-            //r_write_to_ixr_cmd_data    = new sc_signal<data_t>[nwords];
 
             // Allocation for CAS FSM
-            //r_cas_to_ixr_cmd_data      = new sc_signal<data_t>[nwords];
             r_cas_data                 = new sc_signal<data_t>[nwords];
             r_cas_rdata                = new sc_signal<data_t>[2];
@@ -624 +621 @@
         bool data_change = false;
 
-        if ( entry.valid )
+        if (entry.valid)
         {
-            for ( size_t word = 0 ; word<m_words ; word++ )
+            for (size_t word = 0; word < m_words; word++)
             {
                 m_debug_data[word] = m_cache_data.read(way, set, word);
-                if ( m_debug_previous_valid and
-                        (m_debug_data[word] != m_debug_previous_data[word]) )
+                if (m_debug_previous_valid and
+                     (m_debug_data[word] != m_debug_previous_data[word]))
                 {
                     data_change = true;
@@ -638 +635 @@
 
         // print values if any change
-        if ( (entry.valid != m_debug_previous_valid) or
-                (entry.valid and (entry.count != m_debug_previous_count)) or
-                (entry.valid and (entry.dirty != m_debug_previous_dirty)) or data_change )
+        if ((entry.valid != m_debug_previous_valid) or
+            (entry.valid and (entry.count != m_debug_previous_count)) or
+            (entry.valid and (entry.dirty != m_debug_previous_dirty)) or data_change)
         {
             std::cout << "Monitor MEMC " << name()
@@ -672 +669 @@
         m_debug_previous_valid = entry.valid;
         m_debug_previous_dirty = entry.dirty;
-        for( size_t word=0 ; word<m_words ; word++ )
+        for (size_t word = 0; word < m_words; word++)
             m_debug_previous_data[word] = m_debug_data[word];
     }
@@ -814 +811 @@
 
     //////////////////////////////////////////////////
-    tmpl(void)::print_trace( size_t detailed )
+    tmpl(void)::print_trace(size_t detailed)
     //////////////////////////////////////////////////
     {
@@ -837 +834 @@
             << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl;
 
-        if ( detailed ) m_trt.print(0);
+        if (detailed) m_trt.print(0);
     }
 
@@ -910 +907 @@
         std::cout << "*** MEM_CACHE " << name() << std::endl;
         std::cout << "**********************************" << std::dec << std::endl;
-        if (activity_counters) {
+        if (activity_counters)
+        {
             std::cout << "----------------------------------" << std::dec << std::endl;
             std::cout << "---     Activity Counters      ---" << std::dec << std::endl;
@@ -1026 +1024 @@
 
         // RESET
-        if(! p_resetn.read())
+        if (!p_resetn.read())
         {
 
@@ -1075 +1073 @@
             m_cmd_write_data_fifo.init();
 
-            m_cmd_cas_addr_fifo.init()  ;
-            m_cmd_cas_srcid_fifo.init() ;
-            m_cmd_cas_trdid_fifo.init() ;
-            m_cmd_cas_pktid_fifo.init() ;
-            m_cmd_cas_wdata_fifo.init() ;
-            m_cmd_cas_eop_fifo.init()   ;
+            m_cmd_cas_addr_fifo.init();
+            m_cmd_cas_srcid_fifo.init();
+            m_cmd_cas_trdid_fifo.init();
+            m_cmd_cas_pktid_fifo.init();
+            m_cmd_cas_wdata_fifo.init();
+            m_cmd_cas_eop_fifo.init();
 
             r_config_cmd  = MEMC_CMD_NOP;
@@ -1095 +1093 @@
             r_read_to_cleanup_req = false;
 
-            r_write_to_tgt_rsp_req          = false;
-            r_write_to_ixr_cmd_req          = false;
-            r_write_to_cc_send_multi_req    = false;
-            r_write_to_cc_send_brdcast_req  = false;
-            r_write_to_multi_ack_req        = false;
+            r_write_to_tgt_rsp_req         = false;
+            r_write_to_ixr_cmd_req         = false;
+            r_write_to_cc_send_multi_req   = false;
+            r_write_to_cc_send_brdcast_req = false;
+            r_write_to_multi_ack_req       = false;
 
             m_write_to_cc_send_inst_fifo.init();
@@ -1108 +1106 @@
             m_cc_receive_to_cleanup_fifo.init();
 
-            r_multi_ack_to_tgt_rsp_req     = false;
+            r_multi_ack_to_tgt_rsp_req    = false;
 
             m_cc_receive_to_multi_ack_fifo.init();
@@ -1121 +1119 @@
             m_cas_to_cc_send_inst_fifo.init();
             m_cas_to_cc_send_srcid_fifo.init();
-#if L1_MULTI_CACHE
-            m_cas_to_cc_send_cache_id_fifo.init();
-#endif
-
-            for(size_t i=0; i<m_trt_lines ; i++)
+
+            for (size_t i = 0; i < m_trt_lines; i++)
             {
                 r_ixr_rsp_to_xram_rsp_rok[i] = false;
@@ -1152 +1147 @@
             r_cleanup_contains_data    = false;
             r_cleanup_ncc              = false;
-            r_cleanup_to_ixr_cmd_ncc_l1_dirty    = false;
-            r_xram_rsp_to_ixr_cmd_inval_ncc_pending    = false;
             r_cleanup_to_ixr_cmd_req   = false;
             r_cleanup_to_ixr_cmd_srcid = 0;
@@ -1166 +1159 @@
 
             // Activity counters
+            m_cpt_cycles              = 0;
             m_cpt_reset_count         = 0;
-            m_cpt_cycles              = 0;
             m_cpt_read_local          = 0;
             m_cpt_read_remote         = 0;
@@ -1220 +1213 @@
             m_cpt_put                 = 0;
 
-            m_cpt_ncc_to_cc_read          = 0;
-            m_cpt_ncc_to_cc_write         = 0;
+            m_cpt_ncc_to_cc_read      = 0;
+            m_cpt_ncc_to_cc_write     = 0;
+
+            m_cpt_dir_unused          = 0;
+            m_cpt_upt_unused          = 0;
+            m_cpt_ivt_unused          = 0;
+            m_cpt_heap_unused         = 0;
+            m_cpt_trt_unused          = 0;
 
             m_cpt_heap_min_slot_available = m_heap_size;
             m_cpt_heap_slot_available     = m_heap_size;
 
-            m_cpt_dir_unused              = 0;
-            m_cpt_upt_unused              = 0;
-            m_cpt_ivt_unused              = 0;
-            m_cpt_heap_unused             = 0;
-            m_cpt_trt_unused              = 0;
-
-            // Unused
-            m_cpt_read_data_unc           = 0;
-            m_cpt_read_data_miss_CC       = 0;
-            m_cpt_read_ins_unc            = 0;
-            m_cpt_read_ins_miss           = 0;
-            m_cpt_read_ll_CC              = 0;
-            m_cpt_read_data_miss_NCC      = 0;
-            m_cpt_read_ll_NCC             = 0;
-
             return;
         }
 
-        bool    cmd_read_fifo_put = false;
-        bool    cmd_read_fifo_get = false;
-
-        bool    cmd_write_fifo_put = false;
-        bool    cmd_write_fifo_get = false;
-
-        bool    cmd_cas_fifo_put = false;
-        bool    cmd_cas_fifo_get = false;
-
-        bool    cc_receive_to_cleanup_fifo_get = false;
-        bool    cc_receive_to_cleanup_fifo_put = false;
-
-        bool    cc_receive_to_multi_ack_fifo_get = false;
-        bool    cc_receive_to_multi_ack_fifo_put = false;
-
-        bool    write_to_cc_send_fifo_put   = false;
-        bool    write_to_cc_send_fifo_get   = false;
-        bool    write_to_cc_send_fifo_inst  = false;
-        size_t  write_to_cc_send_fifo_srcid = 0;
-
-        bool    xram_rsp_to_cc_send_fifo_put   = false;
-        bool    xram_rsp_to_cc_send_fifo_get   = false;
-        bool    xram_rsp_to_cc_send_fifo_inst  = false;
-        size_t  xram_rsp_to_cc_send_fifo_srcid = 0;
+        bool   cmd_read_fifo_put = false;
+        bool   cmd_read_fifo_get = false;
+
+        bool   cmd_write_fifo_put = false;
+        bool   cmd_write_fifo_get = false;
+
+        bool   cmd_cas_fifo_put = false;
+        bool   cmd_cas_fifo_get = false;
+
+        bool   cc_receive_to_cleanup_fifo_get = false;
+        bool   cc_receive_to_cleanup_fifo_put = false;
+
+        bool   cc_receive_to_multi_ack_fifo_get = false;
+        bool   cc_receive_to_multi_ack_fifo_put = false;
+
+        bool   write_to_cc_send_fifo_put   = false;
+        bool   write_to_cc_send_fifo_get   = false;
+        bool   write_to_cc_send_fifo_inst  = false;
+        size_t write_to_cc_send_fifo_srcid = 0;
+
+        bool   xram_rsp_to_cc_send_fifo_put   = false;
+        bool   xram_rsp_to_cc_send_fifo_get   = false;
+        bool   xram_rsp_to_cc_send_fifo_inst  = false;
+        size_t xram_rsp_to_cc_send_fifo_srcid = 0;
 
         bool   config_rsp_lines_incr          = false;
@@ -1273 +1257 @@
         bool   config_rsp_lines_ixr_rsp_decr  = false;
 
-        bool    config_to_cc_send_fifo_put   = false;
-        bool    config_to_cc_send_fifo_get   = false;
-        bool    config_to_cc_send_fifo_inst  = false;
-        size_t  config_to_cc_send_fifo_srcid = 0;
-
-        bool    cas_to_cc_send_fifo_put   = false;
-        bool    cas_to_cc_send_fifo_get   = false;
-        bool    cas_to_cc_send_fifo_inst  = false;
-        size_t  cas_to_cc_send_fifo_srcid = 0;
+        bool   config_to_cc_send_fifo_put   = false;
+        bool   config_to_cc_send_fifo_get   = false;
+        bool   config_to_cc_send_fifo_inst  = false;
+        size_t config_to_cc_send_fifo_srcid = 0;
+
+        bool   cas_to_cc_send_fifo_put   = false;
+        bool   cas_to_cc_send_fifo_get   = false;
+        bool   cas_to_cc_send_fifo_inst  = false;
+        size_t cas_to_cc_send_fifo_srcid = 0;
 
         m_debug = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
 
 #if DEBUG_MEMC_GLOBAL
-        if(m_debug)
+        if (m_debug)
         {
             std::cout
@@ -1336 +1320 @@
             //////////////////
             case TGT_CMD_IDLE:     // waiting a VCI command (RAM or CONFIG)
-                if(p_vci_tgt.cmdval)
-                {
-
-
+                if (p_vci_tgt.cmdval)
+                {
 #if DEBUG_MEMC_TGT_CMD
-                    if(m_debug)
+                    if (m_debug)
+                    {
                         std::cout << "  <MEMC " << name()
                             << " TGT_CMD_IDLE> Receive command from srcid "
                             << std::hex << p_vci_tgt.srcid.read()
                             << " / address " << std::hex << p_vci_tgt.address.read() << std::endl;
+                    }
 #endif
                     // checking segmentation violation
@@ -1352 +1336 @@
                     bool     config  = false;
 
-                    for (size_t seg_id = 0; (seg_id < m_nseg) ; seg_id++)
+                    for (size_t seg_id = 0; seg_id < m_nseg; seg_id++)
                     {
                         if (m_seg[seg_id]->contains(address) &&
-                                m_seg[seg_id]->contains(address + plen - vci_param_int::B) )
+                                m_seg[seg_id]->contains(address + plen - vci_param_int::B))
                         {
-                            if ( m_seg[seg_id]->special() ) config = true;
+                            if (m_seg[seg_id]->special()) config = true;
                         }
                     }
 
-                    if (config)                     /////////// configuration command
+                    if (config)     /////////// configuration command
                     {
                         if (!p_vci_tgt.eop.read()) r_tgt_cmd_fsm = TGT_CMD_ERROR;
                         else                       r_tgt_cmd_fsm = TGT_CMD_CONFIG;
                     }
-                    else                            //////////// memory access
-                    {
-                        if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ )
+                    else           //////////// memory access
+                    {
+                        if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)
                         {
                             // check that the pktid is either :
@@ -1377 +1361 @@
                             // ==> bit2 must be zero with the TSAR encoding
                             // ==> mask = 0b0100 = 0x4
-                            assert( ((p_vci_tgt.pktid.read() & 0x4) == 0x0) and
+                            assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) and
                                     "The type specified in the pktid field is incompatible with the READ CMD");
                             r_tgt_cmd_fsm = TGT_CMD_READ;
                         }
-                        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
+                        else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
                         {
                             // check that the pktid is TYPE_WRITE
@@ -1390 +1374 @@
                             r_tgt_cmd_fsm = TGT_CMD_WRITE;
                         }
-                        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)
+                        else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)
                         {
                             // check that the pktid is TYPE_LL
@@ -1399 +1383 @@
                             r_tgt_cmd_fsm = TGT_CMD_READ;
                         }
-                        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)
+                        else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)
                         {
                             // check that the pktid is either :
@@ -1410 +1394 @@
                                     "The type specified in the pktid field is incompatible with the NOP CMD");
 
-                            if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS;
-                            else                                           r_tgt_cmd_fsm = TGT_CMD_WRITE;
+                            if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS)
+                            {
+                                r_tgt_cmd_fsm = TGT_CMD_CAS;
+                            }
+                            else
+                            {
+                                r_tgt_cmd_fsm = TGT_CMD_WRITE;
+                            }
                         }
                         else
@@ -1425 +1415 @@
 
                 // wait if pending request
-                if(r_tgt_cmd_to_tgt_rsp_req.read()) break;
+                if (r_tgt_cmd_to_tgt_rsp_req.read()) break;
 
                 // consume all the command packet flits before sending response error
-                if ( p_vci_tgt.cmdval and p_vci_tgt.eop )
+                if (p_vci_tgt.cmdval and p_vci_tgt.eop)
                 {
                     r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read();
@@ -1438 +1428 @@
 
 #if DEBUG_MEMC_TGT_CMD
-                    if(m_debug)
+                    if (m_debug)
+                    {
                         std::cout << "  <MEMC " << name()
                             << " TGT_CMD_ERROR> Segmentation violation:"
@@ -1446 +1437 @@
                             << " / pktid = " << p_vci_tgt.pktid.read()
                             << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
-#endif
-
+                    }
+#endif
                 }
                 break;
@@ -1453 +1444 @@
                 ////////////////////
             case TGT_CMD_CONFIG:    // execute config request and return response
-                {
-                    ///////////////////////////////////////////////////////////
-                    //  Decoding CONFIG interface commands                   //
-                    //                                                       //
-                    //  VCI ADDRESS                                          //
-                    //  ================================================     //
-                    //  GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00      //
-                    //   IDX   |  IDX  |     | (3 bits) | (7 bits) |         //
-                    //  ================================================     //
-                    //                                                       //
-                    //  For instrumentation : FUNC_IDX = 0b001               //
-                    //                                                       //
-                    //  REGS_IDX                                             //
-                    //  ============================================         //
-                    //       Z     |    Y      |    X     |   W              //
-                    //    (1 bit)  | (2 bits)  | (3 bits) | (1 bit)          //
-                    //  ============================================         //
-                    //                                                       //
-                    //  Z : DIRECT / COHERENCE                               //
-                    //  Y : SUBTYPE ( LOCAL, REMOTE, OTHER )                 //
-                    //  X : REGISTER INDEX                                   //
-                    //  W : HI / LO                                          //
-                    //                                                       //
-                    //  For configuration: FUNC_IDX = 0b000                  //
-                    //                                                       //
-                    //  REGS_IDX                                             //
-                    //  ============================================         //
-                    //             RESERVED             |    X     |         //
-                    //             (4 bits)             | (3 bits) |         //
-                    //  ============================================         //
-                    //                                                       //
-                    //  X : REGISTER INDEX                                   //
-                    //                                                       //
-                    //  For WRITE MISS error signaling: FUNC = 0x010         //
-                    //                                                       //
-                    //  REGS_IDX                                             //
-                    //  ============================================         //
-                    //             RESERVED             |    X     |         //
-                    //             (4 bits)             | (3 bits) |         //
-                    //  ============================================         //
-                    //                                                       //
-                    //  X : REGISTER INDEX                                   //
-                    //                                                       //
-                    ///////////////////////////////////////////////////////////
-
-                    addr_t addr_lsb = p_vci_tgt.address.read() &
-                                      m_config_addr_mask;
-
-                    addr_t cell = (addr_lsb / vci_param_int::B);
-
-                    size_t regr = cell &
-                                  m_config_regr_idx_mask;
-
-                    size_t func = (cell >> m_config_regr_width) &
-                                  m_config_func_idx_mask;
-
-                    bool     need_rsp;
-                    int      error;
-                    uint32_t rdata = 0;         // default value
-                    uint32_t wdata = p_vci_tgt.wdata.read();
-
-                    switch(func)
-                    {
-                        // memory operation
-                        case MEMC_CONFIG:
+            {
+                ///////////////////////////////////////////////////////////
+                //  Decoding CONFIG interface commands                   //
+                //                                                       //
+                //  VCI ADDRESS                                          //
+                //  ================================================     //
+                //  GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00      //
+                //   IDX   |  IDX  |     | (3 bits) | (7 bits) |         //
+                //  ================================================     //
+                //                                                       //
+                //  For instrumentation : FUNC_IDX = 0b001               //
+                //                                                       //
+                //  REGS_IDX                                             //
+                //  ============================================         //
+                //       Z     |    Y      |    X     |   W              //
+                //    (1 bit)  | (2 bits)  | (3 bits) | (1 bit)          //
+                //  ============================================         //
+                //                                                       //
+                //  Z : DIRECT / COHERENCE                               //
+                //  Y : SUBTYPE (LOCAL, REMOTE, OTHER)                   //
+                //  X : REGISTER INDEX                                   //
+                //  W : HI / LO                                          //
+                //                                                       //
+                //  For configuration: FUNC_IDX = 0b000                  //
+                //                                                       //
+                //  REGS_IDX                                             //
+                //  ============================================         //
+                //             RESERVED             |    X     |         //
+                //             (4 bits)             | (3 bits) |         //
+                //  ============================================         //
+                //                                                       //
+                //  X : REGISTER INDEX                                   //
+                //                                                       //
+                //  For WRITE MISS error signaling: FUNC = 0x010         //
+                //                                                       //
+                //  REGS_IDX                                             //
+                //  ============================================         //
+                //             RESERVED             |    X     |         //
+                //             (4 bits)             | (3 bits) |         //
+                //  ============================================         //
+                //                                                       //
+                //  X : REGISTER INDEX                                   //
+                //                                                       //
+                ///////////////////////////////////////////////////////////
+
+                addr_t addr_lsb = p_vci_tgt.address.read() & m_config_addr_mask;
+
+                addr_t cell = (addr_lsb / vci_param_int::B);
+
+                size_t regr = cell & m_config_regr_idx_mask;
+
+                size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask;
+
+                bool     need_rsp;
+                int      error;
+                uint32_t rdata = 0; // default value
+                uint32_t wdata = p_vci_tgt.wdata.read();
+
+                switch (func)
+                {
+                    // memory operation
+                    case MEMC_CONFIG:
+                    {
+                        if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock
+                                and (regr == MEMC_LOCK))
                         {
-                            if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)         // get lock
-                                    and (regr == MEMC_LOCK))
-                            {
-                                rdata            = (uint32_t) r_config_lock.read();
-                                need_rsp         = true;
-                                error            = 0;
-                                r_config_lock    = true;
-                            }
-                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)  // release lock
-                                    and (regr == MEMC_LOCK))
-                            {
-                                need_rsp      = true;
-                                error         = 0;
-                                r_config_lock = false;
-                            }
-                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
-                                    and (regr == MEMC_ADDR_LO))
-                            {
-                                assert( ((wdata % (m_words * vci_param_int::B)) == 0) and
-                                        "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line");
-
-                                need_rsp         = true;
-                                error            = 0;
-                                r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) |
-                                    ((addr_t)wdata);
-                            }
-                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_hi
-                                    and (regr == MEMC_ADDR_HI))
-
-                            {
-                                need_rsp         = true;
-                                error            = 0;
-                                r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) |
-                                    (((addr_t) wdata) << 32);
-                            }
-                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set buf_lines
-                                    and (regr == MEMC_BUF_LENGTH))
-                            {
-                                need_rsp         = true;
-                                error            = 0;
-                                size_t lines     = wdata / (m_words << 2);
-                                if (wdata % (m_words << 2)) lines++;
-                                r_config_cmd_lines = lines;
-                                r_config_rsp_lines = 0;
-                            }
-                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set cmd type
-                                    and (regr == MEMC_CMD_TYPE))
-                            {
-                                need_rsp         = false;
-                                error            = 0;
-                                r_config_cmd     = wdata;
-
-                                // prepare delayed response from CONFIG FSM
-                                r_config_srcid   = p_vci_tgt.srcid.read();
-                                r_config_trdid   = p_vci_tgt.trdid.read();
-                                r_config_pktid   = p_vci_tgt.pktid.read();
-                            }
-                            else
-                            {
-                                need_rsp         = true;
-                                error            = 1;
-                            }
-
-                            break;
+                            rdata         = (uint32_t) r_config_lock.read();
+                            need_rsp      = true;
+                            error         = 0;
+                            r_config_lock = true;
                         }
-
-                        // instrumentation registers
-                        case MEMC_INSTRM:
-                        {
-                            need_rsp = true;
-
-                            if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)
-                            {
-                                error = read_instrumentation(regr, rdata);
-                            }
-                            else
-                            {
-                                error = 1;
-                            }
-
-                            break;
-                        }
-
-                        // xram GET bus error registers
-                        case MEMC_RERROR:
+                        else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)  // release lock
+                                and (regr == MEMC_LOCK))
                         {
                             need_rsp = true;
                             error    = 0;
-
-                            if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
-                            {
-                                switch (regr)
-                                {
-                                    case MEMC_RERROR_IRQ_ENABLE:
-                                        r_xram_rsp_rerror_irq_enable =
-                                            (p_vci_tgt.wdata.read() != 0);
-
-                                        break;
-
-                                    default:
-                                        error = 1;
-                                        break;
-                                }
-                            }
-                            else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)
-                            {
-                                switch (regr)
-                                {
-                                    case MEMC_RERROR_SRCID:
-                                        rdata = (uint32_t)
-                                            r_xram_rsp_rerror_rsrcid.read();
-
-                                        break;
-
-                                    case MEMC_RERROR_ADDR_LO:
-                                        rdata = (uint32_t)
-                                            (r_xram_rsp_rerror_address.read()) &
-                                            ((1ULL<<32)-1);
-
-                                        break;
-
-                                    case MEMC_RERROR_ADDR_HI:
-                                        rdata = (uint32_t)
-                                            (r_xram_rsp_rerror_address.read() >> 32) &
-                                            ((1ULL<<32)-1);
-
-                                        break;
-
-                                    case MEMC_RERROR_IRQ_RESET:
-                                        if (not r_xram_rsp_rerror_irq.read()) break;
-
-                                        r_xram_rsp_rerror_irq = false;
-
-                                        break;
-
-                                    case MEMC_RERROR_IRQ_ENABLE:
-                                        rdata = (uint32_t)
-                                            (r_xram_rsp_rerror_irq_enable.read()) ? 1 : 0;
-
-                                        break;
-
-                                    default:
-                                        error = 1;
-                                        break;
-                                }
-                            }
-                            else
-                            {
-                                error = 1;
-                            }
-
-                            break;
+                            r_config_lock = false;
                         }
-
-                        //unknown function
-                        default:
+                        else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
+                                and (regr == MEMC_ADDR_LO))
+                        {
+                            assert(((wdata % (m_words * vci_param_int::B)) == 0) and
+                                    "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line");
+
+                            need_rsp = true;
+                            error    = 0;
+                            r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) |
+                                ((addr_t)wdata);
+                        }
+                        else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_hi
+                                and (regr == MEMC_ADDR_HI))
+
+                        {
+                            need_rsp = true;
+                            error    = 0;
+                            r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) |
+                                (((addr_t) wdata) << 32);
+                        }
+                        else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set buf_lines
+                                and (regr == MEMC_BUF_LENGTH))
+                        {
+                            need_rsp = true;
+                            error    = 0;
+                            size_t lines = wdata / (m_words << 2);
+                            if (wdata % (m_words << 2)) lines++;
+                            r_config_cmd_lines = lines;
+                            r_config_rsp_lines = 0;
+                        }
+                        else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set cmd type
+                                and (regr == MEMC_CMD_TYPE))
+                        {
+                            need_rsp     = false;
+                            error        = 0;
+                            r_config_cmd = wdata;
+
+                            // prepare delayed response from CONFIG FSM
+                            r_config_srcid = p_vci_tgt.srcid.read();
+                            r_config_trdid = p_vci_tgt.trdid.read();
+                            r_config_pktid = p_vci_tgt.pktid.read();
+                        }
+                        else
                         {
                             need_rsp = true;
                             error    = 1;
-
-                            break;
                         }
-                    }
-
-                    if (need_rsp)
-                    {
-                        // blocked if previous pending request to TGT_RSP FSM
-                        if (r_tgt_cmd_to_tgt_rsp_req.read()) break;
-
-                        r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read();
-                        r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read();
-                        r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read();
-                        r_tgt_cmd_to_tgt_rsp_req   = true;
-                        r_tgt_cmd_to_tgt_rsp_error = error;
-                        r_tgt_cmd_to_tgt_rsp_rdata = rdata;
-                    }
-
-                    r_tgt_cmd_fsm = TGT_CMD_IDLE;
+
+                        break;
+                    }
+
+                    // instrumentation registers
+                    case MEMC_INSTRM:
+                    {
+                        need_rsp = true;
+
+                        if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)
+                        {
+                            error = read_instrumentation(regr, rdata);
+                        }
+                        else
+                        {
+                            error = 1;
+                        }
+
+                        break;
+                    }
+
+                    // xram GET bus error registers
+                    case MEMC_RERROR:
+                    {
+                        need_rsp = true;
+                        error    = 0;
+
+                        if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
+                        {
+                            switch (regr)
+                            {
+                                case MEMC_RERROR_IRQ_ENABLE:
+                                    r_xram_rsp_rerror_irq_enable =
+                                        (p_vci_tgt.wdata.read() != 0);
+
+                                    break;
+
+                                default:
+                                    error = 1;
+                                    break;
+                            }
+                        }
+                        else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)
+                        {
+                            switch (regr)
+                            {
+                                case MEMC_RERROR_SRCID:
+                                    rdata = (uint32_t)
+                                        r_xram_rsp_rerror_rsrcid.read();
+                                    break;
+
+                                case MEMC_RERROR_ADDR_LO:
+                                    rdata = (uint32_t)
+                                        (r_xram_rsp_rerror_address.read()) & ((1ULL << 32) - 1);
+                                    break;
+
+                                case MEMC_RERROR_ADDR_HI:
+                                    rdata = (uint32_t)
+                                        (r_xram_rsp_rerror_address.read() >> 32) & ((1ULL << 32) - 1);
+                                    break;
+
+                                case MEMC_RERROR_IRQ_RESET:
+                                    if (not r_xram_rsp_rerror_irq.read()) break;
+                                    r_xram_rsp_rerror_irq = false;
+                                    break;
+
+                                case MEMC_RERROR_IRQ_ENABLE:
+                                    rdata = (uint32_t) (r_xram_rsp_rerror_irq_enable.read()) ? 1 : 0;
+                                    break;
+
+                                default:
+                                    error = 1;
+                                    break;
+                            }
+                        }
+                        else
+                        {
+                            error = 1;
+                        }
+
+                        break;
+                    }
+
+                    //unknown function
+                    default:
+                    {
+                        need_rsp = true;
+                        error = 1;
+                        break;
+                    }
+                }
+
+                if (need_rsp)
+                {
+                    // blocked if previous pending request to TGT_RSP FSM
+                    if (r_tgt_cmd_to_tgt_rsp_req.read()) break;
+
+                    r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read();
+                    r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read();
+                    r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read();
+                    r_tgt_cmd_to_tgt_rsp_req   = true;
+                    r_tgt_cmd_to_tgt_rsp_error = error;
+                    r_tgt_cmd_to_tgt_rsp_rdata = rdata;
+                }
+
+                r_tgt_cmd_fsm = TGT_CMD_IDLE;
 
 #if DEBUG_MEMC_TGT_CMD
-                    if (m_debug)
-                        std::cout << "  <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:"
-                            << " address = " << std::hex << p_vci_tgt.address.read()
-                            << " / func = " << func
-                            << " / regr = " << regr
-                            << " / rdata = " << rdata
-                            << " / wdata = " << p_vci_tgt.wdata.read()
-                            << " / need_rsp = " << need_rsp
-                            << " / error = " << error << std::endl;
-#endif
-                    break;
-                }
-
-#if 0
-            case TGT_CMD_CONFIG:    // execute config request and return response
-                {
-                    addr_t   seg_base = m_seg[m_seg_config]->baseAddress();
-                    addr_t   address  = p_vci_tgt.address.read();
-                    size_t   cell     = (address - seg_base)/vci_param_int::B;
-
-                    bool     need_rsp;
-                    size_t   error;
-                    uint32_t rdata = 0;         // default value
-                    uint32_t wdata = p_vci_tgt.wdata.read();
-
-                    if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)         // get lock
-                            and (cell == MEMC_LOCK) )
-                    {
-                        rdata            = (uint32_t)r_config_lock.read();
-                        need_rsp         = true;
-                        error            = 0;
-                        r_config_lock    = true;
-                    }
-                    else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)  // release lock
-                            and (cell == MEMC_LOCK))
-                    {
-                        need_rsp         = true;
-                        error            = 0;
-                        r_config_lock    = false;
-                    }
-                    else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
-                            and (cell == MEMC_ADDR_LO))
-                    {
-                        assert( ((wdata % (m_words*vci_param_int::B)) == 0) and
-                                "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line");
-
-                        need_rsp         = true;
-                        error            = 0;
-                        r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) |
-                            ((addr_t)wdata);
-                    }
-                    else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_hi
-                            and (cell == MEMC_ADDR_HI))
-                    {
-                        need_rsp         = true;
-                        error            = 0;
-                        r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) |
-                            (((addr_t) wdata) << 32);
-                    }
-                    else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set buf_lines
-                            and (cell == MEMC_BUF_LENGTH))
-                    {
-                        need_rsp         = true;
-                        error            = 0;
-                        size_t lines     = wdata / (m_words << 2);
-                        if (wdata % (m_words << 2)) lines++;
-                        r_config_cmd_lines  = lines;
-                        r_config_rsp_lines  = 0;
-                    }
-                    else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set cmd type
-                            and (cell == MEMC_CMD_TYPE))
-                    {
-                        need_rsp         = false;
-                        error            = 0;
-                        r_config_cmd     = wdata;
-                        r_config_srcid   = p_vci_tgt.srcid.read();
-                        r_config_trdid   = p_vci_tgt.trdid.read();
-                        r_config_pktid   = p_vci_tgt.pktid.read();
-                    }
-                    else
-                    {
-                        need_rsp         = true;
-                        error            = 1;
-                    }
-
-                    if ( need_rsp )
-                    {
-                        // blocked if previous pending request to TGT_RSP FSM
-                        if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break;
-
-                        r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read();
-                        r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read();
-                        r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read();
-                        r_tgt_cmd_to_tgt_rsp_req   = true;
-                        r_tgt_cmd_to_tgt_rsp_error = error;
-                        r_tgt_cmd_to_tgt_rsp_rdata = rdata;
-                        r_tgt_cmd_fsm              = TGT_CMD_IDLE;
-                    }
-                    else
-                    {
-                        r_tgt_cmd_fsm              = TGT_CMD_IDLE;
-                    }
-
-#if DEBUG_MEMC_TGT_CMD
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:"
-                            << " address = " << std::hex << p_vci_tgt.address.read()
-                            << " / wdata = " << p_vci_tgt.wdata.read()
-                            << " / need_rsp = " << need_rsp
-                            << " / error = " << error << std::endl;
-#endif
-                    break;
-                }
-#endif                         // #if 0
-                //////////////////
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:"
+                        << " address = " << std::hex << p_vci_tgt.address.read()
+                        << " / func = " << func
+                        << " / regr = " << regr
+                        << " / rdata = " << rdata
+                        << " / wdata = " << p_vci_tgt.wdata.read()
+                        << " / need_rsp = " << need_rsp
+                        << " / error = " << error << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////
             case TGT_CMD_READ:    // Push a read request into read fifo
 
                 // check that the read does not cross a cache line limit.
-                if ( ((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) and
+                if (((m_x[(addr_t) p_vci_tgt.address.read()] + (p_vci_tgt.plen.read() >> 2)) > 16) and
                         (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ))
                 {
@@ -1825 +1703 @@
                 }
                 // check single flit
-                if(!p_vci_tgt.eop.read())
+                if (!p_vci_tgt.eop.read())
                 {
                     std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
@@ -1832 +1710 @@
                 }
                 // check plen for LL
-                if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and
-                        (p_vci_tgt.plen.read() != 8) )
+                if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and
+                        (p_vci_tgt.plen.read() != 8))
                 {
                     std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
@@ -1840 +1718 @@
                 }
 
-                if ( p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok() )
+                if (p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok())
                 {
 
 #if DEBUG_MEMC_TGT_CMD
-                    if(m_debug)
+                    if (m_debug)
+                    {
                         std::cout << "  <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:"
                             << " address = " << std::hex << p_vci_tgt.address.read()
@@ -1851 +1730 @@
                             << " / pktid = " << p_vci_tgt.pktid.read()
                             << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
+                    }
 #endif
                     cmd_read_fifo_put = true;
                     // <Activity counters>
-                    if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) {
+                    if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)
+                    {
                         if (is_local_req(p_vci_tgt.srcid.read()))
                         {
@@ -1864 +1745 @@
                         }
                         // (1 (CMD) + 2 (RSP)) VCI flits for LL => 2 + 3 dspin flits
-                        m_cpt_ll_cost += 5 * req_distance(p_vci_tgt.srcid.read()); // LL on a single word
+                        m_cpt_ll_cost += 5 * req_distance(p_vci_tgt.srcid.read());
                     }
                     else {
@@ -1885 +1766 @@
                 ///////////////////
             case TGT_CMD_WRITE:
-                if(p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok())
+                if (p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok())
                 {
                     uint32_t plen = p_vci_tgt.plen.read();
 #if DEBUG_MEMC_TGT_CMD
-                    if(m_debug)
+                    if (m_debug)
+                    {
                         std::cout << "  <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:"
                             << " address = " << std::hex << p_vci_tgt.address.read()
@@ -1898 +1780 @@
                             << " / be = " << p_vci_tgt.be.read()
                             << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
+                    }
 #endif
                     cmd_write_fifo_put = true;
                     // <Activity counters>
-                    if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) {
+                    if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)
+                    {
                         // (2 (CMD) + 1 (RSP)) flits VCI => 4 + (1 (success) || 2 (failure)) flits dspin
                         m_cpt_sc_cost += 5 * req_distance(p_vci_tgt.srcid.read());
@@ -1919 +1803 @@
                     // </Activity counters>
 
-                    if (p_vci_tgt.eop) {
+                    if (p_vci_tgt.eop)
+                    {
                         // <Activity counters>
-                        if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) {
+                        if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)
+                        {
                             if (is_local_req(p_vci_tgt.srcid.read()))
                             {
@@ -1949 +1835 @@
                 /////////////////
             case TGT_CMD_CAS:
-                if((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16))
+                if ((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16))
                 {
                     std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state"
@@ -1956 +1842 @@
                 }
 
-                if(p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok())
+                if (p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok())
                 {
 
 #if DEBUG_MEMC_TGT_CMD
-                    if(m_debug)
+                    if (m_debug)
+                    {
                         std::cout << "  <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:"
                             << " address = " << std::hex << p_vci_tgt.address.read()
@@ -1969 +1856 @@
                             << " be = " << p_vci_tgt.be.read()
                             << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
+                    }
 #endif
                     cmd_cas_fifo_put = true;
-                    if (p_vci_tgt.eop) {
+                    if (p_vci_tgt.eop)
+                    {
                         // <Activity counters>
                         if (is_local_req(p_vci_tgt.srcid.read()))
@@ -2005 +1894 @@
         ////////////////////////////////////////////////////////////////////////
 
-        switch(r_multi_ack_fsm.read())
+        switch (r_multi_ack_fsm.read())
         {
             ////////////////////
             case MULTI_ACK_IDLE:
-                {
-                    bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok();
-
-                    // No CC_RECEIVE FSM request and no WRITE FSM request
-                    if( not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read())
-                        break;
-
-                    uint8_t updt_index;
-
-                    // handling WRITE FSM request to decrement update table response
-                    // counter if no CC_RECEIVE FSM request
-                    if(not multi_ack_fifo_rok)
-                    {
-                        updt_index               = r_write_to_multi_ack_upt_index.read();
-                        r_write_to_multi_ack_req = false;
-                    }
-                    // Handling CC_RECEIVE FSM request
+            {
+                bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok();
+
+                // No CC_RECEIVE FSM request and no WRITE FSM request
+                if (not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read())
+                    break;
+
+                uint8_t updt_index;
+
+                // handling WRITE FSM request to decrement update table response
+                // counter if no CC_RECEIVE FSM request
+                if (not multi_ack_fifo_rok)
+                {
+                    updt_index               = r_write_to_multi_ack_upt_index.read();
+                    r_write_to_multi_ack_req = false;
+                }
+                // Handling CC_RECEIVE FSM request
+                else
+                {
+                    uint64_t flit = m_cc_receive_to_multi_ack_fifo.read();
+                    updt_index = DspinRwtParam::dspin_get(flit,
+                            DspinRwtParam::MULTI_ACK_UPDT_INDEX);
+
+                    cc_receive_to_multi_ack_fifo_get = true;
+                }
+
+                assert((updt_index < m_upt.size()) and
+                        "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : "
+                        "index too large for UPT");
+
+                r_multi_ack_upt_index = updt_index;
+                r_multi_ack_fsm       = MULTI_ACK_UPT_LOCK;
+
+#if DEBUG_MEMC_MULTI_ACK
+                if (m_debug)
+                {
+                    if (multi_ack_fifo_rok)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " MULTI_ACK_IDLE> Response for UPT entry "
+                            << (size_t) updt_index << std::endl;
+                    }
                     else
                     {
-                        uint64_t flit = m_cc_receive_to_multi_ack_fifo.read();
-                        updt_index    = DspinRwtParam::dspin_get(flit,
-                                DspinRwtParam::MULTI_ACK_UPDT_INDEX);
-
-                        cc_receive_to_multi_ack_fifo_get = true;
-                    }
-
-                    assert((updt_index < m_upt.size()) and
-                            "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : "
-                            "index too large for UPT");
-
-                    r_multi_ack_upt_index = updt_index;
-                    r_multi_ack_fsm       = MULTI_ACK_UPT_LOCK;
+                        std::cout << "  <MEMC " << name()
+                            << " MULTI_ACK_IDLE> Write FSM request to decrement UPT entry "
+                            << updt_index << std::endl;
+                    }
+                }
+#endif
+                break;
+            }
+
+            ////////////////////////
+            case MULTI_ACK_UPT_LOCK:
+            {
+                // get lock to the UPDATE table
+                if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break;
+
+                // decrement the number of expected responses
+                size_t count = 0;
+                bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count);
+
+                if (not valid)
+                {
+                    std::cout << "VCI_MEM_CACHE ERROR " << name()
+                        << " MULTI_ACK_UPT_LOCK state" << std::endl
+                        << "unsuccessful access to decrement the UPT" << std::endl;
+                    exit(0);
+                }
+
+                if (count == 0)
+                {
+                    r_multi_ack_fsm = MULTI_ACK_UPT_CLEAR;
+                }
+                else
+                {
+                    r_multi_ack_fsm = MULTI_ACK_IDLE;
+                }
 
 #if DEBUG_MEMC_MULTI_ACK
-                    if(m_debug)
-                    {
-                        if (multi_ack_fifo_rok)
-                        {
-                            std::cout << "  <MEMC " << name()
-                                << " MULTI_ACK_IDLE> Response for UPT entry "
-                                << (size_t)updt_index << std::endl;
-                        }
-                        else
-                        {
-                            std::cout << "  <MEMC " << name()
-                                << " MULTI_ACK_IDLE> Write FSM request to decrement UPT entry "
-                                << updt_index << std::endl;
-                        }
-                    }
-#endif
-                    break;
-                }
-
-                ////////////////////////
-            case MULTI_ACK_UPT_LOCK:
-                {
-                    // get lock to the UPDATE table
-                    if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK)  break;
-
-                    // decrement the number of expected responses
-                    size_t count = 0;
-                    bool valid   = m_upt.decrement(r_multi_ack_upt_index.read(), count);
-
-
-                    if(not valid)
-                    {
-                        std::cout << "VCI_MEM_CACHE ERROR " << name()
-                            << " MULTI_ACK_UPT_LOCK state" << std::endl
-                            << "unsuccessful access to decrement the UPT" << std::endl;
-                        exit(0);
-                    }
-
-                    if(count == 0)
-                    {
-                        r_multi_ack_fsm = MULTI_ACK_UPT_CLEAR;
-                    }
-                    else
-                    {
-                        r_multi_ack_fsm = MULTI_ACK_IDLE;
-                    }
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:"
+                        << " entry = "       << r_multi_ack_upt_index.read()
+                        << " / rsp_count = " << std::dec << count << std::endl;
+                }
+#endif
+                break;
+            }
+
+            /////////////////////////
+            case MULTI_ACK_UPT_CLEAR:   // Clear UPT entry / Test if rsp or ack required
+            {
+                if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK)
+                {
+                    std::cout << "VCI_MEM_CACHE ERROR " << name()
+                        << " MULTI_ACK_UPT_CLEAR state"
+                        << " bad UPT allocation" << std::endl;
+                    exit(0);
+                }
+
+                r_multi_ack_srcid = m_upt.srcid(r_multi_ack_upt_index.read());
+                r_multi_ack_trdid = m_upt.trdid(r_multi_ack_upt_index.read());
+                r_multi_ack_pktid = m_upt.pktid(r_multi_ack_upt_index.read());
+                r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read());
+                bool need_rsp     = m_upt.need_rsp(r_multi_ack_upt_index.read());
+
+                // clear the UPT entry
+                m_upt.clear(r_multi_ack_upt_index.read());
+
+                if (need_rsp) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP;
+                else          r_multi_ack_fsm = MULTI_ACK_IDLE;
 
 #if DEBUG_MEMC_MULTI_ACK
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:"
-                            << " entry = "       << r_multi_ack_upt_index.read()
-                            << " / rsp_count = " << std::dec << count << std::endl;
-#endif
-                    break;
-                }
-
-                /////////////////////////
-            case MULTI_ACK_UPT_CLEAR:   // Clear UPT entry / Test if rsp or ack required
-                {
-                    if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK)
-                    {
-                        std::cout << "VCI_MEM_CACHE ERROR " << name()
-                            << " MULTI_ACK_UPT_CLEAR state"
-                            << " bad UPT allocation" << std::endl;
-                        exit(0);
-                    }
-
-                    r_multi_ack_srcid = m_upt.srcid(r_multi_ack_upt_index.read());
-                    r_multi_ack_trdid = m_upt.trdid(r_multi_ack_upt_index.read());
-                    r_multi_ack_pktid = m_upt.pktid(r_multi_ack_upt_index.read());
-                    r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read());
-                    bool need_rsp     = m_upt.need_rsp(r_multi_ack_upt_index.read());
-
-                    // clear the UPT entry
-                    m_upt.clear(r_multi_ack_upt_index.read());
-
-                    if      ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP;
-                    else                 r_multi_ack_fsm = MULTI_ACK_IDLE;
+                if (m_debug)
+                {
+                    std::cout <<  "  <MEMC " << name()
+                        << " MULTI_ACK_UPT_CLEAR> Clear UPT entry "
+                        << std::dec << r_multi_ack_upt_index.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////////////
+            case MULTI_ACK_WRITE_RSP:     // Post a response request to TGT_RSP FSM
+            // Wait if pending request
+            {
+                if (r_multi_ack_to_tgt_rsp_req.read()) break;
+
+                r_multi_ack_to_tgt_rsp_req   = true;
+                r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read();
+                r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read();
+                r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read();
+                r_multi_ack_fsm              = MULTI_ACK_IDLE;
 
 #if DEBUG_MEMC_MULTI_ACK
-                    if(m_debug)
-                        std::cout <<  "  <MEMC " << name()
-                            << " MULTI_ACK_UPT_CLEAR> Clear UPT entry "
-                            << std::dec << r_multi_ack_upt_index.read() << std::endl;
-#endif
-                    break;
-                }
-                /////////////////////////
-            case MULTI_ACK_WRITE_RSP:     // Post a response request to TGT_RSP FSM
-                // Wait if pending request
-                {
-                    if ( r_multi_ack_to_tgt_rsp_req.read() ) break;
-
-                    r_multi_ack_to_tgt_rsp_req   = true;
-                    r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read();
-                    r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read();
-                    r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read();
-                    r_multi_ack_fsm              = MULTI_ACK_IDLE;
-
-#if DEBUG_MEMC_MULTI_ACK
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " MULTI_ACK_WRITE_RSP>"
-                            << " Request TGT_RSP FSM to send a response to srcid "
-                            << std::hex << r_multi_ack_srcid.read() << std::endl;
-#endif
-                    break;
-                }
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " MULTI_ACK_WRITE_RSP>"
+                        << " Request TGT_RSP FSM to send a response to srcid "
+                        << std::hex << r_multi_ack_srcid.read() << std::endl;
+                }
+#endif
+                break;
+            }
         } // end switch r_multi_ack_fsm
 
@@ -2162 +2056 @@
         // An INVAL or SYNC configuration operation is defined by the following registers:
         // - bool      r_config_cmd        : INVAL / SYNC / NOP
-
         // - uint64_t  r_config_address    : buffer base address
         // - uint32_t  r_config_cmd_lines  : number of lines to be handled
         // - uint32_t  r_config_rsp_lines  : number of lines not completed
-
         //
         // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling
-        //
         // all cache lines covered by the buffer. The various lines of a given buffer
         // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send
@@ -2187 +2078 @@
         //   a response is requested to TGT_RSP FSM.
         //   If there is copies, a multi-inval, or a broadcast-inval coherence transaction
-        //
         //   is launched and registered in UPT. The multi-inval transaction completion
         //   is signaled by the CLEANUP FSM by decrementing the r_config_rsp_lines counter.
@@ -2215 +2105 @@
         ////////////////////////////////////////////////////////////////////////////////////
 
-        switch( r_config_fsm.read() )
+        switch (r_config_fsm.read())
         {
             /////////////////
             case CONFIG_IDLE:  // waiting a config request
-                {
-                    if ( r_config_cmd.read() != MEMC_CMD_NOP )
-                    {
-                        r_config_fsm    = CONFIG_LOOP;
+            {
+                if (r_config_cmd.read() != MEMC_CMD_NOP)
+                {
+                    r_config_fsm = CONFIG_LOOP;
 
 #if DEBUG_MEMC_CONFIG
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received"
-                                << " address = " << std::hex << r_config_address.read()
-                                << " / nlines = " << std::dec << r_config_cmd_lines.read()
-                                << " / type = " << r_config_cmd.read() << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////////
-            case CONFIG_LOOP:   // test last line to be handled
-                {
-                    if ( r_config_cmd_lines.read() == 0 )
-                    {
-                        r_config_cmd = MEMC_CMD_NOP;
-                        r_config_fsm = CONFIG_WAIT;
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received"
+                            << " / address = " << std::hex << r_config_address.read()
+                            << " / lines = " << std::dec << r_config_cmd_lines.read()
+                            << " / type = " << r_config_cmd.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////
+            case CONFIG_LOOP:   // test if last line to be handled
+            {
+                if (r_config_cmd_lines.read() == 0)
+                {
+                    r_config_cmd = MEMC_CMD_NOP;
+                    r_config_fsm = CONFIG_WAIT;
+                }
+                else
+                {
+                    r_config_fsm = CONFIG_DIR_REQ;
+                }
+
+#if DEBUG_MEMC_CONFIG
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CONFIG_LOOP>"
+                        << " / address = " << std::hex << r_config_address.read()
+                        << " / lines not handled = " << std::dec << r_config_cmd_lines.read()
+                        << " / command = " << r_config_cmd.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////
+            case CONFIG_WAIT:   // wait completion (last response)
+            {
+                if (r_config_rsp_lines.read() == 0)  // last response received
+                {
+                    r_config_fsm = CONFIG_RSP;
+                }
+
+#if DEBUG_MEMC_CONFIG
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CONFIG_WAIT>"
+                        << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////
+            case CONFIG_RSP:  // request TGT_RSP FSM to return response
+            {
+                if (not r_config_to_tgt_rsp_req.read())
+                {
+                    r_config_to_tgt_rsp_srcid = r_config_srcid.read();
+                    r_config_to_tgt_rsp_trdid = r_config_trdid.read();
+                    r_config_to_tgt_rsp_pktid = r_config_pktid.read();
+                    r_config_to_tgt_rsp_error = false;
+                    r_config_to_tgt_rsp_req   = true;
+                    r_config_fsm              = CONFIG_IDLE;
+
+#if DEBUG_MEMC_CONFIG
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to send response:"
+                            << " error = " << r_config_to_tgt_rsp_error.read()
+                            << " / rsrcid = " << std::hex << r_config_srcid.read()
+                            << " / rtrdid = " << std::hex << r_config_trdid.read()
+                            << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ////////////////////
+            case CONFIG_DIR_REQ:  // Request directory lock
+            {
+                if (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG)
+                {
+                    r_config_fsm = CONFIG_DIR_ACCESS;
+                }
+
+#if DEBUG_MEMC_CONFIG
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CONFIG_DIR_REQ>"
+                        << " Request DIR access" << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////
+            case CONFIG_DIR_ACCESS:   // Access directory and decode config command
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+                "MEMC ERROR in CONFIG_DIR_ACCESS state: bad DIR allocation");
+
+                size_t way = 0;
+                DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way);
+
+                r_config_dir_way        = way;
+                r_config_dir_copy_inst  = entry.owner.inst;
+                r_config_dir_copy_srcid = entry.owner.srcid;
+                r_config_dir_is_cnt     = entry.is_cnt;
+                r_config_dir_lock       = entry.lock;
+                r_config_dir_count      = entry.count;
+                r_config_dir_ptr        = entry.ptr;
+
+                if (entry.valid and   // hit & inval command
+                   (r_config_cmd.read() == MEMC_CMD_INVAL))
+                {
+                    r_config_fsm = CONFIG_IVT_LOCK;
+                }
+                else if (entry.valid and  // hit & sync command
+                         entry.dirty and
+                         (r_config_cmd.read() == MEMC_CMD_SYNC))
+                {
+                    r_config_fsm = CONFIG_TRT_LOCK;
+                }
+                else    // miss : return to LOOP
+                {
+                    r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+                    r_config_address   = r_config_address.read() + (m_words << 2);
+                    r_config_fsm       = CONFIG_LOOP;
+                }
+
+#if DEBUG_MEMC_CONFIG
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CONFIG_DIR_ACCESS> Accessing directory: "
+                        << " address = " << std::hex << r_config_address.read()
+                        << " / hit = " << std::dec << entry.valid
+                        << " / dirty = " << entry.dirty
+                        << " / count = " << entry.count
+                        << " / is_cnt = " << entry.is_cnt << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////////
+            case CONFIG_TRT_LOCK:      // enter this state in case of SYNC command
+                                       // to a dirty cache line
+                                       // keep DIR lock, and try to get TRT lock
+                                       // return to LOOP state if TRT full
+                                       // reset dirty bit in DIR and register a PUT
+                                       // transaction in TRT if not full.
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+                "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation");
+
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG)
+                {
+                    size_t index = 0;
+                    bool wok = not m_trt.full(index);
+
+                    if (not wok)
+                    {
+                        r_config_fsm = CONFIG_LOOP;
                     }
                     else
                     {
-                        r_config_fsm = CONFIG_DIR_REQ;
+                        size_t way = r_config_dir_way.read();
+                        size_t set = m_y[r_config_address.read()];
+
+                        // reset dirty bit in DIR
+                        DirectoryEntry entry;
+                        entry.valid       = true;
+                        entry.dirty       = false;
+                        entry.tag         = m_z[r_config_address.read()];
+                        entry.is_cnt      = r_config_dir_is_cnt.read();
+                        entry.lock        = r_config_dir_lock.read();
+                        entry.ptr         = r_config_dir_ptr.read();
+                        entry.count       = r_config_dir_count.read();
+                        entry.owner.inst  = r_config_dir_copy_inst.read();
+                        entry.owner.srcid = r_config_dir_copy_srcid.read();
+                        m_cache_directory.write(set, way, entry);
+
+                        r_config_trt_index = index;
+                        r_config_fsm       = CONFIG_TRT_SET;
                     }
 
 #if DEBUG_MEMC_CONFIG
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_LOOP>"
-                            << " address = " << std::hex << r_config_address.read()
-                            << " / nlines = " << std::dec << r_config_cmd_lines.read()
-                            << " / command = " << r_config_cmd.read() << std::endl;
-#endif
-                    break;
-                }
-                /////////////////
-            case CONFIG_WAIT:   // wait completion (last response)
-                {
-                    if ( r_config_rsp_lines.read() == 0 )  // last response received
-                    {
-                        r_config_fsm = CONFIG_RSP;
-                    }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CONFIG_TRT_LOCK> Access TRT: "
+                            << " wok = " << std::dec << wok
+                            << " index = " << index << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ////////////////////
+            case CONFIG_TRT_SET:       // read data in cache
+            // and post a PUT request in TRT
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+                "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation");
+
+                assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and
+                "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation");
+
+                // read data into cache
+                size_t way = r_config_dir_way.read();
+                size_t set = m_y[r_config_address.read()];
+                std::vector<data_t> data_vector;
+                data_vector.clear();
+                for (size_t word = 0; word < m_words; word++)
+                {
+                    uint32_t data = m_cache_data.read(way, set, word);
+                    data_vector.push_back(data);
+                }
+
+                // post the PUT request in TRT
+                m_trt.set(r_config_trt_index.read(),
+                          false,                            // PUT transaction
+                          m_nline[r_config_address.read()], // line index
+                          0,                                // srcid:       unused
+                          0,                                // trdid:       unused
+                          0,                                // pktid:       unused
+                          false,                            // not proc_read
+                          0,                                // read_length: unused
+                          0,                                // word_index:  unused
+                          std::vector<be_t>(m_words, 0xF),  // byte-enable: unused
+                          data_vector,                      // data to be written
+                          0,                                // ll_key:      unused
+                          true);                            // requested by config FSM
+                config_rsp_lines_incr = true;
+                r_config_fsm          = CONFIG_PUT_REQ;
 
 #if DEBUG_MEMC_CONFIG
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_WAIT>"
-                            << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl;
-#endif
-                    break;
-                }
-                ////////////////
-            case CONFIG_RSP:  // request TGT_RSP FSM to return response
-                {
-                    if ( not r_config_to_tgt_rsp_req.read() )
-                    {
-                        r_config_to_tgt_rsp_srcid  = r_config_srcid.read();
-                        r_config_to_tgt_rsp_trdid  = r_config_trdid.read();
-                        r_config_to_tgt_rsp_pktid  = r_config_pktid.read();
-                        r_config_to_tgt_rsp_error  = false;
-                        r_config_to_tgt_rsp_req    = true;
-                        r_config_fsm               = CONFIG_IDLE;
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:"
+                        << " address = " << std::hex << r_config_address.read()
+                        << " index = " << std::dec << r_config_trt_index.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////////
+            case CONFIG_PUT_REQ:       // post PUT request to IXR_CMD_FSM
+            {
+                if (not r_config_to_ixr_cmd_req.read())
+                {
+                    r_config_to_ixr_cmd_req   = true;
+                    r_config_to_ixr_cmd_index = r_config_trt_index.read();
+
+                    // prepare next iteration
+                    r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+                    r_config_address   = r_config_address.read() + (m_words << 2);
+                    r_config_fsm       = CONFIG_LOOP;
 
 #if DEBUG_MEMC_CONFIG
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:"
-                                << " error = " << r_config_to_tgt_rsp_error.read()
-                                << " / rsrcid = " << std::hex << r_config_srcid.read()
-                                << " / rtrdid = " << std::hex << r_config_trdid.read()
-                                << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl;
-#endif
-                    }
-                    break;
-
-                }
-
-                ////////////////////
-            case CONFIG_DIR_REQ:  // Request directory lock
-                {
-                    if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG )
-                    {
-                        r_config_fsm = CONFIG_DIR_ACCESS;
-                    }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM"
+                            << " / address = " << std::hex << r_config_address.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////
+            case CONFIG_IVT_LOCK:  // enter this state in case of INVAL command
+                                   // Keep DIR lock and Try to get IVT lock.
+                                   // Return to LOOP state if IVT full.
+                                   // Register inval in IVT, and invalidate the
+                                   // directory if IVT not full.
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+                "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation");
+
+                if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG)
+                {
+                    size_t set = m_y[(addr_t) (r_config_address.read())];
+                    size_t way = r_config_dir_way.read();
+
+                    if (r_config_dir_count.read() == 0)  // inval DIR and return to LOOP
+                    {
+                        m_cache_directory.inval(way, set);
+                        r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+                        r_config_address   = r_config_address.read() + (m_words << 2);
+                        r_config_fsm       = CONFIG_LOOP;
 
 #if DEBUG_MEMC_CONFIG
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_DIR_REQ>"
-                            << " Request DIR access" << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////
-            case CONFIG_DIR_ACCESS:   // Access directory and decode config command
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
-                            "MEMC ERROR in CONFIG_DIR_ACCESS state: bad DIR allocation");
-
-                    size_t way = 0;
-                    DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way);
-
-                    r_config_dir_way        = way;
-                    r_config_dir_copy_inst  = entry.owner.inst;
-                    r_config_dir_copy_srcid = entry.owner.srcid;
-                    r_config_dir_is_cnt     = entry.is_cnt;
-                    r_config_dir_count      = entry.count;
-                    r_config_dir_lock       = entry.lock;
-                    r_config_dir_ptr        = entry.ptr;
-
-                    if (entry.valid and                            // hit & inval command
-                            (r_config_cmd.read() == MEMC_CMD_INVAL))
-                    {
-                        r_config_fsm    = CONFIG_IVT_LOCK;
-                    }
-                    else if ( entry.valid and                       // hit & sync command
-                            entry.dirty and
-                            (r_config_cmd.read() == MEMC_CMD_SYNC) )
-                    {
-                        r_config_fsm = CONFIG_TRT_LOCK;
-                    }
-                    else                                            // return to LOOP
-                    {
-                        r_config_cmd_lines = r_config_cmd_lines.read() - 1;
-                        r_config_address   = r_config_address.read() + (m_words<<2);
-                        r_config_fsm       = CONFIG_LOOP;
-                    }
+                        if (m_debug)
+                        {
+                            std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
+                                << " No copies in L1 : inval DIR entry"  << std::endl;
+                        }
+#endif
+                    }
+                    else    // try to register inval in IVT
+                    {
+                        bool   wok       = false;
+                        size_t index     = 0;
+                        bool   broadcast = r_config_dir_is_cnt.read();
+                        size_t srcid     = r_config_srcid.read();
+                        size_t trdid     = r_config_trdid.read();
+                        size_t pktid     = r_config_pktid.read();
+                        addr_t nline     = m_nline[(addr_t) (r_config_address.read())];
+                        size_t nb_copies = r_config_dir_count.read();
+
+                        wok = m_ivt.set(false,       // it's an inval transaction
+                                        broadcast,
+                                        false,       // no response required
+                                        true,        // acknowledge required
+                                        srcid,
+                                        trdid,
+                                        pktid,
+                                        nline,
+                                        nb_copies,
+                                        index);
+
+                        if (wok)  // IVT success => inval DIR slot
+                        {
+                            m_cache_directory.inval(way, set);
+                            r_config_ivt_index = index;
+                            config_rsp_lines_incr = true;
+                            if (broadcast)
+                            {
+                                r_config_fsm = CONFIG_BC_SEND;
+                            }
+                            else
+                            {
+                                r_config_fsm = CONFIG_INVAL_SEND;
+                            }
 
 #if DEBUG_MEMC_CONFIG
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_DIR_ACCESS> Accessing directory: "
-                            << " address = " << std::hex << r_config_address.read()
-                            << " / hit = " << std::dec << entry.valid
-                            << " / dirty = " << entry.dirty
-                            << " / count = " << entry.count
-                            << " / is_cnt = " << entry.is_cnt << std::endl;
-#endif
-                    break;
-                }
-                /////////////////////
-            case CONFIG_TRT_LOCK:      // enter this state in case of SYNC command
-                // to a dirty cache line
-                // keep DIR lock, and try to get TRT lock
-                // return to LOOP state if TRT full
-                // reset dirty bit in DIR and register a PUT
-                // trabsaction in TRT if not full.
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
-                            "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation");
-
-                    if ( r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG )
-                    {
-                        size_t index = 0;
-                        bool   wok   = not m_trt.full(index);
-
-                        if ( not wok )
+                            if (m_debug)
+                            {
+                                std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
+                                    << " Inval DIR entry and register inval in IVT"
+                                    << " / index = " << std::dec << index
+                                    << " / broadcast = " << broadcast << std::endl;
+                            }
+#endif
+                        }
+                        else       // IVT full => release both DIR and IVT locks
                         {
                             r_config_fsm = CONFIG_LOOP;
+
+#if DEBUG_MEMC_CONFIG
+                            if (m_debug)
+                            {
+                                std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
+                                    << " IVT full : release DIR & IVT locks and retry" << std::endl;
+                            }
+#endif
                         }
-                        else
-                        {
-                            size_t          way = r_config_dir_way.read();
-                            size_t          set = m_y[r_config_address.read()];
-
-                            // reset dirty bit in DIR
-                            DirectoryEntry  entry;
-                            entry.valid       = true;
-                            entry.dirty       = false;
-                            entry.tag         = m_z[r_config_address.read()];
-                            entry.is_cnt      = r_config_dir_is_cnt.read();
-                            entry.lock        = r_config_dir_lock.read();
-                            entry.ptr         = r_config_dir_ptr.read();
-                            entry.count       = r_config_dir_count.read();
-                            entry.owner.inst  = r_config_dir_copy_inst.read();
-                            entry.owner.srcid = r_config_dir_copy_srcid.read();
-                            m_cache_directory.write( set, way, entry );
-
-                            r_config_trt_index = index;
-                            r_config_fsm       = CONFIG_TRT_SET;
-                        }
+                    }
+                }
+                break;
+            }
+            ////////////////////
+            case CONFIG_BC_SEND:    // Post a broadcast inval request to CC_SEND FSM
+            {
+                if (not r_config_to_cc_send_multi_req.read() and
+                    not r_config_to_cc_send_brdcast_req.read())
+                {
+                    // post bc inval request
+                    r_config_to_cc_send_multi_req   = false;
+                    r_config_to_cc_send_brdcast_req = true;
+                    r_config_to_cc_send_trdid       = r_config_ivt_index.read();
+                    r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
+
+                    // prepare next iteration
+                    r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+                    r_config_address   = r_config_address.read() + (m_words << 2);
+                    r_config_fsm       = CONFIG_LOOP;
 
 #if DEBUG_MEMC_CONFIG
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CONFIG_TRT_LOCK> Access TRT: "
-                                << " wok = " << std::dec << wok
-                                << " index = " << index << std::endl;
-#endif
-                    }
-                    break;
-                }
-                ////////////////////
-            case CONFIG_TRT_SET:       // read data in cache
-                // and post a PUT request in TRT
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
-                            "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation");
-
-                    assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and
-                            "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation");
-
-                    // read data into cache
-                    size_t          way = r_config_dir_way.read();
-                    size_t          set = m_y[r_config_address.read()];
-                    std::vector<data_t> data_vector;
-                    data_vector.clear();
-                    for(size_t word=0; word<m_words; word++)
-                    {
-                        uint32_t data = m_cache_data.read( way, set, word );
-                        data_vector.push_back( data );
-                    }
-
-                    // post the PUT request in TRT
-                    m_trt.set( r_config_trt_index.read(),
-                            false,                               // PUT transaction
-                            m_nline[r_config_address.read()],    // line index
-                            0,                                   // srcid:       unused
-                            0,                                   // trdid:       unused
-                            0,                                   // pktid:       unused
-                            false,                               // not proc_read
-                            0,                                   // read_length: unused
-                            0,                                   // word_index:  unused
-                            std::vector<be_t>(m_words,0xF),      // byte-enable:     unused
-                            data_vector,                         // data to be written
-                            0,                                   // ll_key:          unused
-                            true );                              // requested by config FSM
-                    config_rsp_lines_incr = true;
-                    r_config_fsm = CONFIG_PUT_REQ;
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CONFIG_BC_SEND>"
+                            << " Post a broadcast inval request to CC_SEND FSM"
+                            << " / address = " << r_config_address.read() <<std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ///////////////////////
+            case CONFIG_INVAL_SEND:    // Post a multi inval request to CC_SEND FSM
+            {
+                if (not r_config_to_cc_send_multi_req.read() and
+                    not r_config_to_cc_send_brdcast_req.read())
+                {
+                    // post multi inval request
+                    r_config_to_cc_send_multi_req   = true;
+                    r_config_to_cc_send_brdcast_req = false;
+                    r_config_to_cc_send_trdid       = r_config_ivt_index.read();
+                    r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
+
+                    // post data into FIFO
+                    config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read();
+                    config_to_cc_send_fifo_inst  = r_config_dir_copy_inst.read();
+                    config_to_cc_send_fifo_put   = true;
+
+                    if (r_config_dir_count.read() == 1)  // one copy
+                    {
+                        // prepare next iteration
+                        r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+                        r_config_address   = r_config_address.read() + (m_words << 2);
+                        r_config_fsm       = CONFIG_LOOP;
+                    }
+                    else                                   // several copies
+                    {
+                        r_config_fsm = CONFIG_HEAP_REQ;
+                    }
 
 #if DEBUG_MEMC_CONFIG
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:"
-                            << " address = " << std::hex << r_config_address.read()
-                            << " index = " << std::dec << r_config_trt_index.read() << std::endl;
-#endif
-                    break;
-                }
-                ////////////////////
-            case CONFIG_PUT_REQ:       // post PUT request to IXR_CMD_FSM
-                {
-                    if ( not r_config_to_ixr_cmd_req.read() )
-                    {
-                        r_config_to_ixr_cmd_req   = true;
-                        r_config_to_ixr_cmd_index = r_config_trt_index.read();
-
-                        // prepare next iteration
-                        r_config_cmd_lines              = r_config_cmd_lines.read() - 1;
-                        r_config_address                = r_config_address.read() + (m_words<<2);
-                        r_config_fsm                    = CONFIG_LOOP;
-
-#if DEBUG_MEMC_CONFIG
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM"
-                                << " / address = " << std::hex << r_config_address.read() << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////////////
-            case CONFIG_IVT_LOCK:  // enter this state in case of INVAL command
-                // Keep DIR lock and Try to get IVT lock.
-                // Return to LOOP state if IVT full.
-                // Register inval in IVT, and invalidate the
-                // directory if IVT not full.
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
-                            "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation");
-
-                    if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG )
-                    {
-                        size_t set        = m_y[(addr_t)(r_config_address.read())];
-                        size_t way        = r_config_dir_way.read();
-
-                        if ( r_config_dir_count.read() == 0 )     // inval DIR and return to LOOP
-                        {
-                            m_cache_directory.inval( way, set );
-                            r_config_cmd_lines  = r_config_cmd_lines.read() - 1;
-                            r_config_address    = r_config_address.read() + (m_words<<2);
-                            r_config_fsm        = CONFIG_LOOP;
-
-#if DEBUG_MEMC_CONFIG
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
-                                    << " No copies in L1 : inval DIR entry"  << std::endl;
-#endif
-                        }
-                        else    // try to register inval in IVT
-                        {
-                            bool        wok       = false;
-                            size_t      index     = 0;
-                            bool        broadcast = r_config_dir_is_cnt.read();
-                            size_t      srcid     = r_config_srcid.read();
-                            size_t      trdid     = r_config_trdid.read();
-                            size_t      pktid     = r_config_pktid.read();
-                            addr_t      nline     = m_nline[(addr_t)(r_config_address.read())];
-                            size_t      nb_copies = r_config_dir_count.read();
-
-                            wok = m_ivt.set(false,       // it's an inval transaction
-                                    broadcast,
-                                    false,       // no response required
-                                    true,        // acknowledge required
-                                    srcid,
-                                    trdid,
-                                    pktid,
-                                    nline,
-                                    nb_copies,
-                                    index);
-
-                            if ( wok )  // IVT success => inval DIR slot
-                            {
-                                m_cache_directory.inval( way, set );
-                                r_config_ivt_index = index;
-                                config_rsp_lines_incr = true;
-                                if ( broadcast )  r_config_fsm = CONFIG_BC_SEND;
-                                else              r_config_fsm = CONFIG_INVAL_SEND;
-
-#if DEBUG_MEMC_CONFIG
-                                if(m_debug)
-                                    std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
-                                        << " Inval DIR entry and register inval in IVT"
-                                        << " : index = " << std::dec << index
-                                        << " / broadcast = " << broadcast << std::endl;
-#endif
-                            }
-                            else       // IVT full => release both DIR and IVT locks
-                            {
-                                r_config_fsm = CONFIG_LOOP;
-
-#if DEBUG_MEMC_CONFIG
-                                if(m_debug)
-                                    std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
-                                        << " IVT full : release DIR & IVT locks and retry" << std::endl;
-#endif
-                            }
-                        }
-                    }
-                    break;
-                }
-                ////////////////////
-            case CONFIG_BC_SEND:    // Post a broadcast inval request to CC_SEND FSM
-                {
-                    if( not r_config_to_cc_send_multi_req.read() and
-                            not r_config_to_cc_send_brdcast_req.read() )
-                    {
-                        // post bc inval request
-                        r_config_to_cc_send_multi_req   = false;
-                        r_config_to_cc_send_brdcast_req = true;
-                        r_config_to_cc_send_trdid       = r_config_ivt_index.read();
-                        r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
-
-                        // prepare next iteration
-                        r_config_cmd_lines              = r_config_cmd_lines.read() - 1;
-                        r_config_address                = r_config_address.read() + (m_words<<2);
-                        r_config_fsm                    = CONFIG_LOOP;
-
-#if DEBUG_MEMC_CONFIG
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CONFIG_BC_SEND>"
-                                << " Post a broadcast inval request to CC_SEND FSM"
-                                << " / address = " << r_config_address.read() <<std::endl;
-#endif
-                    }
-                    break;
-                }
-                ///////////////////////
-            case CONFIG_INVAL_SEND:    // Post a multi inval request to CC_SEND FSM
-                {
-                    if( not r_config_to_cc_send_multi_req.read() and
-                            not r_config_to_cc_send_brdcast_req.read() )
-                    {
-                        r_config_to_cc_send_multi_req   = true;
-                        r_config_to_cc_send_brdcast_req = false;
-                        r_config_to_cc_send_trdid       = r_config_ivt_index.read();
-                        r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
-
-                        // post data into FIFO
-                        config_to_cc_send_fifo_srcid    = r_config_dir_copy_srcid.read();
-                        config_to_cc_send_fifo_inst     = r_config_dir_copy_inst.read();
-                        config_to_cc_send_fifo_put      = true;
-
-                        if ( r_config_dir_count.read() == 1 )  // one copy
-                        {
-                            // prepare next iteration
-                            r_config_cmd_lines          = r_config_cmd_lines.read() - 1;
-                            r_config_address            = r_config_address.read() + (m_words<<2);
-                            r_config_fsm                = CONFIG_LOOP;
-                        }
-                        else                                   // several copies
-                        {
-                            r_config_fsm = CONFIG_HEAP_REQ;
-                        }
-
-#if DEBUG_MEMC_CONFIG
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CONFIG_INVAL_SEND>"
-                                << " Post multi inval request to CC_SEND FSM"
-                                << " / address = " << std::hex << r_config_address.read()
-                                << " / copy = " << r_config_dir_copy_srcid.read()
-                                << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////////////
-            case CONFIG_HEAP_REQ:  // Try to get access to Heap
-                {
-                    if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG )
-                    {
-                        r_config_fsm       = CONFIG_HEAP_SCAN;
-                        r_config_heap_next = r_config_dir_ptr.read();
-                    }
-
-#if DEBUG_MEMC_CONFIG
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_HEAP_REQ>"
-                            << " Requesting HEAP lock" << std::endl;
-#endif
-                    break;
-                }
-                //////////////////////
-            case CONFIG_HEAP_SCAN:      // scan HEAP and send inval to CC_SEND FSM
-                {
-                    HeapEntry entry = m_heap.read( r_config_heap_next.read() );
-                    bool last_copy  = (entry.next == r_config_heap_next.read());
-
-                    config_to_cc_send_fifo_srcid = entry.owner.srcid;
-                    config_to_cc_send_fifo_inst  = entry.owner.inst;
-                    // config_to_cc_send_fifo_last  = last_copy;
-                    config_to_cc_send_fifo_put   = true;
-
-                    if ( m_config_to_cc_send_inst_fifo.wok() ) // inval request accepted
-                    {
-                        r_config_heap_next = entry.next;
-                        if ( last_copy ) r_config_fsm = CONFIG_HEAP_LAST;
-
-                        // <Activity counters>
-                        m_cpt_heap_slot_available++;
-                        // </Activity counters>
-                    }
-
-#if DEBUG_MEMC_CONFIG
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_HEAP_SCAN>"
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CONFIG_INVAL_SEND>"
                             << " Post multi inval request to CC_SEND FSM"
                             << " / address = " << std::hex << r_config_address.read()
-                            << " / copy = " << entry.owner.srcid
-                            << " / inst = " << std::dec << entry.owner.inst << std::endl;
-#endif
-                    break;
-                }
-                //////////////////////
-            case CONFIG_HEAP_LAST:      // HEAP housekeeping
-                {
-                    size_t free_pointer = m_heap.next_free_ptr();
-                    HeapEntry last_entry;
-                    last_entry.owner.srcid = 0;
-                    last_entry.owner.inst  = false;
-
-                    if ( m_heap.is_full() )
-                    {
-                        last_entry.next = r_config_dir_ptr.read();
-                        m_heap.unset_full();
-                    }
-                    else
-                    {
-                        last_entry.next = free_pointer;
-                    }
-
-                    m_heap.write_free_ptr( r_config_dir_ptr.read() );
-                    m_heap.write( r_config_heap_next.read(), last_entry );
-
-                    // prepare next iteration
-                    r_config_cmd_lines          = r_config_cmd_lines.read() - 1;
-                    r_config_address            = r_config_address.read() + (m_words<<2);
-                    r_config_fsm                = CONFIG_LOOP;
+                            << " / copy = " << r_config_dir_copy_srcid.read()
+                            << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////
+            case CONFIG_HEAP_REQ:  // Try to get access to Heap
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG)
+                {
+                    r_config_fsm = CONFIG_HEAP_SCAN;
+                    r_config_heap_next = r_config_dir_ptr.read();
+                }
 
 #if DEBUG_MEMC_CONFIG
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_HEAP_LAST>"
-                            << " Heap housekeeping" << std::endl;
-#endif
-                    break;
-                }
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CONFIG_HEAP_REQ>"
+                        << " Requesting HEAP lock" << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////
+            case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM
+            {
+                HeapEntry entry = m_heap.read(r_config_heap_next.read());
+                bool last_copy = (entry.next == r_config_heap_next.read());
+
+                config_to_cc_send_fifo_srcid = entry.owner.srcid;
+                config_to_cc_send_fifo_inst  = entry.owner.inst;
+                config_to_cc_send_fifo_put   = true;
+
+                if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted
+                {
+                    r_config_heap_next = entry.next;
+                    if (last_copy) r_config_fsm = CONFIG_HEAP_LAST;
+
+                    // <Activity counters>
+                    m_cpt_heap_slot_available++;
+                    // </Activity counters>
+                }
+
+#if DEBUG_MEMC_CONFIG
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CONFIG_HEAP_SCAN>"
+                        << " Post multi inval request to CC_SEND FSM"
+                        << " / address = " << std::hex << r_config_address.read()
+                        << " / copy = " << entry.owner.srcid
+                        << " / inst = " << std::dec << entry.owner.inst << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////
+            case CONFIG_HEAP_LAST:  // HEAP housekeeping
+            {
+                size_t free_pointer = m_heap.next_free_ptr();
+                HeapEntry last_entry;
+                last_entry.owner.srcid = 0;
+                last_entry.owner.inst  = false;
+
+                if (m_heap.is_full())
+                {
+                    last_entry.next = r_config_dir_ptr.read();
+                    m_heap.unset_full();
+                }
+                else
+                {
+                    last_entry.next = free_pointer;
+                }
+
+                m_heap.write_free_ptr(r_config_dir_ptr.read());
+                m_heap.write(r_config_heap_next.read(), last_entry);
+
+                // prepare next iteration
+                r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+                r_config_address   = r_config_address.read() + (m_words << 2);
+                r_config_fsm       = CONFIG_LOOP;
+
+#if DEBUG_MEMC_CONFIG
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CONFIG_HEAP_LAST>"
+                        << " Heap housekeeping" << std::endl;
+                }
+#endif
+                break;
+            }
         }  // end switch r_config_fsm
+
+
 
         ////////////////////////////////////////////////////////////////////////////////////
@@ -2729 +2659 @@
             ///////////////
             case READ_IDLE:  // waiting a read request
-                {
-                    if(m_cmd_read_addr_fifo.rok())
-                    {
+            {
+                if (m_cmd_read_addr_fifo.rok())
+                {
 
 #if DEBUG_MEMC_READ
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
-                                << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
-                                << " / srcid = " << m_cmd_read_srcid_fifo.read()
-                                << " / trdid = " << m_cmd_read_trdid_fifo.read()
-                                << " / pktid = " << m_cmd_read_pktid_fifo.read()
-                                << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
-#endif
-                        r_read_coherent = false; //WB by default
-                        r_read_ll_done  = false;
-                        r_read_fsm = READ_DIR_REQ;
-                    }
-                    break;
-                }
-
-                //////////////////
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
+                            << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
+                            << " / srcid = " << m_cmd_read_srcid_fifo.read()
+                            << " / trdid = " << m_cmd_read_trdid_fifo.read()
+                            << " / pktid = " << m_cmd_read_pktid_fifo.read()
+                            << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
+                    }
+#endif
+                    r_read_coherent = false; // WB by default
+                    r_read_ll_done  = false;
+                    r_read_fsm      = READ_DIR_REQ;
+                }
+                break;
+            }
+            //////////////////
             case READ_DIR_REQ:  // Get the lock to the directory
-                {
-                    if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
-                    {
-                        r_read_fsm = READ_DIR_LOCK;
-                    }
+            {
+                if (r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
+                {
+                    r_read_fsm = READ_DIR_LOCK;
+                }
 
 #if DEBUG_MEMC_READ
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl;
-#endif
-                    break;
-                }
-
-                ///////////////////
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl;
+                }
+#endif
+                break;
+            }
+
+            ///////////////////
             case READ_DIR_LOCK:  // check directory for hit / miss
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and
-                            "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation");
-
-                    size_t way = 0;
-                    DirectoryEntry entry =
-                        m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
-                    if(((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and not r_read_ll_done.read())   // access the global table ONLY when we have an LL cmd
-                    {
-                        r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
-                        r_read_ll_done  = true;
-                    }
-                    r_read_is_cnt     = entry.is_cnt;
-                    r_read_dirty      = entry.dirty;
-                    r_read_lock       = entry.lock;
-                    r_read_tag        = entry.tag;
-                    r_read_way        = way;
-                    r_read_count      = entry.count;
-                    r_read_copy       = entry.owner.srcid;
-
-                    r_read_copy_inst  = entry.owner.inst;
-                    r_read_ptr        = entry.ptr; // pointer to the heap
-
-                    // check if this is a cached read, this means pktid is either
-                    // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
-                    // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-                    bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1);
-
-                    if(entry.valid)    // hit
-                    {
-                        r_read_coherent = entry.cache_coherent;
-
-                        // hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request)
-                        if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read()))
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and
+                        "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation");
+
+                size_t way = 0;
+                DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+
+                // access the global table ONLY when we have an LL cmd
+                if (((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and
+                    not r_read_ll_done.read())
+                {
+                    r_read_ll_key  = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
+                    r_read_ll_done = true;
+                }
+                r_read_is_cnt    = entry.is_cnt;
+                r_read_dirty     = entry.dirty;
+                r_read_lock      = entry.lock;
+                r_read_tag       = entry.tag;
+                r_read_way       = way;
+                r_read_count     = entry.count;
+                r_read_copy      = entry.owner.srcid;
+                r_read_copy_inst = entry.owner.inst;
+                r_read_ptr       = entry.ptr; // pointer to the heap
+
+                // check if this is a cached read, this means pktid is either
+                // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
+                // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+                bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1);
+                if (entry.valid)    // hit
+                {
+                    r_read_coherent = entry.cache_coherent;
+
+                    // hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request)
+                    if (entry.cache_coherent or (entry.count == 0)) // or (entry.owner.srcid == m_cmd_read_srcid_fifo.read()))
+                    {
+                        // test if we need to register a new copy in the heap
+                        if (entry.is_cnt or (entry.count == 0) or !cached_read)
                         {
-                            // test if we need to register a new copy in the heap
-                            if(entry.is_cnt || (entry.count == 0) || !cached_read)
-                            {
-                                r_read_fsm = READ_DIR_HIT;
-                            }
-                            else
-                            {
-                                r_read_fsm = READ_HEAP_REQ;
-                            }
-                        }
-                        else //hit on a WB line owned by an other proc
-                        {
-                            r_read_fsm = READ_IVT_LOCK;
-                        }
-                    }
-                    else      // miss
-                    {
-                        r_read_fsm = READ_TRT_LOCK;
-                    }
-
-#if DEBUG_MEMC_READ
-                    if(m_debug)
-                    {
-                        std::cout << "  <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: "
-                            << " address = " << std::hex << m_cmd_read_addr_fifo.read()
-                            << " / hit = " << std::dec << entry.valid
-                            << " / count = " <<std::dec << entry.count
-                            << " / is_cnt = " << entry.is_cnt
-                            << " / is_coherent = " << entry.cache_coherent;
-                        if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl;
-                        else                                                std::cout << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-                ///////////////////
-            case READ_IVT_LOCK:
-                {
-                    if (r_alloc_ivt_fsm.read() == ALLOC_IVT_READ)
-                    {
-                        size_t index;
-                        addr_t nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
-                        if(m_ivt.search_inval(nline, index) or m_ivt.is_full() or r_read_to_cc_send_req.read() or r_read_to_cleanup_req.read()) //Check pending inval
-                        {
-                            r_read_fsm = READ_WAIT;
-#if DEBUG_MEMC_READ
-                            if(m_debug)
-                            {
-                                std::cout
-                                    << "  <MEMC " << name() << " READ_IVT_LOCK>"
-                                    << " Wait cleanup completion"
-                                    << std::endl;
-                            }
-#endif
+                            r_read_fsm = READ_DIR_HIT;
                         }
                         else
                         {
-                            r_read_to_cc_send_req = true;
-                            r_read_to_cc_send_dest = r_read_copy.read();
-                            r_read_to_cc_send_nline = nline;
-                            r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
-                            r_read_to_cleanup_req = true;
-                            r_read_to_cleanup_nline = nline;
-                            r_read_to_cleanup_srcid = m_cmd_read_srcid_fifo.read();
-                            r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
-                            r_read_to_cleanup_length  = m_cmd_read_length_fifo.read();
-                            r_read_to_cleanup_first_word = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
-                            r_read_to_cleanup_cached_read = (m_cmd_read_pktid_fifo.read() & 0x1);
-                            r_read_to_cleanup_addr = m_cmd_read_addr_fifo.read();
-                            r_read_to_cleanup_is_ll= ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL);
-                            r_read_to_cleanup_ll_key = r_read_ll_key.read();
-
-                            m_ivt.set(false,     // it's an inval transaction
-                                    false,     // it's not a broadcast
-                                    false,     // it needs a read response
-                                    false,     // no acknowledge required
-                                    m_cmd_read_srcid_fifo.read(),
-                                    m_cmd_read_trdid_fifo.read(),
-                                    m_cmd_read_pktid_fifo.read(),
-                                    nline,
-                                    0x1, //Expect only one answer
-                                    index);
-
-                            cmd_read_fifo_get = true;
-                            r_read_fsm = READ_IDLE;
+                            r_read_fsm = READ_HEAP_REQ;
+                        }
+                    }
+                    else // hit on a WB line owned by an other proc
+                    {
+                        r_read_fsm = READ_IVT_LOCK;
+                    }
+                }
+                else      // miss
+                {
+                    r_read_fsm = READ_TRT_LOCK;
+                }
+
 #if DEBUG_MEMC_READ
-                            if(m_debug)
-                            {
-                                std::cout
-                                    << "  <MEMC " << name() << " READ_IVT_LOCK>"
-                                    << std::hex
-                                    << " Inval req on an NCC line"
-                                    << " | owner = " << r_read_copy.read()
-                                    << " | nline = " << nline
-                                    << std::dec
-                                    << std::endl;
-                            }
-#endif
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: "
+                        << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+                        << " / hit = " << std::dec << entry.valid
+                        << " / count = " <<std::dec << entry.count
+                        << " / is_cnt = " << entry.is_cnt
+                        << " / is_coherent = " << entry.cache_coherent;
+                    if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl;
+                    else                                                 std::cout << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////
+            case READ_IVT_LOCK:
+            {
+                if (r_alloc_ivt_fsm.read() == ALLOC_IVT_READ)
+                {
+                    size_t index;
+                    addr_t nline = m_nline[(addr_t) (m_cmd_read_addr_fifo.read())];
+                    //Check pending inval
+                    if (m_ivt.search_inval(nline, index) or
+                        m_ivt.is_full() or
+                        r_read_to_cc_send_req.read() or
+                        r_read_to_cleanup_req.read())
+                    {
+                        r_read_fsm = READ_WAIT;
+#if DEBUG_MEMC_READ
+                        if (m_debug)
+                        {
+                            std::cout
+                                << "  <MEMC " << name() << " READ_IVT_LOCK>"
+                                << " Wait cleanup completion"
+                                << std::endl;
                         }
-                    }
-
-
-                    break;
-                }
-
-                //////////////////
-            case READ_WAIT://Release the locks
-                {
-                    r_read_fsm = READ_DIR_REQ;
+#endif
+                    }
+                    else
+                    {
+                        r_read_to_cc_send_req   = true;
+                        r_read_to_cc_send_dest  = r_read_copy.read();
+                        r_read_to_cc_send_nline = nline;
+                        r_read_to_cc_send_inst  = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
+
+                        r_read_to_cleanup_req         = true;
+                        r_read_to_cleanup_nline       = nline;
+                        r_read_to_cleanup_srcid       = m_cmd_read_srcid_fifo.read();
+                        r_read_to_cleanup_inst        = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
+                        r_read_to_cleanup_length      = m_cmd_read_length_fifo.read();
+                        r_read_to_cleanup_first_word  = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
+                        r_read_to_cleanup_cached_read = (m_cmd_read_pktid_fifo.read() & 0x1);
+                        r_read_to_cleanup_addr        = m_cmd_read_addr_fifo.read();
+                        r_read_to_cleanup_is_ll       = ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL);
+                        r_read_to_cleanup_ll_key      = r_read_ll_key.read();
+
+                        m_ivt.set(false,     // it's an inval transaction
+                                  false,     // it's not a broadcast
+                                  false,     // it needs a read response
+                                  false,     // no acknowledge required
+                                  m_cmd_read_srcid_fifo.read(),
+                                  m_cmd_read_trdid_fifo.read(),
+                                  m_cmd_read_pktid_fifo.read(),
+                                  nline,
+                                  0x1,       //Expect only one answer
+                                  index);
+
+                        cmd_read_fifo_get = true;
+                        r_read_fsm = READ_IDLE;
 #if DEBUG_MEMC_READ
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC " << name() << " READ_WAIT>" << std::endl;
-                    }
-#endif
-                    break;
-                }
-                ///////////////////
+                        if (m_debug)
+                        {
+                            std::cout
+                                << "  <MEMC " << name() << " READ_IVT_LOCK>"
+                                << std::hex
+                                << " Inval req on an NCC line"
+                                << " | owner = " << r_read_copy.read()
+                                << " | nline = " << nline
+                                << std::dec
+                                << std::endl;
+                        }
+#endif
+                    }
+                }
+                break;
+            }
+            //////////////////
+            case READ_WAIT:  //Release the locks
+            {
+                r_read_fsm = READ_DIR_REQ;
+#if DEBUG_MEMC_READ
+                if (m_debug)
+                {
+                    std::cout
+                        << "  <MEMC " << name() << " READ_WAIT>" << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////
             case READ_DIR_HIT:    //  read data in cache & update the directory
-                //  we enter this state in 3 cases:
-                //  - the read request is uncachable
-                //  - the cache line is in counter mode
-                //  - the cache line is valid but not replicated
-
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and
-                            "MEMC ERROR in READ_DIR_HIT state: Bad DIR allocation");
-                    // check if this is an instruction read, this means pktid is either
-                    // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
-                    // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-                    bool inst_read    = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
-                    // check if this is a cached read, this means pktid is either
-                    // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
-                    // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-                    bool cached_read  = (m_cmd_read_pktid_fifo.read() & 0x1);
-                    bool is_cnt       = r_read_is_cnt.read();
-
+            //  we enter this state in 3 cases:
+            //  - the read request is uncachable
+            //  - the cache line is in counter mode
+            //  - the cache line is valid but not replicated
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and
+                        "MEMC ERROR in READ_DIR_HIT state: Bad DIR allocation");
+
+                // check if this is an instruction read, this means pktid is either
+                // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
+                // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+                bool inst_read = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
+                // check if this is a cached read, this means pktid is either
+                // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
+                // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+                bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1);
+                bool is_cnt      = r_read_is_cnt.read();
+
+                // read data in the cache
+                size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
+                size_t way = r_read_way.read();
+
+                m_cache_data.read_line(way, set, r_read_data);
+
+                // update the cache directory
+                DirectoryEntry entry;
+                entry.valid = true;
+
+                entry.cache_coherent = r_read_coherent.read() or inst_read or !cached_read;
+                r_read_coherent      = r_read_coherent.read() or inst_read or !cached_read;
+
+                entry.is_cnt  = is_cnt;
+                entry.dirty   = r_read_dirty.read();
+                entry.tag     = r_read_tag.read();
+                entry.lock    = r_read_lock.read();
+                entry.ptr     = r_read_ptr.read();
+
+                if (cached_read) // Cached read => we must update the copies
+                {
+                    if (!is_cnt) // Not counter mode
+                    {
+                        entry.owner.srcid = m_cmd_read_srcid_fifo.read();
+                        entry.owner.inst  = inst_read;
+                        entry.count       = r_read_count.read() + 1;
+                    }
+                    else  // Counter mode
+                    {
+                        entry.owner.srcid = 0;
+                        entry.owner.inst  = false;
+                        entry.count       = r_read_count.read() + 1;
+                    }
+                }
+                else // Uncached read
+                {
+                    entry.owner.srcid = r_read_copy.read();
+                    entry.owner.inst  = r_read_copy_inst.read();
+                    entry.count       = r_read_count.read();
+                }
+
+#if DEBUG_MEMC_READ
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
+                        << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
+                        << " / set = " << std::dec << set
+                        << " / way = " << way
+                        << " / owner_id = " << std::hex << entry.owner.srcid
+                        << " / owner_ins = " << std::dec << entry.owner.inst
+                        << " / coherent = " << entry.cache_coherent
+                        << " / count = " << entry.count
+                        << " / is_cnt = " << entry.is_cnt << std::endl;
+                }
+#endif
+                m_cache_directory.write(set, way, entry);
+                r_read_fsm = READ_RSP;
+                break;
+            }
+            ///////////////////
+            case READ_HEAP_REQ:    // Get the lock to the HEAP directory
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
+                {
+                    r_read_fsm = READ_HEAP_LOCK;
+                }
+
+#if DEBUG_MEMC_READ
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " READ_HEAP_REQ>"
+                        << " Requesting HEAP lock " << std::endl;
+                }
+#endif
+                break;
+            }
+
+            ////////////////////
+            case READ_HEAP_LOCK:   // read data in cache, update the directory
+            // and prepare the HEAP update
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
+                {
+                    // enter counter mode when we reach the limit of copies or the heap is full
+                    bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full();
+
+                    assert(r_read_coherent.read() && "Heap access on line NCC");
                     // read data in the cache
-                    size_t set        = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
-                    size_t way        = r_read_way.read();
+                    size_t set = m_y[(addr_t) (m_cmd_read_addr_fifo.read())];
+                    size_t way = r_read_way.read();
 
                     m_cache_data.read_line(way, set, r_read_data);
@@ -2948 +2969 @@
                     // update the cache directory
                     DirectoryEntry entry;
-                    entry.valid   = true;
-                    //entry.cache_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read());
-                    //r_read_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read());
-
-                    entry.cache_coherent = r_read_coherent.read() or inst_read or (!(cached_read));
-                    r_read_coherent = r_read_coherent.read() or inst_read or (!(cached_read));
-
-                    entry.is_cnt  = is_cnt;
-                    entry.dirty   = r_read_dirty.read();
-                    entry.tag     = r_read_tag.read();
-                    entry.lock    = r_read_lock.read();
-                    entry.ptr     = r_read_ptr.read();
-                    if(cached_read)   // Cached read => we must update the copies
-                    {
-                        if(!is_cnt)  // Not counter mode
+                    entry.valid  = true;
+                    entry.is_cnt = go_cnt;
+                    entry.dirty  = r_read_dirty.read();
+                    entry.tag    = r_read_tag.read();
+                    entry.lock   = r_read_lock.read();
+                    entry.count  = r_read_count.read() + 1;
+                    entry.cache_coherent = r_read_coherent.read();
+
+                    if (not go_cnt) // Not entering counter mode
+                    {
+                        entry.owner.srcid = r_read_copy.read();
+                        entry.owner.inst  = r_read_copy_inst.read();
+                        entry.ptr         = m_heap.next_free_ptr();   // set pointer on the heap
+                    }
+                    else    // Entering Counter mode
+                    {
+                        entry.owner.srcid = 0;
+                        entry.owner.inst  = false;
+                        entry.ptr         = 0;
+                    }
+
+                    m_cache_directory.write(set, way, entry);
+
+                    // prepare the heap update (add an entry, or clear the linked list)
+                    if (not go_cnt)      // not switching to counter mode
+                    {
+                        // We test if the next free entry in the heap is the last
+                        HeapEntry heap_entry = m_heap.next_free_entry();
+                        r_read_next_ptr      = heap_entry.next;
+                        r_read_last_free     = (heap_entry.next == m_heap.next_free_ptr());
+
+                        r_read_fsm = READ_HEAP_WRITE; // add an entry in the HEAP
+                    }
+                    else // switching to counter mode
+                    {
+                        if (r_read_count.read() > 1) // heap must be cleared
                         {
-                            entry.owner.srcid    = m_cmd_read_srcid_fifo.read();
-                            entry.owner.inst     = inst_read;
-                            entry.count          = r_read_count.read() + 1;
-                        }
-                        else  // Counter mode
-                        {
-                            entry.owner.srcid    = 0;
-                            entry.owner.inst     = false;
-                            entry.count          = r_read_count.read() + 1;
-                        }
-                    }
-                    else            // Uncached read
-                    {
-                        entry.owner.srcid     = r_read_copy.read();
-                        entry.owner.inst      = r_read_copy_inst.read();
-                        entry.count           = r_read_count.read();
-                    }
-
-#if DEBUG_MEMC_READ
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
-                            << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
-                            << " / set = " << std::dec << set
-                            << " / way = " << way
-                            << " / owner_id = " << std::hex << entry.owner.srcid
-                            << " / owner_ins = " << std::dec << entry.owner.inst
-                            << " / coherent = " << entry.cache_coherent
-                            << " / count = " << entry.count
-                            << " / is_cnt = " << entry.is_cnt << std::endl;
-#endif
-
-                    m_cache_directory.write(set, way, entry);
-                    r_read_fsm    = READ_RSP;
-                    break;
-                }
-                ///////////////////
-            case READ_HEAP_REQ:    // Get the lock to the HEAP directory
-                {
-                    if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
-                    {
-                        r_read_fsm = READ_HEAP_LOCK;
-                    }
-
-#if DEBUG_MEMC_READ
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " READ_HEAP_REQ>"
-                            << " Requesting HEAP lock " << std::endl;
-#endif
-                    break;
-                }
-
-                ////////////////////
-            case READ_HEAP_LOCK:   // read data in cache, update the directory
-                // and prepare the HEAP update
-                {
-                    if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
-                    {
-                        // enter counter mode when we reach the limit of copies or the heap is full
-                        bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full();
-
-                        assert (r_read_coherent.read() && "Heap access on line NCC");
-                        // read data in the cache
-                        size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
-                        size_t way = r_read_way.read();
-
-                        m_cache_data.read_line(way, set, r_read_data);
-
-                        // update the cache directory
-                        DirectoryEntry entry;
-                        entry.valid  = true;
-                        entry.cache_coherent = r_read_coherent.read();
-                        entry.is_cnt = go_cnt;
-                        entry.dirty  = r_read_dirty.read();
-                        entry.tag    = r_read_tag.read();
-                        entry.lock   = r_read_lock.read();
-                        entry.count  = r_read_count.read() + 1;
-
-                        if(not go_cnt)         // Not entering counter mode
-                        {
-                            entry.owner.srcid    = r_read_copy.read();
-                            entry.owner.inst     = r_read_copy_inst.read();
-                            entry.ptr            = m_heap.next_free_ptr();   // set pointer on the heap
-                        }
-                        else                // Entering Counter mode
-                        {
-                            entry.owner.srcid    = 0;
-                            entry.owner.inst     = false;
-                            entry.ptr            = 0;
-                        }
-
-                        m_cache_directory.write(set, way, entry);
-
-                        // prepare the heap update (add an entry, or clear the linked list)
-                        if(not go_cnt)      // not switching to counter mode
-                        {
-                            // We test if the next free entry in the heap is the last
-                            HeapEntry heap_entry = m_heap.next_free_entry();
-                            r_read_next_ptr      = heap_entry.next;
-                            r_read_last_free     = (heap_entry.next == m_heap.next_free_ptr());
-
-                            r_read_fsm           = READ_HEAP_WRITE; // add an entry in the HEAP
-                        }
-                        else            // switching to counter mode
-                        {
-                            if(r_read_count.read() > 1)              // heap must be cleared
+                            HeapEntry next_entry = m_heap.read(r_read_ptr.read());
+                            r_read_next_ptr      = m_heap.next_free_ptr();
+                            m_heap.write_free_ptr(r_read_ptr.read());
+
+                            if (next_entry.next == r_read_ptr.read())    // last entry
                             {
-                                HeapEntry next_entry = m_heap.read(r_read_ptr.read());
-                                r_read_next_ptr      = m_heap.next_free_ptr();
-                                m_heap.write_free_ptr(r_read_ptr.read());
-
-                                if(next_entry.next == r_read_ptr.read())    // last entry
-                                {
-                                    r_read_fsm = READ_HEAP_LAST;    // erase the entry
-                                }
-                                else                                        // not the last entry
-                                {
-                                    r_read_ptr = next_entry.next;
-                                    r_read_fsm = READ_HEAP_ERASE;   // erase the list
-                                }
+                                r_read_fsm = READ_HEAP_LAST;    // erase the entry
                             }
-                            else  // the heap is not used / nothing to do
+                            else                                        // not the last entry
                             {
-                                r_read_fsm = READ_RSP;
+                                r_read_ptr = next_entry.next;
+                                r_read_fsm = READ_HEAP_ERASE;   // erase the list
                             }
                         }
+                        else  // the heap is not used / nothing to do
+                        {
+                            r_read_fsm = READ_RSP;
+                        }
+                    }
 
 #if DEBUG_MEMC_READ
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " READ_HEAP_LOCK> Update directory:"
-                                << " tag = " << std::hex << entry.tag
-                                << " set = " << std::dec << set
-                                << " way = " << way
-                                << " count = " << entry.count
-                                << " is_cnt = " << entry.is_cnt << std::endl;
-#endif
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " READ_HEAP_LOCK> Update directory:"
+                            << " tag = " << std::hex << entry.tag
+                            << " set = " << std::dec << set
+                            << " way = " << way
+                            << " count = " << entry.count
+                            << " is_cnt = " << entry.is_cnt << std::endl;
+                    }
+#endif
+                }
+                else
+                {
+                    std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK"
+                        << "Bad HEAP allocation"   << std::endl;
+                    exit(0);
+                }
+                break;
+            }
+            /////////////////////
+            case READ_HEAP_WRITE:       // add an entry in the heap
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
+                {
+                    HeapEntry heap_entry;
+                    heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read();
+                    heap_entry.owner.inst  = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
+
+                    if (r_read_count.read() == 1)  // creation of a new linked list
+                    {
+                        heap_entry.next = m_heap.next_free_ptr();
+                    }
+                    else                         // head insertion in existing list
+                    {
+                        heap_entry.next = r_read_ptr.read();
+                    }
+                    m_heap.write_free_entry(heap_entry);
+                    m_heap.write_free_ptr(r_read_next_ptr.read());
+                    if (r_read_last_free.read()) {
+                        m_heap.set_full();
+                    }
+
+                    // <Activity counters>
+                    m_cpt_heap_slot_available--;
+                    // </Activity counters>
+
+                    r_read_fsm = READ_RSP;
+
+#if DEBUG_MEMC_READ
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:"
+                            << " owner_id = " << std::hex << heap_entry.owner.srcid
+                            << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl;
+                    }
+#endif
+                }
+                else
+                {
+                    std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE"
+                        << "Bad HEAP allocation" << std::endl;
+                    exit(0);
+                }
+                break;
+            }
+            /////////////////////
+            case READ_HEAP_ERASE:
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
+                {
+                    HeapEntry next_entry = m_heap.read(r_read_ptr.read());
+                    if (next_entry.next == r_read_ptr.read())
+                    {
+                        r_read_fsm = READ_HEAP_LAST;
                     }
                     else
                     {
-                        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK"
-                            << "Bad HEAP allocation"   << std::endl;
-                        exit(0);
-                    }
-                    break;
-                }
-                /////////////////////
-            case READ_HEAP_WRITE:       // add an entry in the heap
-                {
-                    if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
-                    {
-                        HeapEntry heap_entry;
-                        heap_entry.owner.srcid    = m_cmd_read_srcid_fifo.read();
-                        heap_entry.owner.inst     = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
-
-                        if(r_read_count.read() == 1)  // creation of a new linked list
-                        {
-                            heap_entry.next         = m_heap.next_free_ptr();
-                        }
-                        else                         // head insertion in existing list
-                        {
-                            heap_entry.next         = r_read_ptr.read();
-                        }
-                        m_heap.write_free_entry(heap_entry);
-                        m_heap.write_free_ptr(r_read_next_ptr.read());
-
-                        if(r_read_last_free.read()) {
-                            m_heap.set_full();
-                        }
-
-                        // <Activity counters>
-                        m_cpt_heap_slot_available--;
-                        // </Activity counters>
-
-                        r_read_fsm = READ_RSP;
+                        r_read_ptr = next_entry.next;
+                        r_read_fsm = READ_HEAP_ERASE;
+                    }
+                }
+                else
+                {
+                    std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE"
+                        << "Bad HEAP allocation" << std::endl;
+                    exit(0);
+                }
+                break;
+            }
+
+            ////////////////////
+            case READ_HEAP_LAST:
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
+                {
+                    HeapEntry last_entry;
+                    last_entry.owner.srcid = 0;
+                    last_entry.owner.inst  = false;
+
+                    if (m_heap.is_full())
+                    {
+                        last_entry.next = r_read_ptr.read();
+                        m_heap.unset_full();
+                    }
+                    else
+                    {
+                        last_entry.next = r_read_next_ptr.read();
+                    }
+                    m_heap.write(r_read_ptr.read(),last_entry);
+                    r_read_fsm = READ_RSP;
+
+                    // <Activity counters>
+                    m_cpt_heap_slot_available = m_cpt_heap_slot_available + (r_read_count.read() - 1);
+                    // </Activity counters>
+                }
+                else
+                {
+                    std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST"
+                        << "Bad HEAP allocation" << std::endl;
+                    exit(0);
+                }
+                break;
+            }
+            //////////////
+            case READ_RSP:    //  request the TGT_RSP FSM to return data
+            {
+                if (!r_read_to_tgt_rsp_req)
+                {
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        r_read_to_tgt_rsp_data[i] = r_read_data[i];
+                    }
+                    r_read_to_tgt_rsp_word   = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
+                    r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
+                    r_read_to_tgt_rsp_srcid  = m_cmd_read_srcid_fifo.read();
+
+                    if (r_read_coherent.read())
+                    {
+                        r_read_to_tgt_rsp_pktid = 0x0 + m_cmd_read_pktid_fifo.read();
+                    }
+                    else
+                    {
+                        r_read_to_tgt_rsp_pktid = 0x8 + m_cmd_read_pktid_fifo.read();
+                    }
+                    r_read_to_tgt_rsp_trdid  = m_cmd_read_trdid_fifo.read();
+                    r_read_to_tgt_rsp_ll_key = r_read_ll_key.read();
+                    cmd_read_fifo_get        = true;
+                    r_read_to_tgt_rsp_req    = true;
+                    r_read_fsm               = READ_IDLE;
 
 #if DEBUG_MEMC_READ
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:"
-                                << " owner_id = " << std::hex << heap_entry.owner.srcid
-                                << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl;
-#endif
-                    }
-                    else
-                    {
-                        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE"
-                            << "Bad HEAP allocation" << std::endl;
-                        exit(0);
-                    }
-                    break;
-                }
-                /////////////////////
-            case READ_HEAP_ERASE:
-                {
-                    if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
-                    {
-                        HeapEntry next_entry = m_heap.read(r_read_ptr.read());
-                        if(next_entry.next == r_read_ptr.read())
-                        {
-                            r_read_fsm = READ_HEAP_LAST;
-                        }
-                        else
-                        {
-                            r_read_ptr = next_entry.next;
-                            r_read_fsm = READ_HEAP_ERASE;
-                        }
-                    }
-                    else
-                    {
-                        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE"
-                            << "Bad HEAP allocation" << std::endl;
-                        exit(0);
-                    }
-                    break;
-                }
-
-                ////////////////////
-            case READ_HEAP_LAST:
-                {
-                    if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
-                    {
-                        HeapEntry last_entry;
-                        last_entry.owner.srcid    = 0;
-                        last_entry.owner.inst     = false;
-
-                        if(m_heap.is_full())
-                        {
-                            last_entry.next       = r_read_ptr.read();
-                            m_heap.unset_full();
-                        }
-                        else
-                        {
-                            last_entry.next       = r_read_next_ptr.read();
-                        }
-                        m_heap.write(r_read_ptr.read(),last_entry);
-                        r_read_fsm = READ_RSP;
-
-                        // <Activity counters>
-                        m_cpt_heap_slot_available = m_cpt_heap_slot_available + (r_read_count.read() - 1);
-                        // </Activity counters>
-                    }
-                    else
-                    {
-                        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST"
-                            << "Bad HEAP allocation" << std::endl;
-                        exit(0);
-                    }
-                    break;
-                }
-                //////////////
-            case READ_RSP:    //  request the TGT_RSP FSM to return data
-                {
-                    if(!r_read_to_tgt_rsp_req)
-                    {
-                        for(size_t i=0 ; i<m_words ; i++)  r_read_to_tgt_rsp_data[i] = r_read_data[i];
-                        r_read_to_tgt_rsp_word   = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
-                        r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
-                        r_read_to_tgt_rsp_srcid  = m_cmd_read_srcid_fifo.read();
-
-                        if (r_read_coherent.read())
-                        {
-                            r_read_to_tgt_rsp_pktid = 0x0 + m_cmd_read_pktid_fifo.read();
-                        }
-                        else
-                        {
-                            r_read_to_tgt_rsp_pktid = 0x8 + m_cmd_read_pktid_fifo.read();
-                        }
-                        r_read_to_tgt_rsp_trdid  = m_cmd_read_trdid_fifo.read();
-                        r_read_to_tgt_rsp_ll_key = r_read_ll_key.read();
-                        cmd_read_fifo_get        = true;
-                        r_read_to_tgt_rsp_req    = true;
-                        r_read_fsm               = READ_IDLE;
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:"
+                            << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read()
+                            << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
+                            << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ///////////////////
+            case READ_TRT_LOCK: // read miss : check the Transaction Table
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)
+                {
+                    size_t index     = 0;
+                    addr_t addr      = (addr_t) m_cmd_read_addr_fifo.read();
+                    bool   hit_read  = m_trt.hit_read(m_nline[addr], index);
+                    bool   hit_write = m_trt.hit_write(m_nline[addr]);
+                    bool   wok       = not m_trt.full(index);
+
+                    if (hit_read or !wok or hit_write) // line already requested or no space
+                    {
+                        if (!wok)                  m_cpt_trt_full++;
+                        if (hit_read or hit_write) m_cpt_trt_rb++;
+                        r_read_fsm = READ_IDLE;
+                    }
+                    else // missing line is requested to the XRAM
+                    {
+                        m_cpt_read_miss++;
+                        r_read_trt_index = index;
+                        r_read_fsm       = READ_TRT_SET;
+                    }
 
 #if DEBUG_MEMC_READ
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:"
-                                << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read()
-                                << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
-                                << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
-#endif
-                    }
-                    break;
-                }
-                ///////////////////
-            case READ_TRT_LOCK: // read miss : check the Transaction Table
-                {
-                    if(r_alloc_trt_fsm.read() == ALLOC_TRT_READ)
-                    {
-                        size_t      index     = 0;
-                        addr_t      addr      = (addr_t) m_cmd_read_addr_fifo.read();
-                        bool        hit_read  = m_trt.hit_read(m_nline[addr], index);
-                        bool        hit_write = m_trt.hit_write(m_nline[addr]);
-                        bool        wok       = !m_trt.full(index);
-
-                        if(hit_read or !wok or hit_write)    // missing line already requested or no space
-                        {
-                            if(!wok)
-                            {
-                                m_cpt_trt_full++;
-                            }
-                            if(hit_read or hit_write)   m_cpt_trt_rb++;
-                            r_read_fsm = READ_IDLE;
-                        }
-                        else                  // missing line is requested to the XRAM
-                        {
-                            m_cpt_read_miss++;
-                            r_read_trt_index = index;
-                            r_read_fsm       = READ_TRT_SET;
-                        }
-
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " READ_TRT_LOCK> Check TRT:"
+                            << " hit_read = " << hit_read
+                            << " / hit_write = " << hit_write
+                            << " / full = " << !wok << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            //////////////////
+            case READ_TRT_SET: // register get transaction in TRT
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)
+                {
+                    m_trt.set(r_read_trt_index.read(),
+                              true,      // GET
+                              m_nline[(addr_t) (m_cmd_read_addr_fifo.read())],
+                              m_cmd_read_srcid_fifo.read(),
+                              m_cmd_read_trdid_fifo.read(),
+                              m_cmd_read_pktid_fifo.read(),
+                              true,     // proc read
+                              m_cmd_read_length_fifo.read(),
+                              m_x[(addr_t) (m_cmd_read_addr_fifo.read())],
+                              std::vector<be_t> (m_words, 0),
+                              std::vector<data_t> (m_words, 0),
+                              r_read_ll_key.read());
 #if DEBUG_MEMC_READ
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " READ_TRT_LOCK> Check TRT:"
-                                << " hit_read = " << hit_read
-                                << " / hit_write = " << hit_write
-                                << " / full = " << !wok << std::endl;
-#endif
-                    }
-                    break;
-                }
-
-                //////////////////
-            case READ_TRT_SET:      // register get transaction in TRT
-                {
-                    if(r_alloc_trt_fsm.read() == ALLOC_TRT_READ)
-                    {
-                        m_trt.set(r_read_trt_index.read(),
-                                true,
-                                m_nline[(addr_t)(m_cmd_read_addr_fifo.read())],
-                                m_cmd_read_srcid_fifo.read(),
-                                m_cmd_read_trdid_fifo.read(),
-                                m_cmd_read_pktid_fifo.read(),
-                                true,
-                                m_cmd_read_length_fifo.read(),
-                                m_x[(addr_t)(m_cmd_read_addr_fifo.read())],
-                                std::vector<be_t> (m_words,0),
-                                std::vector<data_t> (m_words,0),
-                                r_read_ll_key.read());
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " READ_TRT_SET> Set a GET in TRT:"
+                            << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+                            << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl;
+                    }
+#endif
+                    r_read_fsm = READ_TRT_REQ;
+                }
+                break;
+            }
+
+            //////////////////
+            case READ_TRT_REQ:   // consume the read request in FIFO and send it to IXR_CMD_FSM
+            {
+                if (not r_read_to_ixr_cmd_req)
+                {
+                    cmd_read_fifo_get       = true;
+                    r_read_to_ixr_cmd_req   = true;
+                    r_read_to_ixr_cmd_index = r_read_trt_index.read();
+                    r_read_fsm              = READ_IDLE;
 
 #if DEBUG_MEMC_READ
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " READ_TRT_SET> Set a GET in TGT:"
-                                << " address = " << std::hex << m_cmd_read_addr_fifo.read()
-                                << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl;
-#endif
-                        r_read_fsm = READ_TRT_REQ;
-                    }
-                    break;
-                }
-
-                //////////////////
-            case READ_TRT_REQ:   // consume the read request in FIFO and send it to IXR_CMD_FSM
-                {
-                    if(not r_read_to_ixr_cmd_req)
-                    {
-                        cmd_read_fifo_get       = true;
-                        r_read_to_ixr_cmd_req   = true;
-                        //r_read_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
-                        r_read_to_ixr_cmd_index = r_read_trt_index.read();
-                        r_read_fsm              = READ_IDLE;
-
-#if DEBUG_MEMC_READ
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address "
-                                << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
-#endif
-                    }
-                    break;
-                }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address "
+                            << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
         } // end switch read_fsm
 
@@ -3366 +3310 @@
         /////////////////////////////////////////////////////////////////////////////////////
 
-        switch(r_write_fsm.read())
+        switch (r_write_fsm.read())
         {
             ////////////////
             case WRITE_IDLE:  // copy first word of a write burst in local buffer
-                {
-                    if (not m_cmd_write_addr_fifo.rok()) break;
-                    // consume a word in the FIFO & write it in the local buffer
-                    cmd_write_fifo_get  = true;
-                    size_t index        = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
-
-                    r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
-                    r_write_word_index  = index;
-                    r_write_word_count  = 0;
-                    r_write_data[index] = m_cmd_write_data_fifo.read();
-                    r_write_srcid       = m_cmd_write_srcid_fifo.read();
-                    r_write_trdid       = m_cmd_write_trdid_fifo.read();
-                    r_write_pktid       = m_cmd_write_pktid_fifo.read();
-
-                    // if SC command, get the SC key
-                    if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
-                    {
-                        assert( not m_cmd_write_eop_fifo.read() &&
-                                "MEMC ERROR in WRITE_IDLE state: "
-                                "invalid packet format for SC command");
-
-                        r_write_sc_key = m_cmd_write_data_fifo.read();
-                    }
-                    // initialize the be field for all words
-                    for(size_t word=0 ; word<m_words ; word++)
-                    {
-                        if(word == index) r_write_be[word] = m_cmd_write_be_fifo.read();
-                        else              r_write_be[word] = 0x0;
-                    }
-
-                    if (m_cmd_write_eop_fifo.read())
-                    {
-                        r_write_fsm = WRITE_DIR_REQ;
-                    }
-                    else
-                    {
-                        r_write_fsm = WRITE_NEXT;
-                    }
+            {
+                if (not m_cmd_write_addr_fifo.rok()) break;
+
+                // consume a word in the FIFO & write it in the local buffer
+                cmd_write_fifo_get  = true;
+                size_t index        = m_x[(addr_t) (m_cmd_write_addr_fifo.read())];
+
+                r_write_address     = (addr_t) (m_cmd_write_addr_fifo.read());
+                r_write_word_index  = index;
+                r_write_word_count  = 0;
+                r_write_data[index] = m_cmd_write_data_fifo.read();
+                r_write_srcid       = m_cmd_write_srcid_fifo.read();
+                r_write_trdid       = m_cmd_write_trdid_fifo.read();
+                r_write_pktid       = m_cmd_write_pktid_fifo.read();
+
+                // if SC command, get the SC key
+                if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
+                {
+                    assert(not m_cmd_write_eop_fifo.read() &&
+                            "MEMC ERROR in WRITE_IDLE state: "
+                            "invalid packet format for SC command");
+
+                    r_write_sc_key = m_cmd_write_data_fifo.read();
+                }
+
+                // initialize the be field for all words
+                for (size_t word = 0; word < m_words; word++)
+                {
+                    if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read();
+                    else               r_write_be[word] = 0x0;
+                }
+
+                if (m_cmd_write_eop_fifo.read())
+                {
+                    r_write_fsm = WRITE_DIR_REQ;
+                }
+                else
+                {
+                    r_write_fsm = WRITE_NEXT;
+                }
 
 #if DEBUG_MEMC_WRITE
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " WRITE_IDLE> Write request "
-                            << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
-                            << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
-                            << " / data = " << m_cmd_write_data_fifo.read()
-                            << " / pktid = " << m_cmd_write_pktid_fifo.read()
-                            << std::endl;
-#endif
-                    break;
-                }
-
-                ////////////////
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " WRITE_IDLE> Write request "
+                        << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
+                        << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
+                        << " / data = " << m_cmd_write_data_fifo.read()
+                        << " / pktid = " << m_cmd_write_pktid_fifo.read()
+                        << std::dec << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////
             case WRITE_NEXT:  // copy next word of a write burst in local buffer
-                {
-                    if (not m_cmd_write_addr_fifo.rok()) break;
-
-                    // check that the next word is in the same cache line
-                    assert((m_nline[(addr_t)(r_write_address.read())] ==
-                                m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) &&
-                            "MEMC ERROR in WRITE_NEXT state: Illegal write burst");
-
-                    size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
-                    bool   is_sc = ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC);
-
-                    // check that SC command has constant address
-                    assert((not is_sc or (index == r_write_word_index)) &&
-                            "MEMC ERROR in WRITE_NEXT state: "
-                            "the address must be constant on a SC command");
-
-                    // check that SC command has two flits
-                    assert((not is_sc or m_cmd_write_eop_fifo.read()) &&
-                            "MEMC ERROR in WRITE_NEXT state: "
-                            "invalid packet format for SC command");
-                    // consume a word in the FIFO & write it in the local buffer
-                    cmd_write_fifo_get  = true;
-
-                    r_write_be[index]   = m_cmd_write_be_fifo.read();
-                    r_write_data[index] = m_cmd_write_data_fifo.read();
-
-                    // the first flit of a SC command is the reservation key and
-                    // therefore it must not be counted as a data to write
-                    if (not is_sc)
-                    {
-                        r_write_word_count = r_write_word_count.read() + 1;
-                    }
-
-                    if (m_cmd_write_eop_fifo.read()) r_write_fsm = WRITE_DIR_REQ;
+            {
+                if (not m_cmd_write_addr_fifo.rok()) break;
+
+                // check that the next word is in the same cache line
+                assert((m_nline[(addr_t)(r_write_address.read())] ==
+                            m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) &&
+                        "MEMC ERROR in WRITE_NEXT state: Illegal write burst");
+
+                size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
+                bool   is_sc = ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC);
+
+                // check that SC command has constant address
+                assert((not is_sc or (index == r_write_word_index)) &&
+                        "MEMC ERROR in WRITE_NEXT state: "
+                        "the address must be constant on a SC command");
+
+                // check that SC command has two flits
+                assert((not is_sc or m_cmd_write_eop_fifo.read()) &&
+                        "MEMC ERROR in WRITE_NEXT state: "
+                        "invalid packet format for SC command");
+
+                // consume a word in the FIFO & write it in the local buffer
+                cmd_write_fifo_get  = true;
+
+                r_write_be[index]   = m_cmd_write_be_fifo.read();
+                r_write_data[index] = m_cmd_write_data_fifo.read();
+
+                // the first flit of a SC command is the reservation key and
+                // therefore it must not be counted as a data to write
+                if (not is_sc)
+                {
+                    r_write_word_count = r_write_word_count.read() + 1;
+                }
+
+                if (m_cmd_write_eop_fifo.read())
+                {
+                    r_write_fsm = WRITE_DIR_REQ;
+                }
 
 #if DEBUG_MEMC_WRITE
-                    if (m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " WRITE_NEXT> Write another word in local buffer"
-                            << std::endl;
-#endif
-                    break;
-                }
-
-                ////////////////////
-            case WRITE_DIR_REQ:
-                {
-                    // Get the lock to the directory
-                    // and access the llsc_global_table
-                    if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) break;
-
-                    if ((r_write_pktid.read() & 0x7) == TYPE_SC)
-                    {
-                        // test address and key match of the SC command on the
-                        // LL/SC table without removing reservation. The reservation
-                        // will be erased after in this FSM.
-                        bool sc_success = m_llsc_table.check(r_write_address.read(),
-                                r_write_sc_key.read());
-
-                        r_write_sc_fail     = not sc_success;
-
-                        if (not sc_success) r_write_fsm = WRITE_RSP;
-                        else                r_write_fsm = WRITE_DIR_LOCK;
-                    }
-                    else
-                    {
-                        // write burst
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " WRITE_NEXT> Write another word in local buffer"
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////
+            case WRITE_DIR_REQ: // Get the lock to the directory
+                                // and access the llsc_global_table
+            {
+                if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE) break;
+
+                if ((r_write_pktid.read() & 0x7) == TYPE_SC)
+                {
+                    // test address and key match of the SC command on the
+                    // LL/SC table without removing reservation. The reservation
+                    // will be erased after in this FSM.
+                    bool sc_success = m_llsc_table.check(r_write_address.read(),
+                            r_write_sc_key.read());
+
+                    r_write_sc_fail = not sc_success;
+
+                    if (not sc_success) r_write_fsm = WRITE_RSP;
+                    else                r_write_fsm = WRITE_DIR_LOCK;
+                }
+                else
+                {
+                    // write burst
 #define L2 soclib::common::uint32_log2
-                        addr_t min = r_write_address.read();
-                        addr_t max = r_write_address.read() +
-                            (r_write_word_count.read() << L2(vci_param_int::B));
+                    addr_t min = r_write_address.read();
+                    addr_t max = r_write_address.read() +
+                        (r_write_word_count.read() << L2(vci_param_int::B));
 #undef L2
 
-                        m_llsc_table.sw(min, max);
-
-                        r_write_fsm = WRITE_DIR_LOCK;
-                    }
+                    m_llsc_table.sw(min, max);
+
+                    r_write_fsm = WRITE_DIR_LOCK;
+                }
 
 #if DEBUG_MEMC_WRITE
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock "
-                            << std::endl;
-#endif
-                    break;
-                }
-
-                ////////////////////
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock "
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////////
             case WRITE_DIR_LOCK:     // access directory to check hit/miss
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
-                            "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation");
-                    size_t  way = 0;
-                    DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
-
-                    if(entry.valid)    // hit
-                    {
-                        // copy directory entry in local buffer in case of hit
-                        r_write_is_cnt     = entry.is_cnt;
-                        r_write_lock       = entry.lock;
-                        r_write_tag        = entry.tag;
-                        r_write_copy       = entry.owner.srcid;
-                        r_write_copy_inst  = entry.owner.inst;
-                        r_write_count      = entry.count;
-                        r_write_ptr        = entry.ptr;
-                        r_write_way        = way;
-
-                        r_write_coherent   = entry.cache_coherent;
-
-                        if((entry.cache_coherent == false) and (entry.count != 0))
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+                        "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation");
+
+                size_t way = 0;
+                DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
+
+                if (entry.valid)    // hit
+                {
+                    // copy directory entry in local buffer in case of hit
+                    r_write_is_cnt    = entry.is_cnt;
+                    r_write_lock      = entry.lock;
+                    r_write_tag       = entry.tag;
+                    r_write_copy      = entry.owner.srcid;
+                    r_write_copy_inst = entry.owner.inst;
+                    r_write_count     = entry.count;
+                    r_write_ptr       = entry.ptr;
+                    r_write_way       = way;
+                    r_write_coherent  = entry.cache_coherent;
+
+                    if ((entry.cache_coherent == false) and (entry.count != 0))
+                    {
+                        m_cpt_write_ncc_miss++;
+                    }
+
+                    if (entry.cache_coherent or (entry.owner.srcid == r_write_srcid.read()) or (entry.count == 0)) // hit WT
+                    {
+                        if (entry.is_cnt and entry.count)
                         {
-                            m_cpt_write_ncc_miss++;
-                        }
-
-                        if (entry.cache_coherent or (entry.owner.srcid == r_write_srcid.read()) or (entry.count == 0)) // hit WT
-                        {
-                            if(entry.is_cnt && entry.count)
-                            {
-                                r_write_fsm = WRITE_BC_DIR_READ;
-                            }
-                            else
-                            {
-                                r_write_fsm = WRITE_DIR_HIT;
-                            }
+                            r_write_fsm = WRITE_BC_DIR_READ;
                         }
                         else
                         {
-                            if (r_write_to_cleanup_req.read())//inval already sent
-                            {
-                                r_write_fsm = WRITE_WAIT;
-                            }
-                            else // hit on a NCC line with a different owner
-                            {
-                                r_write_fsm = WRITE_IVT_LOCK_HIT_WB;
-                            }
+                            r_write_fsm = WRITE_DIR_HIT;
                         }
                     }
-                    else  // miss
-                    {
-                        r_write_fsm = WRITE_MISS_IVT_LOCK;
-                    }
+                    else
+                    {
+                        if (r_write_to_cleanup_req.read()) //inval already sent
+                        {
+                            r_write_fsm = WRITE_WAIT;
+                        }
+                        else // hit on a NCC line with a different owner
+                        {
+                            r_write_fsm = WRITE_IVT_LOCK_HIT_WB;
+                        }
+                    }
+                }
+                else  // miss
+                {
+                    r_write_fsm = WRITE_MISS_IVT_LOCK;
+                }
 
 #if DEBUG_MEMC_WRITE
-                    if(m_debug)
-                    {
-                        std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: "
-                            << " address = " << std::hex << r_write_address.read()
-                            << " / hit = " << std::dec << entry.valid
-                            << " / count = " << entry.count
-                            << " / is_cnt = " << entry.is_cnt ;
-                        if((r_write_pktid.read() & 0x7) == TYPE_SC)
-                            std::cout << " / SC access" << std::endl;
-                        else
-                            std::cout << " / SW access" << std::endl;
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: "
+                        << " address = " << std::hex << r_write_address.read()
+                        << " / hit = " << std::dec << entry.valid
+                        << " / count = " << entry.count
+                        << " / is_cnt = " << entry.is_cnt ;
+                    if ((r_write_pktid.read() & 0x7) == TYPE_SC)
+                        std::cout << " / SC access" << std::endl;
+                    else
+                        std::cout << " / SW access" << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////////
+            case WRITE_IVT_LOCK_HIT_WB:
+            {
+                if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
+                {
+
+                    size_t index = 0;
+                    bool   match_inval;
+                    addr_t nline = m_nline[(addr_t) (r_write_address.read())];
+
+                    // if there is a matched updt req, we should wait until it is over.
+                    // Because we need the lastest updt data.
+                    match_inval = m_ivt.search_inval(nline, index);
+
+                    assert((r_write_count.read() == 1) and "NCC to CC req without copy");
+
+                    if (not match_inval                          and
+                        not m_ivt.is_full()                      and
+                        not r_write_to_cc_send_req.read()        and
+                        not r_write_to_cc_send_multi_req.read()  and
+                        not r_write_to_cc_send_brdcast_req.read())
+                    {
+                        r_write_to_cc_send_req   = true;
+                        r_write_to_cc_send_dest  = r_write_copy;
+                        r_write_to_cc_send_nline = nline;
+                        r_write_to_cleanup_req   = true;
+                        r_write_to_cleanup_nline = nline;
+
+                        m_ivt.set(false,  // it's an inval transaction
+                                  false,  // it's not a broadcast
+                                  true,   // it needs no read response
+                                  false,  // no acknowledge required
+                                  m_cmd_write_srcid_fifo.read(), // never read, used for debug
+                                  m_cmd_write_trdid_fifo.read(), // never read, used for debug
+                                  m_cmd_write_pktid_fifo.read(), // never read, used for debug
+                                  nline,
+                                  0x1,    //Expect only one answer
+                                  index);
+                    }
+                    r_write_fsm = WRITE_WAIT;
+#if DEBUG_MEMC_WRITE
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> get access to the IVT: "
+                            << " Inval requested =  " << (not match_inval and not r_write_to_cc_send_req.read())
+                            << std::endl;
                     }
 #endif
                     break;
                 }
-                ////////////////////
-            case WRITE_IVT_LOCK_HIT_WB:
-                {
-                    if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
-                    {
-
-                        size_t index = 0;
-                        bool   match_inval;
-                        addr_t nline = m_nline[(addr_t)(r_write_address.read())];
-
-                        //if there is a matched updt req, we should wait until it is over. Because
-                        //we need the lastest updt data.
-                        match_inval = m_ivt.search_inval(nline, index);
-
-                        assert ((r_write_count.read() == 1) and "NCC to CC req without copy");
-
-                        if( not match_inval                          and
-                            not m_ivt.is_full()                      and
-                            not r_write_to_cc_send_req.read()        and
-                            not r_write_to_cc_send_multi_req.read()  and
-                            not r_write_to_cc_send_brdcast_req.read()   )
-                        {
-                            r_write_to_cc_send_req   = true;
-                            r_write_to_cc_send_dest  = r_write_copy;
-                            r_write_to_cc_send_nline = nline;
-                            r_write_to_cleanup_req   = true;
-                            r_write_to_cleanup_nline = nline;
-
-                            m_ivt.set(false,  // it's an inval transaction
-                                    false,     // it's not a broadcast
-                                    true,      // it needs no read response
-                                    false,     // no acknowledge required
-                                    m_cmd_write_srcid_fifo.read(), //never read, used for debug
-                                    m_cmd_write_trdid_fifo.read(), //never read, used for debug
-                                    m_cmd_write_pktid_fifo.read(), //never read, used for debug
+#if DEBUG_MEMC_WRITE
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> failed to access to the IVT: "
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////
+            case WRITE_DIR_HIT:    // update the cache directory with Dirty bit
+                                   // and update data cache
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+                        "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation");
+
+                DirectoryEntry entry;
+                entry.valid          = true;
+                entry.dirty          = true;
+                entry.tag            = r_write_tag.read();
+                entry.is_cnt         = r_write_is_cnt.read();
+                entry.lock           = r_write_lock.read();
+                entry.owner.srcid    = r_write_copy.read();
+                entry.owner.inst     = r_write_copy_inst.read();
+                entry.count          = r_write_count.read();
+                entry.ptr            = r_write_ptr.read();
+                entry.cache_coherent = r_write_coherent.read();
+
+                size_t set = m_y[(addr_t) (r_write_address.read())];
+                size_t way = r_write_way.read();
+
+                // update directory
+                m_cache_directory.write(set, way, entry);
+
+                // owner is true when the  the first registered copy is the writer itself
+                bool owner = ((r_write_copy.read() == r_write_srcid.read())
+                        and not r_write_copy_inst.read());
+
+                // no_update is true when there is no need for coherence transaction
+                bool no_update = ((r_write_count.read() == 0) or
+                        (owner and (r_write_count.read() == 1) and
+                         ((r_write_pktid.read() & 0x7) != TYPE_SC)));
+
+                // write data in the cache if no coherence transaction
+                if (no_update)
+                {
+                    // SC command but zero copies
+                    if ((r_write_pktid.read() & 0x7) == TYPE_SC)
+                    {
+                        m_llsc_table.sc(r_write_address.read(),
+                                r_write_sc_key.read());
+                    }
+
+                    for (size_t word = 0; word < m_words; word++)
+                    {
+                        m_cache_data.write(way,
+                                           set,
+                                           word,
+                                           r_write_data[word].read(),
+                                           r_write_be[word].read());
+                    }
+                }
+
+                if (owner and not no_update and ((r_write_pktid.read() & 0x7) != TYPE_SC))
+                {
+                    r_write_count = r_write_count.read() - 1;
+                }
+
+                if (no_update) // Write transaction completed
+                {
+                    r_write_fsm = WRITE_RSP;
+                }
+                else // coherence update required
+                {
+                    if (not r_write_to_cc_send_multi_req.read()   and
+                        not r_write_to_cc_send_brdcast_req.read() and
+                        not r_write_to_cc_send_req.read())
+                    {
+                        r_write_fsm = WRITE_UPT_LOCK;
+                    }
+                    else
+                    {
+                        r_write_fsm = WRITE_WAIT;
+                    }
+                }
+
+#if DEBUG_MEMC_WRITE
+                if (m_debug)
+                {
+                    if (no_update)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " WRITE_DIR_HIT> Write into cache / No coherence transaction"
+                            << std::endl;
+                    }
+                    else
+                    {
+                        std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:"
+                            << " is_cnt = " << r_write_is_cnt.read()
+                            << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
+                        if (owner) std::cout << "       ... but the first copy is the writer" << std::endl;
+                    }
+                }
+#endif
+                break;
+            }
+            ////////////////////
+            case WRITE_UPT_LOCK:  // Try to register the update request in UPT
+            {
+                if (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE)
+                {
+                    bool   wok       = false;
+                    size_t index     = 0;
+                    size_t srcid     = r_write_srcid.read();
+                    size_t trdid     = r_write_trdid.read();
+                    size_t pktid     = r_write_pktid.read();
+                    addr_t nline     = m_nline[(addr_t) (r_write_address.read())];
+                    size_t nb_copies = r_write_count.read();
+                    size_t set       = m_y[(addr_t) (r_write_address.read())];
+                    size_t way       = r_write_way.read();
+
+                    wok = m_upt.set(true,  // it's an update transaction
+                                    false, // it's not a broadcast
+                                    true,  // response required
+                                    false, // no acknowledge required
+                                    srcid,
+                                    trdid,
+                                    pktid,
                                     nline,
-                                    0x1, //Expect only one answer
+                                    nb_copies,
                                     index);
-                        }
-                        r_write_fsm = WRITE_WAIT;
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                        {
-                            std::cout << "  <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> get access to the IVT: "
-                                << " Inval requested =  " << (not match_inval and not r_write_to_cc_send_req.read())
-                                << std::endl;
-                        }
-#endif
-                        break;
-                    }
-#if DEBUG_MEMC_WRITE
-                    if(m_debug)
-                    {
-                        std::cout << "  <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> failed to access to the IVT: "
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-                ///////////////////
-            case WRITE_DIR_HIT:
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
-                            "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation");
-
-                    // update the cache directory
-                    // update directory with Dirty bit
-                    DirectoryEntry entry;
-                    entry.valid          = true;
-                    entry.cache_coherent = r_write_coherent.read();
-                    entry.dirty          = true;
-                    entry.tag            = r_write_tag.read();
-                    entry.is_cnt         = r_write_is_cnt.read();
-                    entry.lock           = r_write_lock.read();
-                    entry.owner.srcid    = r_write_copy.read();
-                    entry.owner.inst     = r_write_copy_inst.read();
-                    entry.count          = r_write_count.read();
-                    entry.ptr            = r_write_ptr.read();
-
-                    size_t set           = m_y[(addr_t)(r_write_address.read())];
-                    size_t way           = r_write_way.read();
-
-                    // update directory
-                    m_cache_directory.write(set, way, entry);
-
-                    // owner is true when the  the first registered copy is the writer itself
-                    bool owner = (((r_write_copy.read() == r_write_srcid.read())
-                                ) and not r_write_copy_inst.read());
-
-                    // no_update is true when there is no need for coherence transaction
-                    bool no_update = ( (r_write_count.read() == 0) or
-                            (owner and (r_write_count.read() == 1) and
-                             ((r_write_pktid.read() & 0x7) != TYPE_SC)));
-
-                    // write data in the cache if no coherence transaction
-                    if(no_update)
-                    {
-                        // SC command but zero copies
+
+                    if (wok) // write data in cache
+                    {
                         if ((r_write_pktid.read() & 0x7) == TYPE_SC)
                         {
@@ -3685 +3722 @@
                         }
 
-                        for(size_t word=0 ; word<m_words ; word++)
+                        for (size_t word = 0; word < m_words; word++)
                         {
-                            m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read());
-
+                            m_cache_data.write(way,
+                                               set,
+                                               word,
+                                               r_write_data[word].read(),
+                                               r_write_be[word].read());
                         }
                     }
 
-                    if (owner and not no_update and ((r_write_pktid.read() & 0x7) != TYPE_SC))
-                    {
-                        r_write_count = r_write_count.read() - 1;
-                    }
-
-                    if(no_update)
-                        // Write transaction completed
-                    {
-                        r_write_fsm = WRITE_RSP;
+#if DEBUG_MEMC_WRITE
+                    if (m_debug and wok)
+                    {
+                        if (wok)
+                        {
+                            std::cout << "  <MEMC " << name()
+                                << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
+                                << " nb_copies = " << r_write_count.read() << std::endl;
+                        }
+                    }
+#endif
+                    r_write_upt_index = index;
+                    // releases the lock protecting UPT and the DIR if no entry...
+                    if (wok) r_write_fsm = WRITE_UPT_HEAP_LOCK;
+                    else     r_write_fsm = WRITE_WAIT;
+                }
+                break;
+            }
+
+            /////////////////////////
+            case WRITE_UPT_HEAP_LOCK:   // get access to heap
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)
+                {
+
+#if DEBUG_MEMC_WRITE
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
+                    }
+#endif
+                    r_write_fsm = WRITE_UPT_REQ;
+                }
+                break;
+            }
+
+            //////////////////
+            case WRITE_UPT_REQ:    // prepare the coherence transaction for the CC_SEND FSM
+            // and write the first copy in the FIFO
+            // send the request if only one copy
+            {
+                assert(not r_write_to_cc_send_multi_req.read()   and
+                       not r_write_to_cc_send_brdcast_req.read() and
+                       not r_write_to_cc_send_req.read()         and
+                       "Error in VCI_MEM_CACHE : pending multicast or broadcast\n"
+                       "transaction in WRITE_UPT_REQ state");
+
+                r_write_to_cc_send_brdcast_req = false;
+                r_write_to_cc_send_trdid       = r_write_upt_index.read();
+                r_write_to_cc_send_nline       = m_nline[(addr_t)(r_write_address.read())];
+                r_write_to_cc_send_index       = r_write_word_index.read();
+                r_write_to_cc_send_count       = r_write_word_count.read();
+
+                for (size_t i = 0; i < m_words; i++)
+                {
+                    r_write_to_cc_send_be[i] = r_write_be[i].read();
+                }
+
+                size_t min = r_write_word_index.read();
+                size_t max = r_write_word_index.read() + r_write_word_count.read();
+                for (size_t i = min; i <= max; i++)
+                {
+                    r_write_to_cc_send_data[i] = r_write_data[i];
+                }
+
+                if ((r_write_copy.read() != r_write_srcid.read()) or
+                   ((r_write_pktid.read() & 0x7) == TYPE_SC)      or
+                     r_write_copy_inst.read())
+                {
+                    // put the first srcid in the fifo
+                    write_to_cc_send_fifo_put   = true;
+                    write_to_cc_send_fifo_inst  = r_write_copy_inst.read();
+                    write_to_cc_send_fifo_srcid = r_write_copy.read();
+                    if (r_write_count.read() == 1)
+                    {
+                        r_write_fsm = WRITE_IDLE;
+                        r_write_to_cc_send_multi_req = true;
                     }
                     else
-                        // coherence update required
-                    {
-                        if( not r_write_to_cc_send_multi_req.read()   and
-                            not r_write_to_cc_send_brdcast_req.read() and
-                            not r_write_to_cc_send_req.read()            )
+                    {
+                        r_write_fsm = WRITE_UPT_NEXT;
+                        r_write_to_dec = false;
+
+                    }
+                }
+                else
+                {
+                    r_write_fsm = WRITE_UPT_NEXT;
+                    r_write_to_dec = false;
+                }
+
+#if DEBUG_MEMC_WRITE
+                if (m_debug)
+                {
+                    std::cout
+                        << "  <MEMC " << name()
+                        << " WRITE_UPT_REQ> Post first request to CC_SEND FSM"
+                        << " / srcid = " << std::dec << r_write_copy.read()
+                        << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
+
+                    if (r_write_count.read() == 1)
+                        std::cout << "         ... and this is the last" << std::endl;
+                }
+#endif
+                break;
+            }
+
+            ///////////////////
+            case WRITE_UPT_NEXT:
+            {
+                // continue the multi-update request to CC_SEND fsm
+                // when there is copies in the heap.
+                // if one copy in the heap is the writer itself
+                // the corresponding SRCID should not be written in the fifo,
+                // but the UPT counter must be decremented.
+                // As this decrement is done in the WRITE_UPT_DEC state,
+                // after the last copy has been found, the decrement request
+                // must be  registered in the r_write_to_dec flip-flop.
+
+                HeapEntry entry = m_heap.read(r_write_ptr.read());
+
+                bool dec_upt_counter;
+
+                // put the next srcid in the fifo
+                if ((entry.owner.srcid != r_write_srcid.read()) or
+                   ((r_write_pktid.read() & 0x7) == TYPE_SC)    or
+                     entry.owner.inst)
+                {
+                    dec_upt_counter             = false;
+                    write_to_cc_send_fifo_put   = true;
+                    write_to_cc_send_fifo_inst  = entry.owner.inst;
+                    write_to_cc_send_fifo_srcid = entry.owner.srcid;
+
+#if DEBUG_MEMC_WRITE
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Post another request to CC_SEND FSM"
+                            << " / heap_index = " << std::dec << r_write_ptr.read()
+                            << " / srcid = " << std::dec << r_write_copy.read()
+                            << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
+                        if (entry.next == r_write_ptr.read())
+                            std::cout << "        ... and this is the last" << std::endl;
+                    }
+#endif
+                }
+                else // the UPT counter must be decremented
+                {
+                    dec_upt_counter = true;
+#if DEBUG_MEMC_WRITE
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
+                            << " / heap_index = " << std::dec << r_write_ptr.read()
+                            << " / srcid = " << std::dec << r_write_copy.read()
+                            << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
+                        if (entry.next == r_write_ptr.read())
+                            std::cout << "        ... and this is the last" << std::endl;
+                    }
+#endif
+                }
+
+                // register the possible UPT decrement request
+                r_write_to_dec = dec_upt_counter or r_write_to_dec.read();
+
+                if (not m_write_to_cc_send_inst_fifo.wok())
+                {
+                    std::cout << "*** VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl
+                        << "The write_to_cc_send_fifo should not be full" << std::endl
+                        << "as the depth should be larger than the max number of copies" << std::endl;
+                    exit(0);
+                }
+
+                r_write_ptr = entry.next;
+
+                if (entry.next == r_write_ptr.read()) // last copy
+                {
+                    r_write_to_cc_send_multi_req = true;
+                    if (r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC;
+                    else                                          r_write_fsm = WRITE_IDLE;
+                }
+                break;
+            }
+
+            //////////////////
+            case WRITE_UPT_DEC:
+            {
+                // If the initial writer has a copy, it should not
+                // receive an update request, but the counter in the
+                // update table must be decremented by the MULTI_ACK FSM.
+
+                if (!r_write_to_multi_ack_req.read())
+                {
+                    r_write_to_multi_ack_req = true;
+                    r_write_to_multi_ack_upt_index = r_write_upt_index.read();
+                    r_write_fsm = WRITE_IDLE;
+                }
+                break;
+            }
+
+            ///////////////
+            case WRITE_RSP:  // Post a request to TGT_RSP FSM to acknowledge the write
+                             // In order to increase the Write requests throughput,
+                             // we don't wait to return in the IDLE state to consume
+                             // a new request in the write FIFO
+            {
+                if (not r_write_to_tgt_rsp_req.read())
+                {
+                    // post the request to TGT_RSP_FSM
+                    r_write_to_tgt_rsp_req     = true;
+                    r_write_to_tgt_rsp_srcid   = r_write_srcid.read();
+                    r_write_to_tgt_rsp_trdid   = r_write_trdid.read();
+                    r_write_to_tgt_rsp_pktid   = r_write_pktid.read();
+                    r_write_to_tgt_rsp_sc_fail = r_write_sc_fail.read();
+
+                    // try to get a new write request from the FIFO
+                    if (not m_cmd_write_addr_fifo.rok())
+                    {
+                        r_write_fsm = WRITE_IDLE;
+                    }
+                    else
+                    {
+                        // consume a word in the FIFO & write it in the local buffer
+                        cmd_write_fifo_get  = true;
+                        size_t index        = m_x[(addr_t) (m_cmd_write_addr_fifo.read())];
+
+                        r_write_address     = (addr_t) (m_cmd_write_addr_fifo.read());
+                        r_write_word_index  = index;
+                        r_write_word_count  = 0;
+                        r_write_data[index] = m_cmd_write_data_fifo.read();
+                        r_write_srcid       = m_cmd_write_srcid_fifo.read();
+                        r_write_trdid       = m_cmd_write_trdid_fifo.read();
+                        r_write_pktid       = m_cmd_write_pktid_fifo.read();
+
+                        // if SC command, get the SC key
+                        if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
                         {
-                            r_write_fsm = WRITE_UPT_LOCK;
+                            assert(not m_cmd_write_eop_fifo.read() &&
+                                    "MEMC ERROR in WRITE_RSP state: "
+                                    "invalid packet format for SC command");
+
+                            r_write_sc_key = m_cmd_write_data_fifo.read();
+                        }
+
+                        // initialize the be field for all words
+                        for (size_t word = 0; word < m_words; word++)
+                        {
+                            if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read();
+                            else               r_write_be[word] = 0x0;
+                        }
+
+                        if (m_cmd_write_eop_fifo.read())
+                        {
+                            r_write_fsm = WRITE_DIR_REQ;
                         }
                         else
                         {
-                            r_write_fsm = WRITE_WAIT;
+                            r_write_fsm = WRITE_NEXT;
                         }
                     }
 
 #if DEBUG_MEMC_WRITE
-                    if(m_debug)
-                    {
-                        if(no_update)
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM"
+                            << " : rsrcid = " << std::hex << r_write_srcid.read()
+                            << " : rpktid = " << std::hex << r_write_pktid.read()
+                            << " : sc_fail= " << std::hex << r_write_sc_fail.read()
+                            << std::endl;
+                        if (m_cmd_write_addr_fifo.rok())
                         {
-                            std::cout << "  <MEMC " << name()
-                                << " WRITE_DIR_HIT> Write into cache / No coherence transaction"
+                            std::cout << "                    New Write request: "
+                                << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
+                                << " / address = " << m_cmd_write_addr_fifo.read()
+                                << " / data = " << m_cmd_write_data_fifo.read()
+                                << " / pktid = " << m_cmd_write_pktid_fifo.read()
                                 << std::endl;
                         }
-                        else
-                        {
-                            std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:"
-                                << " is_cnt = " << r_write_is_cnt.read()
-                                << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
-                            if(owner) std::cout << "       ... but the first copy is the writer" << std::endl;
-                        }
-                    }
-#endif
-                    break;
-                }
-                ////////////////////
-            case WRITE_UPT_LOCK:  // Try to register the update request in UPT
-                {
-                    if(r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE)
-                    {
-                        bool        wok        = false;
-                        size_t      index      = 0;
-                        size_t      srcid      = r_write_srcid.read();
-                        size_t      trdid      = r_write_trdid.read();
-                        size_t      pktid      = r_write_pktid.read();
-                        addr_t      nline      = m_nline[(addr_t)(r_write_address.read())];
-                        size_t      nb_copies  = r_write_count.read();
-                        size_t      set        = m_y[(addr_t)(r_write_address.read())];
-                        size_t      way        = r_write_way.read();
-
-
-                        wok = m_upt.set(true,  // it's an update transaction
-                                false, // it's not a broadcast
-                                true,  // response required
-                                false, // no acknowledge required
-                                srcid,
-                                trdid,
-                                pktid,
-                                nline,
-                                nb_copies,
-                                index);
-                        if(wok)       // write data in cache
-                        {
-
-                            if ((r_write_pktid.read() & 0x7) == TYPE_SC)
-                            {
-                                m_llsc_table.sc(r_write_address.read(),
-                                        r_write_sc_key.read());
-                            }
-
-                            for(size_t word=0 ; word<m_words ; word++)
-                            {
-                                m_cache_data.write(way,
-                                        set,
-                                        word,
-                                        r_write_data[word].read(),
-                                        r_write_be[word].read());
-
-                            }
-                        }
-
-#if DEBUG_MEMC_WRITE
-                        if(m_debug and wok)
-                        {
-                            if(wok)
-                            {
-                                std::cout << "  <MEMC " << name()
-                                    << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
-                                    << " nb_copies = " << r_write_count.read() << std::endl;
-                            }
-                        }
-#endif
-                        r_write_upt_index = index;
-                        //  releases the lock protecting UPT and the DIR if no entry...
-                        if(wok) r_write_fsm = WRITE_UPT_HEAP_LOCK;
-                        else    r_write_fsm = WRITE_WAIT;
-                    }
-                    break;
-                }
-
-                /////////////////////////
-            case WRITE_UPT_HEAP_LOCK:   // get access to heap
-                {
-                    if(r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)
-                    {
-
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
-#endif
-                        r_write_fsm = WRITE_UPT_REQ;
-                    }
-                    break;
-                }
-
-                //////////////////
-            case WRITE_UPT_REQ:    // prepare the coherence transaction for the CC_SEND FSM
-                // and write the first copy in the FIFO
-                // send the request if only one copy
-                {
-                    assert( not r_write_to_cc_send_multi_req.read()   and
-                            not r_write_to_cc_send_brdcast_req.read() and
-                            not r_write_to_cc_send_req.read()         and
-                            "Error in VCI_MEM_CACHE : pending multicast or broadcast\n"
-                            "transaction in WRITE_UPT_REQ state"
-                          );
-
-
-                    r_write_to_cc_send_brdcast_req  = false;
-                    r_write_to_cc_send_trdid        = r_write_upt_index.read();
-                    r_write_to_cc_send_nline        = m_nline[(addr_t)(r_write_address.read())];
-                    r_write_to_cc_send_index        = r_write_word_index.read();
-                    r_write_to_cc_send_count        = r_write_word_count.read();
-
-                    for(size_t i=0; i<m_words ; i++) r_write_to_cc_send_be[i]=r_write_be[i].read();
-
-                    size_t min = r_write_word_index.read();
-                    size_t max = r_write_word_index.read() + r_write_word_count.read();
-                    for(size_t i=min ; i<=max ; i++) r_write_to_cc_send_data[i] = r_write_data[i];
-
-                    if ((r_write_copy.read() != r_write_srcid.read()) or
-                            ((r_write_pktid.read() & 0x7) == TYPE_SC)      or
-                            r_write_copy_inst.read())
-                    {
-                        // put the first srcid in the fifo
-                        write_to_cc_send_fifo_put     = true;
-                        write_to_cc_send_fifo_inst    = r_write_copy_inst.read();
-                        write_to_cc_send_fifo_srcid   = r_write_copy.read();
-                        if(r_write_count.read() == 1)
-                        {
-                            r_write_fsm = WRITE_IDLE;
-                            r_write_to_cc_send_multi_req = true;
-                        }
-                        else
-                        {
-                            r_write_fsm = WRITE_UPT_NEXT;
-                            r_write_to_dec = false;
-
-                        }
+                    }
+#endif
+                }
+                break;
+            }
+            ///////////////////////// RWT
+            case WRITE_MISS_IVT_LOCK:
+            {
+                if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
+                {
+                    size_t index;
+                    if (m_ivt.search_inval(m_nline[(addr_t) (r_write_address.read())], index))
+                    {
+                        r_write_fsm = WRITE_WAIT;
                     }
                     else
                     {
-                        r_write_fsm = WRITE_UPT_NEXT;
-                        r_write_to_dec = false;
-                    }
-
-#if DEBUG_MEMC_WRITE
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC "    << name()
-                            << " WRITE_UPT_REQ> Post first request to CC_SEND FSM"
-                            << " / srcid = " << std::dec << r_write_copy.read()
-                            << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
-
-                        if(r_write_count.read() == 1)
-                            std::cout << "         ... and this is the last" << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-                ///////////////////
-            case WRITE_UPT_NEXT:
-                {
-                    // continue the multi-update request to CC_SEND fsm
-                    // when there is copies in the heap.
-                    // if one copy in the heap is the writer itself
-                    // the corresponding SRCID should not be written in the fifo,
-                    // but the UPT counter must be decremented.
-                    // As this decrement is done in the WRITE_UPT_DEC state,
-                    // after the last copy has been found, the decrement request
-                    // must be  registered in the r_write_to_dec flip-flop.
-
-                    HeapEntry entry = m_heap.read(r_write_ptr.read());
-
-                    bool dec_upt_counter;
-
-                    // put the next srcid in the fifo
-                    if ((entry.owner.srcid != r_write_srcid.read()) or
-                            ((r_write_pktid.read() & 0x7) == TYPE_SC)    or
-                            entry.owner.inst)
-                    {
-                        dec_upt_counter                = false;
-                        write_to_cc_send_fifo_put      = true;
-                        write_to_cc_send_fifo_inst     = entry.owner.inst;
-                        write_to_cc_send_fifo_srcid    = entry.owner.srcid;
-
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                        {
-                            std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Post another request to CC_SEND FSM"
-                                << " / heap_index = " << std::dec << r_write_ptr.read()
-                                << " / srcid = " << std::dec << r_write_copy.read()
-                                << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
-                            if(entry.next == r_write_ptr.read())
-                                std::cout << "        ... and this is the last" << std::endl;
-                        }
-#endif
-                    }
-                    else                                // the UPT counter must be decremented
-                    {
-                        dec_upt_counter = true;
-
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                        {
-                            std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
-                                << " / heap_index = " << std::dec << r_write_ptr.read()
-                                << " / srcid = " << std::dec << r_write_copy.read()
-                                << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
-                            if(entry.next == r_write_ptr.read())
-                                std::cout << "        ... and this is the last" << std::endl;
-                        }
-#endif
-                    }
-
-                    // register the possible UPT decrement request
-                    r_write_to_dec = dec_upt_counter or r_write_to_dec.read();
-
-                    if(not m_write_to_cc_send_inst_fifo.wok())
-                    {
-                        std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl
-                            << "The write_to_cc_send_fifo should not be full" << std::endl
-                            << "as the depth should be larger than the max number of copies" << std::endl;
-                        exit(0);
-                    }
-
-                    r_write_ptr = entry.next;
-
-                    if(entry.next == r_write_ptr.read())    // last copy
-                    {
-                        r_write_to_cc_send_multi_req = true;
-                        if(r_write_to_dec.read() or dec_upt_counter)  r_write_fsm = WRITE_UPT_DEC;
-                        else                                          r_write_fsm = WRITE_IDLE;
-                    }
-                    break;
-                }
-
-                //////////////////
-            case WRITE_UPT_DEC:
-                {
-                    // If the initial writer has a copy, it should not
-                    // receive an update request, but the counter in the
-                    // update table must be decremented by the MULTI_ACK FSM.
-
-                    if(!r_write_to_multi_ack_req.read())
-                    {
-                        r_write_to_multi_ack_req = true;
-                        r_write_to_multi_ack_upt_index = r_write_upt_index.read();
-                        r_write_fsm = WRITE_IDLE;
-                    }
-                    break;
-                }
-
-                ///////////////
-            case WRITE_RSP:
-                {
-                    // Post a request to TGT_RSP FSM to acknowledge the write
-                    // In order to increase the Write requests throughput,
-                    // we don't wait to return in the IDLE state to consume
-                    // a new request in the write FIFO
-
-                    if (not r_write_to_tgt_rsp_req.read())
-                    {
-                        // post the request to TGT_RSP_FSM
-                        r_write_to_tgt_rsp_req     = true;
-                        r_write_to_tgt_rsp_srcid   = r_write_srcid.read();
-                        r_write_to_tgt_rsp_trdid   = r_write_trdid.read();
-                        r_write_to_tgt_rsp_pktid   = r_write_pktid.read();
-                        r_write_to_tgt_rsp_sc_fail = r_write_sc_fail.read();
-
-                        // try to get a new write request from the FIFO
-                        if (not m_cmd_write_addr_fifo.rok())
-                        {
-                            r_write_fsm = WRITE_IDLE;
-                        }
-                        else
-                        {
-                            // consume a word in the FIFO & write it in the local buffer
-                            cmd_write_fifo_get  = true;
-                            size_t index        = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
-
-                            r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
-                            r_write_word_index  = index;
-                            r_write_word_count  = 0;
-                            r_write_data[index] = m_cmd_write_data_fifo.read();
-                            r_write_srcid       = m_cmd_write_srcid_fifo.read();
-                            r_write_trdid       = m_cmd_write_trdid_fifo.read();
-                            r_write_pktid       = m_cmd_write_pktid_fifo.read();
-
-                            // if SC command, get the SC key
-                            if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
-                            {
-                                assert( not m_cmd_write_eop_fifo.read() &&
-                                        "MEMC ERROR in WRITE_RSP state: "
-                                        "invalid packet format for SC command");
-
-                                r_write_sc_key = m_cmd_write_data_fifo.read();
-                            }
-
-                            // initialize the be field for all words
-                            for(size_t word=0 ; word<m_words ; word++)
-                            {
-                                if(word == index) r_write_be[word] = m_cmd_write_be_fifo.read();
-                                else              r_write_be[word] = 0x0;
-                            }
-
-                            if( m_cmd_write_eop_fifo.read())
-                            {
-                                r_write_fsm = WRITE_DIR_REQ;
-                            }
-                            else
-                            {
-                                r_write_fsm = WRITE_NEXT;
-                            }
-                        }
-
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                        {
-                            std::cout << "  <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM"
-                                << " : rsrcid = " << std::hex << r_write_srcid.read()
-                                << " : rpktid = " << std::hex << r_write_pktid.read()
-                                << " : sc_fail= " << std::hex << r_write_sc_fail.read()
-                                << std::endl;
-                            if(m_cmd_write_addr_fifo.rok())
-                            {
-                                std::cout << "                    New Write request: "
-                                    << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
-                                    << " / address = " << m_cmd_write_addr_fifo.read()
-                                    << " / data = " << m_cmd_write_data_fifo.read()
-                                    << " / pktid = " << m_cmd_write_pktid_fifo.read()
-                                    << std::endl;
-                            }
-                        }
-#endif
-                    }
-                    break;
-                }
-                ///////////////////////// RWT
-            case WRITE_MISS_IVT_LOCK:
-                {
-                    if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
-                    {
-                        size_t index;
-                        if(m_ivt.search_inval(m_nline[(addr_t)(r_write_address.read())], index))
-                        {
-                            r_write_fsm = WRITE_WAIT;
-                        }
-                        else
-                        {
-                            r_write_fsm = WRITE_MISS_TRT_LOCK;
-                        }
-                    }
-                    break;
-                }
-
-                /////////////////////////
+                        r_write_fsm = WRITE_MISS_TRT_LOCK;
+                    }
+                }
+                break;
+            }
+
+            /////////////////////////
             case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table
-                {
-                    if(r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)
-                    {
-
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
-#endif
-                        size_t  hit_index = 0;
-                        size_t  wok_index = 0;
-                        addr_t  addr  = (addr_t) r_write_address.read();
-                        bool    hit_read  = m_trt.hit_read(m_nline[addr], hit_index);
-                        bool    hit_write = m_trt.hit_write(m_nline[addr]);
-                        bool    wok       = not m_trt.full(wok_index);
-
-                        // wait an empty entry in TRT
-                        if(not hit_read and (not wok or hit_write))
-                        {
-                            r_write_fsm       = WRITE_WAIT;
-                            m_cpt_trt_full++;
-
-                            break;
-                        }
-
-                        if ((r_write_pktid.read() & 0x7) == TYPE_SC)
-                        {
-                            m_llsc_table.sc(r_write_address.read(),
-                                    r_write_sc_key.read());
-                        }
-
-                        // register the modified data in TRT
-                        if (hit_read)
-                        {
-                            r_write_trt_index = hit_index;
-                            r_write_fsm       = WRITE_MISS_TRT_DATA;
-                            m_cpt_write_miss++;
-                            break;
-                        }
-                        // set a new entry in TRT
-                        if (wok and not hit_write)
-                        {
-                            r_write_trt_index = wok_index;
-                            r_write_fsm       = WRITE_MISS_TRT_SET;
-                            m_cpt_write_miss++;
-                            break;
-                        }
-
-                        assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached");
-                    }
-                    break;
-                }
-
-                ////////////////
-            case WRITE_WAIT:  // release the locks protecting the shared ressources
-                {
-
-#if DEBUG_MEMC_WRITE
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl;
-#endif
-                    r_write_fsm = WRITE_DIR_REQ;
-                    break;
-                }
-
-                ////////////////////////
-            case WRITE_MISS_TRT_SET:  // register a new transaction in TRT (Write Buffer)
-                {
-                    if(r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)
-                    {
-                        std::vector<be_t>   be_vector;
-                        std::vector<data_t> data_vector;
-                        be_vector.clear();
-                        data_vector.clear();
-                        for(size_t i=0; i<m_words; i++)
-                        {
-                            be_vector.push_back(r_write_be[i]);
-                            data_vector.push_back(r_write_data[i]);
-                        }
-                        m_trt.set(r_write_trt_index.read(),
-                                true,     // read request to XRAM
-                                m_nline[(addr_t)(r_write_address.read())],
-                                r_write_srcid.read(),
-                                r_write_trdid.read(),
-                                r_write_pktid.read(),
-                                false,      // not a processor read
-                                0,        // not a single word
-                                0,            // word index
-                                be_vector,
-                                data_vector);
-                        r_write_fsm = WRITE_MISS_XRAM_REQ;
-
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
-#endif
-                    }
-                    break;
-                }
-
-                /////////////////////////
-            case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer)
-                {
-                    if(r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)
-                    {
-                        std::vector<be_t> be_vector;
-                        std::vector<data_t> data_vector;
-                        be_vector.clear();
-                        data_vector.clear();
-                        for(size_t i=0; i<m_words; i++)
-                        {
-                            be_vector.push_back(r_write_be[i]);
-                            data_vector.push_back(r_write_data[i]);
-                        }
-                        m_trt.write_data_mask(r_write_trt_index.read(),
-                                be_vector,
-                                data_vector);
-                        r_write_fsm = WRITE_RSP;
-
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
-#endif
-                    }
-                    break;
-                }
-
-                /////////////////////////
-            case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM
-                {
-                    if(not r_write_to_ixr_cmd_req.read())
-                    {
-                        r_write_to_ixr_cmd_req   = true;
-                        r_write_to_ixr_cmd_index = r_write_trt_index.read();
-                        r_write_fsm              = WRITE_RSP;
-
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " WRITE_MISS_XRAM_REQ> Post a GET request to the"
-                                << " IXR_CMD FSM" << std::endl;
-#endif
-                    }
-                    break;
-                }
-
-                ///////////////////////
-            case WRITE_BC_DIR_READ:  // enter this state if a broadcast-inval is required
-                // the cache line must be erased in mem-cache, and written
-                // into XRAM.
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
-                            "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation");
-
-                    m_cpt_write_broadcast++;
-
-                    // write enable signal for data buffer.
-                    r_write_bc_data_we = true;
-
-                    r_write_fsm = WRITE_BC_TRT_LOCK;
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)
+                {
 
 #if DEBUG_MEMC_WRITE
                     if (m_debug)
-                        std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_READ>"
-                            << " Read the cache to complete local buffer" << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////
-            case WRITE_BC_TRT_LOCK:     // get TRT lock to check TRT not full
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
-                            "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation");
-
-                    // We read the cache and complete the buffer. As the DATA cache uses a
-                    // synchronous RAM, the read DATA request has been performed in the
-                    // WRITE_BC_DIR_READ state but the data is available in this state.
-                    if (r_write_bc_data_we.read())
-                    {
-                        size_t set  = m_y[(addr_t)(r_write_address.read())];
-                        size_t way  = r_write_way.read();
-                        for(size_t word=0 ; word<m_words ; word++)
-                        {
-                            data_t mask = 0;
-                            if(r_write_be[word].read() & 0x1) mask = mask | 0x000000FF;
-                            if(r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00;
-                            if(r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000;
-                            if(r_write_be[word].read() & 0x8) mask = mask | 0xFF000000;
-
-                            // complete only if mask is not null (for energy consumption)
-                            r_write_data[word] =
-                                (r_write_data[word].read()         &  mask) |
-                                (m_cache_data.read(way, set, word) & ~mask);
-                        }
-#if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                            std::cout
-                                << "  <MEMC "  << name()
-                                << " WRITE_BC_TRT_LOCK> Complete data buffer" << std::endl;
-#endif
-                    }
-
-                    if (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE)
-                    {
-                        // if we loop in this state, the data does not need to be
-                        // rewritten (for energy consuption)
-                        r_write_bc_data_we = false;
+                    {
+                        std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
+                    }
+#endif
+                    size_t hit_index = 0;
+                    size_t wok_index = 0;
+                    addr_t addr      = (addr_t) r_write_address.read();
+                    bool   hit_read  = m_trt.hit_read(m_nline[addr], hit_index);
+                    bool   hit_write = m_trt.hit_write(m_nline[addr]);
+                    bool   wok       = not m_trt.full(wok_index);
+
+                    // wait an empty entry in TRT
+                    if (not hit_read and (not wok or hit_write))
+                    {
+                        r_write_fsm = WRITE_WAIT;
+                        m_cpt_trt_full++;
                         break;
                     }
-
-                    size_t wok_index = 0;
-                    bool wok = not m_trt.full(wok_index);
-                    if(wok)       // set a new entry in TRT
-                    {
-                        r_write_trt_index = wok_index;
-                        r_write_fsm       = WRITE_BC_IVT_LOCK;
-                    }
-                    else  // wait an empty entry in TRT
-                    {
-                        r_write_fsm       = WRITE_WAIT;
-                    }
-
-#if DEBUG_MEMC_WRITE
-                    if(m_debug)
-                        std::cout << "  <MEMC "  << name()
-                            << " WRITE_BC_TRT_LOCK> Check TRT : wok = " << wok
-                            << " / index = " << wok_index << std::endl;
-#endif
-                    break;
-                }
-
-                //////////////////////
-            case WRITE_BC_IVT_LOCK:      // register BC transaction in IVT
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
-                            "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation");
-
-                    assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and
-                            "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation");
-
-                    if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
-                    {
-                        bool        wok       = false;
-                        size_t      index     = 0;
-                        size_t      srcid     = r_write_srcid.read();
-                        size_t      trdid     = r_write_trdid.read();
-                        size_t      pktid     = r_write_pktid.read();
-                        addr_t      nline     = m_nline[(addr_t)(r_write_address.read())];
-                        size_t      nb_copies = r_write_count.read();
-
-                        wok = m_ivt.set(false,  // it's an inval transaction
-                                true,   // it's a broadcast
-                                true,   // response required
-                                false,  // no acknowledge required
-                                srcid,
-                                trdid,
-                                pktid,
-                                nline,
-                                nb_copies,
-                                index);
-#if DEBUG_MEMC_WRITE
-                        if( m_debug and wok )
-                            std::cout << "  <MEMC " << name() << " WRITE_BC_IVT_LOCK> Register broadcast inval in IVT"
-                                << " / nb_copies = " << r_write_count.read() << std::endl;
-#endif
-                        r_write_upt_index = index;
-
-                        if(wok) r_write_fsm = WRITE_BC_DIR_INVAL;
-                        else    r_write_fsm = WRITE_WAIT;
-                    }
-                    break;
-                }
-
-                ////////////////////////
-            case WRITE_BC_DIR_INVAL:
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
-                            "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation");
-
-                    assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and
-                            "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation");
-
-                    assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and
-                            "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation");
-
-                    // register PUT request in TRT
-                    std::vector<data_t> data_vector;
-                    data_vector.clear();
-                    for(size_t i=0; i<m_words; i++) data_vector.push_back(r_write_data[i].read());
-                    m_trt.set( r_write_trt_index.read(),
-                            false,             // PUT request
-                            m_nline[(addr_t)(r_write_address.read())],
-                            0,                 // unused
-                            0,                 // unused
-                            0,                 // unused
-                            false,             // not a processor read
-                            0,                 // unused
-                            0,                 // unused
-                            std::vector<be_t> (m_words,0),
-                            data_vector );
-
-                    // invalidate directory entry
-                    DirectoryEntry entry;
-                    entry.valid         = false;
-                    entry.cache_coherent= false;
-                    entry.dirty         = false;
-                    entry.tag           = 0;
-                    entry.is_cnt        = false;
-                    entry.lock          = false;
-                    entry.owner.srcid   = 0;
-                    entry.owner.inst    = false;
-                    entry.ptr           = 0;
-                    entry.count         = 0;
-                    size_t set          = m_y[(addr_t)(r_write_address.read())];
-                    size_t way          = r_write_way.read();
-
-                    m_cache_directory.write(set, way, entry);
 
                     if ((r_write_pktid.read() & 0x7) == TYPE_SC)
@@ -4406 +4066 @@
                     }
 
+                    // register the modified data in TRT
+                    if (hit_read)
+                    {
+                        r_write_trt_index = hit_index;
+                        r_write_fsm       = WRITE_MISS_TRT_DATA;
+                        m_cpt_write_miss++;
+                        break;
+                    }
+
+                    // set a new entry in TRT
+                    if (wok and not hit_write)
+                    {
+                        r_write_trt_index = wok_index;
+                        r_write_fsm       = WRITE_MISS_TRT_SET;
+                        m_cpt_write_miss++;
+                        break;
+                    }
+
+                    assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached");
+                }
+                break;
+            }
+
+            ////////////////
+            case WRITE_WAIT:  // release the locks protecting the shared ressources
+            {
+
 #if DEBUG_MEMC_WRITE
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
-                            << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
-#endif
-                    r_write_fsm = WRITE_BC_CC_SEND;
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl;
+                }
+#endif
+                r_write_fsm = WRITE_DIR_REQ;
+                break;
+            }
+
+            ////////////////////////
+            case WRITE_MISS_TRT_SET:  // register a new transaction in TRT (Write Buffer)
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)
+                {
+                    std::vector<be_t> be_vector;
+                    std::vector<data_t> data_vector;
+                    be_vector.clear();
+                    data_vector.clear();
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        be_vector.push_back(r_write_be[i]);
+                        data_vector.push_back(r_write_data[i]);
+                    }
+                    m_trt.set(r_write_trt_index.read(),
+                              true,     // read request to XRAM
+                              m_nline[(addr_t)(r_write_address.read())],
+                              r_write_srcid.read(),
+                              r_write_trdid.read(),
+                              r_write_pktid.read(),
+                              false,    // not a processor read
+                              0,        // not a single word
+                              0,        // word index
+                              be_vector,
+                              data_vector);
+                    r_write_fsm = WRITE_MISS_XRAM_REQ;
+
+#if DEBUG_MEMC_WRITE
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+
+            /////////////////////////
+            case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer)
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)
+                {
+                    std::vector<be_t> be_vector;
+                    std::vector<data_t> data_vector;
+                    be_vector.clear();
+                    data_vector.clear();
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        be_vector.push_back(r_write_be[i]);
+                        data_vector.push_back(r_write_data[i]);
+                    }
+                    m_trt.write_data_mask(r_write_trt_index.read(),
+                                          be_vector,
+                                          data_vector);
+                    r_write_fsm = WRITE_RSP;
+
+#if DEBUG_MEMC_WRITE
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////////
+            case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM
+            {
+                if (not r_write_to_ixr_cmd_req.read())
+                {
+                    r_write_to_ixr_cmd_req   = true;
+                    r_write_to_ixr_cmd_index = r_write_trt_index.read();
+                    r_write_fsm              = WRITE_RSP;
+
+#if DEBUG_MEMC_WRITE
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " WRITE_MISS_XRAM_REQ> Post a GET request to the"
+                            << " IXR_CMD FSM" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ///////////////////////
+            case WRITE_BC_DIR_READ:  // enter this state if a broadcast-inval is required
+                                     // the cache line must be erased in mem-cache, and written
+                                     // into XRAM.
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+                        "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation");
+
+                m_cpt_write_broadcast++;
+
+                // write enable signal for data buffer.
+                r_write_bc_data_we = true;
+
+                r_write_fsm = WRITE_BC_TRT_LOCK;
+
+#if DEBUG_MEMC_WRITE
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_READ>"
+                        << " Read the cache to complete local buffer" << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////
+            case WRITE_BC_TRT_LOCK:     // get TRT lock to check TRT not full
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+                        "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation");
+
+                // We read the cache and complete the buffer. As the DATA cache uses a
+                // synchronous RAM, the read DATA request has been performed in the
+                // WRITE_BC_DIR_READ state but the data is available in this state.
+                if (r_write_bc_data_we.read())
+                {
+                    size_t set = m_y[(addr_t) (r_write_address.read())];
+                    size_t way = r_write_way.read();
+                    for (size_t word = 0; word < m_words; word++)
+                    {
+                        data_t mask = 0;
+                        if (r_write_be[word].read() & 0x1) mask = mask | 0x000000FF;
+                        if (r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00;
+                        if (r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000;
+                        if (r_write_be[word].read() & 0x8) mask = mask | 0xFF000000;
+
+                        // complete only if mask is not null (for energy consumption)
+                        r_write_data[word] =
+                            (r_write_data[word].read()         &  mask) |
+                            (m_cache_data.read(way, set, word) & ~mask);
+                    }
+#if DEBUG_MEMC_WRITE
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC "  << name()
+                            << " WRITE_BC_TRT_LOCK> Complete data buffer" << std::endl;
+                    }
+#endif
+                }
+
+                if (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE)
+                {
+                    // if we loop in this state, the data does not need to be
+                    // rewritten (for energy consuption)
+                    r_write_bc_data_we = false;
                     break;
                 }
 
-                //////////////////////
+                size_t wok_index = 0;
+                bool wok = not m_trt.full(wok_index);
+                if (wok) // set a new entry in TRT
+                {
+                    r_write_trt_index = wok_index;
+                    r_write_fsm       = WRITE_BC_IVT_LOCK;
+                }
+                else  // wait an empty entry in TRT
+                {
+                    r_write_fsm = WRITE_WAIT;
+                }
+
+#if DEBUG_MEMC_WRITE
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC "  << name()
+                        << " WRITE_BC_TRT_LOCK> Check TRT : wok = " << wok
+                        << " / index = " << wok_index << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////
+            case WRITE_BC_IVT_LOCK:      // register BC transaction in IVT
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+                        "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation");
+
+                assert((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and
+                        "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation");
+
+                if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
+                {
+                    bool   wok       = false;
+                    size_t index     = 0;
+                    size_t srcid     = r_write_srcid.read();
+                    size_t trdid     = r_write_trdid.read();
+                    size_t pktid     = r_write_pktid.read();
+                    addr_t nline     = m_nline[(addr_t) (r_write_address.read())];
+                    size_t nb_copies = r_write_count.read();
+
+                    wok = m_ivt.set(false,  // it's an inval transaction
+                                    true,   // it's a broadcast
+                                    true,   // response required
+                                    false,  // no acknowledge required
+                                    srcid,
+                                    trdid,
+                                    pktid,
+                                    nline,
+                                    nb_copies,
+                                    index);
+#if DEBUG_MEMC_WRITE
+                    if (m_debug and wok)
+                    {
+                        std::cout << "  <MEMC " << name() << " WRITE_BC_IVT_LOCK> Register broadcast inval in IVT"
+                            << " / nb_copies = " << r_write_count.read() << std::endl;
+                    }
+#endif
+                    r_write_upt_index = index;
+
+                    if (wok) r_write_fsm = WRITE_BC_DIR_INVAL;
+                    else     r_write_fsm = WRITE_WAIT;
+                }
+                break;
+            }
+            ////////////////////////
+            case WRITE_BC_DIR_INVAL:
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+                        "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation");
+
+                assert((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and
+                        "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation");
+
+                assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and
+                        "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation");
+
+                // register PUT request in TRT
+                std::vector<data_t> data_vector;
+                data_vector.clear();
+                for (size_t i = 0; i < m_words; i++)
+                {
+                    data_vector.push_back(r_write_data[i].read());
+                }
+                m_trt.set(r_write_trt_index.read(),
+                          false,             // PUT request
+                          m_nline[(addr_t) (r_write_address.read())],
+                          0,                 // unused
+                          0,                 // unused
+                          0,                 // unused
+                          false,             // not a processor read
+                          0,                 // unused
+                          0,                 // unused
+                          std::vector<be_t> (m_words, 0),
+                          data_vector);
+
+                // invalidate directory entry
+                DirectoryEntry entry;
+                entry.valid          = false;
+                entry.dirty          = false;
+                entry.tag            = 0;
+                entry.is_cnt         = false;
+                entry.lock           = false;
+                entry.owner.srcid    = 0;
+                entry.owner.inst     = false;
+                entry.ptr            = 0;
+                entry.count          = 0;
+                entry.cache_coherent = false;
+
+                size_t set = m_y[(addr_t) (r_write_address.read())];
+                size_t way = r_write_way.read();
+
+                m_cache_directory.write(set, way, entry);
+
+                if ((r_write_pktid.read() & 0x7) == TYPE_SC)
+                {
+                    m_llsc_table.sc(r_write_address.read(),
+                                    r_write_sc_key.read());
+                }
+
+#if DEBUG_MEMC_WRITE
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
+                        << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
+                }
+#endif
+                r_write_fsm = WRITE_BC_CC_SEND;
+                break;
+            }
+
+            //////////////////////
             case WRITE_BC_CC_SEND:    // Post a coherence broadcast request to CC_SEND FSM
-                {
-                    if( not r_write_to_cc_send_multi_req.read()   and
-                        not r_write_to_cc_send_brdcast_req.read() and
-                        not r_write_to_cc_send_req.read()            )
-                    {
-                        r_write_to_cc_send_multi_req   = false;
-                        r_write_to_cc_send_brdcast_req = true;
-                        r_write_to_cc_send_trdid       = r_write_upt_index.read();
-                        r_write_to_cc_send_nline       = m_nline[(addr_t)(r_write_address.read())];
-                        r_write_to_cc_send_index       = 0;
-                        r_write_to_cc_send_count       = 0;
-
-                        for(size_t i=0; i<m_words ; i++)
-                        {
-                            r_write_to_cc_send_be[i]=0;
-                            r_write_to_cc_send_data[i] = 0;
-                        }
-                        r_write_fsm = WRITE_BC_XRAM_REQ;
+            {
+                if(not r_write_to_cc_send_multi_req.read()   and
+                   not r_write_to_cc_send_brdcast_req.read() and
+                   not r_write_to_cc_send_req.read())
+                {
+                    r_write_to_cc_send_multi_req   = false;
+                    r_write_to_cc_send_brdcast_req = true;
+                    r_write_to_cc_send_trdid       = r_write_upt_index.read();
+                    r_write_to_cc_send_nline       = m_nline[(addr_t) (r_write_address.read())];
+                    r_write_to_cc_send_index       = 0;
+                    r_write_to_cc_send_count       = 0;
+
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        r_write_to_cc_send_be[i] = 0;
+                        r_write_to_cc_send_data[i] = 0;
+                    }
+                    r_write_fsm = WRITE_BC_XRAM_REQ;
 
 #if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
-#endif
-                    }
-                    break;
-                }
-
-                ///////////////////////
-            case WRITE_BC_XRAM_REQ:   // Post a put request to IXR_CMD FSM
-                {
-                    if( not r_write_to_ixr_cmd_req.read() )
-                    {
-                        r_write_to_ixr_cmd_req     = true;
-                        r_write_to_ixr_cmd_index   = r_write_trt_index.read();
-                        r_write_fsm = WRITE_IDLE;
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+
+            ///////////////////////
+            case WRITE_BC_XRAM_REQ:   // Post a PUT request to IXR_CMD FSM
+            {
+                if (not r_write_to_ixr_cmd_req.read())
+                {
+                    r_write_to_ixr_cmd_req   = true;
+                    r_write_to_ixr_cmd_index = r_write_trt_index.read();
+                    r_write_fsm = WRITE_IDLE;
 
 #if DEBUG_MEMC_WRITE
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
-#endif
-                    }
-                    break;
-                }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
         } // end switch r_write_fsm
 
@@ -4485 +4460 @@
         ////////////////////////////////////////////////////////////////////////
 
-        switch(r_ixr_cmd_fsm.read())
+        switch (r_ixr_cmd_fsm.read())
         {
+            ///////////////////////
+            case IXR_CMD_READ_IDLE:
+            {
+                if      (r_write_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+                else if (r_cas_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+                else if (r_cleanup_to_ixr_cmd_req.read())  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+                else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+                else if (r_config_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+                else if (r_read_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+                break;
+            }
             ////////////////////////
-            case IXR_CMD_READ_IDLE:
-                if     (r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
-                else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
-                else if(r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
-                else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
-                else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
-                else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
-                break;
-                ////////////////////////
             case IXR_CMD_WRITE_IDLE:
-                if     (r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
-                else if(r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
-                else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
-                else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
-                else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
-                else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
-                break;
-                ////////////////////////
+            {
+                if      (r_cas_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+                else if (r_cleanup_to_ixr_cmd_req.read())  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+                else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+                else if (r_config_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+                else if (r_read_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+                else if (r_write_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+                break;
+            }
+            //////////////////////
             case IXR_CMD_CAS_IDLE:
-                if     (r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
-                else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
-                else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
-                else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
-                else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
-                else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
-                break;
-                ////////////////////////
+            {
+                if      (r_cleanup_to_ixr_cmd_req.read())  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+                else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+                else if (r_config_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+                else if (r_read_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+                else if (r_write_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+                else if (r_cas_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+                break;
+            }
+            ///////////////////////
             case IXR_CMD_XRAM_IDLE:
-                if     (r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
-                else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
-                else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
-                else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
-                else if(r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
-                else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
-                break;
-                ////////////////////////
+            {
+                if      (r_config_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+                else if (r_read_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+                else if (r_write_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+                else if (r_cas_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+                else if (r_cleanup_to_ixr_cmd_req.read())  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+                else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+                break;
+            }
+            ////////////////////////
             case IXR_CMD_CLEANUP_IDLE:
-                if     (r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
-                else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
-                else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
-                else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
-                else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
-                else if(r_cleanup_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
-                break;
-                /////////////////////////
+            {
+                if      (r_read_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+                else if (r_write_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+                else if (r_cas_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+                else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+                else if (r_config_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+                else if (r_cleanup_to_ixr_cmd_req)         r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+                break;
+            }
+            /////////////////////////
             case IXR_CMD_CONFIG_IDLE:
-                {
-                    if     (r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
-                    else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
-                    else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
-                    else if(r_cleanup_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
-                    else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
-                    else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
-                    break;
-                }
-
-                //////////////////////
+            {
+                if      (r_read_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+                else if (r_write_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+                else if (r_cas_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+                else if (r_cleanup_to_ixr_cmd_req)         r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+                else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+                else if (r_config_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+                break;
+            }
+            //////////////////////
             case IXR_CMD_READ_TRT:       // access TRT for a GET
-                {
-                    if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
-                    {
-                        TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read() );
-                        r_ixr_cmd_address = entry.nline * (m_words<<2);
-                        r_ixr_cmd_trdid   = r_read_to_ixr_cmd_index.read();
-                        r_ixr_cmd_get     = true;
-                        r_ixr_cmd_word    = 0;
-                        r_ixr_cmd_fsm     = IXR_CMD_READ_SEND;
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD)
+                {
+                    TransactionTabEntry entry = m_trt.read(r_read_to_ixr_cmd_index.read());
+                    r_ixr_cmd_address = entry.nline * (m_words << 2);
+                    r_ixr_cmd_trdid   = r_read_to_ixr_cmd_index.read();
+                    r_ixr_cmd_get     = true;
+                    r_ixr_cmd_word    = 0;
+                    r_ixr_cmd_fsm     = IXR_CMD_READ_SEND;
 
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_CMD_READ_TRT> TRT access"
-                                << " index = " << std::dec << r_read_to_ixr_cmd_index.read()
-                                << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
-#endif
-                    }
-                    break;
-                }
-                ///////////////////////
-            case IXR_CMD_WRITE_TRT:       // access TRT for a PUT or a GET
-                {
-                    if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
-                    {
-                        TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read() );
-                        r_ixr_cmd_address = entry.nline * (m_words<<2);
-                        r_ixr_cmd_trdid   = r_write_to_ixr_cmd_index.read();
-                        r_ixr_cmd_get     = entry.xram_read;
-                        r_ixr_cmd_word    = 0;
-                        r_ixr_cmd_fsm     = IXR_CMD_WRITE_SEND;
-
-                        // Read data from TRT if PUT transaction
-                        if (not entry.xram_read)
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_CMD_READ_TRT> TRT access"
+                            << " index = " << std::dec << r_read_to_ixr_cmd_index.read()
+                            << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ///////////////////////
+            case IXR_CMD_WRITE_TRT: // access TRT for a PUT or a GET
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD)
+                {
+                    TransactionTabEntry entry = m_trt.read(r_write_to_ixr_cmd_index.read());
+                    r_ixr_cmd_address = entry.nline * (m_words << 2);
+                    r_ixr_cmd_trdid   = r_write_to_ixr_cmd_index.read();
+                    r_ixr_cmd_get     = entry.xram_read;
+                    r_ixr_cmd_word    = 0;
+                    r_ixr_cmd_fsm     = IXR_CMD_WRITE_SEND;
+
+                    // Read data from TRT if PUT transaction
+                    if (not entry.xram_read)
+                    {
+                        for (size_t i = 0; i < m_words; i++)
                         {
-                            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
+                            r_ixr_cmd_wdata[i] = entry.wdata[i];
                         }
+                    }
 
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_TRT> TRT access"
-                                << " index = " << std::dec << r_write_to_ixr_cmd_index.read()
-                                << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////////////
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_TRT> TRT access"
+                            << " index = " << std::dec << r_write_to_ixr_cmd_index.read()
+                            << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////
             case IXR_CMD_CAS_TRT:       // access TRT for a PUT or a GET
-                {
-                    if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
-                    {
-                        TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read() );
-                        r_ixr_cmd_address = entry.nline * (m_words<<2);
-                        r_ixr_cmd_trdid   = r_cas_to_ixr_cmd_index.read();
-                        r_ixr_cmd_get     = entry.xram_read;
-                        r_ixr_cmd_word    = 0;
-                        r_ixr_cmd_fsm     = IXR_CMD_CAS_SEND;
-
-                        // Read data from TRT if PUT transaction
-                        if (not entry.xram_read)
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD)
+                {
+                    TransactionTabEntry entry = m_trt.read(r_cas_to_ixr_cmd_index.read());
+                    r_ixr_cmd_address = entry.nline * (m_words << 2);
+                    r_ixr_cmd_trdid   = r_cas_to_ixr_cmd_index.read();
+                    r_ixr_cmd_get     = entry.xram_read;
+                    r_ixr_cmd_word    = 0;
+                    r_ixr_cmd_fsm     = IXR_CMD_CAS_SEND;
+
+                    // Read data from TRT if PUT transaction
+                    if (not entry.xram_read)
+                    {
+                        for (size_t i = 0; i < m_words; i++)
                         {
-                            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
+                            r_ixr_cmd_wdata[i] = entry.wdata[i];
                         }
+                    }
 
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_TRT> TRT access"
-                                << " index = " << std::dec << r_cas_to_ixr_cmd_index.read()
-                                << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
-#endif
-                    }
-                    break;
-                }
-                //////////////////////
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_TRT> TRT access"
+                            << " index = " << std::dec << r_cas_to_ixr_cmd_index.read()
+                            << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            //////////////////////
             case IXR_CMD_XRAM_TRT:       // access TRT for a PUT
-                {
-                    if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
-                    {
-                        TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read() );
-                        r_ixr_cmd_address = entry.nline * (m_words<<2);
-                        r_ixr_cmd_trdid   = r_xram_rsp_to_ixr_cmd_index.read();
-                        r_ixr_cmd_get     = false;
-                        r_ixr_cmd_word    = 0;
-                        r_ixr_cmd_fsm     = IXR_CMD_XRAM_SEND;
-                        for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD)
+                {
+                    TransactionTabEntry entry = m_trt.read(r_xram_rsp_to_ixr_cmd_index.read());
+                    r_ixr_cmd_address = entry.nline * (m_words << 2);
+                    r_ixr_cmd_trdid   = r_xram_rsp_to_ixr_cmd_index.read();
+                    r_ixr_cmd_get     = false;
+                    r_ixr_cmd_word    = 0;
+                    r_ixr_cmd_fsm     = IXR_CMD_XRAM_SEND;
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        r_ixr_cmd_wdata[i] = entry.wdata[i];
+                    }
 
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM_TRT> TRT access"
-                                << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read()
-                                << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
-#endif
-                    }
-                    break;
-                }
-                //////////////////////
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM_TRT> TRT access"
+                            << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read()
+                            << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            //////////////////////
             case IXR_CMD_CLEANUP_TRT:       // access TRT for a PUT
-                {
-                    if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
-                    {
-
-                        TransactionTabEntry entry = m_trt.read( r_cleanup_to_ixr_cmd_index.read() );
-                        r_ixr_cmd_address = entry.nline * (m_words<<2);
-                        r_ixr_cmd_trdid   = r_cleanup_to_ixr_cmd_index.read();
-                        r_ixr_cmd_get     = false;
-                        r_ixr_cmd_word    = 0;
-                        r_ixr_cmd_fsm     = IXR_CMD_CLEANUP_DATA_SEND;
-                        for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD)
+                {
+                    TransactionTabEntry entry = m_trt.read(r_cleanup_to_ixr_cmd_index.read());
+                    r_ixr_cmd_address = entry.nline * (m_words << 2);
+                    r_ixr_cmd_trdid   = r_cleanup_to_ixr_cmd_index.read();
+                    r_ixr_cmd_get     = false;
+                    r_ixr_cmd_word    = 0;
+                    r_ixr_cmd_fsm     = IXR_CMD_CLEANUP_DATA_SEND;
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        r_ixr_cmd_wdata[i] = entry.wdata[i];
+                    }
 
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_CMD_CLEANUP_TRT> TRT access"
-                                << " index = " << std::dec << r_cleanup_to_ixr_cmd_index.read()
-                                << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
-#endif
-                    }
-                    break;
-                }
-                ////////////////////////
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_CMD_CLEANUP_TRT> TRT access"
+                            << " index = " << std::dec << r_cleanup_to_ixr_cmd_index.read()
+                            << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ////////////////////////
             case IXR_CMD_CONFIG_TRT:       // access TRT for a PUT
-                {
-                    if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
-                    {
-                        TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read() );
-                        r_ixr_cmd_address = entry.nline * (m_words<<2);
-                        r_ixr_cmd_trdid   = r_config_to_ixr_cmd_index.read();
-                        r_ixr_cmd_get     = false;
-                        r_ixr_cmd_word    = 0;
-                        r_ixr_cmd_fsm     = IXR_CMD_CONFIG_SEND;
-                        for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD)
+                {
+                    TransactionTabEntry entry = m_trt.read(r_config_to_ixr_cmd_index.read());
+                    r_ixr_cmd_address = entry.nline * (m_words << 2);
+                    r_ixr_cmd_trdid   = r_config_to_ixr_cmd_index.read();
+                    r_ixr_cmd_get     = false;
+                    r_ixr_cmd_word    = 0;
+                    r_ixr_cmd_fsm     = IXR_CMD_CONFIG_SEND;
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        r_ixr_cmd_wdata[i] = entry.wdata[i];
+                    }
 
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_CMD_CONFIG_TRT> TRT access"
-                                << " index = " << std::dec << r_config_to_ixr_cmd_index.read()
-                                << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
-#endif
-                    }
-                    break;
-                }
-
-                ///////////////////////
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_CMD_CONFIG_TRT> TRT access"
+                            << " index = " << std::dec << r_config_to_ixr_cmd_index.read()
+                            << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+
+            ///////////////////////
             case IXR_CMD_READ_SEND:      // send a get from READ FSM
-                {
-                    if(p_vci_ixr.cmdack)
-                    {
-                        r_ixr_cmd_fsm         = IXR_CMD_READ_IDLE;
-                        r_read_to_ixr_cmd_req = false;
+            {
+                if (p_vci_ixr.cmdack)
+                {
+                    r_ixr_cmd_fsm         = IXR_CMD_READ_IDLE;
+                    r_read_to_ixr_cmd_req = false;
 
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_CMD_READ_SEND> GET request:" << std::hex
-                                << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
-#endif
-                    }
-                    break;
-                }
-                ////////////////////////
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_CMD_READ_SEND> GET request:" << std::hex
+                            << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ////////////////////////
             case IXR_CMD_WRITE_SEND:     // send a put or get from WRITE FSM
-                {
-                    if(p_vci_ixr.cmdack)
-                    {
-                        if (not r_ixr_cmd_get.read())   // PUT
-                        {
-                            if(r_ixr_cmd_word.read() == (m_words - 2))
-                            {
-                                r_ixr_cmd_fsm          = IXR_CMD_WRITE_IDLE;
-                                r_write_to_ixr_cmd_req = false;
-                            }
-                            else
-                            {
-                                r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
-                            }
-
-#if DEBUG_MEMC_IXR_CMD
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_SEND> PUT request:" << std::hex
-                                    << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
-#endif
-                        }
-                        else                                  // GET
+            {
+                if (p_vci_ixr.cmdack)
+                {
+                    if (not r_ixr_cmd_get.read())   // PUT
+                    {
+                        if (r_ixr_cmd_word.read() == (m_words - 2))
                         {
                             r_ixr_cmd_fsm          = IXR_CMD_WRITE_IDLE;
                             r_write_to_ixr_cmd_req = false;
-
-#if DEBUG_MEMC_IXR_CMD
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_SEND> GET request:" << std::hex
-                                    << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
-#endif
-                        }
-                    }
-                    break;
-                }
-                //////////////////////
-            case IXR_CMD_CAS_SEND:      // send a put or get command from CAS FSM
-                {
-                    if(p_vci_ixr.cmdack)
-                    {
-                        if (not r_ixr_cmd_get.read()) // PUT
-                        {
-                            if(r_ixr_cmd_word.read() == (m_words - 2))
-                            {
-                                r_ixr_cmd_fsm        = IXR_CMD_CAS_IDLE;
-                                r_cas_to_ixr_cmd_req = false;
-                            }
-                            else
-                            {
-                                r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
-                            }
-
-#if DEBUG_MEMC_IXR_CMD
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_SEND> PUT request:" << std::hex
-                                    << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
-#endif
-                        }
-                        else                            // GET
-                        {
-                            r_ixr_cmd_fsm        = IXR_CMD_CAS_IDLE;
-                            r_cas_to_ixr_cmd_req = false;
-
-#if DEBUG_MEMC_IXR_CMD
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_SEND> GET request:" << std::hex
-                                    << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
-#endif
-                        }
-                    }
-                    break;
-                }
-                ///////////////////////
-            case IXR_CMD_XRAM_SEND:     // send a put from XRAM_RSP FSM
-                {
-                    if(p_vci_ixr.cmdack.read())
-                    {
-                        if(r_ixr_cmd_word.read() == (m_words - 2))
-                        {
-                            r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
-                            r_xram_rsp_to_ixr_cmd_req = false;
                         }
                         else
@@ -4791 +4731 @@
                             r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
                         }
+
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM_SEND> PUT request:" << std::hex
-                                << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
-#endif
-                    }
-                    break;
-                }
-
-                ////////////////////////
-            case IXR_CMD_CLEANUP_DATA_SEND:     // send a put command to XRAM
-                {
-                    if(p_vci_ixr.cmdack.read())
-                    {
-                        if(r_ixr_cmd_word.read() == (m_words - 2))
+                        if (m_debug)
                         {
-                            r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE;
-                            r_cleanup_to_ixr_cmd_req = false;
-                            //r_ixr_cmd_word = 0;
-                            //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;
+                            std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_SEND> PUT request:" << std::hex
+                                << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl;
+                        }
+#endif
+                    }
+                    else // GET
+                    {
+                        r_ixr_cmd_fsm          = IXR_CMD_WRITE_IDLE;
+                        r_write_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+                        if (m_debug)
+                        {
+                            std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_SEND> GET request:" << std::hex
+                                << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl;
+                        }
+#endif
+                    }
+                }
+                break;
+            }
+            //////////////////////
+            case IXR_CMD_CAS_SEND: // send a put or get command from CAS FSM
+            {
+                if (p_vci_ixr.cmdack)
+                {
+                    if (not r_ixr_cmd_get.read()) // PUT
+                    {
+                        if (r_ixr_cmd_word.read() == (m_words - 2))
+                        {
+                            r_ixr_cmd_fsm        = IXR_CMD_CAS_IDLE;
+                            r_cas_to_ixr_cmd_req = false;
                         }
                         else
@@ -4818 +4774 @@
 
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
+                        if (m_debug)
                         {
-                            std::cout << "  <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA_SEND> Send a put request to xram" << std::endl;
+                            std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_SEND> PUT request:" << std::hex
+                                << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl;
                         }
 #endif
                     }
-                    break;
-                }
-
-                /////////////////////////
+                    else // GET
+                    {
+                        r_ixr_cmd_fsm        = IXR_CMD_CAS_IDLE;
+                        r_cas_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+                        if (m_debug)
+                        {
+                            std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_SEND> GET request:" << std::hex
+                                << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl;
+                        }
+#endif
+                    }
+                }
+                break;
+            }
+            ///////////////////////
+            case IXR_CMD_XRAM_SEND: // send a put from XRAM_RSP FSM
+            {
+                if (p_vci_ixr.cmdack.read())
+                {
+                    if (r_ixr_cmd_word.read() == (m_words - 2))
+                    {
+                        r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
+                        r_xram_rsp_to_ixr_cmd_req = false;
+                    }
+                    else
+                    {
+                        r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+                    }
+#if DEBUG_MEMC_IXR_CMD
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM_SEND> PUT request:" << std::hex
+                            << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+
+            ////////////////////////
+            case IXR_CMD_CLEANUP_DATA_SEND: // send a put command to XRAM
+            {
+                if (p_vci_ixr.cmdack.read())
+                {
+                    if (r_ixr_cmd_word.read() == (m_words - 2))
+                    {
+                        r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE;
+                        r_cleanup_to_ixr_cmd_req = false;
+                    }
+                    else
+                    {
+                        r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+                    }
+
+#if DEBUG_MEMC_IXR_CMD
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA_SEND> Send a put request to xram" << std::hex
+                            << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////////
             case IXR_CMD_CONFIG_SEND:     // send a put from CONFIG FSM
-                {
-                    if(p_vci_ixr.cmdack.read())
-                    {
-                        if(r_ixr_cmd_word.read() == (m_words - 2))
-                        {
-                            r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE;
-                            r_config_to_ixr_cmd_req = false;
-                        }
-                        else
-                        {
-                            r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
-                        }
+            {
+                if (p_vci_ixr.cmdack.read())
+                {
+                    if (r_ixr_cmd_word.read() == (m_words - 2))
+                    {
+                        r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE;
+                        r_config_to_ixr_cmd_req = false;
+                    }
+                    else
+                    {
+                        r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+                    }
 
 #if DEBUG_MEMC_IXR_CMD
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_CMD_CONFIG_SEND> PUT request:" << std::hex
-                                << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
-#endif
-                    }
-                    break;
-                }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_CMD_CONFIG_SEND> PUT request:" << std::hex
+                            << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
         } // end switch r_ixr_cmd_fsm
 
@@ -4877 +4899 @@
             //////////////////
             case IXR_RSP_IDLE:  // test transaction type: PUT/GET
-                {
-                    if(p_vci_ixr.rspval.read())
-                    {
-                        r_ixr_rsp_cpt       = 0;
-                        r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
-
-                        if (p_vci_ixr.reop.read() and not
+            {
+                if (p_vci_ixr.rspval.read())
+                {
+                    r_ixr_rsp_cpt       = 0;
+                    r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+
+                    if (p_vci_ixr.reop.read() and not
                             p_vci_ixr.rerror.read())   // PUT
+                    {
+                        r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+
+#if DEBUG_MEMC_IXR_RSP
+                        if (m_debug)
                         {
-                            r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+                            std::cout << "  <MEMC " << name()
+                                << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
                         }
-
-                        else                       // GET transaction
+#endif
+                    }
+                    else // GET
+                    {
+                        r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+
+#if DEBUG_MEMC_IXR_RSP
+                        if (m_debug)
                         {
-                            r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
-
-#if DEBUG_MEMC_IXR_RSP
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name()
-                                    << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
-#endif
+                            std::cout << "  <MEMC " << name()
+                                << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
                         }
-                    }
-                    break;
-                }
-                ////////////////////////
-            case IXR_RSP_ACK:     // Acknowledge PUT transaction
-                {
-                    r_ixr_rsp_fsm = IXR_RSP_IDLE;
-                    break;
-                }
-
-               ///////////////////////
+#endif
+                    }
+                }
+                break;
+            }
+            //////////////////////////
             case IXR_RSP_TRT_ERASE: // erase the entry in the TRT
                                     // decrease the line counter if config request
-                {
-                    if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)
-                    {
-                        size_t  index = r_ixr_rsp_trt_index.read();
-                        if (m_trt.is_config(index))     // it's a config transaction
-                        {
-                            config_rsp_lines_ixr_rsp_decr = true;
-                        }
-                        m_trt.erase(index);
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)
+                {
+                    size_t index = r_ixr_rsp_trt_index.read();
+
+                    if (m_trt.is_config(index)) // it's a config transaction
+                    {
+                        config_rsp_lines_ixr_rsp_decr = true;
+                    }
+
+                    m_trt.erase(index);
+                    r_ixr_rsp_fsm = IXR_RSP_IDLE;
+
+#if DEBUG_MEMC_IXR_RSP
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry "
+                            << r_ixr_rsp_trt_index.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            //////////////////////
+            case IXR_RSP_TRT_READ: // write a 64 bits data word in TRT
+            {
+                if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval)
+                {
+                    size_t      index  = r_ixr_rsp_trt_index.read();
+                    size_t      word   = r_ixr_rsp_cpt.read();
+                    bool        eop    = p_vci_ixr.reop.read();
+                    wide_data_t data   = p_vci_ixr.rdata.read();
+                    bool        rerror = ((p_vci_ixr.rerror.read() & 0x1) == 1);
+
+                    assert(((eop == (word == (m_words - 2))) or rerror) and
+                    "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM");
+
+                    m_trt.write_rsp(index, word, data, rerror);
+
+                    r_ixr_rsp_cpt = word + 2;
+
+                    if (eop)
+                    {
+                        r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()] = true;
                         r_ixr_rsp_fsm = IXR_RSP_IDLE;
+                    }
 
 #if DEBUG_MEMC_IXR_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry "
-                                << r_ixr_rsp_trt_index.read() << std::endl;
-#endif
-                    }
-                    break;
-                }
-                //////////////////////
-            case IXR_RSP_TRT_READ:    // write a 64 bits data in the TRT
-                {
-                    if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and  p_vci_ixr.rspval)
-                    {
-                        size_t      index    = r_ixr_rsp_trt_index.read();
-                        size_t      word     = r_ixr_rsp_cpt.read();
-                        bool        eop      = p_vci_ixr.reop.read();
-                        wide_data_t data     = p_vci_ixr.rdata.read();
-                        bool        rerror   = ((p_vci_ixr.rerror.read() & 0x1) == 1);
-
-                        assert(((eop == (word == (m_words-2))) or rerror) and
-                                "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM");
-
-                        m_trt.write_rsp( index, word, data, rerror );
-
-                        r_ixr_rsp_cpt = word + 2;
-
-                        if(eop)
-                        {
-                            r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
-                            r_ixr_rsp_fsm = IXR_RSP_IDLE;
-                        }
-
-#if DEBUG_MEMC_IXR_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : "
-                                << " index = " << std::dec << index
-                                << " / word = " << word
-                                << " / data = " << std::hex << data << std::endl;
-#endif
-                    }
-                    break;
-                }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_READ> Writing 2 words in TRT : "
+                            << " index = " << std::dec << index
+                            << " / word = " << word
+                            << " / data = " << std::hex << data << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
         } // end swich r_ixr_rsp_fsm
 
@@ -4994 +5024 @@
             ///////////////////
             case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin)
-                {
-                    size_t old   = r_xram_rsp_trt_index.read();
-                    size_t lines = m_trt_lines;
-                    for(size_t i=0 ; i<lines ; i++)
-                    {
-                        size_t index = (i+old+1) %lines;
-                        if(r_ixr_rsp_to_xram_rsp_rok[index])
+            {
+                size_t old = r_xram_rsp_trt_index.read();
+                size_t lines = m_trt_lines;
+                for (size_t i = 0; i < lines; i++)
+                {
+                    size_t index = (i + old + 1) % lines;
+                    if (r_ixr_rsp_to_xram_rsp_rok[index])
+                    {
+                        r_xram_rsp_trt_index             = index;
+                        r_ixr_rsp_to_xram_rsp_rok[index] = false;
+                        r_xram_rsp_fsm                   = XRAM_RSP_DIR_LOCK;
+
+#if DEBUG_MEMC_XRAM_RSP
+                        if (m_debug)
                         {
-                            r_xram_rsp_trt_index             = index;
-                            r_ixr_rsp_to_xram_rsp_rok[index] = false;
-                            r_xram_rsp_fsm                   = XRAM_RSP_DIR_LOCK;
+                            std::cout << "  <MEMC " << name() << " XRAM_RSP_IDLE>"
+                                << " Available cache line in TRT:"
+                                << " index = " << std::dec << index << std::endl;
+                        }
+#endif
+                        break;
+                    }
+                }
+                break;
+            }
+            ///////////////////////
+            case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock
+            // Copy the TRT entry in a local buffer
+            {
+                if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+                        (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP))
+                {
+                    // copy the TRT entry in the r_xram_rsp_trt_buf local buffer
+                    size_t index = r_xram_rsp_trt_index.read();
+                    r_xram_rsp_trt_buf.copy(m_trt.read(index));
+                    r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
 
 #if DEBUG_MEMC_XRAM_RSP
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " XRAM_RSP_IDLE>"
-                                    << " Available cache line in TRT:"
-                                    << " index = " << std::dec << index << std::endl;
-#endif
-                            break;
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_LOCK>"
+                            << " Get access to DIR and TRT" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ///////////////////////
+            case XRAM_RSP_TRT_COPY: // Select a victim cache line
+            // and copy it in a local buffer
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+                        "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation");
+
+                assert((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+                        "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation");
+
+                // selects & extracts a victim line from cache
+                size_t way = 0;
+                size_t set = m_y[(addr_t) (r_xram_rsp_trt_buf.nline * m_words * 4)];
+
+                DirectoryEntry victim(m_cache_directory.select(set, way));
+
+                bool inval = (victim.count and victim.valid) or
+                             (!victim.cache_coherent and (victim.count == 1));
+
+                // copy the victim line in a local buffer (both data dir)
+                m_cache_data.read_line(way, set, r_xram_rsp_victim_data);
+
+                r_xram_rsp_victim_copy      = victim.owner.srcid;
+                r_xram_rsp_victim_coherent  = victim.cache_coherent;
+                r_xram_rsp_victim_copy_inst = victim.owner.inst;
+                r_xram_rsp_victim_count     = victim.count;
+                r_xram_rsp_victim_ptr       = victim.ptr;
+                r_xram_rsp_victim_way       = way;
+                r_xram_rsp_victim_set       = set;
+                r_xram_rsp_victim_nline     = (addr_t) victim.tag * m_sets + set;
+                r_xram_rsp_victim_is_cnt    = victim.is_cnt;
+                r_xram_rsp_victim_inval     = inval;
+                // a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry
+                r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent and (victim.count == 1));
+
+                // A line that undergoes a change in its state (ncc to cc), should not be evicted from the memory cache.
+                if (((addr_t) victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read())
+                {
+                    r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+
+#if DEBUG_MEMC_XRAM_RSP
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
+                            << " Victim line is in ncc to cc mecanism"
+                            << " / nline = " << std::hex << (victim.tag * m_sets + set)
+                            << std::endl;
+                    }
+#endif
+                }
+                else if (not r_xram_rsp_trt_buf.rerror)
+                {
+                    r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;
+                }
+                else
+                {
+                    r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
+                }
+
+#if DEBUG_MEMC_XRAM_RSP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
+                        << " Select a victim slot: "
+                        << " way = " << std::dec << way
+                        << " / set = " << set
+                        << "/ count = " << victim.count
+                        << " / inval_required = " << inval << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////
+            case XRAM_RSP_IVT_LOCK:   // Keep DIR and TRT locks and take the IVT lock
+            // to check a possible pending inval
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+                        "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation");
+
+                assert((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+                        "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation");
+
+                if (r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP)
+                {
+                    size_t index = 0;
+                    if (m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index))  // pending inval
+                    {
+                        r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+
+#if DEBUG_MEMC_XRAM_RSP
+                        if (m_debug)
+                        {
+                            std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
+                                << " Get acces to IVT, but line invalidation registered"
+                                << " / address = " << std::hex << r_xram_rsp_trt_buf.nline * m_words * 4
+                                << " / index = " << std::dec << index << std::endl;
                         }
-                    }
-                    break;
-                }
-                ///////////////////////
-            case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock
-                // Copy the TRT entry in a local buffer
-                {
-                    if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
-                            (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP))
-                    {
-                        // copy the TRT entry in the r_xram_rsp_trt_buf local buffer
-                        size_t  index = r_xram_rsp_trt_index.read();
-                        r_xram_rsp_trt_buf.copy( m_trt.read(index) );
-                        r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
+#endif
+
+                    }
+                    else if (m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full
+                    {
+                        r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_LOCK>"
-                                << " Get access to DIR and TRT" << std::endl;
-#endif
-                    }
-                    break;
-                }
-                ///////////////////////
-            case XRAM_RSP_TRT_COPY: // Select a victim cache line
-                // and copy it in a local buffer
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
-                            "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation");
-
-                    assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
-                            "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation");
-
-                    // selects & extracts a victim line from cache
-                    size_t way = 0;
-                    size_t set = m_y[(addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)];
-
-                    DirectoryEntry victim(m_cache_directory.select(set, way));
-
-                    bool inval = (victim.count && victim.valid) or (!victim.cache_coherent and (victim.count == 1)) ;
-
-
-                    // copy the victim line in a local buffer
-                    m_cache_data.read_line(way, set, r_xram_rsp_victim_data);
-
-                    r_xram_rsp_victim_copy      = victim.owner.srcid;
-                    r_xram_rsp_victim_coherent  = victim.cache_coherent;
-                    r_xram_rsp_victim_copy_inst = victim.owner.inst;
-                    r_xram_rsp_victim_count     = victim.count;
-                    r_xram_rsp_victim_ptr       = victim.ptr;
-                    r_xram_rsp_victim_way       = way;
-                    r_xram_rsp_victim_set       = set;
-                    r_xram_rsp_victim_nline     = victim.tag*m_sets + set;
-                    r_xram_rsp_victim_is_cnt    = victim.is_cnt;
-                    r_xram_rsp_victim_inval     = inval ;
-                    // a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry
-                    r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent && (victim.count == 1));
-
-
-                    // A line that undergoes a change in its state (ncc to cc), should not be evicted from the memory cache.
-                    if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read())
-                    {
-                        r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+                        if (m_debug)
+                        {
+                            std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
+                                << " Get acces to IVT, but inval required and IVT full" << std::endl;
+                        }
+#endif
+                    }
+                    else
+                    {
+                        r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
 
 #if DEBUG_MEMC_XRAM_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
-                                << " Victim line is in ncc to cc mecanism"
-                                << " / nline = " << std::hex << (victim.tag * m_sets + set)
-                                << std::endl;
-#endif
-                    }
-                    else if( not r_xram_rsp_trt_buf.rerror )
-                    {
-                        r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;
+                        if (m_debug)
+                        {
+                            std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
+                                << " Get acces to IVT / no pending inval request" << std::endl;
+                        }
+#endif
+                    }
+                }
+                break;
+            }
+            /////////////////////////
+            case XRAM_RSP_INVAL_WAIT: // release all locks and returns to DIR_LOCK to retry
+            {
+
+#if DEBUG_MEMC_XRAM_RSP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_WAIT>"
+                        << " Release all locks and retry" << std::endl;
+                }
+#endif
+                r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
+                break;
+            }
+            ///////////////////////
+            case XRAM_RSP_DIR_UPDT:   // updates the cache (both data & directory),
+            // erases the TRT entry if victim not dirty,
+            // and set inval request in IVT if required
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+                        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad DIR allocation");
+
+                assert((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+                        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad TRT allocation");
+
+                assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_XRAM_RSP) and
+                        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad IVT allocation");
+
+                // check if this is an instruction read, this means pktid is either
+                // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
+                // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+                bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read;
+
+                // check if this is a cached read, this means pktid is either
+                // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
+                // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+                bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read;
+
+                bool dirty = false;
+
+                // update cache data
+                size_t set = r_xram_rsp_victim_set.read();
+                size_t way = r_xram_rsp_victim_way.read();
+
+                for (size_t word = 0; word < m_words; word++)
+                {
+                    m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
+                    dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0);
+                }
+
+                // update cache directory
+                DirectoryEntry entry;
+                entry.valid  = true;
+                entry.is_cnt = false;
+                entry.lock   = false;
+                entry.dirty  = dirty;
+                entry.tag    = r_xram_rsp_trt_buf.nline / m_sets;
+                entry.ptr    = 0;
+                entry.cache_coherent = (inst_read or (!cached_read)) and (r_xram_rsp_trt_buf.proc_read);
+
+                if (cached_read)
+                {
+                    entry.owner.srcid = r_xram_rsp_trt_buf.srcid;
+                    entry.owner.inst  = inst_read;
+                    entry.count       = 1;
+                }
+                else
+                {
+                    entry.owner.srcid = 0;
+                    entry.owner.inst  = 0;
+                    entry.count       = 0;
+                }
+                m_cache_directory.write(set, way, entry);
+                //RWT: keep the coherence information in order to send it to the read_rsp
+                r_xram_rsp_coherent = inst_read or (!cached_read);
+                // request an invalidattion request in IVT for victim line
+                if (r_xram_rsp_victim_inval.read())
+                {
+                    bool   broadcast    = r_xram_rsp_victim_is_cnt.read();
+                    size_t index        = 0;
+                    size_t count_copies = r_xram_rsp_victim_count.read();
+
+                    bool wok = m_ivt.set(false,     // it's an inval transaction
+                                         broadcast, // set broadcast bit
+                                         false,     // no response required
+                                         false,     // no acknowledge required
+                                         0,         // srcid
+                                         0,         // trdid
+                                         0,         // pktid
+                                         r_xram_rsp_victim_nline.read(),
+                                         count_copies,
+                                         index);
+
+                    r_xram_rsp_ivt_index = index;
+                    assert(wok and
+                           "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full");
+
+                }
+                if (!r_xram_rsp_victim_coherent.read())
+                {
+                    addr_t min = r_xram_rsp_victim_nline.read() * m_words * 4;
+                    addr_t max = r_xram_rsp_victim_nline.read() * m_words * 4 + (m_words - 1) * 4;
+                    m_llsc_table.sw(min, max);
+                }
+#if DEBUG_MEMC_XRAM_RSP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_UPDT>"
+                        << " Cache update: "
+                        << " way = " << std::dec << way
+                        << " / set = " << set
+                        << " / owner_id = " << std::hex << entry.owner.srcid
+                        << " / owner_ins = " << std::dec << entry.owner.inst
+                        << " / count = " << entry.count
+                        << " / nline = " << r_xram_rsp_trt_buf.nline
+                        << " / is_cnt = " << entry.is_cnt << std::endl;
+                    if (r_xram_rsp_victim_inval.read())
+                    {
+                        std::cout << "          Invalidation request for address "
+                            << std::hex << r_xram_rsp_victim_nline.read() * m_words * 4
+                            << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl;
+                    }
+                }
+#endif
+
+                // If the victim is not dirty (RWT: if it is not coherent,
+                // we can not know wether it is dirty or not), we don't
+                // need another XRAM  put transaction, and we can erase the
+                // TRT entry
+                if (!r_xram_rsp_victim_dirty.read() and
+                        (r_xram_rsp_victim_coherent.read() or (r_xram_rsp_victim_count.read() == 0)))
+                {
+                    m_trt.erase(r_xram_rsp_trt_index.read());
+                }
+
+                // Next state
+                if (r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1)))  r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+                else if (r_xram_rsp_trt_buf.proc_read)    r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+                else if (r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
+                else                                      r_xram_rsp_fsm = XRAM_RSP_IDLE;
+                break;
+            }
+            ////////////////////////
+            case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (PUT to XRAM) if the victim is dirty or not coherent (RWT)
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)
+                {
+                    std::vector<data_t> data_vector;
+                    data_vector.clear();
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        data_vector.push_back(r_xram_rsp_victim_data[i].read());
+                    }
+                    m_trt.set(r_xram_rsp_trt_index.read(),
+                              false,                          // PUT
+                              r_xram_rsp_victim_nline.read(), // line index
+                              0,                              // unused
+                              0,                              // unused
+                              0,                              // unused
+                              false,                          // not proc_read
+                              0,                              // unused
+                              0,                              // unused
+                              std::vector<be_t>(m_words,0xF),
+                              data_vector);
+
+#if DEBUG_MEMC_XRAM_RSP
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>"
+                            << " Set TRT entry for the put transaction"
+                            << " / address = " << (r_xram_rsp_victim_nline.read() * m_words * 4) << std::endl;
+                    }
+#endif
+                    if (r_xram_rsp_trt_buf.proc_read)        r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+                    else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL;
+                    else                                     r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+                }
+                break;
+            }
+            //////////////////////
+            case XRAM_RSP_DIR_RSP:     // Request a response to TGT_RSP FSM
+            {
+                if (not r_xram_rsp_to_tgt_rsp_req.read())
+                {
+                    r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
+                    r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
+                    if (r_xram_rsp_coherent.read())
+                    {
+                        r_xram_rsp_to_tgt_rsp_pktid = 0x0 + r_xram_rsp_trt_buf.pktid; //RWT CC
                     }
                     else
                     {
-                        r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
-                    }
+                        r_xram_rsp_to_tgt_rsp_pktid = 0x8 + r_xram_rsp_trt_buf.pktid; //RWT NCC
+                    }
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+                    }
+                    r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
+                    r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+                    r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key;
+                    r_xram_rsp_to_tgt_rsp_rerror = false;
+                    r_xram_rsp_to_tgt_rsp_req    = true;
+
+                    if (r_xram_rsp_victim_inval.read())      r_xram_rsp_fsm = XRAM_RSP_INVAL;
+                    else if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+                    else                                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
-                            << " Select a victim slot: "
-                            << " way = " << std::dec << way
-                            << " / set = " << set
-                            << "/ count = " << victim.count
-                            << " / inval_required = " << inval << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////
-            case XRAM_RSP_IVT_LOCK:   // Keep DIR and TRT locks and take the IVT lock
-                // to check a possible pending inval
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
-                            "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation");
-
-                    assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
-                            "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation");
-
-                    if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP)
-                    {
-                        size_t index = 0;
-                        if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index))  // pending inval
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_RSP>"
+                            << " Request the TGT_RSP FSM to return data:"
+                            << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid
+                            << " / address = " << std::hex << r_xram_rsp_trt_buf.nline * m_words * 4
+                            << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ////////////////////
+            case XRAM_RSP_INVAL:  // send invalidate request to CC_SEND FSM
+            {
+                if (!r_xram_rsp_to_cc_send_multi_req.read() and
+                        !r_xram_rsp_to_cc_send_brdcast_req.read())
+                {
+                    bool multi_req = !r_xram_rsp_victim_is_cnt.read();
+                    bool last_multi_req  = multi_req and (r_xram_rsp_victim_count.read() == 1);
+                    bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
+
+                    r_xram_rsp_to_cc_send_multi_req   = last_multi_req;
+                    r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read();
+                    r_xram_rsp_to_cc_send_nline       = r_xram_rsp_victim_nline.read();
+                    r_xram_rsp_to_cc_send_trdid       = r_xram_rsp_ivt_index;
+                    xram_rsp_to_cc_send_fifo_srcid    = r_xram_rsp_victim_copy.read();
+                    xram_rsp_to_cc_send_fifo_inst     = r_xram_rsp_victim_copy_inst.read();
+                    xram_rsp_to_cc_send_fifo_put      = multi_req;
+                    r_xram_rsp_next_ptr               = r_xram_rsp_victim_ptr.read();
+
+                    if (r_xram_rsp_victim_dirty and r_xram_rsp_victim_coherent) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+                    else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
+                    else                         r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#if DEBUG_MEMC_XRAM_RSP
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL>"
+                            << " Send an inval request to CC_SEND FSM"
+                            << " / address = " << r_xram_rsp_victim_nline.read() * m_words * 4 << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            //////////////////////////
+            case XRAM_RSP_WRITE_DIRTY:  // send a write request to IXR_CMD FSM
+            {
+                if (not r_xram_rsp_to_ixr_cmd_req.read())
+                {
+                    r_xram_rsp_to_ixr_cmd_req = true;
+                    r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read();
+
+                    m_cpt_write_dirty++;
+
+                    bool multi_req = not r_xram_rsp_victim_is_cnt.read() and
+                        r_xram_rsp_victim_inval.read();
+                    bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
+
+                    if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
+                    else                    r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#if DEBUG_MEMC_XRAM_RSP
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY>"
+                            << " Send the put request to IXR_CMD FSM"
+                            << " / address = " << r_xram_rsp_victim_nline.read() * m_words * 4 << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////////
+            case XRAM_RSP_HEAP_REQ:    // Get the lock to the HEAP
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
+                {
+                    r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+                }
+
+#if DEBUG_MEMC_XRAM_RSP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_REQ>"
+                        << " Requesting HEAP lock" << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////////////
+            case XRAM_RSP_HEAP_ERASE: // erase the copies and send invalidations
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
+                {
+                    HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read());
+
+                    xram_rsp_to_cc_send_fifo_srcid = entry.owner.srcid;
+                    xram_rsp_to_cc_send_fifo_inst  = entry.owner.inst;
+                    xram_rsp_to_cc_send_fifo_put   = true;
+                    if (m_xram_rsp_to_cc_send_inst_fifo.wok())
+                    {
+                        r_xram_rsp_next_ptr = entry.next;
+                        if (entry.next == r_xram_rsp_next_ptr.read())   // last copy
                         {
-                            r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
-
-#if DEBUG_MEMC_XRAM_RSP
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
-                                    << " Get acces to IVT, but line invalidation registered"
-                                    << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
-                                    << " / index = " << std::dec << index << std::endl;
-#endif
-
-                        }
-                        else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full
-                        {
-                            r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
-
-#if DEBUG_MEMC_XRAM_RSP
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
-                                    << " Get acces to IVT, but inval required and IVT full" << std::endl;
-#endif
-                        }
-                        else
-                        {
-                            r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
-
-#if DEBUG_MEMC_XRAM_RSP
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
-                                    << " Get acces to IVT / no pending inval request" << std::endl;
-#endif
-                        }
-                    }
-                    break;
-                }
-                /////////////////////////
-            case XRAM_RSP_INVAL_WAIT: // release all locks and returns to DIR_LOCK to retry
-                {
-
-#if DEBUG_MEMC_XRAM_RSP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_WAIT>"
-                            << " Release all locks and retry" << std::endl;
-#endif
-                    r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
-                    break;
-                }
-                ///////////////////////
-            case XRAM_RSP_DIR_UPDT:   // updates the cache (both data & directory),
-                // erases the TRT entry if victim not dirty,
-                // and set inval request in IVT if required
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
-                            "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad DIR allocation");
-
-                    assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
-                            "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad TRT allocation");
-
-                    assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_XRAM_RSP) and
-                            "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad IVT allocation");
-
-                    // check if this is an instruction read, this means pktid is either
-                    // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
-                    // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-
-                    // check if this is a cached read, this means pktid is either
-                    // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
-                    // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-                    bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read;
-
-                    bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read;
-
-                    bool dirty = false;
-
-                    // update cache data
-                    size_t set   = r_xram_rsp_victim_set.read();
-                    size_t way   = r_xram_rsp_victim_way.read();
-                    for(size_t word=0; word<m_words ; word++)
-                    {
-                        m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
-                        dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0);
-
-                    }
-
-                    // update cache directory
-                    DirectoryEntry entry;
-                    entry.valid   = true;
-                    entry.cache_coherent = (inst_read or (not(cached_read))) and (r_xram_rsp_trt_buf.proc_read);
-                    entry.is_cnt  = false;
-                    entry.lock    = false;
-                    entry.dirty   = dirty;
-                    entry.tag     = r_xram_rsp_trt_buf.nline / m_sets;
-                    entry.ptr     = 0;
-                    if(cached_read)
-                    {
-                        entry.owner.srcid   = r_xram_rsp_trt_buf.srcid;
-                        entry.owner.inst    = inst_read;
-                        entry.count         = 1;
-                    }
-                    else
-                    {
-                        entry.owner.srcid    = 0;
-                        entry.owner.inst     = 0;
-                        entry.count          = 0;
-                    }
-                    m_cache_directory.write(set, way, entry);
-                    //RWT: keep the coherence information in order to send it to the read_rsp
-                    r_xram_rsp_coherent = inst_read or (not(cached_read));
-                    // request an invalidattion request in IVT for victim line
-                    if(r_xram_rsp_victim_inval.read())
-                    {
-                        bool   broadcast    = r_xram_rsp_victim_is_cnt.read();
-                        size_t index        = 0;
-                        size_t count_copies = r_xram_rsp_victim_count.read();
-
-                        bool   wok = m_ivt.set(false,      // it's an inval transaction
-                                broadcast,  // set broadcast bit
-                                false,      // no response required
-                                false,      // no acknowledge required
-                                0,          // srcid
-                                0,          // trdid
-                                0,          // pktid
-                                r_xram_rsp_victim_nline.read(),
-                                count_copies,
-                                index);
-
-                        r_xram_rsp_ivt_index = index;
-                        assert( wok and
-                                "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full");
-
-                    }
-                    if (!r_xram_rsp_victim_coherent.read())
-                    {
-                        addr_t min = r_xram_rsp_victim_nline.read()*m_words*4 ;
-                        addr_t max = r_xram_rsp_victim_nline.read()*m_words*4 + (m_words - 1)*4;
-                        m_llsc_table.sw(min, max);
-                    }
-#if DEBUG_MEMC_XRAM_RSP
-                    if(m_debug)
-                    {
-                        std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_UPDT>"
-                            << " Cache update: "
-                            << " way = " << std::dec << way
-                            << " / set = " << set
-                            << " / owner_id = " << std::hex << entry.owner.srcid
-                            << " / owner_ins = " << std::dec << entry.owner.inst
-                            << " / count = " << entry.count
-                            << " / nline = " << r_xram_rsp_trt_buf.nline
-                            << " / is_cnt = " << entry.is_cnt << std::endl;
-                        if(r_xram_rsp_victim_inval.read())
-                            std::cout << "                           Invalidation request for victim line "
-                                << std::hex << r_xram_rsp_victim_nline.read()
-                                << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl;
-                    }
-#endif
-
-                    // If the victim is not dirty (RWT: if it is not coherent,
-                    // we can not know wether it is dirty or not), we don't
-                    // need another XRAM  put transaction, and we can erase the
-                    // TRT entry
-                    if(!r_xram_rsp_victim_dirty.read() and (r_xram_rsp_victim_coherent.read() or (r_xram_rsp_victim_count.read() == 0)))  m_trt.erase(r_xram_rsp_trt_index.read());
-
-                    // Next state
-                    if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1)))  r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
-                    else if(r_xram_rsp_trt_buf.proc_read)    r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
-                    else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
-                    else                                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
-                    break;
-                }
-                ////////////////////////
-            case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (write to XRAM) if the victim is dirty or not coherent (RWT)
-                {
-                    if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)
-                    {
-                        std::vector<data_t> data_vector;
-                        data_vector.clear();
-                        for(size_t i=0; i<m_words; i++)
-                        {
-                            data_vector.push_back(r_xram_rsp_victim_data[i].read());
-                        }
-                        m_trt.set( r_xram_rsp_trt_index.read(),
-                                false,                             // PUT
-                                r_xram_rsp_victim_nline.read(),    // line index
-                                0,                                 // unused
-                                0,                                 // unused
-                                0,                                 // unused
-                                false,                             // not proc_read
-                                0,                                 // unused
-                                0,                                 // unused
-                                std::vector<be_t>(m_words,0xF),
-                                data_vector);
-#if DEBUG_MEMC_XRAM_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>"
-                                << " Set TRT entry for the put transaction"
-                                << " / dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-#endif
-
-                        if(r_xram_rsp_trt_buf.proc_read)         r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
-                        else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
-                        else                                     r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
-                    }
-                    break;
-                }
-                //////////////////////
-            case XRAM_RSP_DIR_RSP:     // Request a response to TGT_RSP FSM
-                {
-                    if( not r_xram_rsp_to_tgt_rsp_req.read())
-                    {
-                        r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
-                        r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
-                        if (r_xram_rsp_coherent.read())
-                        {
-                            r_xram_rsp_to_tgt_rsp_pktid = 0x0 + r_xram_rsp_trt_buf.pktid;//RWT CC
-                        }
-                        else
-                        {
-                            r_xram_rsp_to_tgt_rsp_pktid = 0x8 + r_xram_rsp_trt_buf.pktid;//RWT NCC
-                        }
-                        for(size_t i=0; i < m_words; i++)
-                        {
-                            r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
-                        }
-                        r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
-                        r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
-                        r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key;
-                        r_xram_rsp_to_tgt_rsp_rerror = false;
-                        r_xram_rsp_to_tgt_rsp_req    = true;
-
-
-                        if(r_xram_rsp_victim_inval)      r_xram_rsp_fsm = XRAM_RSP_INVAL;
-                        else if(r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
-                        else                             r_xram_rsp_fsm = XRAM_RSP_IDLE;
-
-#if DEBUG_MEMC_XRAM_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_RSP>"
-                                << " Request the TGT_RSP FSM to return data:"
-                                << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid
-                                << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
-                                << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl;
-#endif
-                    }
-                    break;
-                }
-                ////////////////////
-            case XRAM_RSP_INVAL:  // send invalidate request to CC_SEND FSM
-                {
-                    if(!r_xram_rsp_to_cc_send_multi_req.read() and
-                            !r_xram_rsp_to_cc_send_brdcast_req.read())
-                    {
-                        bool multi_req = !r_xram_rsp_victim_is_cnt.read();
-                        bool last_multi_req  = multi_req and (r_xram_rsp_victim_count.read() == 1);
-                        bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
-
-                        r_xram_rsp_to_cc_send_multi_req    = last_multi_req;
-                        r_xram_rsp_to_cc_send_brdcast_req  = r_xram_rsp_victim_is_cnt.read();
-                        r_xram_rsp_to_cc_send_nline        = r_xram_rsp_victim_nline.read();
-                        r_xram_rsp_to_cc_send_trdid        = r_xram_rsp_ivt_index;
-                        xram_rsp_to_cc_send_fifo_srcid     = r_xram_rsp_victim_copy.read();
-                        xram_rsp_to_cc_send_fifo_inst      = r_xram_rsp_victim_copy_inst.read();
-                        xram_rsp_to_cc_send_fifo_put       = multi_req;
-                        r_xram_rsp_next_ptr                = r_xram_rsp_victim_ptr.read();
-
-                        if(r_xram_rsp_victim_dirty and r_xram_rsp_victim_coherent)  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
-                        else if(not_last_multi_req)  r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
-                        else                         r_xram_rsp_fsm = XRAM_RSP_IDLE;
-
-#if DEBUG_MEMC_XRAM_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL>"
-                                << " Send an inval request to CC_SEND FSM"
-                                << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl;
-#endif
-                    }
-                    break;
-                }
-                //////////////////////////
-            case XRAM_RSP_WRITE_DIRTY:  // send a write request to IXR_CMD FSM
-                {
-                    if ( not r_xram_rsp_to_ixr_cmd_req.read() )
-                    {
-                        r_xram_rsp_to_ixr_cmd_req = true;
-                        r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read();
-
-                        m_cpt_write_dirty++;
-
-                        bool multi_req = not r_xram_rsp_victim_is_cnt.read() and
-                            r_xram_rsp_victim_inval.read();
-                        bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
-
-                        if(not_last_multi_req)   r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
-                        else                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
-
-#if DEBUG_MEMC_XRAM_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY>"
-                                << " Send the put request to IXR_CMD FSM"
-                                << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////////////////
-            case XRAM_RSP_HEAP_REQ:    // Get the lock to the HEAP
-                {
-                    if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
-                    {
-                        r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
-                    }
-
-#if DEBUG_MEMC_XRAM_RSP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_REQ>"
-                            << " Requesting HEAP lock" << std::endl;
-#endif
-                    break;
-                }
-                /////////////////////////
-            case XRAM_RSP_HEAP_ERASE: // erase the copies and send invalidations
-                {
-                    if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
-                    {
-                        HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read());
-
-                        xram_rsp_to_cc_send_fifo_srcid = entry.owner.srcid;
-                        xram_rsp_to_cc_send_fifo_inst  = entry.owner.inst;
-                        xram_rsp_to_cc_send_fifo_put   = true;
-                        if(m_xram_rsp_to_cc_send_inst_fifo.wok())
-                        {
-                            r_xram_rsp_next_ptr = entry.next;
-                            if(entry.next == r_xram_rsp_next_ptr.read())   // last copy
-                            {
-                                r_xram_rsp_to_cc_send_multi_req = true;
-                                r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST;
-                            }
-                            else
-                            {
-                                r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
-
-                            }
+                            r_xram_rsp_to_cc_send_multi_req = true;
+                            r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST;
                         }
                         else
@@ -5466 +5520 @@
                             r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
                         }
-
-#if DEBUG_MEMC_XRAM_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_ERASE>"
-                                << " Erase copy:"
-                                << " srcid = " << std::hex << entry.owner.srcid
-                                << " / inst = " << std::dec << entry.owner.inst << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////////////////
-            case XRAM_RSP_HEAP_LAST:  // last copy
-                {
-                    if(r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP)
-                    {
-                        std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST"
-                            << " bad HEAP allocation" << std::endl;
-                        exit(0);
-                    }
-                    size_t free_pointer = m_heap.next_free_ptr();
-
-                    HeapEntry last_entry;
-                    last_entry.owner.srcid    = 0;
-                    last_entry.owner.inst     = false;
-                    if(m_heap.is_full())
-                    {
-                        last_entry.next     = r_xram_rsp_next_ptr.read();
-                        m_heap.unset_full();
                     }
                     else
                     {
-                        last_entry.next     = free_pointer;
-                    }
-
-                    m_heap.write_free_ptr(r_xram_rsp_victim_ptr.read());
-                    m_heap.write(r_xram_rsp_next_ptr.read(),last_entry);
-
-                    // <Activity counters>
-                    m_cpt_heap_slot_available = m_cpt_heap_slot_available + (r_xram_rsp_victim_count.read() - 1);
-                    // </Activity counters>
-
-                    r_xram_rsp_fsm = XRAM_RSP_IDLE;
-
-#if DEBUG_MEMC_XRAM_RSP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_LAST>"
-                            << " Heap housekeeping" << std::endl;
-#endif
-                    break;
-                }
-                /////////////////////////
-            case XRAM_RSP_ERROR_ERASE:  // erase TRT entry in case of error
-                {
-                    m_trt.erase(r_xram_rsp_trt_index.read());
-
-                    // Next state
-                    if (r_xram_rsp_trt_buf.proc_read)
-                    {
-                        r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP;
-                    }
-                    else
-                    {
-                        // Trigger an interruption to signal a bus error from
-                        // the XRAM because a processor WRITE MISS (XRAM GET
-                        // transaction and not processor read).
-                        //
-                        // To avoid deadlocks we do not wait an error to be
-                        // acknowledged before signaling another one.
-                        // Therefore, when there is an active error, and other
-                        // errors arrive, these are not considered
-
-                        if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read()
-                                && r_xram_rsp_trt_buf.xram_read )
-                        {
-                            r_xram_rsp_rerror_irq     = true;
-                            r_xram_rsp_rerror_address = r_xram_rsp_trt_buf.nline * m_words * 4;
-                            r_xram_rsp_rerror_rsrcid  = r_xram_rsp_trt_buf.srcid;
-
-#if DEBUG_MEMC_XRAM_RSP
-                            if (m_debug)
-                                std::cout
-                                    << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>"
-                                    << " Triggering interrupt to signal WRITE MISS bus error"
-                                    << " / irq_enable = " << r_xram_rsp_rerror_irq_enable.read()
-                                    << " / nline = "      << r_xram_rsp_trt_buf.nline
-                                    << " / rsrcid = "     << r_xram_rsp_trt_buf.srcid
-                                    << std::endl;
-#endif
-                        }
-
-                        r_xram_rsp_fsm = XRAM_RSP_IDLE;
+                        r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
                     }
 
 #if DEBUG_MEMC_XRAM_RSP
                     if (m_debug)
-                        std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>"
-                            << " Error reported by XRAM / erase the TRT entry" << std::endl;
-#endif
-                    break;
-                }
-                ////////////////////////
+                    {
+                        std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_ERASE>"
+                            << " Erase copy:"
+                            << " srcid = " << std::hex << entry.owner.srcid
+                            << " / inst = " << std::dec << entry.owner.inst << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////////
+            case XRAM_RSP_HEAP_LAST:  // last copy
+            {
+                if (r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP)
+                {
+                    std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST"
+                        << " bad HEAP allocation" << std::endl;
+                    exit(0);
+                }
+                size_t free_pointer = m_heap.next_free_ptr();
+
+                HeapEntry last_entry;
+                last_entry.owner.srcid = 0;
+                last_entry.owner.inst  = false;
+                if (m_heap.is_full())
+                {
+                    last_entry.next = r_xram_rsp_next_ptr.read();
+                    m_heap.unset_full();
+                }
+                else
+                {
+                    last_entry.next = free_pointer;
+                }
+
+                m_heap.write_free_ptr(r_xram_rsp_victim_ptr.read());
+                m_heap.write(r_xram_rsp_next_ptr.read(),last_entry);
+
+                // <Activity counters>
+                m_cpt_heap_slot_available = m_cpt_heap_slot_available + (r_xram_rsp_victim_count.read() - 1);
+                // </Activity counters>
+
+                r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#if DEBUG_MEMC_XRAM_RSP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_LAST>"
+                        << " Heap housekeeping" << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////////
+            case XRAM_RSP_ERROR_ERASE:  // erase TRT entry in case of error
+            {
+                m_trt.erase(r_xram_rsp_trt_index.read());
+
+                // Next state
+                if (r_xram_rsp_trt_buf.proc_read)
+                {
+                    r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP;
+                }
+                else
+                {
+                    // Trigger an interruption to signal a bus error from
+                    // the XRAM because a processor WRITE MISS (XRAM GET
+                    // transaction and not processor read).
+                    //
+                    // To avoid deadlocks we do not wait an error to be
+                    // acknowledged before signaling another one.
+                    // Therefore, when there is an active error, and other
+                    // errors arrive, these are not considered
+
+                    if (!r_xram_rsp_rerror_irq.read() and r_xram_rsp_rerror_irq_enable.read()
+                            and r_xram_rsp_trt_buf.xram_read)
+                    {
+                        r_xram_rsp_rerror_irq     = true;
+                        r_xram_rsp_rerror_address = r_xram_rsp_trt_buf.nline * m_words * 4;
+                        r_xram_rsp_rerror_rsrcid  = r_xram_rsp_trt_buf.srcid;
+
+#if DEBUG_MEMC_XRAM_RSP
+                        if (m_debug)
+                        {
+                            std::cout
+                                << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>"
+                                << " Triggering interrupt to signal WRITE MISS bus error"
+                                << " / irq_enable = " << r_xram_rsp_rerror_irq_enable.read()
+                                << " / nline = "      << r_xram_rsp_trt_buf.nline
+                                << " / rsrcid = "     << r_xram_rsp_trt_buf.srcid
+                                << std::endl;
+                        }
+#endif
+                    }
+
+                    r_xram_rsp_fsm = XRAM_RSP_IDLE;
+                }
+
+#if DEBUG_MEMC_XRAM_RSP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>"
+                        << " Error reported by XRAM / erase the TRT entry" << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////////////
             case XRAM_RSP_ERROR_RSP:     // Request an error response to TGT_RSP FSM
-                {
-                    if(!r_xram_rsp_to_tgt_rsp_req.read())
-                    {
-                        r_xram_rsp_to_tgt_rsp_srcid  = r_xram_rsp_trt_buf.srcid;
-                        r_xram_rsp_to_tgt_rsp_trdid  = r_xram_rsp_trt_buf.trdid;
-                        r_xram_rsp_to_tgt_rsp_pktid  = r_xram_rsp_trt_buf.pktid;
-                        for(size_t i=0; i < m_words; i++)
-                        {
-                            r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
-                        }
-                        r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
-                        r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
-                        r_xram_rsp_to_tgt_rsp_rerror = true;
-                        r_xram_rsp_to_tgt_rsp_req    = true;
-
-                        r_xram_rsp_fsm = XRAM_RSP_IDLE;
+            {
+                if (!r_xram_rsp_to_tgt_rsp_req.read())
+                {
+                    r_xram_rsp_to_tgt_rsp_srcid  = r_xram_rsp_trt_buf.srcid;
+                    r_xram_rsp_to_tgt_rsp_trdid  = r_xram_rsp_trt_buf.trdid;
+                    r_xram_rsp_to_tgt_rsp_pktid  = r_xram_rsp_trt_buf.pktid;
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+                    }
+                    r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
+                    r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+                    r_xram_rsp_to_tgt_rsp_rerror = true;
+                    r_xram_rsp_to_tgt_rsp_req    = true;
+
+                    r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
-                                << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
-#endif
-                    }
-                    break;
-                }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
+                            << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
         } // end swich r_xram_rsp_fsm
 
@@ -5607 +5676 @@
         {
             //////////////////
-            case CLEANUP_IDLE:     // Get first DSPIN flit of the CLEANUP command
-                {
-                    if(not m_cc_receive_to_cleanup_fifo.rok()) break;
-
+            case CLEANUP_IDLE: // Get first DSPIN flit of the CLEANUP command
+            {
+                if (not m_cc_receive_to_cleanup_fifo.rok()) break;
+
+                uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
+
+                uint32_t srcid =
+                    DspinRwtParam::dspin_get(
+                            flit,
+                            DspinRwtParam::CLEANUP_SRCID);
+
+                uint8_t type =
+                    DspinRwtParam::dspin_get(
+                            flit,
+                            DspinRwtParam::P2M_TYPE);
+
+                r_cleanup_way_index =
+                    DspinRwtParam::dspin_get(
+                            flit,
+                            DspinRwtParam::CLEANUP_WAY_INDEX);
+
+                r_cleanup_nline =
+                    DspinRwtParam::dspin_get(
+                            flit,
+                            DspinRwtParam::CLEANUP_NLINE_MSB) << 32;
+
+                r_cleanup_inst = (type == DspinRwtParam::TYPE_CLEANUP_INST);
+                r_cleanup_srcid = srcid;
+                r_cleanup_ncc =
+                    DspinRwtParam::dspin_get(
+                            flit,
+                            DspinRwtParam::CLEANUP_NCC);
+                r_cleanup_contains_data = false;
+
+                assert((srcid < m_initiators) and
+                        "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value");
+
+                cc_receive_to_cleanup_fifo_get = true;
+                r_cleanup_fsm                  = CLEANUP_GET_NLINE;
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CLEANUP_IDLE> Cleanup request:" << std::hex
+                        << " owner_id = "   << srcid
+                        << " / owner_ins = "  << (type == DspinRwtParam::TYPE_CLEANUP_INST)
+                        << " / ncc = " << DspinRwtParam::dspin_get(
+                                flit,
+                                DspinRwtParam::CLEANUP_NCC)
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////
+            case CLEANUP_GET_NLINE:  // GET second DSPIN flit of the cleanup command
+            {
+                if (not m_cc_receive_to_cleanup_fifo.rok()) break;
+
+                uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
+                uint32_t srcid = r_cleanup_srcid.read();
+
+                addr_t nline = r_cleanup_nline.read() |
+                    DspinRwtParam::dspin_get(flit, DspinRwtParam::CLEANUP_NLINE_LSB);
+
+                bool eop = DspinRwtParam::dspin_get(flit, DspinRwtParam::P2M_EOP) == 0x1;
+
+                if (!eop)
+                {
+                    r_cleanup_fsm = CLEANUP_GET_DATA;
+                    r_cleanup_data_index = 0;
+                    r_cleanup_contains_data = true;
+                    // <Activity Counters>
+                    if (is_local_req(srcid)) {
+                        m_cpt_cleanup_local++;
+                        m_cpt_cleanup_data_local++;
+                    }
+                    else {
+                        m_cpt_cleanup_remote++;
+                        m_cpt_cleanup_data_remote++;
+                    }
+                    // 2 + m_words flits for cleanup with data
+                    m_cpt_cleanup_cost += (m_words + 2) * req_distance(srcid);
+                    m_cpt_cleanup_data_cost += (m_words + 2) * req_distance(srcid);
+                    // </Activity Counters>
+                }
+                else
+                {
+                    r_cleanup_fsm = CLEANUP_DIR_REQ;
+                    // <Activity Counters>
+                    if (is_local_req(srcid)) {
+                        m_cpt_cleanup_local++;
+                    }
+                    else {
+                        m_cpt_cleanup_remote++;
+                    }
+                    // 2 flits for cleanup without data
+                    m_cpt_cleanup_cost += 2 * req_distance(srcid);
+                    // </Activity Counters>
+                }
+                cc_receive_to_cleanup_fifo_get = true;
+                r_cleanup_nline = nline;
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC "         << name()
+                        << " CLEANUP_GET_NLINE> Cleanup request:"
+                        << "  address = " << std::hex << nline * m_words * 4
+                        << " / contains data = " << (!eop)
+                        << std::dec << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////////
+            case CLEANUP_GET_DATA:
+            {
+                if (m_cc_receive_to_cleanup_fifo.rok())
+                {
                     uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
 
-                    uint32_t srcid =
-                        DspinRwtParam::dspin_get(
-                                flit,
-                                DspinRwtParam::CLEANUP_SRCID);
-
-                    uint8_t type =
-                        DspinRwtParam::dspin_get(
-                                flit,
-                                DspinRwtParam::P2M_TYPE);
-
-                    r_cleanup_way_index =
-                        DspinRwtParam::dspin_get(
-                                flit,
-                                DspinRwtParam::CLEANUP_WAY_INDEX);
-
-                    r_cleanup_nline =
-                        DspinRwtParam::dspin_get(
-                                flit,
-                                DspinRwtParam::CLEANUP_NLINE_MSB) << 32;
-
-                    r_cleanup_inst  = (type == DspinRwtParam::TYPE_CLEANUP_INST);
-                    r_cleanup_srcid = srcid;
-                    r_cleanup_ncc =
-                        DspinRwtParam::dspin_get(
-                                flit,
-                                DspinRwtParam::CLEANUP_NCC);
-                    r_cleanup_contains_data = false;
-
-                    assert( (srcid < m_initiators) and
-                            "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value");
-
+                    uint32_t data =
+                        DspinRwtParam::dspin_get(flit, DspinRwtParam::CLEANUP_DATA_UPDT);
+
+                    r_cleanup_data[r_cleanup_data_index] = data;
+                    r_cleanup_data_index = r_cleanup_data_index.read() + 1;
+                    assert(r_cleanup_data_index.read() < m_words and "MEM_CACHE in CLEANUP_GET_DATA : too much flits in cleanup data updt");
                     cc_receive_to_cleanup_fifo_get = true;
-                    r_cleanup_fsm                  = CLEANUP_GET_NLINE;
-
+                    if (r_cleanup_data_index.read() == (m_words - 1))
+                    {
+                        r_cleanup_contains_data = true;
+                        r_cleanup_fsm = CLEANUP_DIR_REQ;
+                    }
 #if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " CLEANUP_GET_DATA> "
+                            << " / word = " << std::dec << r_cleanup_data_index.read()
+                            << " / data = " << std::hex << data
+                            << std::dec << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////
+            case CLEANUP_DIR_REQ:   // Get the lock to the directory
+            {
+                if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break;
+
+                r_cleanup_fsm = CLEANUP_DIR_LOCK;
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////
+            case CLEANUP_DIR_LOCK:    // test directory status
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and
+                        "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation");
+
+                // Read the directory
+                size_t way = 0;
+                addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4;
+
+                DirectoryEntry entry   = m_cache_directory.read(cleanup_address, way);
+                r_cleanup_is_cnt       = entry.is_cnt;
+                r_cleanup_dirty        = entry.dirty;
+                r_cleanup_tag          = entry.tag;
+                r_cleanup_lock         = entry.lock;
+                r_cleanup_way          = way;
+                r_cleanup_count        = entry.count;
+                r_cleanup_ptr          = entry.ptr;
+                r_cleanup_copy         = entry.owner.srcid;
+                r_cleanup_copy_inst    = entry.owner.inst;
+
+                //RWT
+                size_t set = m_y[(addr_t) (cleanup_address)];
+                m_cache_data.read_line(way, set, r_cleanup_old_data);
+                r_cleanup_coherent = entry.cache_coherent;
+
+                if (entry.valid) // hit : the copy must be cleared
+                {
+                    assert((entry.count > 0) and
+                            "MEMC ERROR in CLEANUP_DIR_LOCK state, CLEANUP on valid entry with no copies");
+
+                    if ((entry.count == 1) or (entry.is_cnt)) // no access to the heap
+                    {
+                        r_cleanup_fsm = CLEANUP_DIR_WRITE;
+                    }
+                    else // access to the heap
+                    {
+                        r_cleanup_fsm = CLEANUP_HEAP_REQ;
+                    }
+                }
+                else // miss : check IVT for a pending inval
+                {
+                    r_cleanup_fsm = CLEANUP_IVT_LOCK;
+                }
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CLEANUP_DIR_LOCK> Test directory status: "
+                        << std::hex
+                        << " address = "      << cleanup_address
+                        << " / hit = "        << entry.valid
+                        << " / dir_id = "     << entry.owner.srcid
+                        << " / dir_ins = "    << entry.owner.inst
+                        << " / search_id = "  << r_cleanup_srcid.read()
+                        << " / search_ins = " << r_cleanup_inst.read()
+                        << " / count = "      << entry.count
+                        << " / is_cnt = "     << entry.is_cnt
+                        << std::dec << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////
+            case CLEANUP_DIR_WRITE:      // Update the directory entry without heap access
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and
+                        "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation");
+
+                size_t way       = r_cleanup_way.read();
+                size_t set       = m_y[(addr_t) (r_cleanup_nline.read() * m_words * 4)];
+                bool match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read());
+                bool match_inst  = (r_cleanup_copy_inst.read() == r_cleanup_inst.read());
+                bool match       = match_srcid and match_inst;
+
+                assert((r_cleanup_is_cnt.read() or match) and
+                        "MEMC ERROR in CLEANUP_DIR_LOCK: illegal CLEANUP on valid entry");
+
+                /*RWT*/
+                // NCC to CC initiated by a read transaction
+                bool inval_by_read = r_read_to_cleanup_req.read() and
+                    (r_cleanup_nline.read() == r_read_to_cleanup_nline.read());
+
+                // NCC to CC initiated by a write transaction
+                bool inval_by_write = r_write_to_cleanup_req.read() and
+                    (r_cleanup_nline.read() == r_write_to_cleanup_nline.read());
+
+                bool inval_request = inval_by_read or inval_by_write;
+
+                if (inval_by_write)
+                {
+                    r_write_to_cleanup_req = false;
+                    m_cpt_ncc_to_cc_write ++;
+                }
+
+                // update the cache directory (for the copies)
+                DirectoryEntry entry;
+                entry.valid          = true;
+                entry.cache_coherent = inval_request or r_cleanup_coherent.read();
+                entry.is_cnt         = r_cleanup_is_cnt.read();
+                entry.dirty          = r_cleanup_dirty.read() or r_cleanup_contains_data.read();
+                entry.tag            = r_cleanup_tag.read();
+                entry.lock           = r_cleanup_lock.read();
+                entry.ptr            = r_cleanup_ptr.read();
+
+                if (inval_by_read) // pending READ
+                {
+                    if (r_read_to_cleanup_cached_read.read())
+                    {
+                        entry.count       = r_cleanup_count.read();
+                        entry.owner.srcid = r_read_to_cleanup_srcid.read();
+                        entry.owner.inst  = r_read_to_cleanup_inst.read();
+                    }
+                    else
+                    {
+                        entry.count       = r_cleanup_count.read() - 1;
+                        entry.owner.srcid = r_cleanup_copy.read();
+                        entry.owner.inst  = r_cleanup_copy_inst.read();
+                    }
+                    if (r_read_to_cleanup_is_ll.read())
+                    {
+                        r_cleanup_to_tgt_rsp_ll_key = r_read_to_cleanup_ll_key.read();
+                    }
+                }
+                else
+                {
+                    entry.count       = r_cleanup_count.read() - 1;
+                    entry.owner.srcid = 0;
+                    entry.owner.inst  = 0;
+
+#if REVERT_CC_MECANISM
+                    // Revert CC to NCC if :
+                    //  - no more copy in L1 caches
+                    //  - this line is not in counter mode (broadcast)
+                    //  - this line is not in NCC to CC mecanism
+                    if (((r_cleanup_count.read() - 1) == 0) and (r_cleanup_is_cnt == false) and (inval_request == false))
+                    {
+                        entry.cache_coherent = false;
+                    }
+#endif
+
+#if REVERT_BC_MECANISM
+                    if ((r_cleanup_count.read() - 1) == 0)
+                    {
+                        entry.is_cnt = false;
+                    }
+#endif
+
+                }
+
+                if (r_cleanup_contains_data.read())
+                {
+                    for (size_t word = 0; word < m_words; word++)
+                    {
+                        m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF);
+                    }
+                    addr_t min = r_cleanup_nline.read() * m_words * 4;
+                    addr_t max = r_cleanup_nline.read() * m_words * 4 + (m_words - 1) * 4;
+                    m_llsc_table.sw(min, max);
+                }
+
+                m_cache_directory.write(set, way, entry);
+
+                /*RWT*/
+                if (inval_request)
+                {
+                    r_cleanup_fsm = CLEANUP_IVT_LOCK_DATA;
+                }
+                else
+                {
+                    r_cleanup_fsm = CLEANUP_SEND_CLACK;
+                }
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CLEANUP_DIR_WRITE> Update directory:"
+                        << std::hex
+                        << " address = "   << r_cleanup_nline.read() * m_words * 4
+                        << " / dir_id = "  << entry.owner.srcid
+                        << " / dir_ins = " << entry.owner.inst
+                        << " / count = "   << entry.count
+                        << " / is_cnt = "  << entry.is_cnt
+                        << " / match_inval = " << inval_request
+                        << " / is_coherent = " << entry.cache_coherent
+                        << std::dec << std::endl;
+                }
+#endif
+
+                break;
+            }
+            /////////////////////
+            case CLEANUP_IVT_LOCK_DATA: //RWT
+            {
+                // Search for a matching inval in the IVT (there must be one)
+                // and check if there is a pending read.
+                if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP)
+                {
+                    size_t index = 0;
+                    bool match_inval;
+
+                    match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index);
+                    assert(match_inval and
+                    "VCI MEM CACHE ERROR: In CLEANUP_IVT_LOCK_DATA, NO CORRESPONDING INVAL");
+
+                    r_cleanup_read_srcid    = m_ivt.srcid(index);
+                    r_cleanup_read_trdid    = m_ivt.trdid(index);
+                    r_cleanup_read_pktid    = 0x0 + m_ivt.pktid(index);
+                    r_cleanup_read_need_rsp = !m_ivt.need_rsp(index);
+                    r_cleanup_index         = index;
+
+                    r_cleanup_fsm = CLEANUP_IVT_CLEAR_DATA;
+                }
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << " <MEMC " << name()
+                        << " CLEANUP_IVT_LOCK_DATA> fetch pending inval"
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+
+            //////////////////////////
+            case CLEANUP_IVT_CLEAR_DATA: //RWT
+            {
+                m_ivt.clear(r_cleanup_index.read());
+                assert((r_cleanup_read_need_rsp.read() == (r_read_to_cleanup_req.read() && (r_cleanup_nline.read() == r_read_to_cleanup_nline.read()))) && "condition pending read");
+
+                if (r_cleanup_read_need_rsp.read())
+                {
+                    r_cleanup_fsm = CLEANUP_READ_RSP;
+                }
+                else
+                {
+                    r_cleanup_fsm = CLEANUP_SEND_CLACK;
+                }
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << " <MEMC " << name()
+                        << " CLEANUP_IVT_CLEAR_DATA> clear IVT entry"
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+
+            ////////////////////////
+            case CLEANUP_READ_RSP: //RWT
+            {
+                if (r_cleanup_to_tgt_rsp_req.read()) break;
+
+                r_cleanup_to_tgt_rsp_req     = true;
+                r_cleanup_to_tgt_rsp_srcid   = r_cleanup_read_srcid.read();
+                r_cleanup_to_tgt_rsp_trdid   = r_cleanup_read_trdid.read();
+                r_cleanup_to_tgt_rsp_pktid   = 0x0 + r_cleanup_read_pktid.read();
+                r_cleanup_to_tgt_rsp_type    = 0; // Read instruction
+                r_cleanup_to_tgt_rsp_length  = r_read_to_cleanup_length.read();
+                r_cleanup_to_tgt_rsp_first_word = r_read_to_cleanup_first_word.read();
+                r_read_to_cleanup_req        = false;
+                m_cpt_ncc_to_cc_read++;
+                if (r_cleanup_contains_data.read()) // L1 was dirty
+                {
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        r_cleanup_to_tgt_rsp_data[i] = r_cleanup_data[i].read();
+                    }
+                }
+                else // L2 data are up to date
+                {
+                    for (size_t i = 0; i < m_words; i++)
+                    {
+                        r_cleanup_to_tgt_rsp_data[i] = r_cleanup_old_data[i].read();
+                    }
+                }
+
+                r_cleanup_fsm = CLEANUP_SEND_CLACK;
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << " <MEMC " << name()
+                        << " CLEANUP_READ_RSP> answer READ"
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////
+            case CLEANUP_HEAP_REQ:    // get the lock to the HEAP directory
+            {
+                if (r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break;
+
+                r_cleanup_fsm = CLEANUP_HEAP_LOCK;
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CLEANUP_HEAP_REQ> HEAP lock acquired " << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////
+            case CLEANUP_HEAP_LOCK:   // two cases are handled in this state :
+                                      // 1. the matching copy is directly in the directory
+                                      // 2. the matching copy is the first copy in the heap
+            {
+                assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
+                        "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
+
+                size_t way = r_cleanup_way.read();
+                size_t set = m_y[(addr_t) (r_cleanup_nline.read() * m_words * 4)];
+
+                HeapEntry heap_entry = m_heap.read(r_cleanup_ptr.read());
+                bool last            = (heap_entry.next == r_cleanup_ptr.read());
+
+                // match_dir computation
+                bool match_dir_srcid = (r_cleanup_copy.read()      == r_cleanup_srcid.read());
+                bool match_dir_inst  = (r_cleanup_copy_inst.read() == r_cleanup_inst.read());
+                bool match_dir       = match_dir_srcid  and match_dir_inst;
+
+                // match_heap computation
+                bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read());
+                bool match_heap_inst  = (heap_entry.owner.inst  == r_cleanup_inst.read());
+                bool match_heap       = match_heap_srcid and match_heap_inst;
+
+                r_cleanup_prev_ptr   = r_cleanup_ptr.read();
+                r_cleanup_prev_srcid = heap_entry.owner.srcid;
+                r_cleanup_prev_inst  = heap_entry.owner.inst;
+
+                assert((not last or match_dir or match_heap) and
+                        "MEMC ERROR in CLEANUP_HEAP_LOCK state: hit but no copy found");
+
+                assert((not match_dir or not match_heap) and
+                        "MEMC ERROR in CLEANUP_HEAP_LOCK state: two matching copies found");
+
+                DirectoryEntry dir_entry;
+                dir_entry.valid          = true;
+                dir_entry.is_cnt         = r_cleanup_is_cnt.read();
+                dir_entry.dirty          = r_cleanup_dirty.read();
+                dir_entry.tag            = r_cleanup_tag.read();
+                dir_entry.lock           = r_cleanup_lock.read();
+                dir_entry.count          = r_cleanup_count.read() - 1;
+                dir_entry.cache_coherent = true;
+
+                // the matching copy is registered in the directory and
+                // it must be replaced by the first copy registered in
+                // the heap. The corresponding entry must be freed
+                if (match_dir)
+                {
+                    dir_entry.ptr         = heap_entry.next;
+                    dir_entry.owner.srcid = heap_entry.owner.srcid;
+                    dir_entry.owner.inst  = heap_entry.owner.inst;
+                    r_cleanup_next_ptr    = r_cleanup_ptr.read();
+                    r_cleanup_fsm         = CLEANUP_HEAP_FREE;
+                }
+
+                // the matching copy is the first copy in the heap
+                // It must be freed and the copy registered in directory
+                // must point to the next copy in heap
+                else if (match_heap)
+                {
+                    dir_entry.ptr         = heap_entry.next;
+                    dir_entry.owner.srcid = r_cleanup_copy.read();
+                    dir_entry.owner.inst  = r_cleanup_copy_inst.read();
+                    r_cleanup_next_ptr    = r_cleanup_ptr.read();
+                    r_cleanup_fsm         = CLEANUP_HEAP_FREE;
+                }
+
+                // The matching copy is in the heap, but is not the first copy
+                // The directory entry must be modified to decrement count
+                else
+                {
+                    dir_entry.ptr         = r_cleanup_ptr.read();
+                    dir_entry.owner.srcid = r_cleanup_copy.read();
+                    dir_entry.owner.inst  = r_cleanup_copy_inst.read();
+                    r_cleanup_next_ptr    = heap_entry.next;
+                    r_cleanup_fsm         = CLEANUP_HEAP_SEARCH;
+                }
+
+                m_cache_directory.write(set, way, dir_entry);
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CLEANUP_HEAP_LOCK> Checks matching:"
+                        << " address = "      << r_cleanup_nline.read() * m_words * 4
+                        << " / dir_id = "     << r_cleanup_copy.read()
+                        << " / dir_ins = "    << r_cleanup_copy_inst.read()
+                        << " / heap_id = "    << heap_entry.owner.srcid
+                        << " / heap_ins = "   << heap_entry.owner.inst
+                        << " / search_id = "  << r_cleanup_srcid.read()
+                        << " / search_ins = " << r_cleanup_inst.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////////////
+            case CLEANUP_HEAP_SEARCH:   // This state is handling the case where the copy
+                                        // is in the heap, but is not the first in the linked list
+            {
+                assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
+                        "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
+
+                HeapEntry heap_entry  = m_heap.read(r_cleanup_next_ptr.read());
+
+                bool last             = (heap_entry.next        == r_cleanup_next_ptr.read());
+                bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read());
+                bool match_heap_inst  = (heap_entry.owner.inst  == r_cleanup_inst.read());
+                bool match_heap       = match_heap_srcid and match_heap_inst;
+
+                assert((not last or match_heap) and
+                        "MEMC ERROR in CLEANUP_HEAP_SEARCH state: no copy found");
+
+                // the matching copy must be removed
+                if (match_heap)
+                {
+                    // re-use ressources
+                    r_cleanup_ptr = heap_entry.next;
+                    r_cleanup_fsm = CLEANUP_HEAP_CLEAN;
+                }
+                // test the next in the linked list
+                else
+                {
+                    r_cleanup_prev_ptr   = r_cleanup_next_ptr.read();
+                    r_cleanup_prev_srcid = heap_entry.owner.srcid;
+                    r_cleanup_prev_inst  = heap_entry.owner.inst;
+                    r_cleanup_next_ptr   = heap_entry.next;
+                    r_cleanup_fsm        = CLEANUP_HEAP_SEARCH;
+                }
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    if (not match_heap)
                     {
                         std::cout
-                            << "  <MEMC "         << name()
-                            << " CLEANUP_IDLE> Cleanup request:" << std::hex
-                            << " / owner_id = "   << srcid
-                            << " / owner_ins = "  << (type == DspinRwtParam::TYPE_CLEANUP_INST)
-                            << " / ncc = " << DspinRwtParam::dspin_get(
-                                    flit,
-                                    DspinRwtParam::CLEANUP_NCC)
+                            << "  <MEMC " << name()
+                            << " CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
                             << std::endl;
                     }
-#endif
-                    break;
-                }
-
-                ///////////////////////
-            case CLEANUP_GET_NLINE:  // GET second DSPIN flit of the cleanup command
-                {
-                    if (not m_cc_receive_to_cleanup_fifo.rok()) break;
-
-                    uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
-                    uint32_t srcid = r_cleanup_srcid.read();
-
-                    addr_t nline = r_cleanup_nline.read() |
-                        DspinRwtParam::dspin_get(flit, DspinRwtParam::CLEANUP_NLINE_LSB);
-
-                    bool eop = DspinRwtParam::dspin_get(flit, DspinRwtParam::P2M_EOP) == 0x1;
-
-                    if (! eop)
-                    {
-                        r_cleanup_fsm = CLEANUP_GET_DATA;
-                        r_cleanup_data_index = 0;
-                        r_cleanup_contains_data = true;
-                        // <Activity Counters>
-                        if (is_local_req(srcid)) {
-                            m_cpt_cleanup_local++;
-                            m_cpt_cleanup_data_local++;
+                    else
+                    {
+                        std::cout
+                            << "  <MEMC " << name()
+                            << " CLEANUP_HEAP_SEARCH> Matching copy found:"
+                            << std::endl;
+                    }
+                    std::cout
+                        << " address = "      << r_cleanup_nline.read() * m_words * 4
+                        << " / heap_id = "    << heap_entry.owner.srcid
+                        << " / heap_ins = "   << heap_entry.owner.inst
+                        << " / search_id = "  << r_cleanup_srcid.read()
+                        << " / search_ins = " << r_cleanup_inst.read()
+                        << " / last = "       << last
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////////////
+            case CLEANUP_HEAP_CLEAN:    // remove a copy in the linked list
+            {
+                assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
+                        "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
+
+                HeapEntry heap_entry;
+                heap_entry.owner.srcid = r_cleanup_prev_srcid.read();
+                heap_entry.owner.inst  = r_cleanup_prev_inst.read();
+                bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read());
+
+                if (last)     // this is the last entry of the list of copies
+                {
+                    heap_entry.next = r_cleanup_prev_ptr.read();
+                }
+                else          // this is not the last entry
+                {
+                    heap_entry.next = r_cleanup_ptr.read();
+                }
+
+                m_heap.write(r_cleanup_prev_ptr.read(), heap_entry);
+
+                r_cleanup_fsm = CLEANUP_HEAP_FREE;
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CLEANUP_HEAP_SEARCH>"
+                        << " Remove the copy in the linked list" << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////
+            case CLEANUP_HEAP_FREE:   // The heap entry pointed by r_cleanup_next_ptr is freed
+            // and becomes the head of the list of free entries
+            {
+                assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
+                        "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
+
+                HeapEntry heap_entry;
+                heap_entry.owner.srcid = 0;
+                heap_entry.owner.inst  = false;
+
+                if (m_heap.is_full())
+                {
+                    heap_entry.next = r_cleanup_next_ptr.read();
+                }
+                else
+                {
+                    heap_entry.next = m_heap.next_free_ptr();
+                }
+
+                m_heap.write(r_cleanup_next_ptr.read(), heap_entry);
+                m_heap.write_free_ptr(r_cleanup_next_ptr.read());
+                m_heap.unset_full();
+
+                // <Activity counters>
+                m_cpt_heap_slot_available++;
+                // </Activity counters>
+
+                r_cleanup_fsm = CLEANUP_SEND_CLACK;
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CLEANUP_HEAP_FREE>"
+                        << " Update the list of free entries" << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////
+            case CLEANUP_IVT_LOCK:   // get the lock protecting the IVT to search a pending
+            // invalidate transaction matching the cleanup
+            {
+                if (r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break;
+
+                size_t index = 0;
+                bool match_inval;
+
+                match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index);
+
+                if (not match_inval) // no pending inval in IVT
+                {
+                    r_cleanup_fsm = CLEANUP_SEND_CLACK;
+
+#if DEBUG_MEMC_CLEANUP
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " CLEANUP_IVT_LOCK> Unexpected cleanup"
+                            << " with no corresponding IVT entry:"
+                            << " address = " << std::hex
+                            << (r_cleanup_nline.read() * 4 * m_words)
+                            << std::dec << std::endl;
+                    }
+#endif
+                }
+                else // pending inval in IVT
+                {
+                    r_cleanup_write_srcid = m_ivt.srcid(index);
+                    r_cleanup_write_trdid = m_ivt.trdid(index);
+                    r_cleanup_write_pktid = m_ivt.pktid(index);
+                    r_cleanup_need_rsp    = m_ivt.need_rsp(index);
+                    r_cleanup_need_ack    = m_ivt.need_ack(index);
+                    r_cleanup_index       = index;
+                    r_cleanup_fsm         = CLEANUP_IVT_DECREMENT;
+
+#if DEBUG_MEMC_CLEANUP
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " CLEANUP_IVT_LOCK> Cleanup matching pending"
+                            << " invalidate transaction on IVT:"
+                            << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4
+                            << " / ivt_entry = " << index << std::dec << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ///////////////////////////
+            case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry
+                                        // and test if last
+            {
+                assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and
+                        "MEMC ERROR in CLEANUP_IVT_DECREMENT state: Bad IVT allocation");
+
+                size_t count = 0;
+                m_ivt.decrement(r_cleanup_index.read(), count);
+
+                if (count == 0) // multi inval transaction completed
+                {
+                    r_cleanup_fsm = CLEANUP_IVT_CLEAR;
+                }
+                else            // multi inval transaction not completed
+                {
+                    if (r_cleanup_ncc.read()) // need to put data to the XRAM
+                    {
+                        r_cleanup_fsm = CLEANUP_IXR_REQ;
+                    }
+                    else
+                    {
+                        r_cleanup_fsm = CLEANUP_SEND_CLACK;
+                    }
+                }
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CLEANUP_IVT_DECREMENT>"
+                        << " Decrement response counter in IVT:"
+                        << " IVT_index = " << r_cleanup_index.read()
+                        << " / rsp_count = " << count << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////
+            case CLEANUP_IVT_CLEAR:  // Clear IVT entry
+                                     // Acknowledge CONFIG FSM if required
+            {
+                assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and
+                        "MEMC ERROR in CLEANUP_IVT_CLEAR state : bad IVT allocation");
+
+                m_ivt.clear(r_cleanup_index.read());
+
+                if (r_cleanup_need_ack.read())
+                {
+                    assert((r_config_rsp_lines.read() > 0) and
+                            "MEMC ERROR in CLEANUP_IVT_CLEAR state");
+
+                    config_rsp_lines_cleanup_decr = true;
+                }
+
+                if (r_cleanup_need_rsp.read()) r_cleanup_fsm = CLEANUP_WRITE_RSP;
+                else if (r_cleanup_ncc.read()) r_cleanup_fsm = CLEANUP_IXR_REQ;
+                else                           r_cleanup_fsm = CLEANUP_SEND_CLACK;
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CLEANUP_IVT_CLEAR> Clear entry in IVT:"
+                        << " IVT_index = " << r_cleanup_index.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////
+            case CLEANUP_WRITE_RSP:  // response to a previous write on the direct network
+                                     // wait if pending request to the TGT_RSP FSM
+            {
+                if (r_cleanup_to_tgt_rsp_req.read()) break;
+
+                assert((r_cleanup_ncc.read() == false) and
+                       "CLEANUP_WRITE_RSP : Cleanup on NCC line invalid in "
+                       "MEM_CACHE with write_rsp needed. STRANGE BEHAVIOUR");
+
+                // no pending request
+                r_cleanup_to_tgt_rsp_req   = true;
+                r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read();
+                r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read();
+                r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read();
+                r_cleanup_to_tgt_rsp_type  = true;
+
+                if (r_cleanup_ncc.read()) // need to put data to the XRAM
+                {
+                    r_cleanup_fsm = CLEANUP_IXR_REQ;
+                }
+                else
+                {
+                    r_cleanup_fsm = CLEANUP_SEND_CLACK;
+                }
+
+#if DEBUG_MEMC_CLEANUP
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CLEANUP_WRITE_RSP>"
+                        << " Send a response to a previous write request: "
+                        << " rsrcid = "   << std::hex << r_cleanup_write_srcid.read()
+                        << " / rtrdid = " << r_cleanup_write_trdid.read()
+                        << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////////
+            case CLEANUP_IXR_REQ:
+            {
+                // Send a request to the ixr to write the data in the XRAM using
+                // the prereserved TRT entry
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_CLEANUP)
+                {
+                    if (not r_cleanup_to_ixr_cmd_req.read())
+                    {
+                        size_t index = 0;
+                        bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index);
+
+                        assert(hit and "CLEANUP_IXR_REQ found no matching entry in TRT");
+
+                        r_cleanup_to_ixr_cmd_req = true;
+
+                        if (r_cleanup_contains_data.read())
+                        {
+                            std::vector<data_t> data_vector;
+                            data_vector.clear();
+
+                            for (size_t i = 0; i < m_words; i++)
+                            {
+                                data_vector.push_back(r_cleanup_data[i]);
+                            }
+
+                            m_trt.set(index,
+                                      false,                  // write to XRAM
+                                      r_cleanup_nline.read(), // line index
+                                      0,
+                                      0,
+                                      0,
+                                      false,
+                                      0,
+                                      0,
+                                      std::vector<be_t> (m_words, 0),
+                                      data_vector);
                         }
-                        else {
-                            m_cpt_cleanup_remote++;
-                            m_cpt_cleanup_data_remote++;
-                        }
-                        // 2 + m_words flits for cleanup with data
-                        m_cpt_cleanup_cost += (m_words + 2) * req_distance(srcid);
-                        m_cpt_cleanup_data_cost += (m_words + 2)  * req_distance(srcid);
-                        // </Activity Counters>
-                    }
-                    else
-                    {
-                        r_cleanup_fsm = CLEANUP_DIR_REQ;
-                        // <Activity Counters>
-                        if (is_local_req(srcid)) {
-                            m_cpt_cleanup_local++;
-                        }
-                        else {
-                            m_cpt_cleanup_remote++;
-                        }
-                        // 2 flits for cleanup without data
-                        m_cpt_cleanup_cost += 2 * req_distance(srcid);
-                        // </Activity Counters>
-                    }
-                    cc_receive_to_cleanup_fifo_get = true;
-                    r_cleanup_nline               = nline;
-
+                        r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read();
+                        r_cleanup_to_ixr_cmd_index = index;
+                        r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read();
+                        r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read();
+                        r_cleanup_fsm = CLEANUP_SEND_CLACK;
 #if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC "         << name()
-                            << " CLEANUP_GET_NLINE> Cleanup request:"
-                            << std::hex
-                            << " / address = "    << nline * m_words * 4
-                            << " / contains data = " << (!eop)
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-                /////////////////////
-            case CLEANUP_GET_DATA :
-                {
-                    if (m_cc_receive_to_cleanup_fifo.rok())
-                    {
-                        uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
-
-                        uint32_t data =
-                            DspinRwtParam::dspin_get (flit, DspinRwtParam::CLEANUP_DATA_UPDT);
-
-                        r_cleanup_data[r_cleanup_data_index] = data;
-                        r_cleanup_data_index = r_cleanup_data_index.read() + 1;
-                        assert (r_cleanup_data_index.read() < m_words and "MEM_CACHE in CLEANUP_GET_DATA : too much flits in cleanup data updt");
-                        cc_receive_to_cleanup_fifo_get = true;
-                        if (r_cleanup_data_index.read() == m_words - 1)
+                        if (m_debug)
                         {
-                            r_cleanup_contains_data = true;
-                            r_cleanup_fsm = CLEANUP_DIR_REQ;
-                        }
-#if DEBUG_MEMC_CLEANUP
-                        if(m_debug)
-                        {
-                            std::cout
-                                << "  <MEMC "         << name()
-                                << " CLEANUP_GET_DATA> "
-                                << " / word = "    << std::dec << r_cleanup_data_index.read()
-                                << " / data = " << std::hex << data
+                            std::cout << "  <MEMC " << name()
+                                << " CLEANUP_IXR_REQ>"
+                                << " request send to IXR_CMD"
                                 << std::endl;
                         }
 #endif
                     }
-                    break;
-                }
-                /////////////////////
-            case CLEANUP_DIR_REQ:   // Get the lock to the directory
-                {
-                    if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break;
-
-                    r_cleanup_fsm = CLEANUP_DIR_LOCK;
-
+                    else
+                    {
+                        r_cleanup_fsm = CLEANUP_WAIT;
 #if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl;
-#endif
-                    break;
-                }
-
-                //////////////////////
-            case CLEANUP_DIR_LOCK:
-                {
-                    // test directory status
-                    if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP)
-                    {
-                        std::cout
-                            << "VCI_MEM_CACHE ERROR " << name()
-                            << " CLEANUP_DIR_LOCK state"
-                            << " bad DIR allocation" << std::endl;
-
-                        exit(0);
-                    }
-
-                    // Read the directory
-                    size_t way = 0;
-                    addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4;
-
-                    DirectoryEntry entry   = m_cache_directory.read(cleanup_address , way);
-                    r_cleanup_is_cnt       = entry.is_cnt;
-                    r_cleanup_dirty        = entry.dirty;
-                    r_cleanup_tag          = entry.tag;
-                    r_cleanup_lock         = entry.lock;
-                    r_cleanup_way          = way;
-                    r_cleanup_count        = entry.count;
-                    r_cleanup_ptr          = entry.ptr;
-                    r_cleanup_copy         = entry.owner.srcid;
-                    r_cleanup_copy_inst    = entry.owner.inst;
-
-                    //RWT
-                    size_t set = m_y[(addr_t)(cleanup_address)];
-                    m_cache_data.read_line(way, set, r_cleanup_old_data);
-                    r_cleanup_coherent = entry.cache_coherent;
-
-                    if(entry.valid)      // hit : the copy must be cleared
-                    {
-                        assert(
-                                (entry.count > 0) and
-                                "VCI MEM CACHE ERROR: "
-                                "In CLEANUP_DIR_LOCK, CLEANUP command on a valid entry "
-                                "with no copies");
-
-                        // no access to the heap
-                        if((entry.count == 1) or (entry.is_cnt))
+                        if (m_debug)
                         {
-                            r_cleanup_fsm = CLEANUP_DIR_WRITE;
-                        }
-                        // access to the heap
-                        else
-                        {
-                            r_cleanup_fsm = CLEANUP_HEAP_REQ;
-                        }
-                    }
-                    else           // miss : check IVT for a pending invalidation transaction
-                    {
-                        r_cleanup_fsm = CLEANUP_IVT_LOCK;
-                    }
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC " << name()
-                            << " CLEANUP_DIR_LOCK> Test directory status: "
-                            << std::hex
-                            << " line = "         << cleanup_address
-                            << " / hit = "        << entry.valid
-                            << " / dir_id = "     << entry.owner.srcid
-                            << " / dir_ins = "    << entry.owner.inst
-                            << " / search_id = "  << r_cleanup_srcid.read()
-                            << " / search_ins = " << r_cleanup_inst.read()
-                            << " / count = "      << entry.count
-                            << " / is_cnt = "     << entry.is_cnt
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-                ///////////////////////
-            case CLEANUP_DIR_WRITE:
-                {
-                    // Update the directory entry without heap access
-                    if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP)
-                    {
-                        std::cout
-                            << "VCI_MEM_CACHE ERROR " << name()
-                            << " CLEANUP_DIR_WRITE state"
-                            << " bad DIR allocation" << std::endl;
-
-                        exit(0);
-                    }
-
-                    size_t way         = r_cleanup_way.read();
-                    size_t set         = m_y[(addr_t)(r_cleanup_nline.read()*m_words*4)];
-                    bool   match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read());
-
-                    bool   match_inst  = (r_cleanup_copy_inst.read() == r_cleanup_inst.read());
-                    bool   match       = match_srcid and match_inst;
-
-                    if(not r_cleanup_is_cnt.read() and not match)
-                    {
-                        std::cout
-                            << "VCI_MEM_CACHE ERROR : Cleanup request on a valid"
-                            << "entry using linked list mode with no corresponding"
-                            << "directory or heap entry"
-                            << std::endl;
-
-                        exit(1);
-                    }
-
-                    /*RWT*/
-                    bool   inval_request = (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) // NCC to CC initiated by a read transaction
-                        or (r_write_to_cleanup_req.read() and (r_cleanup_nline.read() == r_write_to_cleanup_nline.read()));              // NCC to CC initiated by a write transaction
-
-
-
-                    if (r_write_to_cleanup_req.read() and (r_cleanup_nline.read() == r_write_to_cleanup_nline.read()))
-                    {
-                        r_write_to_cleanup_req = false;
-                        m_cpt_ncc_to_cc_write ++;
-                    }
-
-
-                    // update the cache directory (for the copies)
-                    DirectoryEntry entry;
-                    entry.valid          = true;
-                    entry.cache_coherent = inval_request or r_cleanup_coherent.read();
-                    entry.is_cnt         = r_cleanup_is_cnt.read();
-                    entry.dirty          = r_cleanup_dirty.read() or r_cleanup_contains_data.read();
-                    entry.tag            = r_cleanup_tag.read();
-                    entry.lock           = r_cleanup_lock.read();
-                    entry.ptr            = r_cleanup_ptr.read();
-                    if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ
-                    {
-                        if (r_read_to_cleanup_cached_read.read())
-                        {
-                            entry.count       = r_cleanup_count.read();
-                            entry.owner.srcid = r_read_to_cleanup_srcid.read();
-                            entry.owner.inst  = r_read_to_cleanup_inst.read();
-                        }
-                        else
-                        {
-                            entry.count       = r_cleanup_count.read() - 1;
-                            entry.owner.srcid = r_cleanup_copy.read();
-                            entry.owner.inst  = r_cleanup_copy_inst.read();
-                        }
-                        if (r_read_to_cleanup_is_ll.read())
-                        {
-                            r_cleanup_to_tgt_rsp_ll_key = r_read_to_cleanup_ll_key.read();
-                        }
-                    }
-                    else
-                    {
-                        entry.count       = r_cleanup_count.read() - 1;
-                        entry.owner.srcid = 0;
-                        entry.owner.inst  = 0;
-
-#if REVERT_CC_MECANISM
-                        // Revert CC to NCC if :
-                        //  - no more copy in L1 caches
-                        //  - this line is not in counter mode (broadcast)
-                        //  - this line is not in NCC to CC mecanism
-                        if (((r_cleanup_count.read() - 1) == 0) and (r_cleanup_is_cnt == false) and (inval_request == false))
-                        {
-                            entry.cache_coherent = false;
-                        }
-#endif
-
-#if REVERT_BC_MECANISM
-                        if ((r_cleanup_count.read() - 1) == 0)
-                        {
-                            entry.is_cnt = false;
-                        }
-#endif
-
-                    }
-
-                    if (r_cleanup_contains_data.read())
-                    {
-                        for (size_t word = 0; word < m_words; word ++)
-                        {
-                            m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF);
-                        }
-                        addr_t min = r_cleanup_nline.read()*m_words*4 ;
-                        addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4;
-                        m_llsc_table.sw(min, max);
-                    }
-
-                    m_cache_directory.write(set, way, entry);
-
-                    /*RWT*/
-                    if (inval_request)
-                    {
-                        r_cleanup_fsm = CLEANUP_IVT_LOCK_DATA;
-                    }
-                    else
-                    {
-                        r_cleanup_fsm = CLEANUP_SEND_CLACK;
-                    }
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC " << name()
-                            << " CLEANUP_DIR_WRITE> Update directory:"
-                            << std::hex
-                            << " address = "   << r_cleanup_nline.read() * m_words * 4
-                            << " / dir_id = "  << entry.owner.srcid
-                            << " / dir_ins = " << entry.owner.inst
-                            << " / count = "   << entry.count
-                            << " / is_cnt = "  << entry.is_cnt
-                            << " / match_inval = " << inval_request
-                            << " / is_coherent = " << entry.cache_coherent
-                            << std::dec
-                            << std::endl;
-                    }
-#endif
-
-                    break;
-                }
-                /////////////////////
-            case CLEANUP_IVT_LOCK_DATA://RWT
-                {
-                    //Search for a matching inval in the IVT (there must be one) and check if there is a pending read.
-                    if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP)
-                    {
-                        size_t index = 0;
-                        bool   match_inval;
-
-                        match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index);
-                        assert (match_inval && "VCI MEM CACHE ERROR: In CLEANUP_IVT_LOCK_DATA, NO CORRESPONDING INVAL");
-                        r_cleanup_read_srcid    = m_ivt.srcid(index);
-                        r_cleanup_read_trdid    = m_ivt.trdid(index);
-                        r_cleanup_read_pktid    = 0x0 + m_ivt.pktid(index);
-                        r_cleanup_read_need_rsp = !m_ivt.need_rsp(index);
-                        r_cleanup_index         = index;
-
-                        r_cleanup_fsm = CLEANUP_IVT_CLEAR_DATA;
-                    }
-#if DEBUG_MEMC_CLEANUP
-                    if (m_debug)
-                    {
-                        std::cout
-                            << " <MEMC " << name()
-                            << " CLEANUP_IVT_LOCK_DATA> fetch pending inval"
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-                //////////////////////////
-            case CLEANUP_IVT_CLEAR_DATA://RWT
-                {
-                    m_ivt.clear(r_cleanup_index.read());
-                    assert ((r_cleanup_read_need_rsp.read() == (r_read_to_cleanup_req.read() && (r_cleanup_nline.read() == r_read_to_cleanup_nline.read()))) && "condition pending read");
-                    if (r_cleanup_read_need_rsp.read())
-                    {
-                        r_cleanup_fsm = CLEANUP_READ_RSP;
-                    }
-                    else
-                    {
-                        r_cleanup_fsm = CLEANUP_SEND_CLACK;
-                    }
-#if DEBUG_MEMC_CLEANUP
-                    if (m_debug)
-                    {
-                        std::cout
-                            << " <MEMC " << name()
-                            << " CLEANUP_IVT_CLEAR_DATA> clear IVT entry"
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-                ////////////////////////
-            case CLEANUP_READ_RSP://RWT
-                {
-                    if(r_cleanup_to_tgt_rsp_req.read()) break;
-
-                    r_cleanup_to_tgt_rsp_req     = true;
-                    r_cleanup_to_tgt_rsp_srcid   = r_cleanup_read_srcid.read();
-                    r_cleanup_to_tgt_rsp_trdid   = r_cleanup_read_trdid.read();
-                    r_cleanup_to_tgt_rsp_pktid   = 0x0 + r_cleanup_read_pktid.read();//RWT
-                    r_cleanup_to_tgt_rsp_type    = 0; //Read instruction
-                    r_cleanup_to_tgt_rsp_length  = r_read_to_cleanup_length.read();
-                    r_cleanup_to_tgt_rsp_first_word  = r_read_to_cleanup_first_word.read();
-                    r_read_to_cleanup_req        = false;
-                    m_cpt_ncc_to_cc_read ++;
-                    if (r_cleanup_contains_data.read()) //L1 was dirty
-                    {
-                        for(size_t i = 0; i<m_words; i++)
-                        {
-                            r_cleanup_to_tgt_rsp_data[i] = r_cleanup_data[i].read();
-                        }
-                    }
-                    else //the L2 data are up to date
-                    {
-                        for(size_t i = 0; i<m_words; i++)
-                        {
-                            r_cleanup_to_tgt_rsp_data[i] = r_cleanup_old_data[i].read();
-                        }
-                    }
-
-                    r_cleanup_fsm                = CLEANUP_SEND_CLACK;
-
-#if DEBUG_MEMC_CLEANUP
-                    if (m_debug)
-                    {
-                        std::cout
-                            << " <MEMC " << name()
-                            << " CLEANUP_READ_RSP> answer READ"
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-                //////////////////////
-            case CLEANUP_HEAP_REQ:
-                {
-                    // get the lock to the HEAP directory
-                    if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break;
-
-                    r_cleanup_fsm = CLEANUP_HEAP_LOCK;
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC " << name()
-                            << " CLEANUP_HEAP_REQ> HEAP lock acquired "
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-                //////////////////////
-            case CLEANUP_HEAP_LOCK:
-                {
-                    // two cases are handled in this state :
-                    // 1. the matching copy is directly in the directory
-                    // 2. the matching copy is the first copy in the heap
-                    assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
-                            "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
-
-                    size_t way            = r_cleanup_way.read();
-                    size_t set            = m_y[(addr_t)(r_cleanup_nline.read() *m_words*4)];
-
-                    HeapEntry heap_entry  = m_heap.read(r_cleanup_ptr.read());
-                    bool last             = (heap_entry.next == r_cleanup_ptr.read());
-
-                    // match_dir computation
-                    bool match_dir_srcid  = (r_cleanup_copy.read()      == r_cleanup_srcid.read());
-                    bool match_dir_inst   = (r_cleanup_copy_inst.read() == r_cleanup_inst.read());
-                    bool match_dir        = match_dir_srcid  and match_dir_inst;
-
-                    // match_heap computation
-                    bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read());
-                    bool match_heap_inst  = (heap_entry.owner.inst  == r_cleanup_inst.read());
-                    bool match_heap       = match_heap_srcid and match_heap_inst;
-
-                    r_cleanup_prev_ptr    = r_cleanup_ptr.read();
-                    r_cleanup_prev_srcid  = heap_entry.owner.srcid;
-                    r_cleanup_prev_inst   = heap_entry.owner.inst;
-
-                    assert( (not last or match_dir or match_heap) and
-                            "MEMC ERROR in CLEANUP_HEAP_LOCK state: hit but no copy found");
-
-                    assert( (not match_dir or not match_heap) and
-                            "MEMC ERROR in CLEANUP_HEAP_LOCK state: two matching copies found");
-
-                    DirectoryEntry dir_entry;
-                    dir_entry.valid          = true;
-                    dir_entry.cache_coherent = true;
-                    dir_entry.is_cnt         = r_cleanup_is_cnt.read();
-                    dir_entry.dirty          = r_cleanup_dirty.read();
-                    dir_entry.tag            = r_cleanup_tag.read();
-                    dir_entry.lock           = r_cleanup_lock.read();
-                    dir_entry.count          = r_cleanup_count.read()-1;
-
-                    // the matching copy is registered in the directory and
-                    // it must be replaced by the first copy registered in
-                    // the heap. The corresponding entry must be freed
-                    if(match_dir)
-                    {
-                        dir_entry.ptr            = heap_entry.next;
-                        dir_entry.owner.srcid    = heap_entry.owner.srcid;
-                        dir_entry.owner.inst     = heap_entry.owner.inst;
-                        r_cleanup_next_ptr       = r_cleanup_ptr.read();
-                        r_cleanup_fsm            = CLEANUP_HEAP_FREE;
-                    }
-
-                    // the matching copy is the first copy in the heap
-                    // It must be freed and the copy registered in directory
-                    // must point to the next copy in heap
-                    else if(match_heap)
-                    {
-                        dir_entry.ptr            = heap_entry.next;
-                        dir_entry.owner.srcid    = r_cleanup_copy.read();
-                        dir_entry.owner.inst     = r_cleanup_copy_inst.read();
-                        r_cleanup_next_ptr       = r_cleanup_ptr.read();
-                        r_cleanup_fsm            = CLEANUP_HEAP_FREE;
-                    }
-
-                    // The matching copy is in the heap, but is not the first copy
-                    // The directory entry must be modified to decrement count
-                    else
-                    {
-                        dir_entry.ptr            = r_cleanup_ptr.read();
-                        dir_entry.owner.srcid    = r_cleanup_copy.read();
-                        dir_entry.owner.inst     = r_cleanup_copy_inst.read();
-                        r_cleanup_next_ptr       = heap_entry.next;
-                        r_cleanup_fsm            = CLEANUP_HEAP_SEARCH;
-                    }
-
-                    m_cache_directory.write(set,way,dir_entry);
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC " << name()
-                            << " CLEANUP_HEAP_LOCK> Checks matching:"
-                            << " address = "      << r_cleanup_nline.read() * m_words * 4
-                            << " / dir_id = "     << r_cleanup_copy.read()
-                            << " / dir_ins = "    << r_cleanup_copy_inst.read()
-                            << " / heap_id = "    << heap_entry.owner.srcid
-                            << " / heap_ins = "   << heap_entry.owner.inst
-                            << " / search_id = "  << r_cleanup_srcid.read()
-                            << " / search_ins = " << r_cleanup_inst.read()
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-                ////////////////////////
-            case CLEANUP_HEAP_SEARCH:
-                {
-                    // This state is handling the case where the copy
-                    // is in the heap, but is not the first in the linked list
-                    assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
-                            "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
-
-                    HeapEntry heap_entry  = m_heap.read(r_cleanup_next_ptr.read());
-
-                    bool last             = (heap_entry.next        == r_cleanup_next_ptr.read());
-                    bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read());
-                    bool match_heap_inst  = (heap_entry.owner.inst  == r_cleanup_inst.read());
-                    bool match_heap       = match_heap_srcid and match_heap_inst;
-
-                    assert( (not last or match_heap) and
-                            "MEMC ERROR in CLEANUP_HEAP_SEARCH state: no copy found");
-
-                    // the matching copy must be removed
-                    if(match_heap)
-                    {
-                        // re-use ressources
-                        r_cleanup_ptr = heap_entry.next;
-                        r_cleanup_fsm = CLEANUP_HEAP_CLEAN;
-                    }
-                    // test the next in the linked list
-                    else
-                    {
-                        r_cleanup_prev_ptr      = r_cleanup_next_ptr.read();
-                        r_cleanup_prev_srcid    = heap_entry.owner.srcid;
-                        r_cleanup_prev_inst     = heap_entry.owner.inst;
-                        r_cleanup_next_ptr      = heap_entry.next;
-                        r_cleanup_fsm           = CLEANUP_HEAP_SEARCH;
-                    }
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                    {
-                        if(not match_heap)
-                        {
-                            std::cout
-                                << "  <MEMC " << name()
-                                << " CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
+                            std::cout << "  <MEMC " << name()
+                                << " CLEANUP_IXR_REQ>"
+                                << " waiting completion of previous request"
                                 << std::endl;
                         }
-                        else
-                        {
-                            std::cout
-                                << "  <MEMC " << name()
-                                << " CLEANUP_HEAP_SEARCH> Matching copy found:"
-                                << std::endl;
-                        }
-
-                        std::cout
-                            << " address = "      << r_cleanup_nline.read() * m_words * 4
-                            << " / heap_id = "    << heap_entry.owner.srcid
-                            << " / heap_ins = "   << heap_entry.owner.inst
-                            << " / search_id = "  << r_cleanup_srcid.read()
-                            << " / search_ins = " << r_cleanup_inst.read()
-                            << " / last = "       << last
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-                ////////////////////////
-            case CLEANUP_HEAP_CLEAN:    // remove a copy in the linked list
-                {
-                    assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
-                            "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
-
-                    HeapEntry heap_entry;
-                    heap_entry.owner.srcid    = r_cleanup_prev_srcid.read();
-                    heap_entry.owner.inst     = r_cleanup_prev_inst.read();
-                    bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read());
-
-                    // this is the last entry of the list of copies
-                    if(last)
-                    {
-                        heap_entry.next = r_cleanup_prev_ptr.read();
-                    }
-                    // this is not the last entry
-                    else
-                    {
-                        heap_entry.next = r_cleanup_ptr.read();
-                    }
-
-                    m_heap.write(r_cleanup_prev_ptr.read(), heap_entry);
-
-                    r_cleanup_fsm = CLEANUP_HEAP_FREE;
+#endif
+                    }
+                }
+                break;
+            }
+
+            /////////////////////
+            case CLEANUP_WAIT :
+            {
+                r_cleanup_fsm = CLEANUP_IXR_REQ;
+                break;
+            }
+
+            ////////////////////////
+            case CLEANUP_SEND_CLACK:  // acknowledgement to a cleanup command
+                                      // on the coherence CLACK network.
+            {
+                if (not p_dspin_clack.read) break;
+
+                r_cleanup_fsm = CLEANUP_IDLE;
 
 #if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CLEANUP_HEAP_SEARCH>"
-                            << " Remove the copy in the linked list" << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////
-            case CLEANUP_HEAP_FREE:   // The heap entry pointed by r_cleanup_next_ptr is freed
-                // and becomes the head of the list of free entries
-                {
-                    assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
-                            "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
-                    HeapEntry heap_entry;
-                    heap_entry.owner.srcid    = 0;
-                    heap_entry.owner.inst     = false;
-
-                    if(m_heap.is_full())
-                    {
-                        heap_entry.next = r_cleanup_next_ptr.read();
-                    }
-                    else
-                    {
-                        heap_entry.next = m_heap.next_free_ptr();
-                    }
-
-                    m_heap.write(r_cleanup_next_ptr.read(),heap_entry);
-                    m_heap.write_free_ptr(r_cleanup_next_ptr.read());
-                    m_heap.unset_full();
-
-                    // <Activity counters>
-                    m_cpt_heap_slot_available++;
-                    // </Activity counters>
-
-                    r_cleanup_fsm = CLEANUP_SEND_CLACK;
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CLEANUP_HEAP_FREE>"
-                            << " Update the list of free entries" << std::endl;
-#endif
-                    break;
-                }
-                //////////////////////
-            case CLEANUP_IVT_LOCK:   // get the lock protecting the IVT to search a pending
-                // invalidate transaction matching the cleanup
-                {
-                    if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break;
-
-                    size_t index = 0;
-                    bool   match_inval;
-
-                    match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index);
-                    if ( not match_inval )     // no pending inval
-                    {
-                        r_cleanup_fsm = CLEANUP_SEND_CLACK;
-
-#if DEBUG_MEMC_CLEANUP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " CLEANUP_IVT_LOCK> Unexpected cleanup"
-                                << " with no corresponding IVT entry:"
-                                << " address = " << std::hex
-                                << (r_cleanup_nline.read() *4*m_words)
-                                << std::endl;
-#endif
-                    }
-                    else
-                    {
-                        // pending inval
-                        r_cleanup_write_srcid = m_ivt.srcid(index);
-                        r_cleanup_write_trdid = m_ivt.trdid(index);
-                        r_cleanup_write_pktid = m_ivt.pktid(index);
-                        r_cleanup_need_rsp    = m_ivt.need_rsp(index);
-                        r_cleanup_need_ack    = m_ivt.need_ack(index);
-                        r_cleanup_index       = index;
-                        r_cleanup_fsm         = CLEANUP_IVT_DECREMENT;
-#if DEBUG_MEMC_CLEANUP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " CLEANUP_IVT_LOCK> Cleanup matching pending"
-                                << " invalidate transaction on IVT:"
-                                << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4
-                                << " / ivt_entry = " << index << std::endl;
-#endif
-                    }
-                    break;
-                }
-                ///////////////////////////
-            case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry
-                {
-                    assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and
-                            "MEMC ERROR in CLEANUP_IVT_DECREMENT state: Bad IVT allocation");
-
-                    size_t count = 0;
-                    m_ivt.decrement(r_cleanup_index.read(), count);
-
-                    if(count == 0)   // multi inval transaction completed
-                    {
-                        r_cleanup_fsm = CLEANUP_IVT_CLEAR;
-                    }
-                    else             // multi inval transaction not completed
-                    {
-                        if (r_cleanup_ncc.read()) //need to put data to the XRAM
-                        {
-                            r_cleanup_fsm = CLEANUP_IXR_REQ;
-                        }
-                        else
-                        {
-                            r_cleanup_fsm = CLEANUP_SEND_CLACK;
-                        }
-                    }
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CLEANUP_IVT_DECREMENT>"
-                            << " Decrement response counter in IVT:"
-                            << " IVT_index = " << r_cleanup_index.read()
-                            << " / rsp_count = " << count << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////
-            case CLEANUP_IVT_CLEAR:    // Clear IVT entry
-                {
-                    assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and
-                            "MEMC ERROR in CLEANUP_IVT_CLEAR state : bad IVT allocation");
-
-                    m_ivt.clear(r_cleanup_index.read());
-
-                    if ( r_cleanup_need_ack.read() )
-                    {
-                        assert( (r_config_rsp_lines.read() > 0) and
-                                "MEMC ERROR in CLEANUP_IVT_CLEAR state");
-
-                        config_rsp_lines_cleanup_decr = true;
-                    }
-
-                    if      ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP;
-                    else if ( r_cleanup_ncc.read() ) r_cleanup_fsm = CLEANUP_IXR_REQ;
-                    else                                  r_cleanup_fsm = CLEANUP_SEND_CLACK;
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                        std::cout << "  <MEMC "      << name()
-                            << " CLEANUP_IVT_CLEAR> Clear entry in IVT:"
-                            << " IVT_index = " << r_cleanup_index.read() << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////
-            case CLEANUP_WRITE_RSP:    // response to a previous write on the direct network
-                // wait if pending request to the TGT_RSP FSM
-                {
-                    if(r_cleanup_to_tgt_rsp_req.read()) break;
-
-                    assert ( (r_cleanup_ncc.read() == false) and
-                            "CLEANUP_WRITE_RSP : Cleanup on NCC line invalid in "
-                            "MEM_CACHE with write_rsp needed. STRANGE BEHAVIOUR");
-                    // no pending request
-                    r_cleanup_to_tgt_rsp_req     = true;
-                    r_cleanup_to_tgt_rsp_srcid   = r_cleanup_write_srcid.read();
-                    r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
-                    r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
-                    r_cleanup_to_tgt_rsp_type    = true;
-
-                    if (r_cleanup_ncc.read() )
-                    {
-                        r_cleanup_fsm = CLEANUP_IXR_REQ;//need to put data to the XRAM
-                    }
-                    else
-                    {
-                        r_cleanup_fsm = CLEANUP_SEND_CLACK;
-                    }
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CLEANUP_WRITE_RSP>"
-                            << " Send a response to a previous write request: "
-                            << " rsrcid = "   << std::hex << r_cleanup_write_srcid.read()
-                            << " / rtrdid = " << r_cleanup_write_trdid.read()
-                            << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl;
-#endif
-                    break;
-                }
-                /////////////////////////
-            case CLEANUP_IXR_REQ:
-                {
-                    //Send a request to the ixr to write the data in the XRAM using the prereserved TRT entry
-                    if (r_alloc_trt_fsm.read() == ALLOC_TRT_CLEANUP)
-                    {
-                        if( not r_cleanup_to_ixr_cmd_req.read())
-                        {
-                            size_t index = 0;
-                            bool   hit   = m_trt.hit_write(r_cleanup_nline.read(), &index);
-
-                            assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT");
-
-                            r_cleanup_to_ixr_cmd_req     = true;
-
-                            if (r_cleanup_contains_data.read())
-                            {
-                                std::vector<data_t> data_vector;
-                                data_vector.clear();
-
-                                for(size_t i=0; i<m_words; i++)
-                                {
-                                    data_vector.push_back(r_cleanup_data[i]);
-                                }
-
-                                m_trt.set(index,
-                                        false,       // write to XRAM
-                                        r_cleanup_nline.read(),  // line index
-                                        0,
-                                        0,
-                                        0,
-                                        false,
-                                        0,
-                                        0,
-                                        std::vector<be_t> (m_words,0),
-                                        data_vector);
-                            }
-                            r_cleanup_to_ixr_cmd_srcid        = r_cleanup_srcid.read();
-                            r_cleanup_to_ixr_cmd_index        = index;
-                            r_cleanup_to_ixr_cmd_pktid        = r_cleanup_pktid.read();
-                            r_cleanup_to_ixr_cmd_nline        = r_cleanup_nline.read();
-                            //r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read();
-                            r_cleanup_fsm = CLEANUP_SEND_CLACK;
-#if DEBUG_MEMC_CLEANUP
-                            if(m_debug)
-                            {
-                                std::cout
-                                    << "  <MEMC " << name()
-                                    << " CLEANUP_IXR_REQ>"
-                                    << " request send to IXR_CMD"
-                                    << std::endl;
-                            }
-#endif
-                        }
-                        else
-                        {
-                            r_cleanup_fsm = CLEANUP_WAIT;
-#if DEBUG_MEMC_CLEANUP
-                            if(m_debug)
-                            {
-                                std::cout
-                                    << "  <MEMC " << name()
-                                    << " CLEANUP_IXR_REQ>"
-                                    << " waiting completion of previous request"
-                                    << std::endl;
-                            }
-#endif
-                        }
-                    }
-                    break;
-                }
-
-                /////////////////////
-            case CLEANUP_WAIT :
-                {
-                    r_cleanup_fsm = CLEANUP_IXR_REQ;
-                    break;
-                }
-
-                ////////////////////////
-            case CLEANUP_SEND_CLACK:  // acknowledgement to a cleanup command
-                // on the coherence CLACK network.
-                {
-                    if(not p_dspin_clack.read) break;
-
-                    r_cleanup_fsm = CLEANUP_IDLE;
-
-#if DEBUG_MEMC_CLEANUP
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:"
-                            << " nline = "   << std::hex << r_cleanup_nline.read()
-                            << " / way = "   << std::dec << r_cleanup_way.read()
-                            << " / srcid = " << std::dec << r_cleanup_srcid.read()
-                            << std::endl;
-#endif
-                    break;
-                }
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:"
+                        << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4
+                        << " / way = "   << std::dec << r_cleanup_way.read()
+                        << " / srcid = " << std::dec << r_cleanup_srcid.read()
+                        << std::endl;
+                }
+#endif
+                break;
+            }
         } // end switch cleanup fsm
 
@@ -6593 +6637 @@
         //    CAS FSM
         ////////////////////////////////////////////////////////////////////////////////////
-        // The CAS FSM handles the CAS (Store Conditionnal) atomic commands,
-        // that are handled as "compare-and-swap instructions.
+        // The CAS FSM handles the CAS (Compare And Swap) atomic commands.
         //
         // This command contains two or four flits:
         // - In case of 32 bits atomic access, the first flit contains the value read
-        // by a previous LL instruction, the second flit contains the value to be writen.
+        // by a previous READ instruction, the second flit contains the value to be writen.
         // - In case of 64 bits atomic access, the 2 first flits contains the value read
-        // by a previous LL instruction, the 2 next flits contains the value to be writen.
+        // by a previous READ instruction, the 2 next flits contains the value to be writen.
         //
         // The target address is cachable. If it is replicated in other L1 caches
@@ -6607 +6650 @@
         // It access the directory to check hit / miss.
         // - In case of miss, the CAS FSM must register a GET transaction in TRT.
-        // If a read transaction to the XRAM for this line already exists,
-        // or if the transaction table is full, it goes to the WAIT state
-        // to release the locks and try again. When the GET transaction has been
-        // launched, it goes to the WAIT state and try again.
-        // The CAS request is not consumed in the FIFO until a HIT is obtained.
+        //   If a read transaction to the XRAM for this line already exists,
+        //   or if the transaction table is full, it goes to the WAIT state
+        //   to release the locks and try again. When the GET transaction has been
+        //   launched, it goes to the WAIT state and try again.
+        //   The CAS request is not consumed in the FIFO until a HIT is obtained.
         // - In case of hit...
         ///////////////////////////////////////////////////////////////////////////////////
 
-        switch(r_cas_fsm.read())
+        switch (r_cas_fsm.read())
         {
+            ////////////
+            case CAS_IDLE:     // fill the local rdata buffers
+            {
+                if (m_cmd_cas_addr_fifo.rok())
+                {
+
+#if DEBUG_MEMC_CAS
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CAS_IDLE> CAS command: " << std::hex
+                            << " srcid = " <<  std::dec << m_cmd_cas_srcid_fifo.read()
+                            << " addr = " << std::hex << m_cmd_cas_addr_fifo.read()
+                            << " wdata = " << m_cmd_cas_wdata_fifo.read()
+                            << " eop = " << std::dec << m_cmd_cas_eop_fifo.read()
+                            << " cpt  = " << std::dec << r_cas_cpt.read() << std::endl;
+                    }
+#endif
+                    if (m_cmd_cas_eop_fifo.read())
+                    {
+                        r_cas_fsm = CAS_DIR_REQ;
+                    }
+                    else  // we keep the last word in the FIFO
+                    {
+                        cmd_cas_fifo_get = true;
+                    }
+
+                    // We fill the two buffers
+                    if (r_cas_cpt.read() < 2)    // 32 bits access
+                    {
+                        r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read();
+                    }
+
+                    if ((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read())
+                    {
+                        r_cas_wdata = m_cmd_cas_wdata_fifo.read();
+                    }
+
+                    assert((r_cas_cpt.read() <= 3) and  // no more than 4 flits...
+                            "MEMC ERROR in CAS_IDLE state: illegal CAS command");
+
+                    if (r_cas_cpt.read() == 2)
+                    {
+                        r_cas_wdata = m_cmd_cas_wdata_fifo.read();
+                    }
+
+                    r_cas_cpt = r_cas_cpt.read() + 1;
+                }
+                break;
+            }
+            /////////////////
+            case CAS_DIR_REQ:
+            {
+                if (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)
+                {
+                    r_cas_fsm = CAS_DIR_LOCK;
+                }
+
+#if DEBUG_MEMC_CAS
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CAS_DIR_REQ> Requesting DIR lock " << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////
+            case CAS_DIR_LOCK:  // Read the directory
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
+                        "MEMC ERROR in CAS_DIR_LOCK: Bad DIR allocation");
+
+                size_t way = 0;
+                DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way));
+
+                r_cas_is_cnt    = entry.is_cnt;
+                r_cas_dirty     = entry.dirty;
+                r_cas_tag       = entry.tag;
+                r_cas_way       = way;
+                r_cas_copy      = entry.owner.srcid;
+                r_cas_copy_inst = entry.owner.inst;
+                r_cas_ptr       = entry.ptr;
+                r_cas_count     = entry.count;
+                r_cas_coherent  = entry.cache_coherent;
+
+                if (entry.valid) r_cas_fsm = CAS_DIR_HIT_READ;
+                else             r_cas_fsm = CAS_MISS_TRT_LOCK;
+
+#if DEBUG_MEMC_CAS
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CAS_DIR_LOCK> Directory acces"
+                        << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
+                        << " / hit = " << std::dec << entry.valid
+                        << " / count = " << entry.count
+                        << " / is_cnt = " << entry.is_cnt << std::endl;
+                }
+#endif
+
+                break;
+            }
+            /////////////////////
+            case CAS_DIR_HIT_READ:  // update directory for lock and dirty bit
+            // and check data change in cache
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
+                        "MEMC ERROR in CAS_DIR_HIT_READ: Bad DIR allocation");
+
+                size_t way = r_cas_way.read();
+                size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
+
+                // update directory (lock & dirty bits)
+                DirectoryEntry entry;
+                entry.valid          = true;
+                entry.is_cnt         = r_cas_is_cnt.read();
+                entry.dirty          = true;
+                entry.lock           = true;
+                entry.tag            = r_cas_tag.read();
+                entry.owner.srcid    = r_cas_copy.read();
+                entry.owner.inst     = r_cas_copy_inst.read();
+                entry.count          = r_cas_count.read();
+                entry.ptr            = r_cas_ptr.read();
+                entry.cache_coherent = r_cas_coherent.read();
+
+                m_cache_directory.write(set, way, entry);
+
+                // Store data from cache in buffer to do the comparison in next state
+                m_cache_data.read_line(way, set, r_cas_data);
+
+                r_cas_fsm = CAS_DIR_HIT_COMPARE;
+
+#if DEBUG_MEMC_CAS
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from "
+                        << " cache and store it in buffer" << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////////////
+            case CAS_DIR_HIT_COMPARE:
+            {
+                size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
+
+                // check data change
+                bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read());
+
+                if (r_cas_cpt.read() == 4)     // 64 bits CAS
+                    ok &= (r_cas_rdata[1] == r_cas_data[word+1]);
+
+                // to avoid livelock, force the atomic access to fail pseudo-randomly
+                bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS);
+                r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001);
+
+                if (ok and not forced_fail) r_cas_fsm = CAS_DIR_HIT_WRITE;
+                else                        r_cas_fsm = CAS_RSP_FAIL;
+
+#if DEBUG_MEMC_CAS
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare old and new data"
+                        << " / expected value = " << std::hex << r_cas_rdata[0].read()
+                        << " / actual value = "   << std::hex << r_cas_data[word].read()
+                        << " / forced_fail = "    << std::dec << forced_fail << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////
+            case CAS_DIR_HIT_WRITE:    // test if a CC transaction is required
+            // write data in cache if no CC request
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
+                        "MEMC ERROR in CAS_DIR_HIT_WRITE: Bad DIR allocation");
+
+                // The CAS is a success => sw access to the llsc_global_table
+                m_llsc_table.sw(m_cmd_cas_addr_fifo.read(), m_cmd_cas_addr_fifo.read());
+
+                // test coherence request
+                if (r_cas_count.read())   // replicated line
+                {
+                    if (r_cas_is_cnt.read())
+                    {
+                        r_cas_fsm = CAS_BC_TRT_LOCK;    // broadcast invalidate required
+
+#if DEBUG_MEMC_CAS
+                        if (m_debug)
+                        {
+                            std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
+                                << " Broacast Inval required"
+                                << " / copies = " << r_cas_count.read() << std::endl;
+                        }
+#endif
+                    }
+                    else if (not r_cas_to_cc_send_multi_req.read() and
+                            not r_cas_to_cc_send_brdcast_req.read())
+                    {
+                        r_cas_fsm = CAS_UPT_LOCK;       // multi update required
+
+#if DEBUG_MEMC_CAS
+                        if (m_debug)
+                        {
+                            std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
+                                << " Multi Inval required"
+                                << " / copies = " << r_cas_count.read() << std::endl;
+                        }
+#endif
+                    }
+                    else
+                    {
+                        r_cas_fsm = CAS_WAIT;
+
+#if DEBUG_MEMC_CAS
+                        if (m_debug)
+                        {
+                            std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
+                                << " CC_SEND FSM busy: release all locks and retry" << std::endl;
+                        }
+#endif
+                    }
+                }
+                else                    // no copies
+                {
+                    size_t way  = r_cas_way.read();
+                    size_t set  = m_y[(addr_t) (m_cmd_cas_addr_fifo.read())];
+                    size_t word = m_x[(addr_t) (m_cmd_cas_addr_fifo.read())];
+
+                    // cache update
+                    m_cache_data.write(way, set, word, r_cas_wdata.read());
+                    if (r_cas_cpt.read() == 4)
+                    {
+                        m_cache_data.write(way, set, word + 1, m_cmd_cas_wdata_fifo.read());
+                    }
+
+                    r_cas_fsm = CAS_RSP_SUCCESS;
+
+#if DEBUG_MEMC_CAS
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:"
+                            << " way = " << std::dec << way
+                            << " / set = " << set
+                            << " / word = " << word
+                            << " / value = " << r_cas_wdata.read()
+                            << " / count = " << r_cas_count.read()
+                            << " / global_llsc_table access" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////
+            case CAS_UPT_LOCK:  // try to register the transaction in UPT
+            // and write data in cache if successful registration
+            // releases locks to retry later if UPT full
+            {
+                if (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS)
+                {
+                    bool   wok       = false;
+                    size_t index     = 0;
+                    size_t srcid     = m_cmd_cas_srcid_fifo.read();
+                    size_t trdid     = m_cmd_cas_trdid_fifo.read();
+                    size_t pktid     = m_cmd_cas_pktid_fifo.read();
+                    addr_t nline     = m_nline[(addr_t) (m_cmd_cas_addr_fifo.read())];
+                    size_t nb_copies = r_cas_count.read();
+
+                    wok = m_upt.set(true,  // it's an update transaction
+                                    false, // it's not a broadcast
+                                    true,  // response required
+                                    false, // no acknowledge required
+                                    srcid,
+                                    trdid,
+                                    pktid,
+                                    nline,
+                                    nb_copies,
+                                    index);
+                    if (wok)   // coherence transaction registered in UPT
+                    {
+                        // cache update
+                        size_t way  = r_cas_way.read();
+                        size_t set  = m_y[(addr_t) (m_cmd_cas_addr_fifo.read())];
+                        size_t word = m_x[(addr_t) (m_cmd_cas_addr_fifo.read())];
+
+                        m_cache_data.write(way, set, word, r_cas_wdata.read());
+                        if (r_cas_cpt.read() == 4)
+                        {
+                            m_cache_data.write(way, set, word + 1, m_cmd_cas_wdata_fifo.read());
+                        }
+
+                        r_cas_upt_index = index;
+                        r_cas_fsm = CAS_UPT_HEAP_LOCK;
+                    }
+                    else       //  releases the locks protecting UPT and DIR UPT full
+                    {
+                        r_cas_fsm = CAS_WAIT;
+                    }
+
+#if DEBUG_MEMC_CAS
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " CAS_UPT_LOCK> Register multi-update transaction in UPT"
+                            << " / wok = " << wok
+                            << " / address  = " << std::hex << nline * m_words * 4
+                            << " / count = " << nb_copies << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
             /////////////
-            case CAS_IDLE:     // fill the local rdata buffers
-                {
-                    if(m_cmd_cas_addr_fifo.rok())
-                    {
+            case CAS_WAIT:   // release all locks and retry from beginning
+            {
 
 #if DEBUG_MEMC_CAS
-                        if(m_debug)
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CAS_WAIT> Release all locks" << std::endl;
+                }
+#endif
+                r_cas_fsm = CAS_DIR_REQ;
+                break;
+            }
+            //////////////////////
+            case CAS_UPT_HEAP_LOCK:  // lock the heap
+            {
+                if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)
+                {
+
+#if DEBUG_MEMC_CAS
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " CAS_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
+                    }
+#endif
+                    r_cas_fsm = CAS_UPT_REQ;
+                }
+                break;
+            }
+            ////////////////
+            case CAS_UPT_REQ:  // send a first update request to CC_SEND FSM
+            {
+                assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and
+                        "VCI_MEM_CACHE ERROR : bad HEAP allocation");
+
+                if (!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read())
+                {
+                    r_cas_to_cc_send_brdcast_req = false;
+                    r_cas_to_cc_send_trdid       = r_cas_upt_index.read();
+                    r_cas_to_cc_send_nline       = m_nline[(addr_t) (m_cmd_cas_addr_fifo.read())];
+                    r_cas_to_cc_send_index       = m_x[(addr_t) (m_cmd_cas_addr_fifo.read())];
+                    r_cas_to_cc_send_wdata       = r_cas_wdata.read();
+
+                    if (r_cas_cpt.read() == 4)
+                    {
+                        r_cas_to_cc_send_is_long    = true;
+                        r_cas_to_cc_send_wdata_high = m_cmd_cas_wdata_fifo.read();
+                    }
+                    else
+                    {
+                        r_cas_to_cc_send_is_long    = false;
+                        r_cas_to_cc_send_wdata_high = 0;
+                    }
+
+                    // We put the first copy in the fifo
+                    cas_to_cc_send_fifo_put   = true;
+                    cas_to_cc_send_fifo_inst  = r_cas_copy_inst.read();
+                    cas_to_cc_send_fifo_srcid = r_cas_copy.read();
+                    if (r_cas_count.read() == 1)  // one single copy
+                    {
+                        r_cas_fsm = CAS_IDLE;   // Response will be sent after receiving
+                        // update responses
+                        cmd_cas_fifo_get = true;
+                        r_cas_to_cc_send_multi_req = true;
+                        r_cas_cpt = 0;
+                    }
+                    else      // several copies
+                    {
+                        r_cas_fsm = CAS_UPT_NEXT;
+                    }
+
+#if DEBUG_MEMC_CAS
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CAS_UPT_REQ> Send the first update request to CC_SEND FSM "
+                            << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
+                            << " / wdata = " << std::hex << r_cas_wdata.read()
+                            << " / srcid = " << std::dec << r_cas_copy.read()
+                            << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////
+            case CAS_UPT_NEXT:     // send a multi-update request to CC_SEND FSM
+            {
+                assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)
+                        and "VCI_MEM_CACHE ERROR : bad HEAP allocation");
+
+                HeapEntry entry = m_heap.read(r_cas_ptr.read());
+                cas_to_cc_send_fifo_srcid = entry.owner.srcid;
+                cas_to_cc_send_fifo_inst  = entry.owner.inst;
+                cas_to_cc_send_fifo_put = true;
+
+                if (m_cas_to_cc_send_inst_fifo.wok())   // request accepted by CC_SEND FSM
+                {
+                    r_cas_ptr = entry.next;
+                    if (entry.next == r_cas_ptr.read())    // last copy
+                    {
+                        r_cas_to_cc_send_multi_req = true;
+                        r_cas_fsm = CAS_IDLE;   // Response will be sent after receiving
+                        // all update responses
+                        cmd_cas_fifo_get = true;
+                        r_cas_cpt        = 0;
+                    }
+                }
+
+#if DEBUG_MEMC_CAS
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CAS_UPT_NEXT> Send the next update request to CC_SEND FSM "
+                        << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
+                        << " / wdata = " << std::hex << r_cas_wdata.read()
+                        << " / srcid = " << std::dec << entry.owner.srcid
+                        << " / inst = " << std::dec << entry.owner.inst << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////////
+            case CAS_BC_TRT_LOCK:      // get TRT lock to check TRT not full
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
+                        "MEMC ERROR in CAS_BC_TRT_LOCK state: Bas DIR allocation");
+
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)
+                {
+                    size_t wok_index = 0;
+                    bool   wok       = !m_trt.full(wok_index);
+                    if (wok)
+                    {
+                        r_cas_trt_index = wok_index;
+                        r_cas_fsm = CAS_BC_IVT_LOCK;
+                    }
+                    else
+                    {
+                        r_cas_fsm = CAS_WAIT;
+                    }
+
+#if DEBUG_MEMC_CAS
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CAS_BC_TRT_LOCK> Check TRT"
+                            << " : wok = " << wok << " / index = " << wok_index << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////
+            case CAS_BC_IVT_LOCK:  // get IVT lock and register BC transaction in IVT
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
+                        "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas DIR allocation");
+
+                assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
+                        "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas TRT allocation");
+
+                if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS)
+                {
+                    // register broadcast inval transaction in IVT
+                    bool   wok       = false;
+                    size_t index     = 0;
+                    size_t srcid     = m_cmd_cas_srcid_fifo.read();
+                    size_t trdid     = m_cmd_cas_trdid_fifo.read();
+                    size_t pktid     = m_cmd_cas_pktid_fifo.read();
+                    addr_t nline     = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
+                    size_t nb_copies = r_cas_count.read();
+
+                    // register a broadcast inval transaction in IVT
+                    wok = m_ivt.set(false, // it's an inval transaction
+                                    true,  // it's a broadcast
+                                    true,  // response required
+                                    false, // no acknowledge required
+                                    srcid,
+                                    trdid,
+                                    pktid,
+                                    nline,
+                                    nb_copies,
+                                    index);
+
+                    if (wok) // IVT not full
+                    {
+                        // cache update
+                        size_t way  = r_cas_way.read();
+                        size_t set  = m_y[(addr_t) (m_cmd_cas_addr_fifo.read())];
+                        size_t word = m_x[(addr_t) (m_cmd_cas_addr_fifo.read())];
+
+                        m_cache_data.write(way, set, word, r_cas_wdata.read());
+                        if (r_cas_cpt.read() == 4)
                         {
-                            std::cout << "  <MEMC " << name() << " CAS_IDLE> CAS command: " << std::hex
-                                << " srcid = " <<  std::dec << m_cmd_cas_srcid_fifo.read()
-                                << " addr = " << std::hex << m_cmd_cas_addr_fifo.read()
-                                << " wdata = " << m_cmd_cas_wdata_fifo.read()
-                                << " eop = " << std::dec << m_cmd_cas_eop_fifo.read()
-                                << " cpt  = " << std::dec << r_cas_cpt.read() << std::endl;
+                            m_cache_data.write(way, set, word + 1, m_cmd_cas_wdata_fifo.read());
                         }
-#endif
-                        if(m_cmd_cas_eop_fifo.read())
-                        {
-                            r_cas_fsm = CAS_DIR_REQ;
-                        }
-                        else  // we keep the last word in the FIFO
-                        {
-                            cmd_cas_fifo_get = true;
-                        }
-                        // We fill the two buffers
-                        if(r_cas_cpt.read() < 2)    // 32 bits access
-                            r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read();
-
-                        if((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read())
-                            r_cas_wdata = m_cmd_cas_wdata_fifo.read();
-
-                        assert( (r_cas_cpt.read() <= 3) and  // no more than 4 flits...
-                                "MEMC ERROR in CAS_IDLE state: illegal CAS command");
-
-                        if(r_cas_cpt.read() ==2)
-                            r_cas_wdata = m_cmd_cas_wdata_fifo.read();
-
-                        r_cas_cpt = r_cas_cpt.read() +1;
-                    }
-                    break;
-                }
-
-                /////////////////
-            case CAS_DIR_REQ:
-                {
-                    if(r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)
-                    {
-                        r_cas_fsm = CAS_DIR_LOCK;
-                    }
+
+                        r_cas_upt_index = index;
+                        r_cas_fsm = CAS_BC_DIR_INVAL;
 
 #if DEBUG_MEMC_CAS
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC " << name() << " CAS_DIR_REQ> Requesting DIR lock "
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-                /////////////////
-            case CAS_DIR_LOCK:  // Read the directory
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
-                            "MEMC ERROR in CAS_DIR_LOCK: Bad DIR allocation");
-
-                    size_t way = 0;
-                    DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way));
-
-                    r_cas_is_cnt     = entry.is_cnt;
-                    r_cas_coherent   = entry.cache_coherent;
-                    r_cas_dirty      = entry.dirty;
-                    r_cas_tag        = entry.tag;
-                    r_cas_way        = way;
-                    r_cas_copy       = entry.owner.srcid;
-                    r_cas_copy_inst  = entry.owner.inst;
-                    r_cas_ptr        = entry.ptr;
-                    r_cas_count      = entry.count;
-
-                    if(entry.valid)  r_cas_fsm = CAS_DIR_HIT_READ;
-                    else             r_cas_fsm = CAS_MISS_TRT_LOCK;
-
-#if DEBUG_MEMC_CAS
-                    if(m_debug)
-                    {
-                        std::cout << "  <MEMC " << name() << " CAS_DIR_LOCK> Directory acces"
-                            << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
-                            << " / hit = " << std::dec << entry.valid
-                            << " / count = " << entry.count
-                            << " / is_cnt = " << entry.is_cnt << std::endl;
-                    }
-#endif
-                    break;
-                }
-                /////////////////////
-            case CAS_DIR_HIT_READ:  // update directory for lock and dirty bit
-                // and check data change in cache
-                {
-                    size_t way  = r_cas_way.read();
-                    size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
-
-                    // update directory (lock & dirty bits)
-                    DirectoryEntry entry;
-                    entry.valid          = true;
-                    entry.cache_coherent = r_cas_coherent.read();
-                    entry.is_cnt         = r_cas_is_cnt.read();
-                    entry.dirty          = true;
-                    entry.lock           = true;
-                    entry.tag            = r_cas_tag.read();
-                    entry.owner.srcid    = r_cas_copy.read();
-                    entry.owner.inst     = r_cas_copy_inst.read();
-                    entry.count          = r_cas_count.read();
-                    entry.ptr            = r_cas_ptr.read();
-
-                    m_cache_directory.write(set, way, entry);
-
-                    // Stored data from cache in buffer to do the comparison in next state
-                    m_cache_data.read_line(way, set, r_cas_data);
-
-                    r_cas_fsm = CAS_DIR_HIT_COMPARE;
-
-#if DEBUG_MEMC_CAS
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from "
-                            << " cache and store it in buffer" << std::endl;
-#endif
-                    break;
-                }
-
-            case CAS_DIR_HIT_COMPARE:
-                {
-                    size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
-
-                    // Read data in buffer & check data change
-                    bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read());
-
-                    if(r_cas_cpt.read() == 4)     // 64 bits CAS
-                        ok &= (r_cas_rdata[1] == r_cas_data[word+1]);
-
-                    // to avoid livelock, force the atomic access to fail pseudo-randomly
-                    bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS);
-                    r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001);
-
-                    // cas success
-                    if(ok and not forced_fail)
-                    {
-                        r_cas_fsm = CAS_DIR_HIT_WRITE;
-                    }
-                    // cas failure
-                    else
-                    {
-                        r_cas_fsm = CAS_RSP_FAIL;
-                    }
-
-#if DEBUG_MEMC_CAS
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old"
-                            << " and the new data"
-                            << " / expected value = " << r_cas_rdata[0].read()
-                            << " / actual value = "   << r_cas_data[word].read()
-                            << " / forced_fail = "    << forced_fail << std::endl;
-#endif
-                    break;
-                }
-                //////////////////////
-            case CAS_DIR_HIT_WRITE:    // test if a CC transaction is required
-                // write data in cache if no CC request
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
-                            "MEMC ERROR in CAS_DIR_HIT_WRITE: Bad DIR allocation");
-
-                    // The CAS is a success => sw access to the llsc_global_table
-                    m_llsc_table.sw(m_cmd_cas_addr_fifo.read(), m_cmd_cas_addr_fifo.read());
-                    // test coherence request
-                    if(r_cas_count.read())   // replicated line
-                    {
-                        if(r_cas_is_cnt.read())
-                        {
-                            r_cas_fsm = CAS_BC_TRT_LOCK;    // broadcast invalidate required
-#if DEBUG_MEMC_CAS
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
-                                    << " Broacast Inval required"
-                                    << " / copies = " << r_cas_count.read() << std::endl;
-#endif
-
-                        }
-                        else if(!r_cas_to_cc_send_multi_req.read() and
-                                !r_cas_to_cc_send_brdcast_req.read())
-                        {
-                            r_cas_fsm = CAS_UPT_LOCK;       // multi update required
-#if DEBUG_MEMC_CAS
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
-                                    << " Multi Inval required"
-                                    << " / copies = " << r_cas_count.read() << std::endl;
-#endif
-                        }
-                        else
-                        {
-                            r_cas_fsm = CAS_WAIT;
-#if DEBUG_MEMC_CAS
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
-                                    << " CC_SEND FSM busy: release all locks and retry" << std::endl;
-#endif
-                        }
-                    }
-                    else                    // no copies
-                    {
-                        size_t way  = r_cas_way.read();
-                        size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                        size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
-
-                        // cache update
-                        m_cache_data.write(way, set, word, r_cas_wdata.read());
-                        if(r_cas_cpt.read() == 4)
-                            m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
-
-                        r_cas_fsm = CAS_RSP_SUCCESS;
-
-#if DEBUG_MEMC_CAS
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:"
-                                << " way = " << std::dec << way
-                                << " / set = " << set
-                                << " / word = " << word
-                                << " / value = " << r_cas_wdata.read()
-                                << " / count = " << r_cas_count.read()
-                                << " / global_llsc_table access" << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////////
-            case CAS_UPT_LOCK:  // try to register the transaction in UPT
-                // and write data in cache if successful registration
-                // releases locks to retry later if UPT full
-                {
-                    if(r_alloc_upt_fsm.read() == ALLOC_UPT_CAS)
-                    {
-                        bool        wok        = false;
-                        size_t      index      = 0;
-                        size_t      srcid      = m_cmd_cas_srcid_fifo.read();
-                        size_t      trdid      = m_cmd_cas_trdid_fifo.read();
-                        size_t      pktid      = m_cmd_cas_pktid_fifo.read();
-                        addr_t      nline      = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                        size_t      nb_copies  = r_cas_count.read();
-
-                        wok = m_upt.set(true,    // it's an update transaction
-                                false,   // it's not a broadcast
-                                true,    // response required
-                                false,   // no acknowledge required
-                                srcid,
-                                trdid,
-                                pktid,
-                                nline,
-                                nb_copies,
-                                index);
-                        if(wok)   // coherence transaction registered in UPT
-                        {
-                            // cache update
-                            size_t way  = r_cas_way.read();
-                            size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                            size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
-
-                            m_cache_data.write(way, set, word, r_cas_wdata.read());
-                            if(r_cas_cpt.read() ==4)
-                                m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
-
-                            r_cas_upt_index = index;
-                            r_cas_fsm = CAS_UPT_HEAP_LOCK;
-
-                        }
-                        else       //  releases the locks protecting UPT and DIR UPT full
-                        {
-                            r_cas_fsm = CAS_WAIT;
-                        }
-
-#if DEBUG_MEMC_CAS
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " CAS_UPT_LOCK> Register multi-update transaction in UPT"
-                                << " / wok = " << wok
-                                << " / nline  = " << std::hex << nline
-                                << " / count = " << nb_copies << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////
-            case CAS_WAIT:   // release all locks and retry from beginning
-                {
-
-#if DEBUG_MEMC_CAS
-                    if(m_debug)
-                    {
-                        std::cout << "  <MEMC " << name()
-                            << " CAS_WAIT> Release all locks" << std::endl;
-                    }
-#endif
-                    r_cas_fsm = CAS_DIR_REQ;
-                    break;
-                }
-                //////////////////
-            case CAS_UPT_HEAP_LOCK:  // lock the heap
-                {
-                    if(r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)
-                    {
-
-#if DEBUG_MEMC_CAS
-                        if(m_debug)
+                        if (m_debug)
                         {
                             std::cout << "  <MEMC " << name()
-                                << " CAS_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
+                                << " CAS_BC_IVT_LOCK> Register a broadcast inval transaction in IVT"
+                                << " / nline = " << std::hex << nline
+                                << " / count = " << std::dec << nb_copies
+                                << " / ivt_index = " << index << std::endl;
                         }
 #endif
-                        r_cas_fsm = CAS_UPT_REQ;
-                    }
-                    break;
-                }
-                ////////////////
-            case CAS_UPT_REQ:  // send a first update request to CC_SEND FSM
-                {
-                    assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and
-                            "VCI_MEM_CACHE ERROR : bad HEAP allocation");
-
-                    if(!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read())
-                    {
-                        r_cas_to_cc_send_brdcast_req  = false;
-                        r_cas_to_cc_send_trdid        = r_cas_upt_index.read();
-                        r_cas_to_cc_send_nline        = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                        r_cas_to_cc_send_index        = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                        r_cas_to_cc_send_wdata        = r_cas_wdata.read();
-
-                        if(r_cas_cpt.read() == 4)
-                        {
-                            r_cas_to_cc_send_is_long    = true;
-                            r_cas_to_cc_send_wdata_high = m_cmd_cas_wdata_fifo.read();
-                        }
-                        else
-                        {
-                            r_cas_to_cc_send_is_long    = false;
-                            r_cas_to_cc_send_wdata_high = 0;
-                        }
-
-                        // We put the first copy in the fifo
-                        cas_to_cc_send_fifo_put     = true;
-                        cas_to_cc_send_fifo_inst    = r_cas_copy_inst.read();
-                        cas_to_cc_send_fifo_srcid   = r_cas_copy.read();
-                        if(r_cas_count.read() == 1)  // one single copy
-                        {
-                            r_cas_fsm = CAS_IDLE;   // Response will be sent after receiving
-                            // update responses
-                            cmd_cas_fifo_get            = true;
-                            r_cas_to_cc_send_multi_req = true;
-                            r_cas_cpt = 0;
-                        }
-                        else      // several copies
-                        {
-                            r_cas_fsm = CAS_UPT_NEXT;
-                        }
+                    }
+                    else      //  releases the lock protecting IVT
+                    {
+                        r_cas_fsm = CAS_WAIT;
+                    }
+                }
+                break;
+            }
+            //////////////////////
+            case CAS_BC_DIR_INVAL:  // Register PUT transaction in TRT,
+                                    // and inval the DIR entry
+            {
+                assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
+                        "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation");
+
+                assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
+                        "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation");
+
+                assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and
+                        "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation");
+
+                // set TRT
+                std::vector<data_t> data_vector;
+                data_vector.clear();
+                size_t word = m_x[(addr_t) (m_cmd_cas_addr_fifo.read())];
+                for (size_t i = 0; i < m_words; i++)
+                {
+                    if (i == word)
+                    {
+                        // first modified word
+                        data_vector.push_back(r_cas_wdata.read());
+                    }
+                    else if ((i == word + 1) and (r_cas_cpt.read() == 4))
+                    {
+                        // second modified word
+                        data_vector.push_back(m_cmd_cas_wdata_fifo.read());
+                    }
+                    else
+                    {
+                        // unmodified words
+                        data_vector.push_back(r_cas_data[i].read());
+                    }
+                }
+                m_trt.set(r_cas_trt_index.read(),
+                          false, // PUT request
+                          m_nline[(addr_t) (m_cmd_cas_addr_fifo.read())],
+                          0,
+                          0,
+                          0,
+                          false, // not a processor read
+                          0,
+                          0,
+                          std::vector<be_t> (m_words, 0),
+                          data_vector);
+
+                // invalidate directory entry
+                DirectoryEntry entry;
+                entry.valid       = false;
+                entry.dirty       = false;
+                entry.tag         = 0;
+                entry.is_cnt      = false;
+                entry.lock        = false;
+                entry.count       = 0;
+                entry.owner.srcid = 0;
+                entry.owner.inst  = false;
+                entry.ptr         = 0;
+                size_t set        = m_y[(addr_t) (m_cmd_cas_addr_fifo.read())];
+                size_t way        = r_cas_way.read();
+
+                m_cache_directory.write(set, way, entry);
+
+                r_cas_fsm = CAS_BC_CC_SEND;
 
 #if DEBUG_MEMC_CAS
-                        if(m_debug)
-                        {
-                            std::cout << "  <MEMC " << name() << " CAS_UPT_REQ> Send the first update request to CC_SEND FSM "
-                                << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
-                                << " / wdata = " << std::hex << r_cas_wdata.read()
-                                << " / srcid = " << std::dec << r_cas_copy.read()
-                                << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl;
-                        }
-#endif
-                    }
-                    break;
-                }
-                /////////////////
-            case CAS_UPT_NEXT:     // send a multi-update request to CC_SEND FSM
-                {
-                    assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)
-                            and "VCI_MEM_CACHE ERROR : bad HEAP allocation");
-
-                    HeapEntry entry = m_heap.read(r_cas_ptr.read());
-                    cas_to_cc_send_fifo_srcid    = entry.owner.srcid;
-                    cas_to_cc_send_fifo_inst     = entry.owner.inst;
-                    cas_to_cc_send_fifo_put = true;
-
-                    if(m_cas_to_cc_send_inst_fifo.wok())   // request accepted by CC_SEND FSM
-                    {
-                        r_cas_ptr = entry.next;
-                        if(entry.next == r_cas_ptr.read())    // last copy
-                        {
-                            r_cas_to_cc_send_multi_req = true;
-                            r_cas_fsm = CAS_IDLE;   // Response will be sent after receiving
-                            // all update responses
-                            cmd_cas_fifo_get = true;
-                            r_cas_cpt        = 0;
-                        }
-                    }
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CAS_BC_DIR_INVAL> Inval DIR & register in TRT:"
+                        << " address = " << m_cmd_cas_addr_fifo.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////
+            case CAS_BC_CC_SEND:  // Request the broadcast inval to CC_SEND FSM
+            {
+                if (not r_cas_to_cc_send_multi_req.read() and
+                        not r_cas_to_cc_send_brdcast_req.read())
+                {
+                    r_cas_to_cc_send_multi_req   = false;
+                    r_cas_to_cc_send_brdcast_req = true;
+                    r_cas_to_cc_send_trdid       = r_cas_upt_index.read();
+                    r_cas_to_cc_send_nline       = m_nline[(addr_t) (m_cmd_cas_addr_fifo.read())];
+                    r_cas_to_cc_send_index       = 0;
+                    r_cas_to_cc_send_wdata       = 0;
+
+                    r_cas_fsm = CAS_BC_XRAM_REQ;
 
 #if DEBUG_MEMC_CAS
-                    if(m_debug)
-                    {
-                        std::cout << "  <MEMC " << name() << " CAS_UPT_NEXT> Send the next update request to CC_SEND FSM "
-                            << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
-                            << " / wdata = " << std::hex << r_cas_wdata.read()
-                            << " / srcid = " << std::dec << entry.owner.srcid
-                            << " / inst = " << std::dec << entry.owner.inst << std::endl;
-                    }
-#endif
-                    break;
-                }
-                /////////////////////
-            case CAS_BC_TRT_LOCK:      // check the TRT to register a PUT transaction
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
-                            "MEMC ERROR in CAS_BC_TRT_LOCK state: Bas DIR allocation");
-
-                    if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)
-                    {
-                        size_t wok_index = 0;
-                        bool   wok       = !m_trt.full(wok_index);
-                        if( wok )
-                        {
-                            r_cas_trt_index = wok_index;
-                            r_cas_fsm       = CAS_BC_IVT_LOCK;
-                        }
-                        else
-                        {
-                            r_cas_fsm       = CAS_WAIT;
-                        }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " CAS_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ////////////////////
+            case CAS_BC_XRAM_REQ: // request the IXR FSM to start a PUT transaction
+            {
+                if (not r_cas_to_ixr_cmd_req.read())
+                {
+                    r_cas_to_ixr_cmd_req   = true;
+                    r_cas_to_ixr_cmd_index = r_cas_trt_index.read();
+                    r_cas_fsm              = CAS_IDLE;
+                    cmd_cas_fifo_get       = true;
+                    r_cas_cpt              = 0;
 
 #if DEBUG_MEMC_CAS
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CAS_BC_TRT_LOCK> Check TRT"
-                                << " : wok = " << wok << " / index = " << wok_index << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////////////
-            case CAS_BC_IVT_LOCK:  // register a broadcast inval transaction in IVT
-                // write data in cache in case of successful registration
-                {
-                    if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS)
-                    {
-                        bool        wok       = false;
-                        size_t      index     = 0;
-                        size_t      srcid     = m_cmd_cas_srcid_fifo.read();
-                        size_t      trdid     = m_cmd_cas_trdid_fifo.read();
-                        size_t      pktid     = m_cmd_cas_pktid_fifo.read();
-                        addr_t      nline     = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                        size_t      nb_copies = r_cas_count.read();
-
-                        // register a broadcast inval transaction in IVT
-                        wok = m_ivt.set(false,  // it's an inval transaction
-                                true,   // it's a broadcast
-                                true,   // response required
-                                false,  // no acknowledge required
-                                srcid,
-                                trdid,
-                                pktid,
-                                nline,
-                                nb_copies,
-                                index);
-
-                        if(wok)     // IVT not full
-                        {
-                            // cache update
-                            size_t way  = r_cas_way.read();
-                            size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                            size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
-
-                            m_cache_data.write(way, set, word, r_cas_wdata.read());
-                            if(r_cas_cpt.read() ==4)
-                                m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
-
-                            r_cas_upt_index = index;
-                            r_cas_fsm = CAS_BC_DIR_INVAL;
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
+                            << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read()
+                            << " / trt_index = " << r_cas_trt_index.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////
+            case CAS_RSP_FAIL:  // request TGT_RSP FSM to send a failure response
+            {
+                if (not r_cas_to_tgt_rsp_req.read())
+                {
+                    cmd_cas_fifo_get       = true;
+                    r_cas_cpt              = 0;
+                    r_cas_to_tgt_rsp_req   = true;
+                    r_cas_to_tgt_rsp_data  = 1;
+                    r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read();
+                    r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read();
+                    r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read();
+                    r_cas_fsm              = CAS_IDLE;
 
 #if DEBUG_MEMC_CAS
-                            if(m_debug)
-                                std::cout << "  <MEMC " << name()
-                                    << " CAS_BC_IVT_LOCK> Register a broadcast inval transaction in IVT"
-                                    << " / nline = " << std::hex << nline
-                                    << " / count = " << std::dec << nb_copies
-                                    << " / ivt_index = " << index << std::endl;
-#endif
-                        }
-                        else      //  releases the lock protecting IVT
-                        {
-                            r_cas_fsm = CAS_WAIT;
-                        }
-                    }
-                    break;
-                }
-                //////////////////////
-            case CAS_BC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
-                {
-                    assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
-                            "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation");
-
-                    assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
-                            "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation");
-
-                    assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and
-                            "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation");
-
-                    std::vector<data_t> data_vector;
-                    data_vector.clear();
-                    size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                    for(size_t i=0; i<m_words; i++)
-                    {
-                        if(i == word)                                        // first modified word
-                            data_vector.push_back( r_cas_wdata.read() );
-                        else if((i == word+1) and (r_cas_cpt.read() == 4))   // second modified word
-                            data_vector.push_back( m_cmd_cas_wdata_fifo.read() );
-                        else                                                 // unmodified words
-                            data_vector.push_back( r_cas_data[i].read() );
-                    }
-                    m_trt.set( r_cas_trt_index.read(),
-                            false,    // PUT request
-                            m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())],
-                            0,
-                            0,
-                            0,
-                            false,    // not a processor read
-                            0,
-                            0,
-                            std::vector<be_t> (m_words,0),
-                            data_vector );
-
-                    // invalidate directory entry
-                    DirectoryEntry entry;
-                    entry.valid         = false;
-                    entry.dirty         = false;
-                    entry.tag           = 0;
-                    entry.is_cnt        = false;
-                    entry.lock          = false;
-                    entry.count         = 0;
-                    entry.owner.srcid   = 0;
-                    entry.owner.inst    = false;
-                    entry.ptr           = 0;
-                    size_t set          = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                    size_t way          = r_cas_way.read();
-                    m_cache_directory.write(set, way, entry);
-
-                    r_cas_fsm = CAS_BC_CC_SEND;
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ////////////////////
+            case CAS_RSP_SUCCESS:  // request TGT_RSP FSM to send a success response
+            {
+                if (not r_cas_to_tgt_rsp_req.read())
+                {
+                    cmd_cas_fifo_get       = true;
+                    r_cas_cpt              = 0;
+                    r_cas_to_tgt_rsp_req   = true;
+                    r_cas_to_tgt_rsp_data  = 0;
+                    r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read();
+                    r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read();
+                    r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read();
+                    r_cas_fsm              = CAS_IDLE;
 
 #if DEBUG_MEMC_CAS
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CAS_BC_DIR_INVAL> Inval DIR & register in TRT:"
-                            << " address = " << m_cmd_cas_addr_fifo.read() << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////
-            case CAS_BC_CC_SEND:  // Request the broadcast inval to CC_SEND FSM
-                {
-                    if( not r_cas_to_cc_send_multi_req.read() and
-                            not r_cas_to_cc_send_brdcast_req.read())
-                    {
-                        r_cas_to_cc_send_multi_req    = false;
-                        r_cas_to_cc_send_brdcast_req  = true;
-                        r_cas_to_cc_send_trdid        = r_cas_upt_index.read();
-                        r_cas_to_cc_send_nline        = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
-                        r_cas_to_cc_send_index        = 0;
-                        r_cas_to_cc_send_wdata        = 0;
-
-                        r_cas_fsm = CAS_BC_XRAM_REQ;
-                    }
-                    break;
-                }
-                ////////////////////
-            case CAS_BC_XRAM_REQ: // request the IXR FSM to start a put transaction
-                {
-                    if( not r_cas_to_ixr_cmd_req.read() )
-                    {
-                        r_cas_to_ixr_cmd_req     = true;
-                        r_cas_to_ixr_cmd_index   = r_cas_trt_index.read();
-                        r_cas_fsm                = CAS_IDLE;
-                        cmd_cas_fifo_get         = true;
-                        r_cas_cpt                = 0;
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name()
+                            << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            ///////////////////////
+            case CAS_MISS_TRT_LOCK: // cache miss : request access to transaction Table
+            {
+                if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)
+                {
+                    size_t index = 0;
+                    bool hit_read = m_trt.hit_read(
+                            m_nline[(addr_t) m_cmd_cas_addr_fifo.read()], index);
+                    bool hit_write = m_trt.hit_write(
+                            m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]);
+                    bool wok = not m_trt.full(index);
 
 #if DEBUG_MEMC_CAS
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
-                                << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read()
-                                << " / trt_index = " << r_cas_trt_index.read() << std::endl;
-#endif
-                    }
-
-                    break;
-                }
-                /////////////////
-            case CAS_RSP_FAIL:  // request TGT_RSP FSM to send a failure response
-                {
-                    if( not r_cas_to_tgt_rsp_req.read() )
-                    {
-                        cmd_cas_fifo_get       = true;
-                        r_cas_cpt              = 0;
-                        r_cas_to_tgt_rsp_req   = true;
-                        r_cas_to_tgt_rsp_data  = 1;
-                        r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read();
-                        r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read();
-                        r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read();
-                        r_cas_fsm              = CAS_IDLE;
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_LOCK> Check TRT state"
+                            << " / hit_read = "  << hit_read
+                            << " / hit_write = " << hit_write
+                            << " / wok = " << wok
+                            << " / index = " << index << std::endl;
+                    }
+#endif
+
+                    if (hit_read or !wok or hit_write)    // missing line already requested or TRT full
+                    {
+                        r_cas_fsm = CAS_WAIT;
+                    }
+                    else
+                    {
+                        r_cas_trt_index = index;
+                        r_cas_fsm       = CAS_MISS_TRT_SET;
+                    }
+                }
+                break;
+            }
+            //////////////////////
+            case CAS_MISS_TRT_SET: // register the GET transaction in TRT
+            {
+                assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
+                        "MEMC ERROR in CAS_MISS_TRT_SET state: Bad TRT allocation");
+
+                std::vector<be_t> be_vector;
+                std::vector<data_t> data_vector;
+                be_vector.clear();
+                data_vector.clear();
+                for (size_t i = 0; i < m_words; i++)
+                {
+                    be_vector.push_back(0);
+                    data_vector.push_back(0);
+                }
+
+                m_trt.set(r_cas_trt_index.read(),
+                        true,     // GET
+                        m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],
+                        m_cmd_cas_srcid_fifo.read(),
+                        m_cmd_cas_trdid_fifo.read(),
+                        m_cmd_cas_pktid_fifo.read(),
+                        false,    // write request from processor
+                        0,
+                        0,
+                        be_vector,
+                        data_vector);
+
+                r_cas_fsm = CAS_MISS_XRAM_REQ;
 
 #if DEBUG_MEMC_CAS
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
-#endif
-                    }
-                    break;
-                }
-                ////////////////////
-            case CAS_RSP_SUCCESS:  // request TGT_RSP FSM to send a success response
-                {
-                    if( not r_cas_to_tgt_rsp_req.read() )
-                    {
-                        cmd_cas_fifo_get       = true;
-                        r_cas_cpt              = 0;
-                        r_cas_to_tgt_rsp_req = true;
-                        r_cas_to_tgt_rsp_data  = 0;
-                        r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read();
-                        r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read();
-                        r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read();
-                        r_cas_fsm              = CAS_IDLE;
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_SET> Register GET transaction in TRT"
+                        << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read()
+                        << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////
+            case CAS_MISS_XRAM_REQ:  // request the IXR_CMD FSM a GET request
+            {
+                if (not r_cas_to_ixr_cmd_req.read())
+                {
+                    r_cas_to_ixr_cmd_req   = true;
+                    r_cas_to_ixr_cmd_index = r_cas_trt_index.read();
+                    r_cas_fsm              = CAS_WAIT;
 
 #if DEBUG_MEMC_CAS
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name()
-                                << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
-#endif
-                    }
-                    break;
-                }
-                /////////////////////
-            case CAS_MISS_TRT_LOCK:         // cache miss : request access to transaction Table
-                {
-                    if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)
-                    {
-                        size_t   index = 0;
-                        bool hit_read = m_trt.hit_read(
-                                m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],index);
-                        bool hit_write = m_trt.hit_write(
-                                m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]);
-                        bool wok = not m_trt.full(index);
-
-#if DEBUG_MEMC_CAS
-                        if(m_debug)
-                        {
-                            std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_LOCK> Check TRT state"
-                                << " / hit_read = "  << hit_read
-                                << " / hit_write = " << hit_write
-                                << " / wok = " << wok
-                                << " / index = " << index << std::endl;
-                        }
-#endif
-
-                        if(hit_read or !wok or hit_write)    // missing line already requested or no space in TRT
-                        {
-                            r_cas_fsm = CAS_WAIT;
-                        }
-                        else
-                        {
-                            r_cas_trt_index = index;
-                            r_cas_fsm       = CAS_MISS_TRT_SET;
-                        }
-                    }
-                    break;
-                }
-                ////////////////////
-            case CAS_MISS_TRT_SET: // register the GET transaction in TRT
-                {
-                    assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
-                            "MEMC ERROR in CAS_MISS_TRT_SET state: Bad TRT allocation");
-
-                    std::vector<be_t> be_vector;
-                    std::vector<data_t> data_vector;
-                    be_vector.clear();
-                    data_vector.clear();
-                    for(size_t i=0; i<m_words; i++)
-                    {
-                        be_vector.push_back(0);
-                        data_vector.push_back(0);
-                    }
-
-                    m_trt.set(r_cas_trt_index.read(),
-                            true,   // read request
-                            m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],
-                            m_cmd_cas_srcid_fifo.read(),
-                            m_cmd_cas_trdid_fifo.read(),
-                            m_cmd_cas_pktid_fifo.read(),
-                            false,    // write request from processor
-                            0,
-                            0,
-                            be_vector,
-                            data_vector);
-                    r_cas_fsm = CAS_MISS_XRAM_REQ;
-
-#if DEBUG_MEMC_CAS
-                    if(m_debug)
-                    {
-                        std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
-                            << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
-                            << " / trt_index = " << r_cas_trt_index.read() << std::endl;
-                    }
-#endif
-                    break;
-                }
-                //////////////////////
-            case CAS_MISS_XRAM_REQ:  // request the IXR_CMD FSM to fetch the missing line
-                {
-                    if( not r_cas_to_ixr_cmd_req.read() )
-                    {
-                        r_cas_to_ixr_cmd_req        = true;
-                        r_cas_to_ixr_cmd_index      = r_cas_trt_index.read();
-                        r_cas_fsm                   = CAS_WAIT;
-
-#if DEBUG_MEMC_CAS
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction"
-                                << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read()
-                                << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl;
-#endif
-                    }
-                    break;
-                }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction"
+                            << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read()
+                            << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
         } // end switch r_cas_fsm
 
@@ -7381 +7483 @@
         ///////////////////////////////////////////////////////////////////////////////
 
-        switch(r_cc_send_fsm.read())
+        switch (r_cc_send_fsm.read())
         {
             /////////////////////////
             case CC_SEND_CONFIG_IDLE:    // XRAM_RSP FSM has highest priority
-                {
-                    // XRAM_RSP
-                    if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
-                            r_xram_rsp_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_xram_rsp_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
-                        break;
-                    }
-                    // CAS
-                    if(m_cas_to_cc_send_inst_fifo.rok() or
-                            r_cas_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
-                        break;
-                    }
-                    if(r_cas_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
-                        break;
-                    }
-
-                    // READ
-                    if(r_read_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
-                        break;
-                    }
-
-                    // WRITE
-                    if(r_write_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
-                        break;
-                    }
-
-                    if(m_write_to_cc_send_inst_fifo.rok() or
-                            r_write_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
-                        break;
-                    }
-                    if(r_write_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
-                        break;
-                    }
-                    // CONFIG
-                    if(r_config_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_config_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
-                        break;
-                    }
+            {
+                // XRAM_RSP
+                if (m_xram_rsp_to_cc_send_inst_fifo.rok() or
+                        r_xram_rsp_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
                     break;
                 }
-                ////////////////////////
-            case CC_SEND_WRITE_IDLE:     // CONFIG FSM has highest priority
-                {
-                    // CONFIG
-                    if(r_config_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_config_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
-                        break;
-                    }
-                    // XRAM_RSP
-                    if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
-                            r_xram_rsp_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_xram_rsp_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
-                        break;
-                    }
-                    // CAS
-                    if(m_cas_to_cc_send_inst_fifo.rok() or
-                            r_cas_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
-                        break;
-                    }
-                    if(r_cas_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
-                        break;
-                    }
-                    // READ
-                    if(r_read_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
-                        break;
-                    }
-                    // WRITE
-                    if(r_write_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
-                        break;
-                    }
-                    if(m_write_to_cc_send_inst_fifo.rok() or
-                            r_write_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
-                        break;
-                    }
-                    if(r_write_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
-                        break;
-                    }
+                if (r_xram_rsp_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
                     break;
                 }
-                ///////////////////////////
-            case CC_SEND_READ_IDLE:
-                {
-                    // WRITE
-                    if(r_write_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
-                        break;
-                    }
-                    if(m_write_to_cc_send_inst_fifo.rok() or
-                            r_write_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
-                        break;
-                    }
-                    if(r_write_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
-                        break;
-                    }
-                    // CONFIG
-                    if(r_config_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_config_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
-                        break;
-                    }
-                    // XRAM_RSP
-                    if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
-                            r_xram_rsp_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_xram_rsp_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
-                        break;
-                    }
-                    // CAS
-                    if(m_cas_to_cc_send_inst_fifo.rok() or
-                            r_cas_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
-                        break;
-                    }
-                    if(r_cas_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
-                        break;
-                    }
-                    // READ
-                    if(r_read_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
-                        break;
-                    }
-                    break;
-
-                }
-                ///////////////////////////
-            case CC_SEND_XRAM_RSP_IDLE:   // CAS FSM has highest priority
-                {
-                    // CAS
-                    if(m_cas_to_cc_send_inst_fifo.rok() or
-                            r_cas_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
-                        break;
-                    }
-                    if(r_cas_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
-                        break;
-                    }
-
-                    // READ
-                    if(r_read_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
-                        break;
-                    }
-
-                    // WRITE
-                    if(r_write_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
-                        break;
-                    }
-                    if(m_write_to_cc_send_inst_fifo.rok() or
-                            r_write_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
-                        break;
-                    }
-
-                    if(r_write_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
-                        break;
-                    }
-                    // CONFIG
-                    if(r_config_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_config_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
-                        break;
-                    }
-                    // XRAM_RSP
-                    if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
-                            r_xram_rsp_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_xram_rsp_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
-                        break;
-                    }
-                    break;
-                }
-                //////////////////////
-            case CC_SEND_CAS_IDLE:   // READ FSM has highest priority
-                {
-
-                    // READ
-                    if(r_read_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
-                        break;
-                    }
-                    // WRITE
-                    if(r_write_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
-                        break;
-                    }
-
-                    if(m_write_to_cc_send_inst_fifo.rok() or
-                            r_write_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
-                        break;
-                    }
-                    if(r_write_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
-                        break;
-                    }
-                    // CONFIG
-                    if(r_config_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_config_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
-                        break;
-                    }
-                    // XRAM RSP
-                    if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
-                            r_xram_rsp_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
-                        break;
-                    }
-                    if(r_xram_rsp_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
-                        break;
-                    }
-                    // CAS
-                    if(m_cas_to_cc_send_inst_fifo.rok() or
-                            r_cas_to_cc_send_multi_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
-                        break;
-                    }
-                    if(r_cas_to_cc_send_brdcast_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
-                        break;
-                    }
-                    break;
-                }
-                /////////////////////////////////
-            case CC_SEND_CONFIG_INVAL_HEADER:   // send first flit multi-inval (from CONFIG FSM)
-                {
-                    if(m_config_to_cc_send_inst_fifo.rok())
-                    {
-                        if(not p_dspin_m2p.read) break;
-
-                        // <Activity Counters>
-                        if (is_local_req(m_config_to_cc_send_srcid_fifo.read()))
-                        {
-                            m_cpt_minval_local++;
-                        }
-                        else
-                        {
-                            m_cpt_minval_remote++;
-                        }
-                        // 2 flits for multi inval
-                        m_cpt_minval_cost += 2 * req_distance(m_config_to_cc_send_srcid_fifo.read());
-                        // </Activity Counters>
-                        r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE;
-                        break;
-                    }
-                    if(r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false;
-                    // <Activity Counters>
-                    m_cpt_minval++;
-                    // </Activity Counters>
-                    r_cc_send_fsm = CC_SEND_CONFIG_IDLE;
-                    break;
-                }
-                ////////////////////////////////
-            case CC_SEND_CONFIG_INVAL_NLINE:    // send second flit multi-inval (from CONFIG FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    config_to_cc_send_fifo_get = true;
-                    r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " CC_SEND_CONFIG_INVAL_NLINE> multi-inval for line "
-                            << std::hex << r_config_to_cc_send_nline.read() << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////////////////
-            case CC_SEND_CONFIG_BRDCAST_HEADER:   // send first flit BC-inval (from CONFIG FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE;
-                    break;
-                }
-                //////////////////////////////////
-            case CC_SEND_CONFIG_BRDCAST_NLINE:    // send second flit BC-inval (from CONFIG FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    // <Activity Counters>
-                    m_cpt_binval++;
-                    // </Activity Counters>
-                    r_config_to_cc_send_brdcast_req = false;
-                    r_cc_send_fsm = CC_SEND_CONFIG_IDLE;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " CC_SEND_CONFIG_BRDCAST_NLINE> BC-Inval for line "
-                            << std::hex << r_config_to_cc_send_nline.read() << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////////////////
-            case CC_SEND_XRAM_RSP_INVAL_HEADER:   // send first flit multi-inval (from XRAM_RSP FSM)
-                {
-                    if(m_xram_rsp_to_cc_send_inst_fifo.rok())
-                    {
-                        if(not p_dspin_m2p.read) break;
-                        // <Activity Counters>
-                        if (is_local_req(m_xram_rsp_to_cc_send_srcid_fifo.read()))
-                        {
-                            m_cpt_minval_local++;
-                        }
-                        else
-                        {
-                            m_cpt_minval_remote++;
-                        }
-                        // 2 flits for multi inval
-                        m_cpt_minval_cost += 2 * req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read());
-                        // </Activity Counters>
-                        r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE;
-                        break;
-                    }
-                    if(r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false;
-                    // <Activity Counters>
-                    m_cpt_minval++;
-                    // </Activity Counters>
-                    r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE;
-                    break;
-                }
-                //////////////////////////////////
-            case CC_SEND_XRAM_RSP_INVAL_NLINE:   // send second flit multi-inval (from XRAM_RSP FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    xram_rsp_to_cc_send_fifo_get = true;
-                    r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " CC_SEND_XRAM_RSP_INVAL_NLINE> Multicast-Inval for line "
-                            << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl;
-#endif
-                    break;
-                }
-                /////////////////////////////////////
-            case CC_SEND_XRAM_RSP_BRDCAST_HEADER:  // send first flit broadcast-inval (from XRAM_RSP FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE;
-                    break;
-                }
-                ////////////////////////////////////
-            case CC_SEND_XRAM_RSP_BRDCAST_NLINE:   // send second flit broadcast-inval (from XRAM_RSP FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    // <Activity Counters>
-                    m_cpt_binval++;
-                    // </Activity Counters>
-                    r_xram_rsp_to_cc_send_brdcast_req = false;
-                    r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> BC-Inval for line "
-                            << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl;
-#endif
-                    break;
-                }
-
-            case CC_SEND_READ_NCC_INVAL_HEADER:
-                {
-                    if(not p_dspin_m2p.read) break;
-
-                    r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_NLINE;
-                    break;
-                }
-
-            case CC_SEND_READ_NCC_INVAL_NLINE:
-                {
-                    if(not p_dspin_m2p.read) break;
-
-                    r_read_to_cc_send_req = false;
-                    r_cc_send_fsm = CC_SEND_READ_IDLE;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC " << name()
-                            << " CC_SEND_READ_NCC_INVAL_HEADER> Inval for line "
-                            << std::hex <<r_read_to_cc_send_nline.read() << std::dec
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-
-            case CC_SEND_WRITE_NCC_INVAL_HEADER:
-                {
-                    if(not p_dspin_m2p.read) break;
-
-                    r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_NLINE;
-                    break;
-                }
-
-            case CC_SEND_WRITE_NCC_INVAL_NLINE:
-                {
-                    if(not p_dspin_m2p.read) break;
-
-                    r_write_to_cc_send_req = false;
-                    r_cc_send_fsm = CC_SEND_WRITE_IDLE;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                    {
-                        std::cout
-                            << "  <MEMC " << name()
-                            << " CC_SEND_WRITE_NCC_INVAL_HEADER> Inval for line "
-                            << std::hex << r_write_to_cc_send_nline.read() << std::dec
-                            << std::endl;
-                    }
-#endif
-                    break;
-                }
-
-
-                //////////////////////////////////
-            case CC_SEND_WRITE_BRDCAST_HEADER:   // send first flit broadcast-inval (from WRITE FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE;
-                    break;
-                }
-                /////////////////////////////////
-            case CC_SEND_WRITE_BRDCAST_NLINE:   // send second flit broadcast-inval (from WRITE FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-
-                    // <Activity Counters>
-                    m_cpt_binval++;
-                    // </Activity Counters>
-
-                    r_write_to_cc_send_brdcast_req = false;
-                    r_cc_send_fsm = CC_SEND_WRITE_IDLE;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " CC_SEND_WRITE_BRDCAST_NLINE> BC-Inval for line "
-                            << std::hex << r_write_to_cc_send_nline.read() << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////////////
-            case CC_SEND_WRITE_UPDT_HEADER:   // send first flit for a multi-update (from WRITE FSM)
-                {
-                    if(m_write_to_cc_send_inst_fifo.rok())
-                    {
-                        if(not p_dspin_m2p.read) break;
-                        // <Activity Counters>
-                        if (is_local_req(m_write_to_cc_send_srcid_fifo.read()))
-                        {
-                            m_cpt_update_local++;
-                        }
-                        else
-                        {
-                            m_cpt_update_remote++;
-                        }
-                        // 2 flits for multi inval
-                        m_cpt_update_cost += 2 * req_distance(m_write_to_cc_send_srcid_fifo.read());
-                        // </Activity Counters>
-
-                        r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE;
-                        break;
-                    }
-
-                    if(r_write_to_cc_send_multi_req.read())
-                    {
-                        r_write_to_cc_send_multi_req = false;
-                    }
-
-                    // <Activity Counters>
-                    m_cpt_update++;
-                    // </Activity Counters>
-                    r_cc_send_fsm = CC_SEND_WRITE_IDLE;
-                    break;
-                }
-                //////////////////////////////
-            case CC_SEND_WRITE_UPDT_NLINE:   // send second flit for a multi-update (from WRITE FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-
-                    r_cc_send_cpt = 0;
-                    r_cc_send_fsm = CC_SEND_WRITE_UPDT_DATA;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " CC_SEND_WRITE_UPDT_NLINE> Multicast-Update for line "
-                            << r_write_to_cc_send_nline.read() << std::endl;
-#endif
-                    break;
-                }
-                /////////////////////////////
-            case CC_SEND_WRITE_UPDT_DATA:   // send N data flits for a multi-update (from WRITE FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    if(r_cc_send_cpt.read() == r_write_to_cc_send_count.read())
-                    {
-                        write_to_cc_send_fifo_get = true;
-                        r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
-                        break;
-                    }
-
-                    r_cc_send_cpt = r_cc_send_cpt.read() + 1;
-                    break;
-                }
-                ////////////////////////////////
-            case CC_SEND_CAS_BRDCAST_HEADER:   // send first flit  broadcast-inval (from CAS FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE;
-                    break;
-                }
-                ///////////////////////////////
-            case CC_SEND_CAS_BRDCAST_NLINE:   // send second flit broadcast-inval (from CAS FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    // <Activity Counters>
-                    m_cpt_binval++;
-                    // </Activity Counters>
-
-                    r_cas_to_cc_send_brdcast_req = false;
-                    r_cc_send_fsm = CC_SEND_CAS_IDLE;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " CC_SEND_CAS_BRDCAST_NLINE> Broadcast-Inval for line "
-                            << r_cas_to_cc_send_nline.read() << std::endl;
-#endif
-                    break;
-                }
-                /////////////////////////////
-            case CC_SEND_CAS_UPDT_HEADER:   // send first flit for a multi-update (from CAS FSM)
-                {
-                    if(m_cas_to_cc_send_inst_fifo.rok())
-                    {
-                        if(not p_dspin_m2p.read) break;
-                        // <Activity Counters>
-                        if (is_local_req(m_cas_to_cc_send_srcid_fifo.read()))
-                        {
-                            m_cpt_update_local++;
-                        }
-                        else
-                        {
-                            m_cpt_update_remote++;
-                        }
-                        // 2 flits for multi inval
-                        m_cpt_update_cost += 2 * req_distance(m_cas_to_cc_send_srcid_fifo.read());
-                        // </Activity Counters>
-                        r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE;
-                        break;
-                    }
-
-                    // no more packets to send for the multi-update
-                    if(r_cas_to_cc_send_multi_req.read())
-                    {
-                        r_cas_to_cc_send_multi_req = false;
-                    }
-
-                    // <Activity Counters>
-                    m_cpt_update++;
-                    // </Activity Counters>
-                    r_cc_send_fsm = CC_SEND_CAS_IDLE;
-                    break;
-                }
-                ////////////////////////////
-            case CC_SEND_CAS_UPDT_NLINE:   // send second flit for a multi-update (from CAS FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    r_cc_send_cpt = 0;
-                    r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA;
-
-#if DEBUG_MEMC_CC_SEND
-                    if(m_debug)
-                        std::cout << "  <MEMC " << name()
-                            << " CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line "
-                            << r_cas_to_cc_send_nline.read() << std::endl;
-#endif
-                    break;
-                }
-                ///////////////////////////
-            case CC_SEND_CAS_UPDT_DATA:   // send first data for a multi-update (from CAS FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-
-                    if(r_cas_to_cc_send_is_long.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA_HIGH;
-                        break;
-                    }
-
-                    cas_to_cc_send_fifo_get = true;
+                // CAS
+                if (m_cas_to_cc_send_inst_fifo.rok() or
+                        r_cas_to_cc_send_multi_req.read())
+                {
                     r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
                     break;
                 }
-                ////////////////////////////////
-            case CC_SEND_CAS_UPDT_DATA_HIGH:   // send second data for a multi-update (from CAS FSM)
-                {
-                    if(not p_dspin_m2p.read) break;
-                    cas_to_cc_send_fifo_get = true;
+                if (r_cas_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
+                    break;
+                }
+
+                // READ
+                if (r_read_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+                    break;
+                }
+
+                // WRITE
+                if (r_write_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+                    break;
+                }
+
+                if (m_write_to_cc_send_inst_fifo.rok() or
+                        r_write_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
+                    break;
+                }
+                if (r_write_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
+                    break;
+                }
+                // CONFIG
+                if (r_config_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+                    break;
+                }
+                if (r_config_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+                    break;
+                }
+                break;
+            }
+            ////////////////////////
+            case CC_SEND_WRITE_IDLE:     // CONFIG FSM has highest priority
+            {
+                // CONFIG
+                if (r_config_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+                    break;
+                }
+                if (r_config_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+                    break;
+                }
+                // XRAM_RSP
+                if (m_xram_rsp_to_cc_send_inst_fifo.rok() or
+                        r_xram_rsp_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
+                    break;
+                }
+                if (r_xram_rsp_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
+                    break;
+                }
+                // CAS
+                if (m_cas_to_cc_send_inst_fifo.rok() or
+                        r_cas_to_cc_send_multi_req.read())
+                {
                     r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
                     break;
                 }
+                if (r_cas_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
+                    break;
+                }
+                // READ
+                if (r_read_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+                    break;
+                }
+                // WRITE
+                if (r_write_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+                    break;
+                }
+                if (m_write_to_cc_send_inst_fifo.rok() or
+                        r_write_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
+                    break;
+                }
+                if (r_write_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
+                    break;
+                }
+                break;
+            }
+            ///////////////////////////
+            case CC_SEND_READ_IDLE:
+            {
+                // WRITE
+                if (r_write_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+                    break;
+                }
+                if (m_write_to_cc_send_inst_fifo.rok() or
+                        r_write_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
+                    break;
+                }
+                if (r_write_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
+                    break;
+                }
+                // CONFIG
+                if (r_config_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+                    break;
+                }
+                if (r_config_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+                    break;
+                }
+                // XRAM_RSP
+                if (m_xram_rsp_to_cc_send_inst_fifo.rok() or
+                        r_xram_rsp_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
+                    break;
+                }
+                if (r_xram_rsp_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
+                    break;
+                }
+                // CAS
+                if (m_cas_to_cc_send_inst_fifo.rok() or
+                        r_cas_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
+                    break;
+                }
+                if (r_cas_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
+                    break;
+                }
+                // READ
+                if (r_read_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+                    break;
+                }
+                break;
+            }
+            ///////////////////////////
+            case CC_SEND_XRAM_RSP_IDLE:   // CAS FSM has highest priority
+            {
+                // CAS
+                if (m_cas_to_cc_send_inst_fifo.rok() or
+                        r_cas_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
+                    break;
+                }
+                if (r_cas_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
+                    break;
+                }
+                // READ
+                if (r_read_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+                    break;
+                }
+                // WRITE
+                if (r_write_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+                    break;
+                }
+                if (m_write_to_cc_send_inst_fifo.rok() or
+                        r_write_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
+                    break;
+                }
+
+                if (r_write_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
+                    break;
+                }
+                // CONFIG
+                if (r_config_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+                    break;
+                }
+                if (r_config_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+                    break;
+                }
+                // XRAM_RSP
+                if (m_xram_rsp_to_cc_send_inst_fifo.rok() or
+                        r_xram_rsp_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
+                    break;
+                }
+                if (r_xram_rsp_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
+                    break;
+                }
+                break;
+            }
+            //////////////////////
+            case CC_SEND_CAS_IDLE:   // READ FSM has highest priority
+            {
+                // READ
+                if (r_read_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_HEADER;
+                    break;
+                }
+                // WRITE
+                if (r_write_to_cc_send_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+                    break;
+                }
+
+                if (m_write_to_cc_send_inst_fifo.rok() or
+                        r_write_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
+                    break;
+                }
+                if (r_write_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
+                    break;
+                }
+                // CONFIG
+                if (r_config_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+                    break;
+                }
+                if (r_config_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+                    break;
+                }
+                // XRAM RSP
+                if (m_xram_rsp_to_cc_send_inst_fifo.rok() or
+                        r_xram_rsp_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
+                    break;
+                }
+                if (r_xram_rsp_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
+                    break;
+                }
+                // CAS
+                if (m_cas_to_cc_send_inst_fifo.rok() or
+                        r_cas_to_cc_send_multi_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
+                    break;
+                }
+                if (r_cas_to_cc_send_brdcast_req.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
+                    break;
+                }
+                break;
+            }
+            /////////////////////////////////
+            case CC_SEND_CONFIG_INVAL_HEADER:   // send first flit multi-inval (from CONFIG FSM)
+            {
+                if (m_config_to_cc_send_inst_fifo.rok())
+                {
+                    if (not p_dspin_m2p.read) break;
+                    // <Activity Counters>
+                    if (is_local_req(m_config_to_cc_send_srcid_fifo.read()))
+                    {
+                        m_cpt_minval_local++;
+                    }
+                    else
+                    {
+                        m_cpt_minval_remote++;
+                    }
+                    // 2 flits for multi inval
+                    m_cpt_minval_cost += 2 * req_distance(m_config_to_cc_send_srcid_fifo.read());
+                    // </Activity Counters>
+                    r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE;
+                    break;
+                }
+                if (r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false;
+                // <Activity Counters>
+                m_cpt_minval++;
+                // </Activity Counters>
+                r_cc_send_fsm = CC_SEND_CONFIG_IDLE;
+                break;
+            }
+            ////////////////////////////////
+            case CC_SEND_CONFIG_INVAL_NLINE:    // send second flit multi-inval (from CONFIG FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                config_to_cc_send_fifo_get = true;
+                r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CC_SEND_CONFIG_INVAL_NLINE> multi-inval for line "
+                        << std::hex << r_config_to_cc_send_nline.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////////////////
+            case CC_SEND_CONFIG_BRDCAST_HEADER:   // send first flit BC-inval (from CONFIG FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE;
+                break;
+            }
+            //////////////////////////////////
+            case CC_SEND_CONFIG_BRDCAST_NLINE:    // send second flit BC-inval (from CONFIG FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                // <Activity Counters>
+                m_cpt_binval++;
+                // </Activity Counters>
+                r_config_to_cc_send_brdcast_req = false;
+                r_cc_send_fsm = CC_SEND_CONFIG_IDLE;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                    std::cout << "  <MEMC " << name()
+                        << " CC_SEND_CONFIG_BRDCAST_NLINE> BC-Inval for line "
+                        << std::hex << r_config_to_cc_send_nline.read() << std::endl;
+#endif
+                break;
+            }
+            ///////////////////////////////////
+            case CC_SEND_XRAM_RSP_INVAL_HEADER:   // send first flit multi-inval (from XRAM_RSP FSM)
+            {
+                if (m_xram_rsp_to_cc_send_inst_fifo.rok())
+                {
+                    if (not p_dspin_m2p.read) break;
+                    // <Activity Counters>
+                    if (is_local_req(m_xram_rsp_to_cc_send_srcid_fifo.read()))
+                    {
+                        m_cpt_minval_local++;
+                    }
+                    else
+                    {
+                        m_cpt_minval_remote++;
+                    }
+                    // 2 flits for multi inval
+                    m_cpt_minval_cost += 2 * req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read());
+                    // </Activity Counters>
+                    r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE;
+                    break;
+                }
+                if (r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false;
+                // <Activity Counters>
+                m_cpt_minval++;
+                // </Activity Counters>
+                r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE;
+                break;
+            }
+            //////////////////////////////////
+            case CC_SEND_XRAM_RSP_INVAL_NLINE:   // send second flit multi-inval (from XRAM_RSP FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                xram_rsp_to_cc_send_fifo_get = true;
+                r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CC_SEND_XRAM_RSP_INVAL_NLINE> Multicast-Inval for line "
+                        << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////////////////////////
+            case CC_SEND_XRAM_RSP_BRDCAST_HEADER:  // send first flit broadcast-inval (from XRAM_RSP FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE;
+                break;
+            }
+            ////////////////////////////////////
+            case CC_SEND_XRAM_RSP_BRDCAST_NLINE:   // send second flit broadcast-inval (from XRAM_RSP FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                // <Activity Counters>
+                m_cpt_binval++;
+                // </Activity Counters>
+                r_xram_rsp_to_cc_send_brdcast_req = false;
+                r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> BC-Inval for line "
+                        << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////////////////////////
+            case CC_SEND_READ_NCC_INVAL_HEADER:
+            {
+                if (not p_dspin_m2p.read) break;
+                r_cc_send_fsm = CC_SEND_READ_NCC_INVAL_NLINE;
+                break;
+            }
+            ////////////////////////////////////
+            case CC_SEND_READ_NCC_INVAL_NLINE:
+            {
+                if (not p_dspin_m2p.read) break;
+                r_read_to_cc_send_req = false;
+                r_cc_send_fsm = CC_SEND_READ_IDLE;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                {
+                    std::cout
+                        << "  <MEMC " << name()
+                        << " CC_SEND_READ_NCC_INVAL_HEADER> Inval for line "
+                        << std::hex <<r_read_to_cc_send_nline.read() << std::dec
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+            ////////////////////////////////////
+            case CC_SEND_WRITE_NCC_INVAL_HEADER:
+            {
+                if (not p_dspin_m2p.read) break;
+                r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_NLINE;
+                break;
+            }
+            ////////////////////////////////////
+            case CC_SEND_WRITE_NCC_INVAL_NLINE:
+            {
+                if (not p_dspin_m2p.read) break;
+                r_write_to_cc_send_req = false;
+                r_cc_send_fsm = CC_SEND_WRITE_IDLE;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                {
+                    std::cout
+                        << "  <MEMC " << name()
+                        << " CC_SEND_WRITE_NCC_INVAL_HEADER> Inval for line "
+                        << std::hex << r_write_to_cc_send_nline.read() << std::dec
+                        << std::endl;
+                }
+#endif
+                break;
+            }
+            //////////////////////////////////
+            case CC_SEND_WRITE_BRDCAST_HEADER:   // send first flit broadcast-inval (from WRITE FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE;
+                break;
+            }
+            /////////////////////////////////
+            case CC_SEND_WRITE_BRDCAST_NLINE:   // send second flit broadcast-inval (from WRITE FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+
+                // <Activity Counters>
+                m_cpt_binval++;
+                // </Activity Counters>
+
+                r_write_to_cc_send_brdcast_req = false;
+                r_cc_send_fsm = CC_SEND_WRITE_IDLE;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CC_SEND_WRITE_BRDCAST_NLINE> BC-Inval for line "
+                        << std::hex << r_write_to_cc_send_nline.read() << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////////////
+            case CC_SEND_WRITE_UPDT_HEADER:   // send first flit for a multi-update (from WRITE FSM)
+            {
+                if (m_write_to_cc_send_inst_fifo.rok())
+                {
+                    if (not p_dspin_m2p.read) break;
+                    // <Activity Counters>
+                    if (is_local_req(m_write_to_cc_send_srcid_fifo.read()))
+                    {
+                        m_cpt_update_local++;
+                    }
+                    else
+                    {
+                        m_cpt_update_remote++;
+                    }
+                    // 2 flits for multi update
+                    m_cpt_update_cost += 2 * req_distance(m_write_to_cc_send_srcid_fifo.read());
+                    // </Activity Counters>
+
+                    r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE;
+                    break;
+                }
+
+                if (r_write_to_cc_send_multi_req.read())
+                {
+                    r_write_to_cc_send_multi_req = false;
+                }
+
+                // <Activity Counters>
+                m_cpt_update++;
+                // </Activity Counters>
+                r_cc_send_fsm = CC_SEND_WRITE_IDLE;
+                break;
+            }
+            //////////////////////////////
+            case CC_SEND_WRITE_UPDT_NLINE:   // send second flit for a multi-update (from WRITE FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+
+                r_cc_send_cpt = 0;
+                r_cc_send_fsm = CC_SEND_WRITE_UPDT_DATA;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CC_SEND_WRITE_UPDT_NLINE> Multicast-Update for address " << std::hex
+                        << r_write_to_cc_send_nline.read() * m_words * 4 << std::dec << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////////////////
+            case CC_SEND_WRITE_UPDT_DATA:   // send data flits for multi-update (from WRITE FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                if (r_cc_send_cpt.read() == r_write_to_cc_send_count.read())
+                {
+                    write_to_cc_send_fifo_get = true;
+                    r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
+                    break;
+                }
+
+                r_cc_send_cpt = r_cc_send_cpt.read() + 1;
+                break;
+            }
+            ////////////////////////////////
+            case CC_SEND_CAS_BRDCAST_HEADER:   // send first flit  broadcast-inval (from CAS FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE;
+                break;
+            }
+            ///////////////////////////////
+            case CC_SEND_CAS_BRDCAST_NLINE:   // send second flit broadcast-inval (from CAS FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                // <Activity Counters>
+                m_cpt_binval++;
+                // </Activity Counters>
+
+                r_cas_to_cc_send_brdcast_req = false;
+                r_cc_send_fsm = CC_SEND_CAS_IDLE;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CC_SEND_CAS_BRDCAST_NLINE> Broadcast-Inval for address: " << std::hex
+                        << r_cas_to_cc_send_nline.read() * m_words * 4 << std::dec << std::endl;
+                }
+#endif
+                break;
+            }
+            /////////////////////////////
+            case CC_SEND_CAS_UPDT_HEADER:   // send first flit for a multi-update (from CAS FSM)
+            {
+                if (m_cas_to_cc_send_inst_fifo.rok())
+                {
+                    if (not p_dspin_m2p.read) break;
+                    // <Activity Counters>
+                    if (is_local_req(m_cas_to_cc_send_srcid_fifo.read()))
+                    {
+                        m_cpt_update_local++;
+                    }
+                    else
+                    {
+                        m_cpt_update_remote++;
+                    }
+                    // 2 flits for multi update
+                    m_cpt_update_cost += 2 * req_distance(m_cas_to_cc_send_srcid_fifo.read());
+                    // </Activity Counters>
+                    r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE;
+                    break;
+                }
+
+                // no more packets to send for the multi-update
+                if (r_cas_to_cc_send_multi_req.read())
+                {
+                    r_cas_to_cc_send_multi_req = false;
+                }
+
+                // <Activity Counters>
+                m_cpt_update++;
+                // </Activity Counters>
+                r_cc_send_fsm = CC_SEND_CAS_IDLE;
+                break;
+            }
+            ////////////////////////////
+            case CC_SEND_CAS_UPDT_NLINE:   // send second flit for a multi-update (from CAS FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                r_cc_send_cpt = 0;
+                r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA;
+
+#if DEBUG_MEMC_CC_SEND
+                if (m_debug)
+                {
+                    std::cout << "  <MEMC " << name()
+                        << " CC_SEND_CAS_UPDT_NLINE> Multicast-Update for address " << std::hex
+                        << r_cas_to_cc_send_nline.read() * m_words * 4 << std::dec << std::endl;
+                }
+#endif
+                break;
+            }
+            ///////////////////////////
+            case CC_SEND_CAS_UPDT_DATA:   // send first data for a multi-update (from CAS FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+
+                if (r_cas_to_cc_send_is_long.read())
+                {
+                    r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA_HIGH;
+                    break;
+                }
+
+                cas_to_cc_send_fifo_get = true;
+                r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
+                break;
+            }
+            ////////////////////////////////
+            case CC_SEND_CAS_UPDT_DATA_HIGH:   // send second data for multi-update (from CAS FSM)
+            {
+                if (not p_dspin_m2p.read) break;
+                cas_to_cc_send_fifo_get = true;
+                r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
+                break;
+            }
         }
         // end switch r_cc_send_fsm
@@ -8102 +8206 @@
         //////////////////////////////////////////////////////////////////////////////
 
-        switch(r_cc_receive_fsm.read())
+        switch (r_cc_receive_fsm.read())
         {
             /////////////////////
             case CC_RECEIVE_IDLE:
-                {
-                    if(not p_dspin_p2m.write) break;
-
-                    uint8_t type =
-                        DspinRwtParam::dspin_get(
-                                p_dspin_p2m.data.read(),
-                                DspinRwtParam::P2M_TYPE);
-
-                    if((type == DspinRwtParam::TYPE_CLEANUP_DATA) or
-                            (type == DspinRwtParam::TYPE_CLEANUP_INST))
-                    {
-                        r_cc_receive_fsm = CC_RECEIVE_CLEANUP;
-                        break;
-                    }
-
-                    if(type == DspinRwtParam::TYPE_MULTI_ACK)
-                    {
-                        r_cc_receive_fsm = CC_RECEIVE_MULTI_ACK;
-                        break;
-                    }
-
-                    assert(false and
-                            "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
-                            "Illegal type in coherence request");
-
+            {
+                if (not p_dspin_p2m.write) break;
+
+                uint8_t type =
+                    DspinRwtParam::dspin_get(
+                            p_dspin_p2m.data.read(),
+                            DspinRwtParam::P2M_TYPE);
+
+                if ((type == DspinRwtParam::TYPE_CLEANUP_DATA) or
+                        (type == DspinRwtParam::TYPE_CLEANUP_INST))
+                {
+                    r_cc_receive_fsm = CC_RECEIVE_CLEANUP;
                     break;
                 }
-                ////////////////////////
+
+                if (type == DspinRwtParam::TYPE_MULTI_ACK)
+                {
+                    r_cc_receive_fsm = CC_RECEIVE_MULTI_ACK;
+                    break;
+                }
+
+                assert(false and
+                        "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
+                        "Illegal type in coherence request");
+
+                break;
+            }
+            ////////////////////////
             case CC_RECEIVE_CLEANUP:
-                {
-                    // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo
-
-                    if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok())
-                        break;
-
-                    cc_receive_to_cleanup_fifo_put = true;
-                    if(p_dspin_p2m.eop.read())
-                        r_cc_receive_fsm               = CC_RECEIVE_IDLE;
-
+            {
+                // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo
+
+                if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok())
                     break;
-                }
-                ////////////////////////////
-            case CC_RECEIVE_CLEANUP_EOP:
-                {
-                    // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo
-
-                    if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok())
-                        break;
-
-                    assert(p_dspin_p2m.eop.read() and
-                            "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
-                            "CLEANUP command must have two flits");
-
-                    cc_receive_to_cleanup_fifo_put = true;
-                    if(p_dspin_p2m.eop.read())
-                        r_cc_receive_fsm               = CC_RECEIVE_IDLE;
+
+                cc_receive_to_cleanup_fifo_put = true;
+                if (p_dspin_p2m.eop.read())
+                    r_cc_receive_fsm               = CC_RECEIVE_IDLE;
+
+                break;
+            }
+            //////////////////////////
+            case CC_RECEIVE_MULTI_ACK:
+            {
+                // write MULTI_ACK flit in CC_RECEIVE to MULTI_ACK fifo
+
+                // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo
+                if (not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok())
                     break;
-                }
-
-                //////////////////////////
-            case CC_RECEIVE_MULTI_ACK:
-                {
-                    // write MULTI_ACK flit in CC_RECEIVE to MULTI_ACK fifo
-
-                    // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo
-                    if(not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok())
-                        break;
-
-                    assert(p_dspin_p2m.eop.read() and
-                            "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
-                            "MULTI_ACK command must have one flit");
-
-                    cc_receive_to_multi_ack_fifo_put = true;
-                    r_cc_receive_fsm                 = CC_RECEIVE_IDLE;
-                    break;
-                }
+
+                assert(p_dspin_p2m.eop.read() and
+                        "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
+                        "MULTI_ACK command must have one flit");
+
+                cc_receive_to_multi_ack_fifo_put = true;
+                r_cc_receive_fsm = CC_RECEIVE_IDLE;
+                break;
+            }
         }
+
         //////////////////////////////////////////////////////////////////////////
         //    TGT_RSP FSM
@@ -8201 +8288 @@
         //////////////////////////////////////////////////////////////////////////
 
-        switch(r_tgt_rsp_fsm.read())
+        switch (r_tgt_rsp_fsm.read())
         {
             /////////////////////////
             case TGT_RSP_CONFIG_IDLE:  // tgt_cmd requests have the highest priority
-                {
-                    if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-                    else if(r_read_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_READ;
-                        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-                    }
-                    else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-                    else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
-                    else if(r_xram_rsp_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-                        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-                    }
-                    else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-                    else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-                    else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-                    break;
-                }
-                //////////////////////////
+            {
+                if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+                else if (r_read_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_READ;
+                    r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+                }
+                else if (r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+                else if (r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
+                else if (r_xram_rsp_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_XRAM;
+                    r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+                }
+                else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+                else if (r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+                else if (r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+                break;
+            }
+            //////////////////////////
             case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority
-                {
-                    if(r_read_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_READ;
-                        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-                    }
-                    else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-                    else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
-                    else if(r_xram_rsp_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-                        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-                    }
-                    else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-                    else if(r_cleanup_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-                        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
-                    }
-                    else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-                    else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-                    break;
-                }
-                ///////////////////////
+            {
+                if (r_read_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_READ;
+                    r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+                }
+                else if (r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+                else if (r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
+                else if (r_xram_rsp_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_XRAM;
+                    r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+                }
+                else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+                else if (r_cleanup_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+                    r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+                }
+                else if (r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+                else if (r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+                break;
+            }
+            ///////////////////////
             case TGT_RSP_READ_IDLE: // write requests have the highest priority
-                {
-                    if(r_write_to_tgt_rsp_req)          r_tgt_rsp_fsm = TGT_RSP_WRITE;
-                    else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
-                    else if(r_xram_rsp_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-                        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-                    }
-                    else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-                    else if(r_cleanup_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-                        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
-                    }
-                    else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-                    else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-                    else if(r_read_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_READ;
-                        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-                    }
-                    break;
-                }
-                ////////////////////////
+            {
+                if (r_write_to_tgt_rsp_req)          r_tgt_rsp_fsm = TGT_RSP_WRITE;
+                else if (r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
+                else if (r_xram_rsp_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_XRAM;
+                    r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+                }
+                else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+                else if (r_cleanup_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+                    r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+                }
+                else if (r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+                else if (r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+                else if (r_read_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_READ;
+                    r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+                }
+                break;
+            }
+            ////////////////////////
             case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority
-                {
-                    if(r_cas_to_tgt_rsp_req)            r_tgt_rsp_fsm = TGT_RSP_CAS;
-                    else if(r_xram_rsp_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-                        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-                    }
-                    else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-                    else if(r_cleanup_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-                        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
-                    }
-                    else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-                    else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-                    else if(r_read_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_READ;
-                        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-                    }
-                    else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-                    break;
-                }
-                ///////////////////////
+            {
+                if (r_cas_to_tgt_rsp_req)            r_tgt_rsp_fsm = TGT_RSP_CAS;
+                else if (r_xram_rsp_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_XRAM;
+                    r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+                }
+                else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+                else if (r_cleanup_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+                    r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+                }
+                else if (r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+                else if (r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+                else if (r_read_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_READ;
+                    r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+                }
+                else if (r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+                break;
+            }
+            ///////////////////////
             case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority
-                {
-                    if(r_xram_rsp_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-                        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-                    }
-                    else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
-                    else if(r_cleanup_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-                        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
-                    }
-                    else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-                    else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-                    else if(r_read_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_READ;
-                        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-                    }
-                    else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-                    else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
-                    break;
-                }
-                ///////////////////////
+            {
+                if (r_xram_rsp_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_XRAM;
+                    r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+                }
+                else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+                else if (r_cleanup_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+                    r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+                }
+                else if (r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+                else if (r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+                else if (r_read_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_READ;
+                    r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+                }
+                else if (r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+                else if (r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
+                break;
+            }
+            ///////////////////////
             case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority
-                {
-
-                    if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
-                    else if(r_cleanup_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-                        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
-                    }
-                    else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-                    else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-                    else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-                    else if(r_read_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_READ;
-                        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-                    }
-                    else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-                    else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
-                    else if(r_xram_rsp_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-                        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-                    }
-                    break;
-                }
-                ////////////////////////////
+            {
+
+                if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+                else if (r_cleanup_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+                    r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+                }
+                else if (r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+                else if (r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+                else if (r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+                else if (r_read_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_READ;
+                    r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+                }
+                else if (r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+                else if (r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
+                else if (r_xram_rsp_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_XRAM;
+                    r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+                }
+                break;
+            }
+            ////////////////////////////
             case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority
-                {
-                    if(r_cleanup_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-                        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
-                    }
-                    else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-                    else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-                    else if(r_read_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_READ;
-                        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-                    }
-                    else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-                    else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
-                    else if(r_xram_rsp_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-                        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-                    }
-                    else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-                    break;
-                }
-                //////////////////////////
+            {
+                if (r_cleanup_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+                    r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+                }
+                else if (r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+                else if (r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+                else if (r_read_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_READ;
+                    r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+                }
+                else if (r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+                else if (r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
+                else if (r_xram_rsp_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_XRAM;
+                    r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+                }
+                else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+                break;
+            }
+            //////////////////////////
             case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority
-                {
-                    if(r_config_to_tgt_rsp_req)         r_tgt_rsp_fsm = TGT_RSP_CONFIG;
-                    else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
-                    else if(r_read_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_READ;
-                        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
-                    }
-                    else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
-                    else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
-                    else if(r_xram_rsp_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_XRAM;
-                        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
-                    }
-                    else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
-                    else if(r_cleanup_to_tgt_rsp_req)
-                    {
-                        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-                        r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
-                    }
-                    break;
-                }
-                ////////////////////
+            {
+                if (r_config_to_tgt_rsp_req)         r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+                else if (r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+                else if (r_read_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_READ;
+                    r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+                }
+                else if (r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+                else if (r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
+                else if (r_xram_rsp_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_XRAM;
+                    r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+                }
+                else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+                else if (r_cleanup_to_tgt_rsp_req)
+                {
+                    r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+                    r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
+                }
+                break;
+            }
+            ////////////////////
             case TGT_RSP_CONFIG:  // send the response for a config transaction
-                {
-                    if ( p_vci_tgt.rspack )
-                    {
-                        r_config_to_tgt_rsp_req = false;
-                        r_tgt_rsp_fsm           = TGT_RSP_CONFIG_IDLE;
+            {
+                if (p_vci_tgt.rspack)
+                {
+                    r_config_to_tgt_rsp_req = false;
+                    r_tgt_rsp_fsm           = TGT_RSP_CONFIG_IDLE;
 
 #if DEBUG_MEMC_TGT_RSP
-                        if( m_debug )
+                    if (m_debug)
+                    {
+                        std::cout
+                            << "  <MEMC " << name()
+                            << " TGT_RSP_CONFIG>  Config transaction completed response"
+                            << " / rsrcid = " << std::hex << r_config_to_tgt_rsp_srcid.read()
+                            << " / rtrdid = " << r_config_to_tgt_rsp_trdid.read()
+                            << " / rpktid = " << r_config_to_tgt_rsp_pktid.read()
+                            << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            /////////////////////
+            case TGT_RSP_TGT_CMD: // send the response for a configuration access
+            {
+                if (p_vci_tgt.rspack)
+                {
+                    r_tgt_cmd_to_tgt_rsp_req = false;
+                    r_tgt_rsp_fsm            = TGT_RSP_TGT_CMD_IDLE;
+
+#if DEBUG_MEMC_TGT_RSP
+                    if (m_debug)
+                    {
+                        std::cout
+                            << "  <MEMC " << name()
+                            << " TGT_RSP_TGT_CMD> Send response for a configuration access"
+                            << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read()
+                            << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read()
+                            << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read()
+                            << " / error = " << r_tgt_cmd_to_tgt_rsp_error.read()
+                            << std::endl;
+                    }
+#endif
+                }
+                break;
+            }
+            //////////////////
+            case TGT_RSP_READ:    // send the response to a read
+            {
+                if (p_vci_tgt.rspack)
+                {
+
+#if DEBUG_MEMC_TGT_RSP
+                    if (m_debug)
+                    {
+                        std::cout
+                            << "  <MEMC " << name() << " TGT_RSP_READ> Read response"
+                            << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read()
+                            << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read()
+                            << " / rpktid = " << r_read_to_tgt_rsp_pktid.read()
+                            << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
+                            << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
+                    }
+#endif
+
+                    uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() +
+                        r_read_to_tgt_rsp_length.read() - 1;
+                    bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx);
+                    bool is_ll        = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+
+                    if ((is_last_word and not is_ll) or
+                       (r_tgt_rsp_key_sent.read() and is_ll))
+                    {
+                        // Last word in case of READ or second flit in case if LL
+                        r_tgt_rsp_key_sent    = false;
+                        r_read_to_tgt_rsp_req = false;
+                        r_tgt_rsp_fsm         = TGT_RSP_READ_IDLE;
+                    }
+                    else
+                    {
+                        if (is_ll)
                         {
-                            std::cout
-                                << "  <MEMC " << name()
-                                << " TGT_RSP_CONFIG>  Config transaction completed response"
-                                << " / rsrcid = " << std::hex << r_config_to_tgt_rsp_srcid.read()
-                                << " / rtrdid = " << r_config_to_tgt_rsp_trdid.read()
-                                << " / rpktid = " << r_config_to_tgt_rsp_pktid.read()
-                                << std::endl;
-                        }
-#endif
-                    }
-                    break;
-                }
-                /////////////////////
-            case TGT_RSP_TGT_CMD: // send the response for a configuration access
-                {
-                    if ( p_vci_tgt.rspack )
-                    {
-                        r_tgt_cmd_to_tgt_rsp_req = false;
-                        r_tgt_rsp_fsm            = TGT_RSP_TGT_CMD_IDLE;
-
-#if DEBUG_MEMC_TGT_RSP
-                        if( m_debug )
-                        {
-                            std::cout
-                                << "  <MEMC " << name()
-                                << " TGT_RSP_TGT_CMD> Send response for a configuration access"
-                                << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read()
-                                << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read()
-                                << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read()
-                                << " / error = " << r_tgt_cmd_to_tgt_rsp_error.read()
-                                << std::endl;
-                        }
-#endif
-                    }
-                    break;
-                }
-                //////////////////
-            case TGT_RSP_READ:    // send the response to a read
-                {
-                    if ( p_vci_tgt.rspack )
-                    {
-
-#if DEBUG_MEMC_TGT_RSP
-                        if( m_debug )
-                        {
-                            std::cout
-                                << "  <MEMC " << name() << " TGT_RSP_READ> Read response"
-                                << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read()
-                                << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read()
-                                << " / rpktid = " << r_read_to_tgt_rsp_pktid.read()
-                                << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
-                                << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
-                        }
-#endif
-
-
-                        uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() +
-                            r_read_to_tgt_rsp_length.read() - 1;
-                        bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
-                        bool     is_ll         = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
-
-                        if ((is_last_word              and not is_ll) or
-                                (r_tgt_rsp_key_sent.read() and is_ll))
-                        {
-                            // Last word in case of READ or second flit in case if LL
-                            r_tgt_rsp_key_sent    = false;
-                            r_read_to_tgt_rsp_req = false;
-                            r_tgt_rsp_fsm         = TGT_RSP_READ_IDLE;
-                            if (r_read_to_tgt_rsp_pktid.read() == 0x0)
-                            {
-                                m_cpt_read_data_unc ++;
-                            }
-                            else if (r_read_to_tgt_rsp_pktid.read() == 0x1)
-                            {
-                                m_cpt_read_data_miss_CC ++;
-                            }
-                            else if (r_read_to_tgt_rsp_pktid.read() == 0x2)
-                            {
-                                m_cpt_read_ins_unc ++;
-                            }
-                            else if (r_read_to_tgt_rsp_pktid.read() == 0x3)
-                            {
-                                m_cpt_read_ins_miss ++;
-                            }
-                            else if (r_read_to_tgt_rsp_pktid.read() == 0x6)
-                            {
-                                m_cpt_read_ll_CC ++;
-                            }
-                            else if (r_read_to_tgt_rsp_pktid.read() == 0x9)
-                            {
-                                m_cpt_read_data_miss_NCC ++;
-                            }
-                            else if (r_read_to_tgt_rsp_pktid.read() == 0x14)
-                            {
-                                m_cpt_read_ll_NCC ++;
-                            }
-                            else
-                            {
-                                assert(false);
-                            }
+                            r_tgt_rsp_key_sent = true; // Send second flit of ll
                         }
                         else
                         {
-                            if (is_ll)
-                            {
-                                r_tgt_rsp_key_sent = true;                // Send second flit of ll
-                            }
-                            else
-                            {
-                                r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read
-                            }
+                            r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read
                         }
                     }
-                    break;
-                }
-                //////////////////
+                }
+                break;
+            }
+            //////////////////
             case TGT_RSP_WRITE:   // send the write acknowledge
-                {
-                    if(p_vci_tgt.rspack)
-                    {
+            {
+                if (p_vci_tgt.rspack)
+                {
 
 #if DEBUG_MEMC_TGT_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " TGT_RSP_WRITE> Write response"
-                                << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read()
-                                << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read()
-                                << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl;
-#endif
-                        r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
-                        r_write_to_tgt_rsp_req = false;
-                    }
-                    break;
-                }
-                /////////////////////
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " TGT_RSP_WRITE> Write response"
+                            << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read()
+                            << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read()
+                            << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl;
+                    }
+#endif
+                    r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
+                    r_write_to_tgt_rsp_req = false;
+                }
+                break;
+            }
+            /////////////////////
             case TGT_RSP_CLEANUP:
-                {
-                    if(p_vci_tgt.rspack)
-                    {
+            {
+                if (p_vci_tgt.rspack)
+                {
 
 #if DEBUG_MEMC_TGT_RSP
-                        if(m_debug)
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response"
+                            << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read()
+                            << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
+                            << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl
+                            << " / data = " << r_cleanup_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() << std::dec << std::endl;
+                    }
+#endif
+
+                    uint32_t last_word_idx = r_cleanup_to_tgt_rsp_first_word.read() + r_cleanup_to_tgt_rsp_length.read() - 1;
+                    bool is_ll = ((r_cleanup_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+
+                    if (r_cleanup_to_tgt_rsp_type.read() or ((r_tgt_rsp_cpt.read() == last_word_idx) and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll))
+                    {
+                        r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
+                        r_cleanup_to_tgt_rsp_req = false;
+                        r_tgt_rsp_key_sent = false;
+                    }
+                    else
+                    {
+                        if (is_ll)
                         {
-                            std::cout << "  <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response"
-                                << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read()
-                                << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
-                                << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl
-                                << " / data = " << std::hex << r_cleanup_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() << std::dec << std::endl;
-                        }
-#endif
-
-                        uint32_t last_word_idx = r_cleanup_to_tgt_rsp_first_word.read() + r_cleanup_to_tgt_rsp_length.read() - 1;
-                        bool is_ll = ((r_cleanup_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
-
-                        if (r_cleanup_to_tgt_rsp_type.read() or ((r_tgt_rsp_cpt.read() == last_word_idx) and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll) )
-                        {
-                            r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
-                            r_cleanup_to_tgt_rsp_req = false;
-                            r_tgt_rsp_key_sent = false;
-
-
-                            if (r_cleanup_to_tgt_rsp_pktid.read() == 0x0)
-                            {
-                                m_cpt_read_data_unc ++;
-                            }
-                            else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x1)
-                            {
-                                m_cpt_read_data_miss_CC ++;
-                            }
-                            else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x2)
-                            {
-                                m_cpt_read_ins_unc ++;
-                            }
-                            else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x3)
-                            {
-                                m_cpt_read_ins_miss ++;
-                            }
-                            else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x6)
-                            {
-                                m_cpt_read_ll_CC ++;
-                            }
-                            else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x9)
-                            {
-                                m_cpt_read_data_miss_NCC ++;
-                            }
-                            else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x14)
-                            {
-                                m_cpt_read_ll_NCC ++;
-                            }
-                            else if (!r_cleanup_to_tgt_rsp_type.read())
-                            {
-                                assert(false);
-                            }
-
+                            r_tgt_rsp_key_sent = true;
                         }
                         else
                         {
-                            if (is_ll)
-                            {
-                                r_tgt_rsp_key_sent = true;
-                            }
-                            else
-                            {
-                                r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
-                            }
+                            r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
                         }
                     }
-                    break;
-                }
-                /////////////////
+                }
+                break;
+            }
+            /////////////////
             case TGT_RSP_CAS:    // send one atomic word response
-                {
-                    if(p_vci_tgt.rspack)
-                    {
+            {
+                if (p_vci_tgt.rspack)
+                {
 
 #if DEBUG_MEMC_TGT_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " TGT_RSP_CAS> CAS response"
-                                << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read()
-                                << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read()
-                                << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl;
-#endif
-                        r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE;
-                        r_cas_to_tgt_rsp_req = false;
-                    }
-                    break;
-                }
-                //////////////////
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " TGT_RSP_CAS> CAS response"
+                            << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read()
+                            << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read()
+                            << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl;
+                    }
+#endif
+                    r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE;
+                    r_cas_to_tgt_rsp_req = false;
+                }
+                break;
+            }
+            //////////////////
             case TGT_RSP_XRAM:    // send the response after XRAM access
-                {
-                    if ( p_vci_tgt.rspack )
-                    {
+            {
+                if (p_vci_tgt.rspack)
+                {
 
 #if DEBUG_MEMC_TGT_RSP
-                        if( m_debug )
-                            std::cout << "  <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access"
-                                << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read()
-                                << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
-                                << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read()
-                                << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
-                                << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
-#endif
-                        uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() +
-                            r_xram_rsp_to_tgt_rsp_length.read() - 1;
-                        bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
-                        bool     is_ll         = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
-                        bool     is_error      = r_xram_rsp_to_tgt_rsp_rerror.read();
-
-                        if (((is_last_word or is_error) and not is_ll) or
-                                (r_tgt_rsp_key_sent.read() and     is_ll))
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access"
+                            << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read()
+                            << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
+                            << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read()
+                            << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
+                            << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
+                    }
+#endif
+                    uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() +
+                        r_xram_rsp_to_tgt_rsp_length.read() - 1;
+                    bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx);
+                    bool is_ll        = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+                    bool is_error     = r_xram_rsp_to_tgt_rsp_rerror.read();
+
+                    if (((is_last_word or is_error) and not is_ll) or
+                            (r_tgt_rsp_key_sent.read() and is_ll))
+                    {
+                        // Last word sent in case of READ or second flit sent in case if LL
+                        r_tgt_rsp_key_sent        = false;
+                        r_xram_rsp_to_tgt_rsp_req = false;
+                        r_tgt_rsp_fsm             = TGT_RSP_XRAM_IDLE;
+                    }
+                    else
+                    {
+                        if (is_ll)
                         {
-                            // Last word sent in case of READ or second flit sent in case if LL
-                            r_tgt_rsp_key_sent        = false;
-                            r_xram_rsp_to_tgt_rsp_req = false;
-                            r_tgt_rsp_fsm             = TGT_RSP_XRAM_IDLE;
-
-
-                            if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x0)
-                            {
-                                m_cpt_read_data_unc ++;
-                            }
-                            else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x1)
-                            {
-                                m_cpt_read_data_miss_CC ++;
-                            }
-                            else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x2)
-                            {
-                                m_cpt_read_ins_unc ++;
-                            }
-                            else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x3)
-                            {
-                                m_cpt_read_ins_miss ++;
-                            }
-                            else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x6)
-                            {
-                                m_cpt_read_ll_CC ++;
-                            }
-                            else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x9)
-                            {
-                                m_cpt_read_data_miss_NCC ++;
-                            }
-                            else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x14)
-                            {
-                                m_cpt_read_ll_NCC ++;
-                            }
-                            else
-                            {
-                                assert(false);
-                            }
-
+                            r_tgt_rsp_key_sent = true; // Send second flit of ll
                         }
                         else
                         {
-                            if (is_ll)
-                            {
-                                r_tgt_rsp_key_sent = true;                     // Send second flit of ll
-                            }
-                            else
-                            {
-                                r_tgt_rsp_cpt      = r_tgt_rsp_cpt.read() + 1; // Send next word of read
-                            }
+                            r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read
                         }
                     }
-                    break;
-                }
-                ///////////////////////
+                }
+                break;
+            }
+            ///////////////////////
             case TGT_RSP_MULTI_ACK:    // send the write response after coherence transaction
-                {
-                    if(p_vci_tgt.rspack)
-                    {
+            {
+                if (p_vci_tgt.rspack)
+                {
 
 #if DEBUG_MEMC_TGT_RSP
-                        if(m_debug)
-                            std::cout << "  <MEMC " << name() << " TGT_RSP_MULTI_ACK> Write response after coherence transaction"
-                                << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read()
-                                << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read()
-                                << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl;
-#endif
-                        r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK_IDLE;
-                        r_multi_ack_to_tgt_rsp_req = false;
-                    }
-                    break;
-                }
+                    if (m_debug)
+                    {
+                        std::cout << "  <MEMC " << name() << " TGT_RSP_MULTI_ACK> Write response after coherence transaction"
+                            << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read()
+                            << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read()
+                            << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl;
+                    }
+#endif
+                    r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK_IDLE;
+                    r_multi_ack_to_tgt_rsp_req = false;
+                }
+                break;
+            }
         } // end switch tgt_rsp_fsm
 
@@ -8747 +8739 @@
         // The resource is always allocated.
         /////////////////////////////////////////////////////////////////////////////////////
-        switch(r_alloc_upt_fsm.read())
+        switch (r_alloc_upt_fsm.read())
         {
             /////////////////////////
             case ALLOC_UPT_WRITE:         // allocated to WRITE FSM
+            {
                 if (r_write_fsm.read() != WRITE_UPT_LOCK)
                 {
@@ -8758 +8751 @@
                     else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
                         r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
+
                     else
                         m_cpt_upt_unused++;
                 }
                 break;
-
-                /////////////////////////
+            }
+            /////////////////////////
             case ALLOC_UPT_CAS:           // allocated to CAS FSM
+            {
                 if (r_cas_fsm.read() != CAS_UPT_LOCK)
                 {
@@ -8777 +8772 @@
                 }
                 break;
-
-                /////////////////////////
+            }
+            /////////////////////////
             case ALLOC_UPT_MULTI_ACK:     // allocated to MULTI_ACK FSM
+            {
                 if ((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK ) and
                         (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR))
@@ -8788 +8784 @@
                     else if (r_cas_fsm.read() == CAS_UPT_LOCK)
                         r_alloc_upt_fsm = ALLOC_UPT_CAS;
+
                     else
                         m_cpt_upt_unused++;
                 }
                 break;
+            }
         } // end switch r_alloc_upt_fsm
 
@@ -8809 +8807 @@
         // The resource is always allocated.
         /////////////////////////////////////////////////////////////////////////////////////
-        switch(r_alloc_ivt_fsm.read())
+        switch (r_alloc_ivt_fsm.read())
         {
-            //////////////////////////
+            /////////////////////
             case ALLOC_IVT_WRITE:            // allocated to WRITE FSM
+            {
                 if ((r_write_fsm.read() != WRITE_BC_IVT_LOCK) and
                         (r_write_fsm.read() != WRITE_IVT_LOCK_HIT_WB) and
                         (r_write_fsm.read() != WRITE_MISS_IVT_LOCK))
                 {
-                    if(r_read_fsm.read() == READ_IVT_LOCK)
+                    if (r_read_fsm.read() == READ_IVT_LOCK)
                         r_alloc_ivt_fsm = ALLOC_IVT_READ;
 
@@ -8837 +8836 @@
                 }
                 break;
-
-                //////////////////////////
+            }
+            //////////////////////////
             case ALLOC_IVT_READ:            // allocated to READ FSM
+            {
                 if (r_read_fsm.read() != READ_IVT_LOCK)
                 {
@@ -8863 +8863 @@
                 }
                 break;
-
-                //////////////////////////
+            }
+            //////////////////////////
             case ALLOC_IVT_XRAM_RSP:         // allocated to XRAM_RSP FSM
-                if(r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)
+            {
+                if (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)
                 {
                     if ((r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) or
@@ -8883 +8884 @@
                         r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
 
-                    else if(r_read_fsm.read() == READ_IVT_LOCK)
+                    else if (r_read_fsm.read() == READ_IVT_LOCK)
                         r_alloc_ivt_fsm = ALLOC_IVT_READ;
 
@@ -8890 +8891 @@
                 }
                 break;
-
-                //////////////////////////
+            }
+            //////////////////////////
             case ALLOC_IVT_CLEANUP:          // allocated to CLEANUP FSM
-                if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK     ) and
+            {
+                if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK) and
                         (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT) and
                         (r_cleanup_fsm.read() != CLEANUP_IVT_LOCK_DATA))
@@ -8908 +8910 @@
                         r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
 
-                    else if(r_read_fsm.read() == READ_IVT_LOCK)
+                    else if (r_read_fsm.read() == READ_IVT_LOCK)
                         r_alloc_ivt_fsm = ALLOC_IVT_READ;
 
@@ -8918 +8920 @@
                 }
                 break;
-
-                //////////////////////////
+            }
+            //////////////////////////
             case ALLOC_IVT_CAS:              // allocated to CAS FSM
+            {
                 if (r_cas_fsm.read() != CAS_BC_IVT_LOCK)
                 {
@@ -8931 +8934 @@
                         r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
 
-                    else if(r_read_fsm.read() == READ_IVT_LOCK)
+                    else if (r_read_fsm.read() == READ_IVT_LOCK)
                         r_alloc_ivt_fsm = ALLOC_IVT_READ;
 
@@ -8945 +8948 @@
                 }
                 break;
-
-                //////////////////////////
+            }
+            //////////////////////////
             case ALLOC_IVT_CONFIG:           // allocated to CONFIG FSM
+            {
                 if (r_config_fsm.read() != CONFIG_IVT_LOCK)
                 {
@@ -8955 +8959 @@
                         r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
 
-                    else if(r_read_fsm.read() == READ_IVT_LOCK)
+                    else if (r_read_fsm.read() == READ_IVT_LOCK)
                         r_alloc_ivt_fsm = ALLOC_IVT_READ;
 
@@ -8965 +8969 @@
                         r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;
 
-                    else if(r_cas_fsm.read() == CAS_BC_IVT_LOCK)
+                    else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)
                         r_alloc_ivt_fsm = ALLOC_IVT_CAS;
                     else
@@ -8971 +8975 @@
                 }
                 break;
+            }
         } // end switch r_alloc_ivt_fsm
 
@@ -8982 +8987 @@
         /////////////////////////////////////////////////////////////////////////////////////
 
-        switch(r_alloc_dir_fsm.read())
+        switch (r_alloc_dir_fsm.read())
         {
             /////////////////////
             case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle.
-                // All the WAYS of a SET initialized in parallel
+                                  // All the WAYS of a SET initialized in parallel
+            {
 
                 r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1);
 
-                if(r_alloc_dir_reset_cpt.read() == (m_sets - 1))
+                if (r_alloc_dir_reset_cpt.read() == (m_sets - 1))
                 {
                     m_cache_directory.init();
@@ -8996 +9002 @@
                 }
                 break;
-
-                //////////////////////
+            }
+            //////////////////////
             case ALLOC_DIR_CONFIG:    // allocated to CONFIG FSM
-                if ( (r_config_fsm.read()    != CONFIG_DIR_REQ) and
-                        (r_config_fsm.read()    != CONFIG_DIR_ACCESS) and
-                        (r_config_fsm.read()    != CONFIG_TRT_LOCK) and
-                        (r_config_fsm.read()    != CONFIG_TRT_SET) and
-                        (r_config_fsm.read()    != CONFIG_IVT_LOCK) )
-                {
-                    if(r_read_fsm.read() == READ_DIR_REQ)
+            {
+                if ((r_config_fsm.read() != CONFIG_DIR_REQ) and
+                    (r_config_fsm.read() != CONFIG_DIR_ACCESS) and
+                    (r_config_fsm.read() != CONFIG_TRT_LOCK) and
+                    (r_config_fsm.read() != CONFIG_TRT_SET) and
+                    (r_config_fsm.read() != CONFIG_IVT_LOCK))
+                {
+                    if (r_read_fsm.read() == READ_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_READ;
 
-                    else if(r_write_fsm.read() == WRITE_DIR_REQ)
+                    else if (r_write_fsm.read() == WRITE_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_WRITE;
 
-                    else if(r_cas_fsm.read() == CAS_DIR_REQ)
+                    else if (r_cas_fsm.read() == CAS_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CAS;
 
-                    else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
+                    else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
 
-                    else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
+                    else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
                         r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
                 }
                 break;
-
-                ////////////////////
+            }
+            ////////////////////
             case ALLOC_DIR_READ:    // allocated to READ FSM
-                if( ((r_read_fsm.read()      != READ_DIR_REQ)   and
-                            (r_read_fsm.read()      != READ_DIR_LOCK)   and
-                            (r_read_fsm.read()      != READ_TRT_LOCK)   and
-                            (r_read_fsm.read()      != READ_HEAP_REQ)   and
-                            (r_read_fsm.read()      != READ_IVT_LOCK))
-                        or
-                        ((r_read_fsm.read()       == READ_TRT_LOCK)   and
-                         (r_alloc_trt_fsm.read()  == ALLOC_TRT_READ)) )
-                {
-                    if(r_write_fsm.read() == WRITE_DIR_REQ)
+            {
+                if (((r_read_fsm.read() != READ_DIR_REQ) and
+                     (r_read_fsm.read() != READ_DIR_LOCK) and
+                     (r_read_fsm.read() != READ_TRT_LOCK) and
+                     (r_read_fsm.read() != READ_HEAP_REQ) and
+                     (r_read_fsm.read() != READ_IVT_LOCK))
+                    or
+                     ((r_read_fsm.read() == READ_TRT_LOCK)   and
+                     (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)))
+                {
+                    if (r_write_fsm.read() == WRITE_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_WRITE;
 
-                    else if(r_cas_fsm.read() == CAS_DIR_REQ)
+                    else if (r_cas_fsm.read() == CAS_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CAS;
 
-                    else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
+                    else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
 
-                    else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
+                    else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
                         r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
-                    else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+                    else if (r_config_fsm.read() == CONFIG_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
 
@@ -9052 +9060 @@
                 }
                 break;
-
-                /////////////////////
+            }
+            /////////////////////
             case ALLOC_DIR_WRITE:
-                if(((r_write_fsm.read()       != WRITE_DIR_REQ)  and
-                            (r_write_fsm.read()       != WRITE_DIR_LOCK)  and
-                            (r_write_fsm.read()       != WRITE_BC_DIR_READ)  and
-                            (r_write_fsm.read()       != WRITE_DIR_HIT)  and
-                            (r_write_fsm.read()       != WRITE_BC_TRT_LOCK)  and
-                            (r_write_fsm.read()       != WRITE_BC_IVT_LOCK)  and
-                            (r_write_fsm.read()       != WRITE_MISS_IVT_LOCK)  and
-                            (r_write_fsm.read()       != WRITE_MISS_TRT_LOCK)  and
-                            (r_write_fsm.read()       != WRITE_UPT_LOCK)  and
-                            (r_write_fsm.read()       != WRITE_UPT_HEAP_LOCK) and
-                            (r_write_fsm.read()       != WRITE_IVT_LOCK_HIT_WB))
-                        or
-                        ((r_write_fsm.read()      == WRITE_UPT_HEAP_LOCK)  and
-                         (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE))
-                        or
-                        ((r_write_fsm.read()      == WRITE_MISS_TRT_LOCK)  and
-                         (r_alloc_trt_fsm.read()  == ALLOC_TRT_WRITE)))
-                {
-                    if(r_cas_fsm.read() == CAS_DIR_REQ)
+            {
+                if (((r_write_fsm.read() != WRITE_DIR_REQ) and
+                     (r_write_fsm.read() != WRITE_DIR_LOCK) and
+                     (r_write_fsm.read() != WRITE_BC_DIR_READ) and
+                     (r_write_fsm.read() != WRITE_DIR_HIT) and
+                     (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and
+                     (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and
+                     (r_write_fsm.read() != WRITE_MISS_IVT_LOCK) and
+                     (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and
+                     (r_write_fsm.read() != WRITE_UPT_LOCK) and
+                     (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and
+                     (r_write_fsm.read() != WRITE_IVT_LOCK_HIT_WB))
+                    or
+                     ((r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) and
+                     (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE))
+                    or
+                     ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) and
+                     (r_alloc_trt_fsm.read()  == ALLOC_TRT_WRITE)))
+                {
+                    if (r_cas_fsm.read() == CAS_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CAS;
 
-                    else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
+                    else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
 
-                    else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
+                    else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
                         r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
-                    else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+                    else if (r_config_fsm.read() == CONFIG_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
 
-                    else if(r_read_fsm.read() == READ_DIR_REQ)
+                    else if (r_read_fsm.read() == READ_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_READ;
 
@@ -9092 +9101 @@
                 }
                 break;
-
-                ///////////////////
+            }
+            ///////////////////
             case ALLOC_DIR_CAS:    // allocated to CAS FSM
-                if(((r_cas_fsm.read()         != CAS_DIR_REQ)  and
-                            (r_cas_fsm.read()         != CAS_DIR_LOCK)  and
-                            (r_cas_fsm.read()         != CAS_DIR_HIT_READ)  and
-                            (r_cas_fsm.read()         != CAS_DIR_HIT_COMPARE)  and
-                            (r_cas_fsm.read()         != CAS_DIR_HIT_WRITE)  and
-                            (r_cas_fsm.read()         != CAS_BC_TRT_LOCK)  and
-                            (r_cas_fsm.read()         != CAS_BC_IVT_LOCK)  and
-                            (r_cas_fsm.read()         != CAS_MISS_TRT_LOCK)  and
-                            (r_cas_fsm.read()         != CAS_UPT_LOCK)  and
-                            (r_cas_fsm.read()         != CAS_UPT_HEAP_LOCK))
-                        or
-                        ((r_cas_fsm.read()        == CAS_UPT_HEAP_LOCK)  and
-                         (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS))
-                        or
-                        ((r_cas_fsm.read()        == CAS_MISS_TRT_LOCK)  and
-                         (r_alloc_trt_fsm.read()  == ALLOC_TRT_CAS)))
-                {
-                    if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
+            {
+                if (((r_cas_fsm.read() != CAS_DIR_REQ) and
+                     (r_cas_fsm.read() != CAS_DIR_LOCK) and
+                     (r_cas_fsm.read() != CAS_DIR_HIT_READ) and
+                     (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) and
+                     (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and
+                     (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and
+                     (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and
+                     (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and
+                     (r_cas_fsm.read() != CAS_UPT_LOCK) and
+                     (r_cas_fsm.read() != CAS_UPT_HEAP_LOCK))
+                    or
+                     ((r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) and
+                     (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS))
+                    or
+                     ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) and
+                     (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)))
+                {
+                    if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
 
-                    else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
+                    else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
                         r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
-                    else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+                    else if (r_config_fsm.read() == CONFIG_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
 
-                    else if(r_read_fsm.read() == READ_DIR_REQ)
+                    else if (r_read_fsm.read() == READ_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_READ;
 
-                    else if(r_write_fsm.read() == WRITE_DIR_REQ)
+                    else if (r_write_fsm.read() == WRITE_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_WRITE;
 
@@ -9131 +9141 @@
                 }
                 break;
-
-                ///////////////////////
+            }
+            ///////////////////////
             case ALLOC_DIR_CLEANUP:    // allocated to CLEANUP FSM
-                if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and
-                        (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and
-                        (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and
-                        (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and
-                        (r_cleanup_fsm.read() != CLEANUP_IVT_LOCK_DATA))
-                {
-                    if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
+            {
+                if ((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and
+                    (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and
+                    (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and
+                    (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and
+                    (r_cleanup_fsm.read() != CLEANUP_IVT_LOCK_DATA))
+                {
+                    if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
                         r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
-                    else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+                    else if (r_config_fsm.read() == CONFIG_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
 
-                    else if(r_read_fsm.read() == READ_DIR_REQ)
+                    else if (r_read_fsm.read() == READ_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_READ;
 
-                    else if(r_write_fsm.read() == WRITE_DIR_REQ)
+                    else if (r_write_fsm.read() == WRITE_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_WRITE;
 
-                    else if(r_cas_fsm.read() == CAS_DIR_REQ)
+                    else if (r_cas_fsm.read() == CAS_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CAS;
 
@@ -9159 +9170 @@
                 }
                 break;
-
-                ////////////////////////
+            }
+            ////////////////////////
             case ALLOC_DIR_XRAM_RSP:    // allocated to XRAM_RSP FSM
-                if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and
-                        (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and
-                        (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK))
-                {
-                    if(r_config_fsm.read() == CONFIG_DIR_REQ)
+            {
+                if ((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and
+                    (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and
+                    (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK))
+                {
+                    if (r_config_fsm.read() == CONFIG_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
 
-                    else if(r_read_fsm.read() == READ_DIR_REQ)
+                    else if (r_read_fsm.read() == READ_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_READ;
 
-                    else if(r_write_fsm.read() == WRITE_DIR_REQ)
+                    else if (r_write_fsm.read() == WRITE_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_WRITE;
 
-                    else if(r_cas_fsm.read() == CAS_DIR_REQ)
+                    else if (r_cas_fsm.read() == CAS_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CAS;
 
-                    else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
+                    else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
                         r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
 
@@ -9185 +9197 @@
                 }
                 break;
-
+            }
         } // end switch alloc_dir_fsm
 
@@ -9192 +9204 @@
         ////////////////////////////////////////////////////////////////////////////////////
         // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer)
-        // with a round robin priority between 4 user FSMs :
-        // The cyclic priority is READ > WRITE > CAS > XRAM_RSP
+        // with a round robin priority between 8 user FSMs :
+        // The priority is READ > WRITE > CAS > IXR_CMD > XRAM_RSP > IXR_RSP > CONFIG > CLEANUP
         // The ressource is always allocated.
         ///////////////////////////////////////////////////////////////////////////////////
 
-        switch(r_alloc_trt_fsm.read())
+        switch (r_alloc_trt_fsm.read())
         {
             ////////////////////
             case ALLOC_TRT_READ:
-                if(r_read_fsm.read() != READ_TRT_LOCK)
-                {
-                    if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
+            {
+                if (r_read_fsm.read() != READ_TRT_LOCK)
+                {
+                    if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                             (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-                    else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
+                    else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                             (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-                    else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                    else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                            (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                            (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                            (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                            (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                            (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT))
+                        r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
+
+                    else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and
+                            (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
+                        r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+                    else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
+                            (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
+                        r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+
+                    else if (r_config_fsm.read() == CONFIG_TRT_LOCK)
+                        r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
+
+                    else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+                        r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
+
+                    else
+                        m_cpt_trt_unused++;
+                }
+                break;
+            }
+            /////////////////////
+            case ALLOC_TRT_WRITE:
+            {
+                if ((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and
+                        (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and
+                        (r_write_fsm.read() != WRITE_BC_IVT_LOCK))
+                {
+                    if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
+                            (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
+                        r_alloc_trt_fsm = ALLOC_TRT_CAS;
+
+                    else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT))
+                        r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
+
+                    else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and
+                            (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
+                        r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+                    else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
+                            (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
+                        r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+
+                    else if (r_config_fsm.read() == CONFIG_TRT_LOCK)
+                        r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
+
+                    else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+                        r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
+
+                    else if (r_read_fsm.read() == READ_TRT_LOCK)
+                        r_alloc_trt_fsm = ALLOC_TRT_READ;
+
+                    else
+                        m_cpt_trt_unused++;
+                }
+                break;
+            }
+            ////////////////////
+            case ALLOC_TRT_CAS:
+            {
+                if ((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and
+                        (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and
+                        (r_cas_fsm.read() != CAS_BC_IVT_LOCK))
+                {
+                    if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
                             (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
                             (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
@@ -9219 +9307 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
 
-                    else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
+                    else if ((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
+                             (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
+                        r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+                    else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
+                            (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
+                        r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+
+                    else if (r_config_fsm.read() == CONFIG_TRT_LOCK)
+                        r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
+
+                    else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+                        r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
+
+                    else if (r_read_fsm.read() == READ_TRT_LOCK)
+                        r_alloc_trt_fsm = ALLOC_TRT_READ;
+
+                    else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
+                            (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
+                        r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+
+                    else
+                        m_cpt_trt_unused++;
+                }
+                break;
+            }
+            ///////////////////////
+            case ALLOC_TRT_IXR_CMD:
+            {
+                if ((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and
+                    (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and
+                    (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and
+                    (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and
+                    (r_ixr_cmd_fsm.read() != IXR_CMD_CLEANUP_TRT) and
+                    (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT))
+                {
+                    if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and
                             (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
                         r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
-                    else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
+                    else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                             (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
+                    else if (r_config_fsm.read() == CONFIG_TRT_LOCK)
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9233 +9357 @@
                         r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
-                    else
-                        m_cpt_trt_unused++;
-                }
-                break;
-
-                /////////////////////
-            case ALLOC_TRT_WRITE:
-                if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and
-                        (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and
-                        (r_write_fsm.read() != WRITE_BC_IVT_LOCK))
-                {
-                    if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
+                    else if (r_read_fsm.read() == READ_TRT_LOCK)
+                        r_alloc_trt_fsm = ALLOC_TRT_READ;
+
+                    else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
+                            (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
+                        r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+
+                    else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                             (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_CAS;
-
-                    else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
-                        r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
-
-                    else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
-                            (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
-                        r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
-
-                    else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
-                            (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
-                        r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
-
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
-                        r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
-
-                    else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
-                        r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
-
-                    else if(r_read_fsm.read() == READ_TRT_LOCK)
-                        r_alloc_trt_fsm = ALLOC_TRT_READ;
-
-                    else
-                        m_cpt_trt_unused++;
-                }
-                break;
-
-                ////////////////////
-            case ALLOC_TRT_CAS:
-                if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and
-                        (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and
-                        (r_cas_fsm.read() != CAS_BC_IVT_LOCK))
-                {
-                    if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
-                        r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
-
-                    else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
-                            (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
-                        r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
-
-                    else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
-                            (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
-                        r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
-
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
-                        r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
-
-                    else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
-                        r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
-
-                    else if(r_read_fsm.read() == READ_TRT_LOCK)
-                        r_alloc_trt_fsm = ALLOC_TRT_READ;
-
-                    else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
-                            (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
-                        r_alloc_trt_fsm = ALLOC_TRT_WRITE;
-
-                    else
-                        m_cpt_trt_unused++;
-                }
-                break;
-                ///////////////////////
-            case ALLOC_TRT_IXR_CMD:
-                if((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and
-                        (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and
-                        (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and
-                        (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and
-                        (r_ixr_cmd_fsm.read() != IXR_CMD_CLEANUP_TRT) and
-                        (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT))
-                {
-                    if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
-                            (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
-                        r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
-
-                    else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
-                            (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
-                        r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
-
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
-                        r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
-
-                    else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
-                        r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
-
-                    else if(r_read_fsm.read() == READ_TRT_LOCK)
-                        r_alloc_trt_fsm = ALLOC_TRT_READ;
-
-                    else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
-                            (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
-                        r_alloc_trt_fsm = ALLOC_TRT_WRITE;
-
-                    else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
-                            (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
-                        r_alloc_trt_fsm = ALLOC_TRT_CAS;
-                }
-                break;
-
-                ////////////////////////
+                }
+                break;
+            }
+            ////////////////////////
             case ALLOC_TRT_XRAM_RSP:
-                if(((r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_LOCK)  or
+            {
+                if (((r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_LOCK)  or
                             (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and
                         (r_xram_rsp_fsm.read()  != XRAM_RSP_TRT_COPY)  and
@@ -9361 +9379 @@
                         (r_xram_rsp_fsm.read()  != XRAM_RSP_IVT_LOCK))
                 {
-                    if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
+                    if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                             (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
+                    else if (r_config_fsm.read() == CONFIG_TRT_LOCK)
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9371 +9389 @@
                         r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
-                    else if(r_read_fsm.read() == READ_TRT_LOCK)
+                    else if (r_read_fsm.read() == READ_TRT_LOCK)
                         r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-                    else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
+                    else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                             (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-                    else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
+                    else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                             (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-                    else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+                    else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
 
@@ -9394 +9412 @@
                 }
                 break;
-
-                ////////////////////////
+            }
+            ////////////////////////
             case ALLOC_TRT_IXR_RSP:
-                if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and
+            {
+                if ((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and
                         (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ))
                 {
-                    if( r_config_fsm.read() == CONFIG_TRT_LOCK )
+                    if (r_config_fsm.read() == CONFIG_TRT_LOCK)
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9406 +9425 @@
                         r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
-                    else if(r_read_fsm.read() == READ_TRT_LOCK)
+                    else if (r_read_fsm.read() == READ_TRT_LOCK)
                         r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-                    else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+                    else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                             (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-                    else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+                    else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                             (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-                    else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+                    else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
 
-                    else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+                    else if ((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
                             (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
                         r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
@@ -9433 +9452 @@
                 }
                 break;
-
-                //////////////////////
+            }
+            //////////////////////
             case ALLOC_TRT_CONFIG:
-                if((r_config_fsm.read() != CONFIG_TRT_LOCK) and
+            {
+                if ((r_config_fsm.read() != CONFIG_TRT_LOCK) and
                         (r_config_fsm.read() != CONFIG_TRT_SET))
                 {
@@ -9442 +9462 @@
                         r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
-                    else if(r_read_fsm.read() == READ_TRT_LOCK)
+                    else if (r_read_fsm.read() == READ_TRT_LOCK)
                         r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-                    else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
+                    else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                             (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-                    else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
+                    else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                             (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-                    else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+                    else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
 
-                    else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
+                    else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and
                             (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
                         r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
-                    else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
+                    else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                             (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
                 }
                 break;
-
-                ////////////////////////
+            }
+            ////////////////////////
             case ALLOC_TRT_CLEANUP:
-                if(r_cleanup_fsm.read() != CLEANUP_IXR_REQ)
-                {
-                    if(r_read_fsm.read() == READ_TRT_LOCK)
+            {
+                if (r_cleanup_fsm.read() != CLEANUP_IXR_REQ)
+                {
+                    if (r_read_fsm.read() == READ_TRT_LOCK)
                         r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-                    else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
+                    else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                             (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-                    else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
+                    else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                             (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
                         r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-                    else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
-                            (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+                    else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                             (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT))
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
 
-                    else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
+                    else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and
                             (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
                         r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
-                    else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                             (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
+                    else if (r_config_fsm.read() == CONFIG_TRT_LOCK)
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
                 }
                 break;
-
-
+            }
         } // end switch alloc_trt_fsm
 
@@ -9519 +9539 @@
         /////////////////////////////////////////////////////////////////////////////////////
 
-        switch(r_alloc_heap_fsm.read())
+        switch (r_alloc_heap_fsm.read())
         {
             ////////////////////
             case ALLOC_HEAP_RESET:
+            {
                 // Initializes the heap one ENTRY each cycle.
 
                 r_alloc_heap_reset_cpt.write(r_alloc_heap_reset_cpt.read() + 1);
 
-                if(r_alloc_heap_reset_cpt.read() == (m_heap_size-1))
+                if (r_alloc_heap_reset_cpt.read() == (m_heap_size - 1))
                 {
                     m_heap.init();
@@ -9534 +9555 @@
                 }
                 break;
-
-                ////////////////////
+            }
+            ////////////////////
             case ALLOC_HEAP_READ:
-                if((r_read_fsm.read() != READ_HEAP_REQ) and
-                        (r_read_fsm.read() != READ_HEAP_LOCK) and
-                        (r_read_fsm.read() != READ_HEAP_ERASE))
-                {
-                    if(r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
+            {
+                if ((r_read_fsm.read() != READ_HEAP_REQ) and
+                    (r_read_fsm.read() != READ_HEAP_LOCK) and
+                    (r_read_fsm.read() != READ_HEAP_ERASE))
+                {
+                    if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
 
-                    else if(r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
+                    else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_CAS;
 
-                    else if(r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
+                    else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
 
-                    else if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
+                    else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
 
-                    else if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+                    else if (r_config_fsm.read() == CONFIG_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
 
@@ -9560 +9582 @@
                 }
                 break;
-
-                /////////////////////
+            }
+            /////////////////////
             case ALLOC_HEAP_WRITE:
-                if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and
-                        (r_write_fsm.read() != WRITE_UPT_REQ) and
-                        (r_write_fsm.read() != WRITE_UPT_NEXT))
-                {
-                    if(r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
+            {
+                if ((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and
+                    (r_write_fsm.read() != WRITE_UPT_REQ) and
+                    (r_write_fsm.read() != WRITE_UPT_NEXT))
+                {
+                    if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_CAS;
 
-                    else if(r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
+                    else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
 
-                    else if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
+                    else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
 
-                    else if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+                    else if (r_config_fsm.read() == CONFIG_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
 
-                    else if(r_read_fsm.read() == READ_HEAP_REQ)
+                    else if (r_read_fsm.read() == READ_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_READ;
 
@@ -9586 +9609 @@
                 }
                 break;
-
-                ////////////////////
+            }
+            ////////////////////
             case ALLOC_HEAP_CAS:
-                if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and
-                        (r_cas_fsm.read() != CAS_UPT_REQ) and
-                        (r_cas_fsm.read() != CAS_UPT_NEXT))
-                {
-                    if(r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
+            {
+                if ((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and
+                    (r_cas_fsm.read() != CAS_UPT_REQ) and
+                    (r_cas_fsm.read() != CAS_UPT_NEXT))
+                {
+                    if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
 
-                    else if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
+                    else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
 
-                    else if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+                    else if (r_config_fsm.read() == CONFIG_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
 
-                    else if(r_read_fsm.read() == READ_HEAP_REQ)
+                    else if (r_read_fsm.read() == READ_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_READ;
 
-                    else if(r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
+                    else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
 
@@ -9612 +9636 @@
                 }
                 break;
-
-                ///////////////////////
+            }
+            ///////////////////////
             case ALLOC_HEAP_CLEANUP:
-                if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and
-                        (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and
-                        (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) and
-                        (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN))
-                {
-                    if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
+            {
+                if ((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and
+                    (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and
+                    (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) and
+                    (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN))
+                {
+                    if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
 
-                    else if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+                    else if (r_config_fsm.read() == CONFIG_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
 
-                    else if(r_read_fsm.read() == READ_HEAP_REQ)
+                    else if (r_read_fsm.read() == READ_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_READ;
 
-                    else if(r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
+                    else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
 
-                    else if(r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
+                    else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_CAS;
 
@@ -9639 +9664 @@
                 }
                 break;
-
-                ////////////////////////
+            }
+            ////////////////////////
             case ALLOC_HEAP_XRAM_RSP:
-                if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and
-                        (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE))
-                {
-                    if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+            {
+                if ((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and
+                    (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE))
+                {
+                    if (r_config_fsm.read() == CONFIG_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
 
-                    else if(r_read_fsm.read() == READ_HEAP_REQ)
+                    else if (r_read_fsm.read() == READ_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_READ;
 
-                    else if(r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
+                    else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
 
-                    else if(r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
+                    else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_CAS;
 
-                    else if(r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
+                    else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
 
                 }
                 break;
-
-                ///////////////////////
+            }
+            ///////////////////////
             case ALLOC_HEAP_CONFIG:
-                if((r_config_fsm.read() != CONFIG_HEAP_REQ) and
-                        (r_config_fsm.read() != CONFIG_HEAP_SCAN))
-                {
-                    if(r_read_fsm.read() == READ_HEAP_REQ)
+            {
+                if ((r_config_fsm.read() != CONFIG_HEAP_REQ) and
+                    (r_config_fsm.read() != CONFIG_HEAP_SCAN))
+                {
+                    if (r_read_fsm.read() == READ_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_READ;
 
-                    else if(r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
+                    else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
 
-                    else if(r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
+                    else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
                         r_alloc_heap_fsm = ALLOC_HEAP_CAS;
 
-                    else if(r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
+                    else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
 
-                    else if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
+                    else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
                         r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
 
@@ -9687 +9714 @@
                 }
                 break;
-
+            }
         } // end switch alloc_heap_fsm
 
@@ -9694 +9721 @@
         /////////////////////////////////////////////////////////////////////
 
-        m_cmd_read_addr_fifo.update(   cmd_read_fifo_get, cmd_read_fifo_put,
-                p_vci_tgt.address.read() );
-        m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put,
-                p_vci_tgt.plen.read()>>2 );
-        m_cmd_read_srcid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put,
-                p_vci_tgt.srcid.read() );
-        m_cmd_read_trdid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put,
-                p_vci_tgt.trdid.read() );
-        m_cmd_read_pktid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put,
-                p_vci_tgt.pktid.read() );
+        m_cmd_read_addr_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put,
+                p_vci_tgt.address.read());
+        m_cmd_read_length_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put,
+                p_vci_tgt.plen.read() >> 2);
+        m_cmd_read_srcid_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put,
+                p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put,
+                p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put,
+                p_vci_tgt.pktid.read());
 
         /////////////////////////////////////////////////////////////////////
@@ -9709 +9736 @@
         /////////////////////////////////////////////////////////////////////
 
-        m_cmd_write_addr_fifo.update(  cmd_write_fifo_get, cmd_write_fifo_put,
-                (addr_t)p_vci_tgt.address.read() );
-        m_cmd_write_eop_fifo.update(   cmd_write_fifo_get, cmd_write_fifo_put,
-                p_vci_tgt.eop.read() );
-        m_cmd_write_srcid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put,
-                p_vci_tgt.srcid.read() );
-        m_cmd_write_trdid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put,
-                p_vci_tgt.trdid.read() );
-        m_cmd_write_pktid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put,
-                p_vci_tgt.pktid.read() );
-        m_cmd_write_data_fifo.update(  cmd_write_fifo_get, cmd_write_fifo_put,
-                p_vci_tgt.wdata.read() );
-        m_cmd_write_be_fifo.update(    cmd_write_fifo_get, cmd_write_fifo_put,
-                p_vci_tgt.be.read() );
+        m_cmd_write_addr_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put,
+                (addr_t)p_vci_tgt.address.read());
+        m_cmd_write_eop_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put,
+                p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put,
+                p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put,
+                p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put,
+                p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put,
+                p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put,
+                p_vci_tgt.be.read());
 
         ////////////////////////////////////////////////////////////////////////////////////
@@ -9728 +9755 @@
         ////////////////////////////////////////////////////////////////////////////////////
 
-        m_cmd_cas_addr_fifo.update(  cmd_cas_fifo_get, cmd_cas_fifo_put,
-                (addr_t)p_vci_tgt.address.read() );
-        m_cmd_cas_eop_fifo.update(   cmd_cas_fifo_get, cmd_cas_fifo_put,
-                p_vci_tgt.eop.read() );
-        m_cmd_cas_srcid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put,
-                p_vci_tgt.srcid.read() );
-        m_cmd_cas_trdid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put,
-                p_vci_tgt.trdid.read() );
-        m_cmd_cas_pktid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put,
-                p_vci_tgt.pktid.read() );
-        m_cmd_cas_wdata_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put,
-                p_vci_tgt.wdata.read() );
+        m_cmd_cas_addr_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put,
+                (addr_t)p_vci_tgt.address.read());
+        m_cmd_cas_eop_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put,
+                p_vci_tgt.eop.read());
+        m_cmd_cas_srcid_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put,
+                p_vci_tgt.srcid.read());
+        m_cmd_cas_trdid_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put,
+                p_vci_tgt.trdid.read());
+        m_cmd_cas_pktid_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put,
+                p_vci_tgt.pktid.read());
+        m_cmd_cas_wdata_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put,
+                p_vci_tgt.wdata.read());
 
         ////////////////////////////////////////////////////////////////////////////////////
@@ -9745 +9772 @@
         ////////////////////////////////////////////////////////////////////////////////////
 
-        if(cc_receive_to_cleanup_fifo_put)
+        if (cc_receive_to_cleanup_fifo_put)
         {
-            if(cc_receive_to_cleanup_fifo_get)
-            {
-                m_cc_receive_to_cleanup_fifo.put_and_get( ((uint64_t)(p_dspin_p2m.eop.read()&0x1) << 32) | p_dspin_p2m.data.read() );
+            if (cc_receive_to_cleanup_fifo_get)
+            {
+                m_cc_receive_to_cleanup_fifo.put_and_get(((uint64_t) (p_dspin_p2m.eop.read() & 0x1) << 32) | p_dspin_p2m.data.read());
             }
             else
             {
-                m_cc_receive_to_cleanup_fifo.simple_put( ((uint64_t)(p_dspin_p2m.eop.read()&0x1) << 32) | p_dspin_p2m.data.read() );
+                m_cc_receive_to_cleanup_fifo.simple_put(((uint64_t) (p_dspin_p2m.eop.read() & 0x1) << 32) | p_dspin_p2m.data.read());
             }
         }
         else
         {
-            if(cc_receive_to_cleanup_fifo_get)
+            if (cc_receive_to_cleanup_fifo_get)
             {
                 m_cc_receive_to_cleanup_fifo.simple_get();
@@ -9768 +9795 @@
         ////////////////////////////////////////////////////////////////////////////////////
 
-        m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get,
+        m_cc_receive_to_multi_ack_fifo.update(cc_receive_to_multi_ack_fifo_get,
                 cc_receive_to_multi_ack_fifo_put,
-                p_dspin_p2m.data.read() );
+                p_dspin_p2m.data.read());
 
         ////////////////////////////////////////////////////////////////////////////////////
@@ -9776 +9803 @@
         ////////////////////////////////////////////////////////////////////////////////////
 
-        m_write_to_cc_send_inst_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put,
-                write_to_cc_send_fifo_inst );
-        m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put,
-                write_to_cc_send_fifo_srcid );
+        m_write_to_cc_send_inst_fifo.update(write_to_cc_send_fifo_get,
+                write_to_cc_send_fifo_put,
+                write_to_cc_send_fifo_inst);
+        m_write_to_cc_send_srcid_fifo.update(write_to_cc_send_fifo_get,
+                write_to_cc_send_fifo_put,
+                write_to_cc_send_fifo_srcid);
 
         ////////////////////////////////////////////////////////////////////////////////////
@@ -9785 +9814 @@
         ////////////////////////////////////////////////////////////////////////////////////
 
-        m_config_to_cc_send_inst_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put,
-                config_to_cc_send_fifo_inst );
-        m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put,
-                config_to_cc_send_fifo_srcid );
+        m_config_to_cc_send_inst_fifo.update(config_to_cc_send_fifo_get,
+                config_to_cc_send_fifo_put,
+                config_to_cc_send_fifo_inst);
+        m_config_to_cc_send_srcid_fifo.update(config_to_cc_send_fifo_get,
+                config_to_cc_send_fifo_put,
+                config_to_cc_send_fifo_srcid);
 
         ////////////////////////////////////////////////////////////////////////////////////
@@ -9794 +9825 @@
         ////////////////////////////////////////////////////////////////////////////////////
 
-        m_xram_rsp_to_cc_send_inst_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put,
-                xram_rsp_to_cc_send_fifo_inst );
-        m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put,
-                xram_rsp_to_cc_send_fifo_srcid );
+        m_xram_rsp_to_cc_send_inst_fifo.update(xram_rsp_to_cc_send_fifo_get,
+                xram_rsp_to_cc_send_fifo_put,
+                xram_rsp_to_cc_send_fifo_inst);
+        m_xram_rsp_to_cc_send_srcid_fifo.update(xram_rsp_to_cc_send_fifo_get,
+                xram_rsp_to_cc_send_fifo_put,
+                xram_rsp_to_cc_send_fifo_srcid);
 
         ////////////////////////////////////////////////////////////////////////////////////
@@ -9803 +9836 @@
         ////////////////////////////////////////////////////////////////////////////////////
 
-        m_cas_to_cc_send_inst_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put,
-                cas_to_cc_send_fifo_inst );
-        m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put,
-                cas_to_cc_send_fifo_srcid );
+        m_cas_to_cc_send_inst_fifo.update(cas_to_cc_send_fifo_get,
+                cas_to_cc_send_fifo_put,
+                cas_to_cc_send_fifo_inst);
+        m_cas_to_cc_send_srcid_fifo.update(cas_to_cc_send_fifo_get,
+                cas_to_cc_send_fifo_put,
+                cas_to_cc_send_fifo_srcid);
         m_cpt_cycles++;
 
@@ -9813 +9848 @@
         // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs
         ////////////////////////////////////////////////////////////////////////////////////
-        if ( config_rsp_lines_incr and not
-             (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) )
+        if (config_rsp_lines_incr and not
+             (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr))
         {
             r_config_rsp_lines = r_config_rsp_lines.read() + 1;
         }
-        if ( not config_rsp_lines_incr and
-             (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) )
+        if (not config_rsp_lines_incr and
+             (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr))
         {
             r_config_rsp_lines = r_config_rsp_lines.read() - 1;
@@ -9839 +9874 @@
     {
 #if MONITOR_MEMCACHE_FSM == 1
-        p_read_fsm.write        (r_read_fsm.read()       );
-        p_write_fsm.write       (r_write_fsm.read()      );
-        p_xram_rsp_fsm.write    (r_xram_rsp_fsm.read()   );
-        p_cas_fsm.write         (r_cas_fsm.read()        );
-        p_cleanup_fsm.write     (r_cleanup_fsm.read()    );
-        p_config_fsm.write      (r_config_fsm.read()     );
-        p_alloc_heap_fsm.write  (r_alloc_heap_fsm.read() );
-        p_alloc_dir_fsm.write   (r_alloc_dir_fsm.read()  );
-        p_alloc_trt_fsm.write   (r_alloc_trt_fsm.read()  );
-        p_alloc_upt_fsm.write   (r_alloc_upt_fsm.read()  );
-        p_alloc_ivt_fsm.write   (r_alloc_ivt_fsm.read()  );
-        p_tgt_cmd_fsm.write     (r_tgt_cmd_fsm.read()    );
-        p_tgt_rsp_fsm.write     (r_tgt_rsp_fsm.read()    );
-        p_ixr_cmd_fsm.write     (r_ixr_cmd_fsm.read()    );
-        p_ixr_rsp_fsm.write     (r_ixr_rsp_fsm.read()    );
-        p_cc_send_fsm.write     (r_cc_send_fsm.read()    );
-        p_cc_receive_fsm.write  (r_cc_receive_fsm.read() );
-        p_multi_ack_fsm.write   (r_multi_ack_fsm.read()  );
+        p_read_fsm.write      (r_read_fsm.read());
+        p_write_fsm.write     (r_write_fsm.read());
+        p_xram_rsp_fsm.write  (r_xram_rsp_fsm.read());
+        p_cas_fsm.write       (r_cas_fsm.read());
+        p_cleanup_fsm.write   (r_cleanup_fsm.read());
+        p_config_fsm.write    (r_config_fsm.read());
+        p_alloc_heap_fsm.write(r_alloc_heap_fsm.read());
+        p_alloc_dir_fsm.write (r_alloc_dir_fsm.read());
+        p_alloc_trt_fsm.write (r_alloc_trt_fsm.read());
+        p_alloc_upt_fsm.write (r_alloc_upt_fsm.read());
+        p_alloc_ivt_fsm.write (r_alloc_ivt_fsm.read());
+        p_tgt_cmd_fsm.write   (r_tgt_cmd_fsm.read());
+        p_tgt_rsp_fsm.write   (r_tgt_rsp_fsm.read());
+        p_ixr_cmd_fsm.write   (r_ixr_cmd_fsm.read());
+        p_ixr_rsp_fsm.write   (r_ixr_rsp_fsm.read());
+        p_cc_send_fsm.write   (r_cc_send_fsm.read());
+        p_cc_receive_fsm.write(r_cc_receive_fsm.read());
+        p_multi_ack_fsm.write (r_multi_ack_fsm.read());
 #endif
 
@@ -9862 +9897 @@
         // Command signals on the p_vci_ixr port
         ////////////////////////////////////////////////////////////
+
         // DATA width is 8 bytes
         // The following values are not transmitted to XRAM
@@ -9875 +9911 @@
         p_vci_ixr.srcid   = m_srcid_x;
         p_vci_ixr.trdid   = r_ixr_cmd_trdid.read();
-        p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2);
+        p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2);
         p_vci_ixr.be      = 0xFF;
         p_vci_ixr.pktid   = 0;
@@ -9884 +9920 @@
         p_vci_ixr.cfixed  = false;
 
-        if ( (r_ixr_cmd_fsm.read() == IXR_CMD_READ_SEND) or
-                (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_SEND) or
-                (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_SEND) or
-                (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_SEND) or
-                (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_SEND) )
+        if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_SEND) or
+            (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_SEND) or
+            (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_SEND) or
+            (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_SEND) or
+            (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_SEND))
         {
-            p_vci_ixr.cmdval    = true;
-
-            if ( r_ixr_cmd_get.read() )  // GET
-            {
-                p_vci_ixr.cmd     = vci_param_ext::CMD_READ;
-                p_vci_ixr.wdata   = 0;
-                p_vci_ixr.eop     = true;
+            p_vci_ixr.cmdval = true;
+
+            if (r_ixr_cmd_get.read())  // GET
+            {
+                p_vci_ixr.cmd   = vci_param_ext::CMD_READ;
+                p_vci_ixr.wdata = 0;
+                p_vci_ixr.eop   = true;
             }
             else                         // PUT
             {
-                size_t word       = r_ixr_cmd_word.read();
-                p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
-                p_vci_ixr.wdata   = ((wide_data_t)(r_ixr_cmd_wdata[word].read()))  |
-                    ((wide_data_t)(r_ixr_cmd_wdata[word+1].read()) << 32);
-                p_vci_ixr.eop     = (word == (m_words-2));
+                size_t word     = r_ixr_cmd_word.read();
+                p_vci_ixr.cmd   = vci_param_ext::CMD_WRITE;
+                p_vci_ixr.wdata = ((wide_data_t) (r_ixr_cmd_wdata[word].read())) |
+                    ((wide_data_t) (r_ixr_cmd_wdata[word + 1].read()) << 32);
+                p_vci_ixr.eop   = (word == (m_words - 2));
             }
         }
@@ -9911 +9947 @@
             p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
             p_vci_ixr.cmdval  = true;
-            p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2);
-            p_vci_ixr.wdata   = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) |
-                    ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read() + 1].read()) << 32));
+            p_vci_ixr.address = (addr_t) r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2);
+            p_vci_ixr.wdata   = ((wide_data_t) (r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) |
+                    ((wide_data_t) (r_ixr_cmd_wdata[r_ixr_cmd_word.read() + 1].read()) << 32));
             p_vci_ixr.trdid   = r_cleanup_to_ixr_cmd_index.read();
             p_vci_ixr.eop     = (r_ixr_cmd_word == (m_words - 2));
         }
-
         else
         {
-            p_vci_ixr.cmdval    = false;
+            p_vci_ixr.cmdval = false;
         }
 
@@ -9927 +9962 @@
         ////////////////////////////////////////////////////
 
-        if( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or
-                (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) )
+        if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or
+            (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE))
         {
             p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP);
-        }
-        else if (r_ixr_rsp_fsm.read() == IXR_RSP_ACK)
-        {
-            p_vci_ixr.rspack = true;
         }
         else // r_ixr_rsp_fsm == IXR_RSP_IDLE
@@ -9945 +9976 @@
         ////////////////////////////////////////////////////
 
-        switch((tgt_cmd_fsm_state_e) r_tgt_cmd_fsm.read())
+        switch ((tgt_cmd_fsm_state_e) r_tgt_cmd_fsm.read())
         {
             case TGT_CMD_IDLE:
@@ -9952 +9983 @@
 
             case TGT_CMD_CONFIG:
+            {
+                addr_t addr_lsb = p_vci_tgt.address.read() &
+                                  m_config_addr_mask;
+
+                addr_t cell = (addr_lsb / vci_param_int::B);
+
+                size_t regr = cell & m_config_regr_idx_mask;
+
+                size_t func = (cell >> m_config_regr_width) &
+                              m_config_func_idx_mask;
+
+                switch (func)
+                {
+                    case MEMC_CONFIG:
+                        if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
+                                and (regr == MEMC_CMD_TYPE))
+                        {
+                            p_vci_tgt.cmdack = true;
+                        }
+                        else
+                        {
+                            p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read();
+                        }
+                        break;
+
+                    default:
+                        p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read();
+                        break;
+                }
+
+                break;
+            }
             case TGT_CMD_ERROR:
                 p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read();
@@ -9973 +10036 @@
         ////////////////////////////////////////////////////
 
-        switch(r_tgt_rsp_fsm.read())
+        switch (r_tgt_rsp_fsm.read())
         {
             case TGT_RSP_CONFIG_IDLE:
@@ -9983 +10046 @@
             case TGT_RSP_MULTI_ACK_IDLE:
             case TGT_RSP_CLEANUP_IDLE:
-                {
-                    p_vci_tgt.rspval  = false;
-                    p_vci_tgt.rsrcid  = 0;
-                    p_vci_tgt.rdata   = 0;
-                    p_vci_tgt.rpktid  = 0;
-                    p_vci_tgt.rtrdid  = 0;
-                    p_vci_tgt.rerror  = 0;
-                    p_vci_tgt.reop    = false;
-                    break;
-                }
+            {
+                p_vci_tgt.rspval = false;
+                p_vci_tgt.rsrcid = 0;
+                p_vci_tgt.rdata  = 0;
+                p_vci_tgt.rpktid = 0;
+                p_vci_tgt.rtrdid = 0;
+                p_vci_tgt.rerror = 0;
+                p_vci_tgt.reop   = false;
+                break;
+            }
             case TGT_RSP_CONFIG:
-                {
-                    p_vci_tgt.rspval  = true;
-                    p_vci_tgt.rdata   = 0;
-                    p_vci_tgt.rsrcid  = r_config_to_tgt_rsp_srcid.read();
-                    p_vci_tgt.rtrdid  = r_config_to_tgt_rsp_trdid.read();
-                    p_vci_tgt.rpktid  = r_config_to_tgt_rsp_pktid.read();
-                    p_vci_tgt.rerror  = r_config_to_tgt_rsp_error.read();
-                    p_vci_tgt.reop    = true;
-
-                    break;
-                }
-
+            {
+                p_vci_tgt.rspval = true;
+                p_vci_tgt.rdata  = 0;
+                p_vci_tgt.rsrcid = r_config_to_tgt_rsp_srcid.read();
+                p_vci_tgt.rtrdid = r_config_to_tgt_rsp_trdid.read();
+                p_vci_tgt.rpktid = r_config_to_tgt_rsp_pktid.read();
+                p_vci_tgt.rerror = r_config_to_tgt_rsp_error.read();
+                p_vci_tgt.reop   = true;
+                break;
+            }
             case TGT_RSP_TGT_CMD:
-                {
-                    p_vci_tgt.rspval  = true;
-                    p_vci_tgt.rdata   = r_tgt_cmd_to_tgt_rsp_rdata.read();
-                    p_vci_tgt.rsrcid  = r_tgt_cmd_to_tgt_rsp_srcid.read();
-                    p_vci_tgt.rtrdid  = r_tgt_cmd_to_tgt_rsp_trdid.read();
-                    p_vci_tgt.rpktid  = r_tgt_cmd_to_tgt_rsp_pktid.read();
-                    p_vci_tgt.rerror  = r_tgt_cmd_to_tgt_rsp_error.read();
-                    p_vci_tgt.reop    = true;
-
-                    break;
-                }
-
+            {
+                p_vci_tgt.rspval = true;
+                p_vci_tgt.rdata  = r_tgt_cmd_to_tgt_rsp_rdata.read();
+                p_vci_tgt.rsrcid = r_tgt_cmd_to_tgt_rsp_srcid.read();
+                p_vci_tgt.rtrdid = r_tgt_cmd_to_tgt_rsp_trdid.read();
+                p_vci_tgt.rpktid = r_tgt_cmd_to_tgt_rsp_pktid.read();
+                p_vci_tgt.rerror = r_tgt_cmd_to_tgt_rsp_error.read();
+                p_vci_tgt.reop   = true;
+                break;
+            }
             case TGT_RSP_READ:
-                {
-                    uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length - 1;
-                    bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
-                    bool     is_ll         = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
-
-                    p_vci_tgt.rspval  = true;
-
-                    if ( is_ll and not r_tgt_rsp_key_sent.read() )
-                    {
-                        // LL response first flit
-                        p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read();
-                    }
-                    else
-                    {
-                        // LL response second flit or READ response
-                        p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
-                    }
-
-                    p_vci_tgt.rsrcid  = r_read_to_tgt_rsp_srcid.read();
-                    p_vci_tgt.rtrdid  = r_read_to_tgt_rsp_trdid.read();
-                    p_vci_tgt.rpktid  = r_read_to_tgt_rsp_pktid.read();
-                    p_vci_tgt.rerror  = 0;
-                    p_vci_tgt.reop    = (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll);
-                    break;
-                }
+            {
+                uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length - 1;
+                bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx);
+                bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+
+                p_vci_tgt.rspval  = true;
+
+                if (is_ll and not r_tgt_rsp_key_sent.read())
+                {
+                    // LL response first flit
+                    p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read();
+                }
+                else
+                {
+                    // LL response second flit or READ response
+                    p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+                }
+
+                p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read();
+                p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read();
+                p_vci_tgt.rpktid = r_read_to_tgt_rsp_pktid.read();
+                p_vci_tgt.rerror = 0;
+                p_vci_tgt.reop   = (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll);
+                break;
+            }
 
             case TGT_RSP_WRITE:
-                p_vci_tgt.rspval   = true;
-                if(((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read())
-                    p_vci_tgt.rdata  = 1;
+                p_vci_tgt.rspval = true;
+                if (((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read())
+                    p_vci_tgt.rdata = 1;
                 else
-                    p_vci_tgt.rdata  = 0;
-                p_vci_tgt.rsrcid   = r_write_to_tgt_rsp_srcid.read();
-                p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
-                p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
-                p_vci_tgt.rerror   = 0;
-                p_vci_tgt.reop     = true;
+                    p_vci_tgt.rdata = 0;
+                p_vci_tgt.rsrcid = r_write_to_tgt_rsp_srcid.read();
+                p_vci_tgt.rtrdid = r_write_to_tgt_rsp_trdid.read();
+                p_vci_tgt.rpktid = r_write_to_tgt_rsp_pktid.read();
+                p_vci_tgt.rerror = 0;
+                p_vci_tgt.reop   = true;
                 break;
 
             case TGT_RSP_CLEANUP:
-                {
-                    uint32_t last_word_idx = r_cleanup_to_tgt_rsp_first_word.read() + r_cleanup_to_tgt_rsp_length - 1;
-                    bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
-                    bool     is_ll         = ((r_cleanup_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
-
-                    p_vci_tgt.rspval   = true;
-                    if (is_ll and not r_tgt_rsp_key_sent.read())
-                    {
-                        p_vci_tgt.rdata   = r_cleanup_to_tgt_rsp_ll_key.read();
-                    }
-                    else if (!r_cleanup_to_tgt_rsp_type.read())
-                    {
-                        p_vci_tgt.rdata    = r_cleanup_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
-                    }
-                    else  //if the CLEANUP fsm sends a SC_RSP, then it is a success (and it caused an inval)
-                    {
-                        p_vci_tgt.rdata    = 0;
-                    }
-                    p_vci_tgt.rsrcid   = r_cleanup_to_tgt_rsp_srcid.read();
-                    p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
-                    p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
-                    p_vci_tgt.rerror   = 0; // Can be a CAS rsp
-                    p_vci_tgt.reop     = r_cleanup_to_tgt_rsp_type.read() or (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll);
-                    break;
-                }
+            {
+                uint32_t last_word_idx = r_cleanup_to_tgt_rsp_first_word.read() + r_cleanup_to_tgt_rsp_length - 1;
+                bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx);
+                bool is_ll = ((r_cleanup_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+
+                p_vci_tgt.rspval = true;
+                if (is_ll and not r_tgt_rsp_key_sent.read())
+                {
+                    p_vci_tgt.rdata = r_cleanup_to_tgt_rsp_ll_key.read();
+                }
+                else if (!r_cleanup_to_tgt_rsp_type.read())
+                {
+                    p_vci_tgt.rdata = r_cleanup_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+                }
+                else  // if the CLEANUP fsm sends a SC_RSP, then it is a success (and it caused an inval)
+                {
+                    p_vci_tgt.rdata = 0;
+                }
+                p_vci_tgt.rsrcid = r_cleanup_to_tgt_rsp_srcid.read();
+                p_vci_tgt.rtrdid = r_cleanup_to_tgt_rsp_trdid.read();
+                p_vci_tgt.rpktid = r_cleanup_to_tgt_rsp_pktid.read();
+                p_vci_tgt.rerror = 0; // Can be a CAS rsp
+                p_vci_tgt.reop   = r_cleanup_to_tgt_rsp_type.read() or (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll);
+                break;
+            }
 
             case TGT_RSP_CAS:
-                p_vci_tgt.rspval   = true;
-                p_vci_tgt.rdata    = r_cas_to_tgt_rsp_data.read();
-                p_vci_tgt.rsrcid   = r_cas_to_tgt_rsp_srcid.read();
-                p_vci_tgt.rtrdid   = r_cas_to_tgt_rsp_trdid.read();
-                p_vci_tgt.rpktid   = r_cas_to_tgt_rsp_pktid.read();
-                p_vci_tgt.rerror   = 0;
-                p_vci_tgt.reop     = true;
+                p_vci_tgt.rspval = true;
+                p_vci_tgt.rdata  = r_cas_to_tgt_rsp_data.read();
+                p_vci_tgt.rsrcid = r_cas_to_tgt_rsp_srcid.read();
+                p_vci_tgt.rtrdid = r_cas_to_tgt_rsp_trdid.read();
+                p_vci_tgt.rpktid = r_cas_to_tgt_rsp_pktid.read();
+                p_vci_tgt.rerror = 0;
+                p_vci_tgt.reop   = true;
                 break;
 
@@ -10103 +10162 @@
                     bool     is_error      = r_xram_rsp_to_tgt_rsp_rerror.read();
 
-                    p_vci_tgt.rspval  = true;
-
-                    if( is_ll and not r_tgt_rsp_key_sent.read() )
+                    p_vci_tgt.rspval = true;
+
+                    if (is_ll and not r_tgt_rsp_key_sent.read())
                     {
                         // LL response first flit
@@ -10116 +10175 @@
                     }
 
-                    p_vci_tgt.rsrcid  = r_xram_rsp_to_tgt_rsp_srcid.read();
-                    p_vci_tgt.rtrdid  = r_xram_rsp_to_tgt_rsp_trdid.read();
-                    p_vci_tgt.rpktid  = r_xram_rsp_to_tgt_rsp_pktid.read();
-                    p_vci_tgt.rerror  = is_error;
-                    p_vci_tgt.reop    = (((is_last_word or is_error) and not is_ll) or
+                    p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read();
+                    p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read();
+                    p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read();
+                    p_vci_tgt.rerror = is_error;
+                    p_vci_tgt.reop   = (((is_last_word or is_error) and not is_ll) or
                             (r_tgt_rsp_key_sent.read() and     is_ll));
-
                     break;
                 }
 
             case TGT_RSP_MULTI_ACK:
-                p_vci_tgt.rspval   = true;
-                p_vci_tgt.rdata    = 0; // Can be a CAS or SC rsp
-                p_vci_tgt.rsrcid   = r_multi_ack_to_tgt_rsp_srcid.read();
-                p_vci_tgt.rtrdid   = r_multi_ack_to_tgt_rsp_trdid.read();
-                p_vci_tgt.rpktid   = r_multi_ack_to_tgt_rsp_pktid.read();
-                p_vci_tgt.rerror   = 0;
-                p_vci_tgt.reop     = true;
+                p_vci_tgt.rspval = true;
+                p_vci_tgt.rdata  = 0; // Can be a CAS or SC rsp
+                p_vci_tgt.rsrcid = r_multi_ack_to_tgt_rsp_srcid.read();
+                p_vci_tgt.rtrdid = r_multi_ack_to_tgt_rsp_trdid.read();
+                p_vci_tgt.rpktid = r_multi_ack_to_tgt_rsp_pktid.read();
+                p_vci_tgt.rerror = 0;
+                p_vci_tgt.reop   = true;
                 break;
         } // end switch r_tgt_rsp_fsm
@@ -10155 +10213 @@
         p_dspin_m2p.data  = 0;
 
-        switch(r_cc_send_fsm.read())
+        switch (r_cc_send_fsm.read())
         {
             ///////////////////////////
@@ -10162 +10220 @@
             case CC_SEND_WRITE_IDLE:
             case CC_SEND_CAS_IDLE:
-                {
-                    break;
-                }
-                ////////////////////////////////
+            {
+                break;
+            }
+            ////////////////////////////////
             case CC_SEND_CONFIG_INVAL_HEADER:
-                {
-                    uint8_t multi_inval_type;
-                    if(m_config_to_cc_send_inst_fifo.read())
-                    {
-                        multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_INST;
-                    }
-                    else
-                    {
-                        multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_DATA;
-                    }
-
-                    uint64_t flit = 0;
-                    uint64_t dest = m_config_to_cc_send_srcid_fifo.read() <<
-                        (DspinRwtParam::SRCID_WIDTH - vci_param_int::S);
-
-                    DspinRwtParam::dspin_set( flit,
-                            dest,
-                            DspinRwtParam::MULTI_INVAL_DEST);
-
-                    // MODIFIED FOR CONFIG INVAL (solution 1 bit in flit multi_inval)
-                    DspinRwtParam::dspin_set( flit,
-                            1,
-                            DspinRwtParam::MULTI_INVAL_IS_CONFIG);
-
-                    DspinRwtParam::dspin_set( flit,
-                            r_config_to_cc_send_trdid.read(),
-                            DspinRwtParam::MULTI_INVAL_UPDT_INDEX);
-
-                    DspinRwtParam::dspin_set( flit,
-                            multi_inval_type,
-                            DspinRwtParam::M2P_TYPE);
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-                ////////////////////////////////
+            {
+                uint8_t multi_inval_type;
+                if (m_config_to_cc_send_inst_fifo.read())
+                {
+                    multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_INST;
+                }
+                else
+                {
+                    multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_DATA;
+                }
+
+                uint64_t flit = 0;
+                uint64_t dest = m_config_to_cc_send_srcid_fifo.read() <<
+                    (DspinRwtParam::SRCID_WIDTH - vci_param_int::S);
+
+                DspinRwtParam::dspin_set(flit,
+                                         dest,
+                                         DspinRwtParam::MULTI_INVAL_DEST);
+
+                DspinRwtParam::dspin_set(flit,
+                                         1,
+                                         DspinRwtParam::MULTI_INVAL_IS_CONFIG);
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_config_to_cc_send_trdid.read(),
+                                         DspinRwtParam::MULTI_INVAL_UPDT_INDEX);
+
+                DspinRwtParam::dspin_set(flit,
+                                         multi_inval_type,
+                                         DspinRwtParam::M2P_TYPE);
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+            ////////////////////////////////
             case CC_SEND_CONFIG_INVAL_NLINE:
-                {
-                    uint64_t flit = 0;
-                    DspinRwtParam::dspin_set( flit,
-                            r_config_to_cc_send_nline.read(),
-                            DspinRwtParam::MULTI_INVAL_NLINE);
-                    p_dspin_m2p.eop   = true;
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-                ///////////////////////////////////
+            {
+                uint64_t flit = 0;
+                DspinRwtParam::dspin_set(flit,
+                                         r_config_to_cc_send_nline.read(),
+                                         DspinRwtParam::MULTI_INVAL_NLINE);
+                p_dspin_m2p.eop   = true;
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+            ///////////////////////////////////
             case CC_SEND_XRAM_RSP_INVAL_HEADER:
-                {
-                    if(not m_xram_rsp_to_cc_send_inst_fifo.rok()) break;
-
-                    uint8_t multi_inval_type;
-                    if(m_xram_rsp_to_cc_send_inst_fifo.read())
-                    {
-                        multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_INST;
-                    }
-                    else
-                    {
-                        multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_DATA;
-                    }
-
-                    uint64_t flit = 0;
-                    uint64_t dest = m_xram_rsp_to_cc_send_srcid_fifo.read() <<
-                        (DspinRwtParam::SRCID_WIDTH - vci_param_int::S);
-
-                    DspinRwtParam::dspin_set( flit,
-                            dest,
-                            DspinRwtParam::MULTI_INVAL_DEST);
-
-                    DspinRwtParam::dspin_set( flit,
-                            r_xram_rsp_to_cc_send_trdid.read(),
-                            DspinRwtParam::MULTI_INVAL_UPDT_INDEX);
-
-                    DspinRwtParam::dspin_set( flit,
-                            multi_inval_type,
-                            DspinRwtParam::M2P_TYPE);
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-
-                //////////////////////////////////
+            {
+                if (not m_xram_rsp_to_cc_send_inst_fifo.rok()) break;
+
+                uint8_t multi_inval_type;
+                if (m_xram_rsp_to_cc_send_inst_fifo.read())
+                {
+                    multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_INST;
+                }
+                else
+                {
+                    multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_DATA;
+                }
+
+                uint64_t flit = 0;
+                uint64_t dest = m_xram_rsp_to_cc_send_srcid_fifo.read() <<
+                    (DspinRwtParam::SRCID_WIDTH - vci_param_int::S);
+
+                DspinRwtParam::dspin_set(flit,
+                                         dest,
+                                         DspinRwtParam::MULTI_INVAL_DEST);
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_xram_rsp_to_cc_send_trdid.read(),
+                                         DspinRwtParam::MULTI_INVAL_UPDT_INDEX);
+
+                DspinRwtParam::dspin_set(flit,
+                                         multi_inval_type,
+                                         DspinRwtParam::M2P_TYPE);
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+
+            //////////////////////////////////
             case CC_SEND_XRAM_RSP_INVAL_NLINE:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set( flit,
-                            r_xram_rsp_to_cc_send_nline.read(),
-                            DspinRwtParam::MULTI_INVAL_NLINE);
-                    p_dspin_m2p.eop   = true;
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-
-                /////////////////////////////////////
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_xram_rsp_to_cc_send_nline.read(),
+                                         DspinRwtParam::MULTI_INVAL_NLINE);
+                p_dspin_m2p.eop   = true;
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+
+            /////////////////////////////////////
             case CC_SEND_CONFIG_BRDCAST_HEADER:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set( flit,
-                            m_broadcast_boundaries,
-                            DspinRwtParam::BROADCAST_BOX);
-
-                    DspinRwtParam::dspin_set( flit,
-                            1,
-                            DspinRwtParam::MULTI_INVAL_IS_CONFIG);
-
-                    DspinRwtParam::dspin_set( flit,
-                            1ULL,
-                            DspinRwtParam::M2P_BC);
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-                /////////////////////////////////////
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         m_broadcast_boundaries,
+                                         DspinRwtParam::BROADCAST_BOX);
+
+                DspinRwtParam::dspin_set(flit,
+                                         1,
+                                         DspinRwtParam::MULTI_INVAL_IS_CONFIG);
+
+                DspinRwtParam::dspin_set(flit,
+                                         1ULL,
+                                         DspinRwtParam::M2P_BC);
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+            /////////////////////////////////////
             case CC_SEND_XRAM_RSP_BRDCAST_HEADER:
             case CC_SEND_WRITE_BRDCAST_HEADER:
             case CC_SEND_CAS_BRDCAST_HEADER:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set( flit,
-                            m_broadcast_boundaries,
-                            DspinRwtParam::BROADCAST_BOX);
-
-                    DspinRwtParam::dspin_set( flit,
-                            1ULL,
-                            DspinRwtParam::M2P_BC);
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-                ////////////////////////////////////
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         m_broadcast_boundaries,
+                                         DspinRwtParam::BROADCAST_BOX);
+
+                DspinRwtParam::dspin_set(flit,
+                                         1ULL,
+                                         DspinRwtParam::M2P_BC);
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+            ////////////////////////////////////
             case CC_SEND_XRAM_RSP_BRDCAST_NLINE:
-                {
-                    uint64_t flit = 0;
-                    DspinRwtParam::dspin_set( flit,
-                            r_xram_rsp_to_cc_send_nline.read(),
-                            DspinRwtParam::BROADCAST_NLINE);
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.eop   = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-                //////////////////////////////////
+            {
+                uint64_t flit = 0;
+                DspinRwtParam::dspin_set(flit,
+                                         r_xram_rsp_to_cc_send_nline.read(),
+                                         DspinRwtParam::BROADCAST_NLINE);
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.eop   = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+            //////////////////////////////////
             case CC_SEND_CONFIG_BRDCAST_NLINE:
-                {
-                    uint64_t flit = 0;
-                    DspinRwtParam::dspin_set( flit,
-                            r_config_to_cc_send_nline.read(),
-                            DspinRwtParam::BROADCAST_NLINE);
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.eop   = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-                /////////////////////////////////
-
+            {
+                uint64_t flit = 0;
+                DspinRwtParam::dspin_set(flit,
+                                         r_config_to_cc_send_nline.read(),
+                                         DspinRwtParam::BROADCAST_NLINE);
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.eop   = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+            /////////////////////////////////
             case CC_SEND_READ_NCC_INVAL_HEADER:
-                {
-                    uint64_t flit = 0;
-
-                    //uint8_t multi_inval_type;
-                    //if (r_read_to_cc_send_inst.read())
-                    //{
-                    //    multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_INST;
-                    //}
-                    //else
-                    //{
-                    //    multi_inval_type = DspinRwtParam::TYPE_MULTI_INVAL_DATA;
-                    //}
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_read_to_cc_send_dest.read(),
-                            DspinRwtParam::MULTI_INVAL_DEST);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            DspinRwtParam::TYPE_MULTI_INVAL_DATA,
-                            DspinRwtParam::M2P_TYPE);
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-
-                    break;
-
-                }
-
-
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_read_to_cc_send_dest.read(),
+                                         DspinRwtParam::MULTI_INVAL_DEST);
+
+                DspinRwtParam::dspin_set(flit,
+                                         DspinRwtParam::TYPE_MULTI_INVAL_DATA,
+                                         DspinRwtParam::M2P_TYPE);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+
+                break;
+            }
+            /////////////////////////////////
             case CC_SEND_READ_NCC_INVAL_NLINE:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_read_to_cc_send_nline.read(),
-                            DspinRwtParam::MULTI_INVAL_NLINE);
-
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-                    p_dspin_m2p.eop   = true;
-
-                    break;
-
-                }
-
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_read_to_cc_send_nline.read(),
+                                         DspinRwtParam::MULTI_INVAL_NLINE);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+                p_dspin_m2p.eop   = true;
+
+                break;
+            }
+            /////////////////////////////////
             case CC_SEND_WRITE_NCC_INVAL_HEADER:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_write_to_cc_send_dest.read(),
-                            DspinRwtParam::MULTI_INVAL_DEST);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            DspinRwtParam::TYPE_MULTI_INVAL_DATA,
-                            DspinRwtParam::M2P_TYPE);
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-
-                    break;
-
-                }
-
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_write_to_cc_send_dest.read(),
+                                         DspinRwtParam::MULTI_INVAL_DEST);
+
+                DspinRwtParam::dspin_set(flit,
+                                         DspinRwtParam::TYPE_MULTI_INVAL_DATA,
+                                         DspinRwtParam::M2P_TYPE);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+
+                break;
+            }
+            /////////////////////////////////
             case CC_SEND_WRITE_NCC_INVAL_NLINE:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_write_to_cc_send_nline.read(),
-                            DspinRwtParam::MULTI_INVAL_NLINE);
-
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-                    p_dspin_m2p.eop   = true;
-
-                    break;
-
-                }
-
-
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_write_to_cc_send_nline.read(),
+                                         DspinRwtParam::MULTI_INVAL_NLINE);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+                p_dspin_m2p.eop   = true;
+
+                break;
+            }
+            /////////////////////////////////
             case CC_SEND_WRITE_BRDCAST_NLINE:
-                {
-                    uint64_t flit = 0;
-                    DspinRwtParam::dspin_set( flit,
-                            r_write_to_cc_send_nline.read(),
-                            DspinRwtParam::BROADCAST_NLINE);
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.eop   = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-                ///////////////////////////////
+            {
+                uint64_t flit = 0;
+                DspinRwtParam::dspin_set(flit,
+                                         r_write_to_cc_send_nline.read(),
+                                         DspinRwtParam::BROADCAST_NLINE);
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.eop   = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+            ///////////////////////////////
             case CC_SEND_CAS_BRDCAST_NLINE:
-                {
-                    uint64_t flit = 0;
-                    DspinRwtParam::dspin_set( flit,
-                            r_cas_to_cc_send_nline.read(),
-                            DspinRwtParam::BROADCAST_NLINE);
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.eop   = true;
-                    p_dspin_m2p.data  = flit;
-                    break;
-                }
-                ///////////////////////////////
+            {
+                uint64_t flit = 0;
+                DspinRwtParam::dspin_set(flit,
+                                         r_cas_to_cc_send_nline.read(),
+                                         DspinRwtParam::BROADCAST_NLINE);
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.eop   = true;
+                p_dspin_m2p.data  = flit;
+                break;
+            }
+            ///////////////////////////////
             case CC_SEND_WRITE_UPDT_HEADER:
-                {
-                    if(not m_write_to_cc_send_inst_fifo.rok()) break;
-
-                    uint8_t multi_updt_type;
-                    if(m_write_to_cc_send_inst_fifo.read())
-                    {
-                        multi_updt_type = DspinRwtParam::TYPE_MULTI_UPDT_INST;
-                    }
-                    else
-                    {
-                        multi_updt_type = DspinRwtParam::TYPE_MULTI_UPDT_DATA;
-                    }
-
-                    uint64_t flit = 0;
-                    uint64_t dest =
-                        m_write_to_cc_send_srcid_fifo.read() <<
-                        (DspinRwtParam::SRCID_WIDTH - vci_param_int::S);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            dest,
-                            DspinRwtParam::MULTI_UPDT_DEST);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_write_to_cc_send_trdid.read(),
-                            DspinRwtParam::MULTI_UPDT_UPDT_INDEX);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            multi_updt_type,
-                            DspinRwtParam::M2P_TYPE);
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-
-                    break;
-                }
-                //////////////////////////////
+            {
+                if (not m_write_to_cc_send_inst_fifo.rok()) break;
+
+                uint8_t multi_updt_type;
+                if (m_write_to_cc_send_inst_fifo.read())
+                {
+                    multi_updt_type = DspinRwtParam::TYPE_MULTI_UPDT_INST;
+                }
+                else
+                {
+                    multi_updt_type = DspinRwtParam::TYPE_MULTI_UPDT_DATA;
+                }
+
+                uint64_t flit = 0;
+                uint64_t dest =
+                    m_write_to_cc_send_srcid_fifo.read() <<
+                    (DspinRwtParam::SRCID_WIDTH - vci_param_int::S);
+
+                DspinRwtParam::dspin_set(flit,
+                                         dest,
+                                         DspinRwtParam::MULTI_UPDT_DEST);
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_write_to_cc_send_trdid.read(),
+                                         DspinRwtParam::MULTI_UPDT_UPDT_INDEX);
+
+                DspinRwtParam::dspin_set(flit,
+                                         multi_updt_type,
+                                         DspinRwtParam::M2P_TYPE);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+
+                break;
+            }
+            //////////////////////////////
             case CC_SEND_WRITE_UPDT_NLINE:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_write_to_cc_send_index.read(),
-                            DspinRwtParam::MULTI_UPDT_WORD_INDEX);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_write_to_cc_send_nline.read(),
-                            DspinRwtParam::MULTI_UPDT_NLINE);
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-
-                    break;
-                }
-                /////////////////////////////
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_write_to_cc_send_index.read(),
+                                         DspinRwtParam::MULTI_UPDT_WORD_INDEX);
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_write_to_cc_send_nline.read(),
+                                         DspinRwtParam::MULTI_UPDT_NLINE);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+
+                break;
+            }
+            /////////////////////////////
             case CC_SEND_WRITE_UPDT_DATA:
-                {
-
-                    uint8_t multi_updt_cpt  =
-                        r_cc_send_cpt.read() + r_write_to_cc_send_index.read();
-
-                    uint8_t  multi_updt_be   = r_write_to_cc_send_be[multi_updt_cpt].read();
-                    uint32_t multi_updt_data = r_write_to_cc_send_data[multi_updt_cpt].read();
-
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            multi_updt_be,
-                            DspinRwtParam::MULTI_UPDT_BE);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            multi_updt_data,
-                            DspinRwtParam::MULTI_UPDT_DATA);
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.eop   = (r_cc_send_cpt.read() == r_write_to_cc_send_count.read());
-                    p_dspin_m2p.data  = flit;
-
-                    break;
-                }
-                ////////////////////////////
+            {
+
+                uint8_t multi_updt_cpt =
+                    r_cc_send_cpt.read() + r_write_to_cc_send_index.read();
+
+                uint8_t multi_updt_be = r_write_to_cc_send_be[multi_updt_cpt].read();
+                uint32_t multi_updt_data = r_write_to_cc_send_data[multi_updt_cpt].read();
+
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         multi_updt_be,
+                                         DspinRwtParam::MULTI_UPDT_BE);
+
+                DspinRwtParam::dspin_set(flit,
+                                         multi_updt_data,
+                                         DspinRwtParam::MULTI_UPDT_DATA);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.eop   = (r_cc_send_cpt.read() == r_write_to_cc_send_count.read());
+                p_dspin_m2p.data  = flit;
+
+                break;
+            }
+            ////////////////////////////
             case CC_SEND_CAS_UPDT_HEADER:
-                {
-                    if (not m_cas_to_cc_send_inst_fifo.rok()) break;
-
-                    uint8_t multi_updt_type;
-                    if(m_cas_to_cc_send_inst_fifo.read())
-                    {
-                        multi_updt_type = DspinRwtParam::TYPE_MULTI_UPDT_INST;
-                    }
-                    else
-                    {
-                        multi_updt_type = DspinRwtParam::TYPE_MULTI_UPDT_DATA;
-                    }
-
-                    uint64_t flit = 0;
-                    uint64_t dest =
-                        m_cas_to_cc_send_srcid_fifo.read() <<
-                        (DspinRwtParam::SRCID_WIDTH - vci_param_int::S);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            dest,
-                            DspinRwtParam::MULTI_UPDT_DEST);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_cas_to_cc_send_trdid.read(),
-                            DspinRwtParam::MULTI_UPDT_UPDT_INDEX);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            multi_updt_type,
-                            DspinRwtParam::M2P_TYPE);
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-
-                    break;
-                }
-                ////////////////////////////
+            {
+                if (not m_cas_to_cc_send_inst_fifo.rok()) break;
+
+                uint8_t multi_updt_type;
+                if (m_cas_to_cc_send_inst_fifo.read())
+                {
+                    multi_updt_type = DspinRwtParam::TYPE_MULTI_UPDT_INST;
+                }
+                else
+                {
+                    multi_updt_type = DspinRwtParam::TYPE_MULTI_UPDT_DATA;
+                }
+
+                uint64_t flit = 0;
+                uint64_t dest =
+                    m_cas_to_cc_send_srcid_fifo.read() <<
+                    (DspinRwtParam::SRCID_WIDTH - vci_param_int::S);
+
+                DspinRwtParam::dspin_set(flit,
+                                         dest,
+                                         DspinRwtParam::MULTI_UPDT_DEST);
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_cas_to_cc_send_trdid.read(),
+                                         DspinRwtParam::MULTI_UPDT_UPDT_INDEX);
+
+                DspinRwtParam::dspin_set(flit,
+                                         multi_updt_type,
+                                         DspinRwtParam::M2P_TYPE);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+
+                break;
+            }
+            ////////////////////////////
             case CC_SEND_CAS_UPDT_NLINE:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_cas_to_cc_send_index.read(),
-                            DspinRwtParam::MULTI_UPDT_WORD_INDEX);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_cas_to_cc_send_nline.read(),
-                            DspinRwtParam::MULTI_UPDT_NLINE);
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.data  = flit;
-
-                    break;
-                }
-                ///////////////////////////
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_cas_to_cc_send_index.read(),
+                                         DspinRwtParam::MULTI_UPDT_WORD_INDEX);
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_cas_to_cc_send_nline.read(),
+                                         DspinRwtParam::MULTI_UPDT_NLINE);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.data  = flit;
+
+                break;
+            }
+            ///////////////////////////
             case CC_SEND_CAS_UPDT_DATA:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            0xF,
-                            DspinRwtParam::MULTI_UPDT_BE);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_cas_to_cc_send_wdata.read(),
-                            DspinRwtParam::MULTI_UPDT_DATA);
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.eop   = not r_cas_to_cc_send_is_long.read();
-                    p_dspin_m2p.data  = flit;
-
-                    break;
-                }
-                ////////////////////////////////
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         0xF,
+                                         DspinRwtParam::MULTI_UPDT_BE);
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_cas_to_cc_send_wdata.read(),
+                                         DspinRwtParam::MULTI_UPDT_DATA);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.eop   = not r_cas_to_cc_send_is_long.read();
+                p_dspin_m2p.data  = flit;
+
+                break;
+            }
+            ////////////////////////////////
             case CC_SEND_CAS_UPDT_DATA_HIGH:
-                {
-                    uint64_t flit = 0;
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            0xF,
-                            DspinRwtParam::MULTI_UPDT_BE);
-
-                    DspinRwtParam::dspin_set(
-                            flit,
-                            r_cas_to_cc_send_wdata_high.read(),
-                            DspinRwtParam::MULTI_UPDT_DATA);
-
-                    p_dspin_m2p.write = true;
-                    p_dspin_m2p.eop   = true;
-                    p_dspin_m2p.data  = flit;
-
-                    break;
-                }
+            {
+                uint64_t flit = 0;
+
+                DspinRwtParam::dspin_set(flit,
+                                         0xF,
+                                         DspinRwtParam::MULTI_UPDT_BE);
+
+                DspinRwtParam::dspin_set(flit,
+                                         r_cas_to_cc_send_wdata_high.read(),
+                                         DspinRwtParam::MULTI_UPDT_DATA);
+
+                p_dspin_m2p.write = true;
+                p_dspin_m2p.eop   = true;
+                p_dspin_m2p.data  = flit;
+
+                break;
+            }
         }
 
@@ -10636 +10652 @@
         ////////////////////////////////////////////////////////////////////
 
-        if ( r_cleanup_fsm.read() == CLEANUP_SEND_CLACK )
+        if (r_cleanup_fsm.read() == CLEANUP_SEND_CLACK)
         {
             uint8_t cleanup_ack_type;
-            if(r_cleanup_inst.read())
+            if (r_cleanup_inst.read())
             {
                 cleanup_ack_type = DspinRwtParam::TYPE_CLACK_INST;
@@ -10652 +10668 @@
                 (DspinRwtParam::SRCID_WIDTH - vci_param_int::S);
 
-            DspinRwtParam::dspin_set(
-                    flit,
-                    dest,
-                    DspinRwtParam::CLACK_DEST);
-
-            DspinRwtParam::dspin_set(
-                    flit,
-                    r_cleanup_nline.read() & 0xFFFF,
-                    DspinRwtParam::CLACK_SET);
-
-            DspinRwtParam::dspin_set(
-                    flit,
-                    r_cleanup_way_index.read(),
-                    DspinRwtParam::CLACK_WAY);
-
-            DspinRwtParam::dspin_set(
-                    flit,
-                    cleanup_ack_type,
-                    DspinRwtParam::CLACK_TYPE);
+            DspinRwtParam::dspin_set(flit,
+                                     dest,
+                                     DspinRwtParam::CLACK_DEST);
+
+            DspinRwtParam::dspin_set(flit,
+                                     r_cleanup_nline.read() & 0xFFFF,
+                                     DspinRwtParam::CLACK_SET);
+
+            DspinRwtParam::dspin_set(flit,
+                                     r_cleanup_way_index.read(),
+                                     DspinRwtParam::CLACK_WAY);
+
+            DspinRwtParam::dspin_set(flit,
+                                     cleanup_ack_type,
+                                     DspinRwtParam::CLACK_TYPE);
 
             p_dspin_clack.eop   = true;
@@ -10682 +10694 @@
             p_dspin_clack.data  = 0;
         }
+
         ///////////////////////////////////////////////////////////////////
         //  p_dspin_p2m port (CC_RECEIVE FSM)
         ///////////////////////////////////////////////////////////////////
         //
-        switch(r_cc_receive_fsm.read())
+        switch (r_cc_receive_fsm.read())
         {
             case CC_RECEIVE_IDLE:
-                {
-                    p_dspin_p2m.read = false;
-                    break;
-                }
+            {
+                p_dspin_p2m.read = false;
+                break;
+            }
             case CC_RECEIVE_CLEANUP:
-            case CC_RECEIVE_CLEANUP_EOP:
-                {
-                    p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok();
-                    break;
-                }
+            {
+                p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok();
+                break;
+            }
             case CC_RECEIVE_MULTI_ACK:
-                {
-                    p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok();
-                    break;
-                }
+            {
+                p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok();
+                break;
+            }
         }
         // end switch r_cc_send_fsm