Changeset 814 for branches/RWT

Timestamp:

Sep 24, 2014, 3:48:50 PM (10 years ago)

Author:

devigne

Message:

RWT commit : Cosmetic (Remove trailing whitespace)

Location:

branches/RWT

Files:

• lib/generic_cache_tsar/include/generic_cache.h (modified) (54 diffs)
• modules/vci_mem_cache (modified) (1 prop)
• modules/vci_mem_cache/caba/source/include (modified) (1 prop)
• modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (modified) (36 diffs)
• modules/vci_mem_cache/caba/source/include/update_tab.h (modified) (21 diffs)
• modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (modified) (21 diffs)
• modules/vci_mem_cache/caba/source/include/xram_transaction.h (modified) (26 diffs)
• modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (133 diffs)

branches/RWT/lib/generic_cache_tsar/include/generic_cache.h

@@ -38 +38 @@
 // Hit if ( (matching tag) and (state == VALID).
 // The replacement policy is pseudo-LRU. The victim selection process cannot
-// fail if the ZOMBI state is not used. 
+// fail if the ZOMBI state is not used.
 // But it can fail if all ways are in ZOMBI state.
 /////////////////////////////////////////////////////////////////////////////////
@@ -49 +49 @@
 // Constructor parameters are :
 // - std::string    &name
-// - size_t         nways   : number of associativity levels 
+// - size_t         nways   : number of associativity levels
 // - size_t         nsets   : number of sets
 // - size_t         nwords  : number of words in a cache line
@@ -58 +58 @@
 /////////////////////////////////////////////////////////////////////////////////
 // Template parameter is :
-// - addr_t : address format to access the cache 
+// - addr_t : address format to access the cache
 /////////////////////////////////////////////////////////////////////////////////
 
@@ -71 +71 @@
 #include <cstring>
 
-namespace soclib { 
+namespace soclib {
 
 enum cache_slot_state_e
@@ -83 +83 @@
 //////////////////////////
 template<typename addr_t>
-class GenericCache 
+class GenericCache
 //////////////////////////
 {
@@ -94 +94 @@
     bool             *r_lru ;
 
-    size_t           m_ways;    
-    size_t           m_sets;    
+    size_t           m_ways;
+    size_t           m_sets;
     size_t           m_words;
 
@@ -119 +119 @@
         return r_lru[(way*m_sets)+set];
     }
-    
+
     //////////////////////////////////////////////
     inline int &cache_state(size_t way, size_t set)
@@ -126 +126 @@
     }
 
-    
+
     /////////////////////////////////////////////////
     inline void cache_set_lru(size_t way, size_t set)
     {
-            size_t way2;
+        size_t way2;
 
         cache_lru(way, set) = true;
 
-            for (way2 = 0; way2 < m_ways; way2++) 
-        {
-                if (cache_lru(way2, set) == false) return;
-            }
-            // all lines are new -> they all become old 
-            for (way2 = 0; way2 < m_ways; way2++) 
-        {
-                cache_lru(way2, set) = false;
-            }
+        for (way2 = 0; way2 < m_ways; way2++)
+        {
+            if (cache_lru(way2, set) == false) return;
+        }
+        // all lines are new -> they all become old
+        for (way2 = 0; way2 < m_ways; way2++)
+        {
+            cache_lru(way2, set) = false;
+        }
     }
 
@@ -160 +160 @@
     //////////////////////////////////////////
     GenericCache(const std::string &name,
-                    size_t            nways, 
-                    size_t            nsets, 
+                    size_t            nways,
+                    size_t            nsets,
                     size_t            nwords)
         : m_ways(nways),
@@ -190 +190 @@
           << "- nsets  = " << nsets << std::endl
           << "- nwords = " << nwords << std::endl
-          << " m_x: " << m_x 
+          << " m_x: " << m_x
           << " m_y: " << m_y
           << " m_z: " << m_z
@@ -224 +224 @@
         return cache_state(way,set);
     }
-    
+
     /////////////////////////////////////////////////////////////////////
     // Read a single 32 bits word.
-    // returns true if (matching tag) and (state == VALID) 
-    // Both data & directory are accessed. 
+    // returns true if (matching tag) and (state == VALID)
+    // Both data & directory are accessed.
     /////////////////////////////////////////////////////////////////////
-    inline bool read(addr_t  ad, 
+    inline bool read(addr_t  ad,
                      data_t* dt)
     {
@@ -237 +237 @@
         const size_t word = m_x[ad];
 
-        for (size_t way = 0; way < m_ways; way++) 
-        {
-            if ((tag == cache_tag(way, set))  
+        for (size_t way = 0; way < m_ways; way++)
+        {
+            if ((tag == cache_tag(way, set))
                    && ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)) )
             {
@@ -252 +252 @@
     ////////////////////////////////////////////////////////////////////
     // Read a single 32 bits word.
-    // returns true if (matching tag) and (state == VALID) 
-    // Both data & directory are accessed. 
+    // returns true if (matching tag) and (state == VALID)
+    // Both data & directory are accessed.
     // The selected way, set and word index are returned in case of hit.
     /////////////////////////////////////////////////////////////////////
-    inline bool read(addr_t ad, 
+    inline bool read(addr_t ad,
                      data_t* dt,
                      size_t* selway,
                      size_t* selset,
-                     size_t* selword) 
+                     size_t* selword)
     {
         const addr_t tag  = m_z[ad];
@@ -266 +266 @@
         const size_t word = m_x[ad];
 
-        for (size_t way = 0; way < m_ways; way++) 
+        for (size_t way = 0; way < m_ways; way++)
         {
             if ((tag == cache_tag(way, set)) and
@@ -286 +286 @@
     // Both data and directory are accessed.
     // returns the access status in the state argument:
-    // - VALID : (matching tag) and (state == VALID) 
-    // - ZOMBI : (matching tag) and (state == ZOMBI) 
+    // - VALID : (matching tag) and (state == VALID)
+    // - ZOMBI : (matching tag) and (state == ZOMBI)
     // - MISS  : no matching tag or EMPTY state
-    // If VALID or ZOMBI, the data, the way, set and word index are 
+    // If VALID or ZOMBI, the data, the way, set and word index are
     // returned in the other arguments.
     ////////////////////////////////////////////////////////////////////
@@ -297 +297 @@
                      size_t* selset,
                      size_t* selword,
-                     int*    state) 
+                     int*    state)
     {
         const addr_t tag  = m_z[ad];
@@ -303 +303 @@
         const size_t word = m_x[ad];
 
-        // default return values 
+        // default return values
         *state   = CACHE_SLOT_STATE_EMPTY;
         *selway  = 0;
@@ -310 +310 @@
         *dt      = 0;
 
-        for (size_t way = 0; way < m_ways; way++) 
+        for (size_t way = 0; way < m_ways; way++)
         {
             if (tag == cache_tag(way, set))  // matching tag
@@ -343 +343 @@
         }
     }
-              
+
     ////////////////////////////////////////////////////////////////////
     // Read a single 32 bits word, without LRU update.
-    // returns true if (matching tag) and (state == VALID) 
-    // Both data & directory are accessed. 
+    // returns true if (matching tag) and (state == VALID)
+    // Both data & directory are accessed.
     // The selected way, set and word index are returned in case of hit.
     /////////////////////////////////////////////////////////////////////
-    inline bool read_neutral(addr_t  ad, 
+    inline bool read_neutral(addr_t  ad,
                              data_t* dt,
                              size_t* selway,
                              size_t* selset,
-                             size_t* selword) 
+                             size_t* selword)
     {
         const addr_t tag  = m_z[ad];
@@ -360 +360 @@
         const size_t word = m_x[ad];
 
-        for (size_t way = 0; way < m_ways; way++) 
-        {
-            if ((tag == cache_tag(way, set))  
+        for (size_t way = 0; way < m_ways; way++)
+        {
+            if ((tag == cache_tag(way, set))
                    && ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC) or (cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC) ))
             {
@@ -377 +377 @@
     /////////////////////////////////////////////////////////////////////////////
     // Read one or two 32 bits word.
-    // Both data & directory are accessed. 
-    // Hit if (matching tag) and (valid == true) and (zombi == false) 
+    // Both data & directory are accessed.
+    // Hit if (matching tag) and (valid == true) and (zombi == false)
     // If the addressed word is not the last in the cache line,
     // two successive words are returned.
@@ -384 +384 @@
     // This function is used by the cc_vcache to get a 64 bits page table entry.
     /////////////////////////////////////////////////////////////////////////////
-    inline bool read( addr_t  ad, 
-                      data_t* dt, 
+    inline bool read( addr_t  ad,
+                      data_t* dt,
                       data_t* dt_next,
                       size_t* selway,
@@ -395 +395 @@
         const size_t word = m_x[ad];
 
-        for (size_t way = 0; way < m_ways; way++) 
-        {
-            if ((tag == cache_tag(way, set))   
-                   &&( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC))) 
+        for (size_t way = 0; way < m_ways; way++)
+        {
+            if ((tag == cache_tag(way, set))
+                   &&( (cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)))
             {
                 *dt = cache_data(way, set, word);
-                if (word + 1 < m_words) 
+                if (word + 1 < m_words)
                 {
                     *dt_next = cache_data(way, set, word + 1);
@@ -419 +419 @@
     // Both data and directory are accessed.
     // returns the access status in the state argument:
-    // - VALID : (matching tag) and (state == VALID) 
-    // - ZOMBI : (matching tag) and (state == ZOMBI) 
+    // - VALID : (matching tag) and (state == VALID)
+    // - ZOMBI : (matching tag) and (state == ZOMBI)
     // - MISS  : no matching tag or EMPTY state
-    // If VALID or ZOMBI, the data, the way, set and word index are 
+    // If VALID or ZOMBI, the data, the way, set and word index are
     // returned in the other arguments.
     ////////////////////////////////////////////////////////////////////
@@ -431 +431 @@
                      size_t* selset,
                      size_t* selword,
-                     int*    state) 
+                     int*    state)
     {
         const addr_t tag  = m_z[ad];
@@ -437 +437 @@
         const size_t word = m_x[ad];
 
-        // default return values 
+        // default return values
         *state   = CACHE_SLOT_STATE_EMPTY;
         *selway  = 0;
@@ -444 +444 @@
         *dt      = 0;
 
-        for (size_t way = 0; way < m_ways; way++) 
+        for (size_t way = 0; way < m_ways; way++)
         {
             if (tag == cache_tag(way, set))  // matching tag
@@ -456 +456 @@
                     *selword = word;
                     *dt      = cache_data(way, set, word);
-                    if (word + 1 < m_words) 
+                    if (word + 1 < m_words)
                     {
                         *dt_next = cache_data(way, set, word+1);
@@ -470 +470 @@
                     *selword = word;
                     *dt      = cache_data(way, set, word);
-                    if (word + 1 < m_words) 
+                    if (word + 1 < m_words)
                     {
                         *dt_next = cache_data(way, set, word + 1);
@@ -490 +490 @@
     ///////////////////////////////////////////////////////////////////////////////
     // Checks the cache state for a given address.
-    // Only the directory is accessed. 
-    // returns true if (matching tag) and (state == VALID) 
+    // Only the directory is accessed.
+    // returns true if (matching tag) and (state == VALID)
     // The selected way, set and first word index are returned in case of hit.
     // This function can be used when we need to access the directory
     // while we write in the data part with a different address in the same cycle.
     ///////////////////////////////////////////////////////////////////////////////
-    inline bool hit(addr_t  ad, 
+    inline bool hit(addr_t  ad,
                     size_t* selway,
                     size_t* selset,
@@ -505 +505 @@
         const size_t word = m_x[ad];
 
-        for (size_t way = 0; way < m_ways; way++) 
-        {
-            if ((tag == cache_tag(way, set)) 
-                   && ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)or(cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC))) 
+        for (size_t way = 0; way < m_ways; way++)
+        {
+            if ((tag == cache_tag(way, set))
+                   && ((cache_state(way, set) == CACHE_SLOT_STATE_VALID_CC)or(cache_state(way, set) == CACHE_SLOT_STATE_VALID_NCC)))
             {
                 *selway  = way;
@@ -519 +519 @@
         return false;
     }
-  
+
     ///////////////////////////////////////////////////////////////////////////////
     // Checks the cache state for a given address, when the ZOMBI state is used.
-    // Only the directory is accessed. 
+    // Only the directory is accessed.
     // Returns the access status in the state argument:
-    // - VALID if (matching tag) and (state == VALID) 
-    // - ZOMBI if (matching tag) and (state == ZOMBI) 
+    // - VALID if (matching tag) and (state == VALID)
+    // - ZOMBI if (matching tag) and (state == ZOMBI)
     // - EMPTY if no match or (state == EMPTY)
     // The selected way, set and first word index are returned if not empty.
@@ -531 +531 @@
     // while we write in the data part with a different address in the same cycle.
     ///////////////////////////////////////////////////////////////////////////////
-    inline void read_dir(addr_t  ad, 
+    inline void read_dir(addr_t  ad,
                          int*    state,
                          size_t* way,
@@ -540 +540 @@
         const size_t ad_set  = m_y[ad];
         const size_t ad_word = m_x[ad];
-        for (size_t _way = 0; _way < m_ways; _way++) 
-        {
-            if ((ad_tag == cache_tag(_way, ad_set)) and 
-                (cache_state(_way, ad_set) != CACHE_SLOT_STATE_EMPTY)) 
+        for (size_t _way = 0; _way < m_ways; _way++)
+        {
+            if ((ad_tag == cache_tag(_way, ad_set)) and
+                (cache_state(_way, ad_set) != CACHE_SLOT_STATE_EMPTY))
             {
                 *state = cache_state(_way, ad_set);
@@ -552 +552 @@
             }
         }
-        
+
         // return value if not (VALID or ZOMBI)
         *state = CACHE_SLOT_STATE_EMPTY;
@@ -559 +559 @@
     ///////////////////////////////////////////////////////////////////////////////
     // Checks the cache state for a slot (set,way), when the ZOMBI state is used.
-    // Only the directory is accessed. 
+    // Only the directory is accessed.
     // Returns the access status and the tag value in the state and tag argument.
     ///////////////////////////////////////////////////////////////////////////////
@@ -581 +581 @@
     // It does not use the directory and cannot miss.
     //////////////////////////////////////////////////////////////////
-    inline void write(size_t way, 
-                      size_t set, 
-                      size_t word, 
+    inline void write(size_t way,
+                      size_t set,
+                      size_t word,
                       data_t data)
     {
@@ -594 +594 @@
     // It does not use the directory and cannot miss.
     ////////////////////////////////////////////////////////////////////////////
-    inline void write(size_t way, 
-                      size_t set, 
-                      size_t word, 
-                      data_t data, 
+    inline void write(size_t way,
+                      size_t set,
+                      size_t word,
+                      data_t data,
                       be_t   be)
     {
@@ -610 +610 @@
     // It returns true if the line was valid, and returns the line index.
     //////////////////////////////////////////////////////////////////////////
-    inline bool inval(size_t  way, 
-                      size_t  set, 
+    inline bool inval(size_t  way,
+                      size_t  set,
                       addr_t* nline)
     {
@@ -626 +626 @@
     // This function selects a victim slot in an associative set.
     // It cannot fail, as a slot in ZOMBI state is considered EMPTY.
-    // - we search first an EMPTY slot 
+    // - we search first an EMPTY slot
     // - if no EMPTY slot, we search an OLD slot, using lru
-    // It returns the line index (Z + Y fields), the selected slot way and set, 
+    // It returns the line index (Z + Y fields), the selected slot way and set,
     // and a Boolean indicating that a cleanup is requested.
     //////////////////////////////////////////////////////////////////////////////////
-    inline bool victim_select(addr_t  ad, 
-                              addr_t* victim, 
-                              size_t* way, 
+    inline bool victim_select(addr_t  ad,
+                              addr_t* victim,
+                              size_t* way,
                               size_t* set)
     {
@@ -642 +642 @@
         *way = 0;
 
-        // Search first empty slot 
+        // Search first empty slot
         for (size_t _way = 0 ; _way < m_ways && !found ; _way++)
         {
@@ -653 +653 @@
         }
 
-        // If no empty slot, search first  old slot (lru == false) 
+        // If no empty slot, search first  old slot (lru == false)
         if (!found)
-        { 
+        {
             for (size_t _way = 0 ; _way < m_ways && !found ; _way++)
             {
@@ -678 +678 @@
     // - if no empty slot, we search an OLD slot not in ZOMBI state,
     // - if not found, we take the first not ZOMBI slot.
-    // It returns the line index (Z + Y fields), the selected slot way and set, 
+    // It returns the line index (Z + Y fields), the selected slot way and set,
     // and two Boolean indicating success and a required cleanup.
     //////////////////////////////////////////////////////////////////////////////////
-    inline void read_select(addr_t  ad, 
-                            addr_t* victim, 
-                            size_t* way, 
+    inline void read_select(addr_t  ad,
+                            addr_t* victim,
+                            size_t* way,
                             size_t* set,
                             bool*   found,
@@ -692 +692 @@
         *found = false;
 
-        // Search first empty slot 
+        // Search first empty slot
         for (size_t _way = 0 ; _way < m_ways && !(*found) ; _way++)
         {
@@ -704 +704 @@
             }
         }
-        
-        // Search first not zombi old slot 
+
+        // Search first not zombi old slot
         for (size_t _way = 0 ; _way < m_ways && !(*found) ; _way++)
         {
-            if (not cache_lru(_way, _set) and 
+            if (not cache_lru(_way, _set) and
                  (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI))
             {
@@ -722 +722 @@
         for (size_t _way = 0 ; _way < m_ways && !(*found) ; _way++)
         {
-            if (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI) 
+            if (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI)
             {
                 *found   = true;
@@ -742 +742 @@
     // identified by the way & set.
     //////////////////////////////////////////////////////////////////
-    inline void victim_update_tag(addr_t ad, 
-                                  size_t way, 
+    inline void victim_update_tag(addr_t ad,
+                                  size_t way,
                                   size_t set)
     {
@@ -757 +757 @@
     // identified by the way & set, when using the ZOMBI state.
     //////////////////////////////////////////////////////////////////
-    inline void write_dir(addr_t ad, 
-                          size_t way, 
+    inline void write_dir(addr_t ad,
+                          size_t way,
                           size_t set,
                           int    state)
@@ -787 +787 @@
     // It does not affect the tag
     //////////////////////////////////////////////////////////////////
-    inline void write_dir(size_t way, 
+    inline void write_dir(size_t way,
                           size_t set,
                           int    state)
@@ -813 +813 @@
     // Both DATA and DIRECTORY are written
     ///////////////////////////////////////////////////////////////////
-    inline void update(addr_t  ad, 
-                       size_t  way, 
-                       size_t  set, 
+    inline void update(addr_t  ad,
+                       size_t  way,
+                       size_t  set,
                        data_t* buf)
     {
@@ -823 +823 @@
         cache_state(way, set) = CACHE_SLOT_STATE_VALID_CC;
         cache_set_lru(way, set);
-        for (size_t word = 0 ; word < m_words ; word++) 
+        for (size_t word = 0 ; word < m_words ; word++)
         {
             cache_data(way, set, word) = buf[word] ;
@@ -832 +832 @@
     void fileTrace(FILE* file)
     {
-        for (size_t nway = 0 ; nway < m_ways ; nway++) 
-        {
-            for (size_t nset = 0 ; nset < m_sets ; nset++) 
+        for (size_t nway = 0 ; nway < m_ways ; nway++)
+        {
+            for (size_t nset = 0 ; nset < m_sets ; nset++)
             {
                 fprintf(file, "%d / ", (int)cache_state(nway, nset));
                 fprintf(file, "way %d / ", (int)nway);
                 fprintf(file, "set %d / ", (int)nset);
-                fprintf(file, "@ = %08zX / ", 
+                fprintf(file, "@ = %08zX / ",
                         ((cache_tag(nway, nset) * m_sets + nset) * m_words * 4));
-                for (size_t nword = m_words ; nword > 0 ; nword--) 
+                for (size_t nword = m_words ; nword > 0 ; nword--)
                 {
                     unsigned int data = cache_data(nway, nset, nword - 1);
@@ -854 +854 @@
     inline void printTrace()
     {
-        for (size_t way = 0; way < m_ways ; way++) 
+        for (size_t way = 0; way < m_ways ; way++)
         {
             for (size_t set = 0 ; set < m_sets ; set++)
             {
                 addr_t addr = (((addr_t)cache_tag(way,set))*m_words*m_sets+m_words*set)*4;
-                std::cout << std::dec << cache_state(way, set) 
-                          << " | way " << way 
-                          << " | set " << set 
+                std::cout << std::dec << cache_state(way, set)
+                          << " | way " << way
+                          << " | set " << set
                           << std::hex << " | @ " << addr;
 
@@ -872 +872 @@
         }
     }
-   
+
 };
 

branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h

@@ -1 +1 @@
 #ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_H
-#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_H 
+#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_H
 
 #include <inttypes.h>
@@ -14 +14 @@
 
   ////////////////////////////////////////////////////////////////////////
-  //                    A LRU entry 
+  //                    A LRU entry
   ////////////////////////////////////////////////////////////////////////
   class LruEntry {
@@ -20 +20 @@
     public:
 
-      bool recent;            
+      bool recent;
 
       void init()
@@ -33 +33 @@
   ////////////////////////////////////////////////////////////////////////
   class Owner{
-    
+
     public:
     // Fields
@@ -66 +66 @@
 
   ////////////////////////////////////////////////////////////////////////
-  //                    A directory entry                               
+  //                    A directory entry
   ////////////////////////////////////////////////////////////////////////
   class DirectoryEntry {
@@ -81 +81 @@
     tag_t   tag;                    // tag of the entry
     size_t  count;                  // number of copies
-    Owner   owner;                  // an owner of the line 
+    Owner   owner;                  // an owner of the line
     size_t  ptr;                    // pointer to the next owner
 
@@ -109 +109 @@
       owner         = source.owner;
       ptr           = source.ptr;
-    }          
-
-    /////////////////////////////////////////////////////////////////////
-    // The init() function initializes the entry 
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry
     /////////////////////////////////////////////////////////////////////
     void init()
@@ -125 +125 @@
 
     /////////////////////////////////////////////////////////////////////
-    // The copy() function copies an existing source entry to a target 
+    // The copy() function copies an existing source entry to a target
     /////////////////////////////////////////////////////////////////////
     void copy(const DirectoryEntry &source)
     {
-      valid         = source.valid;
+      valid     = source.valid;
       cache_coherent = source.cache_coherent;
       is_cnt    = source.is_cnt;
-      dirty         = source.dirty;
-      lock          = source.lock;
-      tag           = source.tag;
+      dirty     = source.dirty;
+      lock      = source.lock;
+      tag       = source.tag;
       count     = source.count;
       owner     = source.owner;
@@ -141 +141 @@
 
     ////////////////////////////////////////////////////////////////////
-    // The print() function prints the entry 
+    // The print() function prints the entry
     ////////////////////////////////////////////////////////////////////
     void print()
     {
-      std::cout << "Valid = " << valid 
+      std::cout << "Valid = " << valid
                 << " ; COHERENCE = " << cache_coherent
-                << " ; IS COUNT = " << is_cnt 
-                << " ; Dirty = " << dirty 
-                << " ; Lock = " << lock 
-                << " ; Tag = " << std::hex << tag << std::dec 
-                << " ; Count = " << count 
-                << " ; Owner = " << owner.srcid 
-                << " " << owner.inst 
+                << " ; IS COUNT = " << is_cnt
+                << " ; Dirty = " << dirty
+                << " ; Lock = " << lock
+                << " ; Tag = " << std::hex << tag << std::dec
+                << " ; Count = " << count
+                << " ; Owner = " << owner.srcid
+                << " " << owner.inst
                 << " ; Pointer = " << ptr << std::endl;
     }
@@ -160 +160 @@
 
   ////////////////////////////////////////////////////////////////////////
-  //                       The directory  
+  //                       The directory
   ////////////////////////////////////////////////////////////////////////
   class CacheDirectory {
@@ -171 +171 @@
 
     // Directory constants
-    size_t                                      m_ways;
-    size_t                                      m_sets;
-    size_t                                      m_words;
-    size_t                                      m_width;
-    uint32_t                lfsr;
+    size_t   m_ways;
+    size_t   m_sets;
+    size_t   m_words;
+    size_t   m_width;
+    uint32_t lfsr;
 
     // the directory & lru tables
-    DirectoryEntry                              **m_dir_tab;
-    LruEntry                                    **m_lru_tab;
+    DirectoryEntry **m_dir_tab;
+    LruEntry       **m_lru_tab;
 
     public:
@@ -186 +186 @@
     // Constructor
     ////////////////////////
-    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)        
-    {
-      m_ways  = ways; 
+    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)
+    {
+      m_ways  = ways;
       m_sets  = sets;
       m_words = words;
@@ -223 +223 @@
     // LRU is updated.
     // Arguments :
-    // - address : the address of the entry 
+    // - address : the address of the entry
     // - way : (return argument) the way of the entry in case of hit
-    // The function returns a copy of a (valid or invalid) entry  
+    // The function returns a copy of a (valid or invalid) entry
     /////////////////////////////////////////////////////////////////////
     DirectoryEntry read(const addr_t &address, size_t &way)
@@ -240 +240 @@
         bool valid = m_dir_tab[set][i].valid;
         hit = equal && valid;
-        if ( hit ) {                    
+        if ( hit ) {
           way = i;
           break;
-        } 
+        }
       }
       if ( hit ) {
@@ -255 +255 @@
     /////////////////////////////////////////////////////////////////////
     // The inval function invalidate an entry defined by the set and
-    // way arguments. 
+    // way arguments.
     /////////////////////////////////////////////////////////////////////
     void inval( const size_t &way, const size_t &set )
@@ -266 +266 @@
     // changing the LRU
     // Arguments :
-    // - address : the address of the entry 
-    // The function returns a copy of a (valid or invalid) entry  
-    /////////////////////////////////////////////////////////////////////
-    DirectoryEntry read_neutral( const addr_t &address, 
+    // - address : the address of the entry
+    // The function returns a copy of a (valid or invalid) entry
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry read_neutral( const addr_t &address,
                                  size_t*      ret_way,
                                  size_t*      ret_set )
@@ -279 +279 @@
 #undef L2
 
-        for ( size_t way = 0 ; way < m_ways ; way++ ) 
+        for ( size_t way = 0 ; way < m_ways ; way++ )
         {
             bool equal = ( m_dir_tab[set][way].tag == tag );
@@ -286 +286 @@
             {
                 *ret_set = set;
-                *ret_way = way; 
+                *ret_way = way;
                 return DirectoryEntry(m_dir_tab[set][way]);
             }
-        } 
+        }
         return DirectoryEntry();
     } // end read_neutral()
 
     /////////////////////////////////////////////////////////////////////
-    // The write function writes a new entry, 
+    // The write function writes a new entry,
     // and updates the LRU bits if necessary.
     // Arguments :
@@ -301 +301 @@
     // - entry : the entry value
     /////////////////////////////////////////////////////////////////////
-    void write( const size_t         &set, 
-                const size_t         &way, 
+    void write( const size_t         &set,
+                const size_t         &way,
                 const DirectoryEntry &entry)
     {
-      assert( (set<m_sets) 
+      assert( (set<m_sets)
           && "Cache Directory write : The set index is invalid");
-      assert( (way<m_ways) 
+      assert( (way<m_ways)
           && "Cache Directory write : The way index is invalid");
 
@@ -315 +315 @@
       // update LRU bits
       bool all_recent = true;
-      for ( size_t i=0 ; i<m_ways ; i++ ) 
+      for ( size_t i=0 ; i<m_ways ; i++ )
       {
           if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
       }
-      if ( all_recent ) 
+      if ( all_recent )
       {
           for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
-      } 
-      else 
+      }
+      else
       {
           m_lru_tab[set][way].recent = true;
@@ -349 +349 @@
     DirectoryEntry select(const size_t &set, size_t &way)
     {
-        assert( (set < m_sets) 
+        assert( (set < m_sets)
           && "Cache Directory : (select) The set index is invalid");
 
@@ -404 +404 @@
 
     /////////////////////////////////////////////////////////////////////
-    //          Global initialisation function
+    //               Global initialisation function
     /////////////////////////////////////////////////////////////////////
     void init()
     {
-      for ( size_t set=0 ; set<m_sets ; set++ ) 
-      {
-        for ( size_t way=0 ; way<m_ways ; way++ ) 
+      for ( size_t set=0 ; set<m_sets ; set++ )
+      {
+        for ( size_t way=0 ; way<m_ways ; way++ )
         {
           m_dir_tab[set][way].init();
@@ -446 +446 @@
         owner.inst  = entry.owner.inst;
         owner.srcid = entry.owner.srcid;
-        next           = entry.next;
+        next        = entry.next;
       } // end constructor
 
     /////////////////////////////////////////////////////////////////////
-    // The copy() function copies an existing source entry to a target 
+    // The copy() function copies an existing source entry to a target
     /////////////////////////////////////////////////////////////////////
       void copy(const HeapEntry &entry)
       {
-        owner.inst     = entry.owner.inst;
-        owner.srcid    = entry.owner.srcid;
-        next           = entry.next;
+        owner.inst  = entry.owner.inst;
+        owner.srcid = entry.owner.srcid;
+        next        = entry.next;
       } // end copy()
 
     ////////////////////////////////////////////////////////////////////
-    // The print() function prints the entry 
+    // The print() function prints the entry
     ////////////////////////////////////////////////////////////////////
       void print(){
-        std::cout 
+        std::cout
         << " -- owner.inst     : " << std::dec << owner.inst << std::endl
         << " -- owner.srcid    : " << std::dec << owner.srcid << std::endl
@@ -473 +473 @@
 
   ////////////////////////////////////////////////////////////////////////
-  //                        The Heap 
+  //                        The Heap
   ////////////////////////////////////////////////////////////////////////
   class HeapDirectory{
-    
+
     private:
     // Registers and the heap
@@ -506 +506 @@
 
     /////////////////////////////////////////////////////////////////////
-    //          Global initialisation function
+    //              Global initialisation function
     /////////////////////////////////////////////////////////////////////
       void init(){
@@ -541 +541 @@
             if(ptr_temp == m_heap_tab[ptr_temp].next) end = true;
             ptr_temp = m_heap_tab[ptr_temp].next;
-        } 
+        }
       } // end print_list()
 
@@ -552 +552 @@
 
     /////////////////////////////////////////////////////////////////////
-    // The next_free_ptr() function returns the pointer 
+    // The next_free_ptr() function returns the pointer
     // to the next free entry.
     /////////////////////////////////////////////////////////////////////
@@ -560 +560 @@
 
     /////////////////////////////////////////////////////////////////////
-    // The next_free_entry() function returns 
+    // The next_free_entry() function returns
     // a copy of the next free entry.
     /////////////////////////////////////////////////////////////////////
@@ -566 +566 @@
         return HeapEntry(m_heap_tab[ptr_free]);
       } // end next_free_entry()
-   
+
     /////////////////////////////////////////////////////////////////////
     // The write_free_entry() function modify the next free entry.
@@ -624 +624 @@
 
   ////////////////////////////////////////////////////////////////////////
-  //                        Cache Data 
-  ////////////////////////////////////////////////////////////////////////
-  class CacheData 
+  //                        Cache Data
+  ////////////////////////////////////////////////////////////////////////
+  class CacheData
   {
     private:
@@ -639 +639 @@
       ///////////////////////////////////////////////////////
       CacheData(uint32_t ways, uint32_t sets, uint32_t words)
-        : m_sets(sets), m_ways(ways), m_words(words) 
+        : m_sets(sets), m_ways(ways), m_words(words)
       {
           m_cache_data = new uint32_t ** [ways];
-          for ( size_t i=0 ; i < ways ; i++ ) 
+          for ( size_t i=0 ; i < ways ; i++ )
           {
               m_cache_data[i] = new uint32_t * [sets];
           }
-          for ( size_t i=0; i<ways; i++ ) 
+          for ( size_t i=0; i<ways; i++ )
           {
-              for ( size_t j=0; j<sets; j++ ) 
+              for ( size_t j=0; j<sets; j++ )
               {
                   m_cache_data[i][j] = new uint32_t [words];
@@ -655 +655 @@
       }
       ////////////
-      ~CacheData() 
+      ~CacheData()
       {
           for(size_t i=0; i<m_ways ; i++)
@@ -673 +673 @@
       uint32_t read ( const uint32_t &way,
                       const uint32_t &set,
-                      const uint32_t &word) const 
+                      const uint32_t &word) const
       {
           assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set" );
@@ -697 +697 @@
                    const uint32_t &word,
                    const uint32_t &data,
-                   const uint32_t &be = 0xF) 
+                   const uint32_t &be = 0xF)
       {
 
@@ -707 +707 @@
           if (be == 0x0) return;
 
-          if (be == 0xF) 
+          if (be == 0xF)
           {
-              m_cache_data[way][set][word] = data; 
+              m_cache_data[way][set][word] = data;
               return;
           }
@@ -719 +719 @@
           if  (be & 0x8) mask = mask | 0xFF000000;
 
-          m_cache_data[way][set][word] = 
+          m_cache_data[way][set][word] =
               (data & mask) | (m_cache_data[way][set][word] & ~mask);
       }

branches/RWT/modules/vci_mem_cache/caba/source/include/update_tab.h

@@ -8 +8 @@
 
 ////////////////////////////////////////////////////////////////////////
-//                  An update tab entry    
+//                  An update tab entry
 ////////////////////////////////////////////////////////////////////////
 class UpdateTabEntry {
@@ -17 +17 @@
   public:
 
-  bool      valid;      // It is a valid pending transaction
-  bool      update;     // It is an update transaction
-  bool      brdcast;    // It is a broadcast invalidate
-  bool      rsp;        // Response to the initiator required
-  bool      ack;        // Acknowledge to the CONFIG FSM required
-  size_t        srcid;      // The srcid of the initiator which wrote the data
-  size_t        trdid;      // The trdid of the initiator which wrote the data
-  size_t        pktid;      // The pktid of the initiator which wrote the data
-  addr_t        nline;      // The identifier of the cache line
-  size_t        count;      // The number of acknowledge responses to receive
+  bool   valid;   // It is a valid pending transaction
+  bool   update;  // It is an update transaction
+  bool   brdcast; // It is a broadcast invalidate
+  bool   rsp;     // Response to the initiator required
+  bool   ack;     // Acknowledge to the CONFIG FSM required
+  size_t srcid;   // The srcid of the initiator which wrote the data
+  size_t trdid;   // The trdid of the initiator which wrote the data
+  size_t pktid;   // The pktid of the initiator which wrote the data
+  addr_t nline;   // The identifier of the cache line
+  size_t count;   // The number of acknowledge responses to receive
 
   UpdateTabEntry()
   {
-    valid       = false;
+    valid   = false;
     update  = false;
     brdcast = false;
     rsp     = false;
     ack     = false;
-    srcid       = 0;
-    trdid       = 0;
-    pktid       = 0;
-    nline       = 0;
-    count       = 0;
-  }
-
-  UpdateTabEntry(bool   i_valid, 
+    srcid   = 0;
+    trdid   = 0;
+    pktid   = 0;
+    nline   = 0;
+    count   = 0;
+  }
+
+  UpdateTabEntry(bool   i_valid,
                  bool   i_update,
                  bool   i_brdcast,
                  bool   i_rsp,
                  bool   i_ack,
-                 size_t i_srcid, 
-                 size_t i_trdid, 
-                 size_t i_pktid, 
+                 size_t i_srcid,
+                 size_t i_trdid,
+                 size_t i_pktid,
                  addr_t i_nline,
-                 size_t i_count) 
-  {
-    valid       = i_valid;
-    update      = i_update;
+                 size_t i_count)
+  {
+    valid   = i_valid;
+    update  = i_update;
     brdcast = i_brdcast;
     rsp     = i_rsp;
     ack     = i_ack;
-    srcid       = i_srcid;
-    trdid       = i_trdid;
-    pktid       = i_pktid;
-    nline       = i_nline;
-    count       = i_count;
+    srcid   = i_srcid;
+    trdid   = i_trdid;
+    pktid   = i_pktid;
+    nline   = i_nline;
+    count   = i_count;
   }
 
@@ -80 +80 @@
 
   ////////////////////////////////////////////////////
-  // The init() function initializes the entry 
+  // The init() function initializes the entry
   ///////////////////////////////////////////////////
   void init()
   {
-    valid  = false;
-    update = false;
-    brdcast= false;
-    rsp    = false;
-    ack    = false;
-    srcid  = 0;
-    trdid  = 0;
-    pktid  = 0;
-    nline  = 0;
-    count  = 0;
+    valid   = false;
+    update  = false;
+    brdcast = false;
+    rsp     = false;
+    ack     = false;
+    srcid   = 0;
+    trdid   = 0;
+    pktid   = 0;
+    nline   = 0;
+    count   = 0;
   }
 
@@ -116 +116 @@
 
   ////////////////////////////////////////////////////////////////////
-  // The print() function prints the entry  
+  // The print() function prints the entry
   ////////////////////////////////////////////////////////////////////
   void print()
   {
-    std::cout << " val = " << std::dec << valid 
-              << " / updt = " << update 
+    std::cout << " val = " << std::dec << valid
+              << " / updt = " << update
               << " / bc = " << brdcast
-              << " / rsp = " << rsp 
-              << " / ack = " << ack   
+              << " / rsp = " << rsp
+              << " / ack = " << ack
               << " / count = " << count
-              << " / srcid = " << std::hex << srcid 
-              << " / trdid = " << trdid   
+              << " / srcid = " << std::hex << srcid
+              << " / trdid = " << trdid
               << " / pktid = " << pktid
               << " / nline = " << nline  << std::endl;
@@ -134 +134 @@
 
 ////////////////////////////////////////////////////////////////////////
-//                        The update tab             
+//                        The update tab
 ////////////////////////////////////////////////////////////////////////
 class UpdateTab{
@@ -159 +159 @@
 
   ////////////////////////////////////////////////////////////////////
-  // The size() function returns the size of the tab  
+  // The size() function returns the size of the tab
   ////////////////////////////////////////////////////////////////////
   const size_t size()
@@ -167 +167 @@
 
   ////////////////////////////////////////////////////////////////////
-  // The print() function diplays the tab content 
+  // The print() function diplays the tab content
   ////////////////////////////////////////////////////////////////////
   void print()
   {
     std::cout << "UPDATE TABLE Content" << std::endl;
-    for(size_t i=0; i<size_tab; i++) 
+    for(size_t i=0; i<size_tab; i++)
     {
       std::cout << "[" << std::dec << i << "] ";
@@ -181 +181 @@
 
   /////////////////////////////////////////////////////////////////////
-  // The init() function initializes the tab 
+  // The init() function initializes the tab
   /////////////////////////////////////////////////////////////////////
   void init()
@@ -189 +189 @@
 
   /////////////////////////////////////////////////////////////////////
-  // The reads() function reads an entry 
+  // The reads() function reads an entry
   // Arguments :
   // - entry : the entry to read
@@ -211 +211 @@
   // This function returns true if the write successed (an entry was empty).
   ///////////////////////////////////////////////////////////////////////////
-  bool set(const bool   update,
+  bool set(const bool   update,
            const bool   brdcast,
            const bool   rsp,
@@ -222 +222 @@
            size_t       &index)
   {
-    for ( size_t i=0 ; i<size_tab ; i++ ) 
-    {
-      if( !tab[i].valid ) 
+    for ( size_t i=0 ; i<size_tab ; i++ )
+    {
+      if( !tab[i].valid )
       {
-        tab[i].valid            = true;
-        tab[i].update           = update;
-        tab[i].brdcast      = brdcast;
-        tab[i].rsp          = rsp;
-        tab[i].ack          = ack;
-        tab[i].srcid            = (size_t) srcid;
-        tab[i].trdid            = (size_t) trdid;
-        tab[i].pktid            = (size_t) pktid;
-        tab[i].nline            = (addr_t) nline;
-        tab[i].count            = (size_t) count;
-        index                       = i;
+        tab[i].valid   = true;
+        tab[i].update  = update;
+        tab[i].brdcast = brdcast;
+        tab[i].rsp     = rsp;
+        tab[i].ack     = ack;
+        tab[i].srcid   = (size_t) srcid;
+        tab[i].trdid   = (size_t) trdid;
+        tab[i].pktid   = (size_t) pktid;
+        tab[i].nline   = (addr_t) nline;
+        tab[i].count   = (size_t) count;
+        index          = i;
         return true;
       }
@@ -251 +251 @@
   /////////////////////////////////////////////////////////////////////
   bool decrement( const size_t index,
-                  size_t &counter ) 
+                  size_t &counter )
   {
     assert((index<size_tab) && "Bad Update Tab Entry");
-    if ( tab[index].valid ) 
+    if ( tab[index].valid )
     {
       tab[index].count--;
       counter = tab[index].count;
       return true;
-    } 
-    else 
+    }
+    else
     {
       return false;
@@ -298 +298 @@
   {
     assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].rsp;      
+    return tab[index].rsp;
   }
 
@@ -309 +309 @@
   {
     assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].ack;      
+    return tab[index].ack;
   }
 
@@ -320 +320 @@
   {
     assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].brdcast;  
+    return tab[index].brdcast;
   }
 
@@ -331 +331 @@
   {
     assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].update;   
+    return tab[index].update;
   }
 
@@ -342 +342 @@
   {
     assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].srcid;    
+    return tab[index].srcid;
   }
 
@@ -353 +353 @@
   {
     assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].trdid;    
+    return tab[index].trdid;
   }
 
@@ -364 +364 @@
   {
     assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].pktid;    
+    return tab[index].pktid;
   }
 
@@ -403 +403 @@
   // - nline : the line number of the entry in the directory
   /////////////////////////////////////////////////////////////////////
-  bool read_nline(const addr_t nline,size_t &index) 
+  bool read_nline(const addr_t nline,size_t &index)
   {
     size_t i ;
@@ -422 +422 @@
   // Arguments :
   // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////       
+  /////////////////////////////////////////////////////////////////////
   void clear(const size_t index)
   {
     assert(index<size_tab && "Bad Update Tab Entry");
     tab[index].valid=false;
-    return;     
+    return;
   }
 

branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -25 +25 @@
  * SOCLIB_LGPL_HEADER_END
  *
- * Maintainers: alain.greiner@lip6.fr 
+ * Maintainers: alain.greiner@lip6.fr
  *              eric.guthmuller@polytechnique.edu
  *              cesar.fuguet-tortolero@lip6.fr
@@ -62 +62 @@
   using namespace sc_core;
 
-  template<typename vci_param_int, 
+  template<typename vci_param_int,
            typename vci_param_ext,
            size_t   dspin_in_width,
@@ -416 +416 @@
       };
 
-      // debug variables 
+      // debug variables
       bool     m_debug;
       bool     m_debug_previous_valid;
@@ -479 +479 @@
       uint32_t m_cpt_heap_unused;             // NB cycles HEAP LOCK unused
       uint32_t m_cpt_heap_slot_available;     // NB HEAP slot available refresh at each cycles
-      uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available 
+      uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available
 
       uint32_t m_cpt_ncc_to_cc_read;         // NB change from NCC to CC caused by a READ
@@ -525 +525 @@
 
 #if MONITOR_MEMCACHE_FSM == 1
-      sc_out<int> p_read_fsm; 
-      sc_out<int> p_write_fsm; 
-      sc_out<int> p_xram_rsp_fsm; 
-      sc_out<int> p_cas_fsm; 
-      sc_out<int> p_cleanup_fsm; 
-      sc_out<int> p_config_fsm; 
-      sc_out<int> p_alloc_heap_fsm; 
-      sc_out<int> p_alloc_dir_fsm; 
-      sc_out<int> p_alloc_trt_fsm; 
-      sc_out<int> p_alloc_upt_fsm; 
-      sc_out<int> p_alloc_ivt_fsm; 
-      sc_out<int> p_tgt_cmd_fsm; 
-      sc_out<int> p_tgt_rsp_fsm; 
-      sc_out<int> p_ixr_cmd_fsm; 
-      sc_out<int> p_ixr_rsp_fsm; 
-      sc_out<int> p_cc_send_fsm; 
-      sc_out<int> p_cc_receive_fsm; 
-      sc_out<int> p_multi_ack_fsm; 
+      sc_out<int> p_read_fsm;
+      sc_out<int> p_write_fsm;
+      sc_out<int> p_xram_rsp_fsm;
+      sc_out<int> p_cas_fsm;
+      sc_out<int> p_cleanup_fsm;
+      sc_out<int> p_config_fsm;
+      sc_out<int> p_alloc_heap_fsm;
+      sc_out<int> p_alloc_dir_fsm;
+      sc_out<int> p_alloc_trt_fsm;
+      sc_out<int> p_alloc_upt_fsm;
+      sc_out<int> p_alloc_ivt_fsm;
+      sc_out<int> p_tgt_cmd_fsm;
+      sc_out<int> p_tgt_rsp_fsm;
+      sc_out<int> p_ixr_cmd_fsm;
+      sc_out<int> p_ixr_rsp_fsm;
+      sc_out<int> p_cc_send_fsm;
+      sc_out<int> p_cc_receive_fsm;
+      sc_out<int> p_multi_ack_fsm;
 #endif
 
@@ -558 +558 @@
           const size_t                       max_copies,      // max number of copies
           const size_t                       heap_size=HEAP_ENTRIES,
-          const size_t                       trt_lines=TRT_ENTRIES, 
-          const size_t                       upt_lines=UPT_ENTRIES,     
-          const size_t                       ivt_lines=IVT_ENTRIES,     
+          const size_t                       trt_lines=TRT_ENTRIES,
+          const size_t                       upt_lines=UPT_ENTRIES,
+          const size_t                       ivt_lines=IVT_ENTRIES,
           const size_t                       debug_start_cycle=0,
           const bool                         debug_ok=false );
@@ -584 +584 @@
 
       // Component attributes
-      std::list<soclib::common::Segment> m_seglist;          // segments allocated 
+      std::list<soclib::common::Segment> m_seglist;          // segments allocated
       size_t                             m_nseg;             // number of segments
       soclib::common::Segment            **m_seg;            // array of segments pointers
@@ -657 +657 @@
       // Fifo between CC_RECEIVE fsm and CLEANUP fsm
       GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
-      
+
       // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
       GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
@@ -686 +686 @@
       sc_signal<int>      r_config_fsm;               // FSM state
       sc_signal<bool>     r_config_lock;              // lock protecting exclusive access
-      sc_signal<int>      r_config_cmd;               // config request type  
+      sc_signal<int>      r_config_cmd;               // config request type
       sc_signal<addr_t>   r_config_address;           // target buffer physical address
       sc_signal<size_t>   r_config_srcid;             // config request srcid
@@ -702 +702 @@
       sc_signal<size_t>   r_config_heap_next;         // current pointer to scan HEAP
       sc_signal<size_t>   r_config_trt_index;         // selected entry in TRT
-      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT 
+      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT
 
       // Buffer between CONFIG fsm and IXR_CMD fsm
@@ -744 +744 @@
       sc_signal<addr_t>   r_read_ll_key;              // LL key from llsc_global_table
 
-      // Buffer between READ fsm and IXR_CMD fsm 
+      // Buffer between READ fsm and IXR_CMD fsm
       sc_signal<bool>     r_read_to_ixr_cmd_req;      // valid request
       sc_signal<size_t>   r_read_to_ixr_cmd_index;    // TRT index
@@ -764 +764 @@
       sc_signal<bool>     r_read_to_cc_send_inst;
 
-      //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) 
+      //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache)
       sc_signal<bool>     r_read_to_cleanup_req;    // valid request
       sc_signal<addr_t>   r_read_to_cleanup_nline;  // cache line index
@@ -771 +771 @@
       sc_signal<size_t>   r_read_to_cleanup_length;
       sc_signal<size_t>   r_read_to_cleanup_first_word;
-      sc_signal<bool>     r_read_to_cleanup_cached_read;    
+      sc_signal<bool>     r_read_to_cleanup_cached_read;
       sc_signal<bool>     r_read_to_cleanup_is_ll;
       sc_signal<addr_t>   r_read_to_cleanup_addr;
@@ -810 +810 @@
       sc_signal<data_t>   r_write_sc_key;             // sc command key
       sc_signal<bool>     r_write_bc_data_we;         // Write enable for data buffer
- 
+
       // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
       sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
@@ -818 +818 @@
       sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
 
-      // Buffer between WRITE fsm and IXR_CMD fsm 
+      // Buffer between WRITE fsm and IXR_CMD fsm
       sc_signal<bool>     r_write_to_ixr_cmd_req;     // valid request
-      sc_signal<size_t>   r_write_to_ixr_cmd_index;   // TRT index 
+      sc_signal<size_t>   r_write_to_ixr_cmd_index;   // TRT index
 
       // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
@@ -908 +908 @@
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
-      sc_signal<addr_t>     r_cleanup_to_tgt_rsp_ll_key;
+      sc_signal<addr_t>   r_cleanup_to_tgt_rsp_ll_key;
 
       //RWT
@@ -948 +948 @@
       // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
       sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
-      sc_signal<size_t>   r_cas_to_ixr_cmd_index; // TRT index 
+      sc_signal<size_t>   r_cas_to_ixr_cmd_index; // TRT index
 
       // Buffer between CAS fsm and TGT_RSP fsm
@@ -978 +978 @@
 
       // Buffer between IXR_RSP fsm and CONFIG fsm  (response from the XRAM)
-      sc_signal<bool>     r_ixr_rsp_to_config_ack;      // one single bit   
+      sc_signal<bool>     r_ixr_rsp_to_config_ack;      // one single bit
 
       // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
@@ -1028 +1028 @@
       GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
 
-      // Buffer between XRAM_RSP fsm and IXR_CMD fsm 
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm
       sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
-      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_index; // TRT index 
+      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_index; // TRT index
 
       //RWT
@@ -1041 +1041 @@
       sc_signal<int>      r_ixr_cmd_fsm;
       sc_signal<size_t>   r_ixr_cmd_word;              // word index for a put
-      sc_signal<size_t>   r_ixr_cmd_trdid;             // TRT index value     
+      sc_signal<size_t>   r_ixr_cmd_trdid;             // TRT index value
       sc_signal<addr_t>   r_ixr_cmd_address;           // address to XRAM
       sc_signal<data_t> * r_ixr_cmd_wdata;             // cache line buffer
@@ -1112 +1112 @@
       sc_signal<data_t>    *r_cleanup_old_data;
       sc_signal<bool>      r_cleanup_contains_data;
-      
+
       sc_signal<bool>      r_cleanup_ncc;
       sc_signal<bool>      r_cleanup_to_ixr_cmd_ncc_l1_dirty;
       sc_signal<bool>      r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
-      
+
       sc_signal<bool>      r_cleanup_to_ixr_cmd_req;
       sc_signal<data_t>    *r_cleanup_to_ixr_cmd_data;

branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h

@@ -10 +10 @@
 
 ////////////////////////////////////////////////////////////////////////
-//                  A transaction tab entry         
+//                  A transaction tab entry
 ////////////////////////////////////////////////////////////////////////
 
-class TransactionTabEntry 
+class TransactionTabEntry
 {
     typedef sc_dt::sc_uint<64>    wide_data_t;
@@ -21 +21 @@
 
     public:
-    bool                        valid;              // entry valid 
-    bool                        xram_read;          // read request to XRAM
-    addr_t              nline;              // index (zy) of the requested line
-    size_t                  srcid;          // processor requesting the transaction
-    size_t                  trdid;          // processor requesting the transaction
-    size_t                  pktid;          // processor requesting the transaction
-    bool                        proc_read;          // read request from processor
-    size_t                  read_length;    // length of the read (for the response)
-    size_t                  word_index;         // index of the first read word (for the response)
-    std::vector<data_t> wdata;          // write buffer (one cache line)
-    std::vector<be_t>   wdata_be;       // be for each data in the write buffer
-    bool                rerror;         // error returned by xram
-    data_t              ll_key;         // LL key returned by the llsc_global_table
-    bool                config;         // transaction required by CONFIG FSM
-
-    /////////////////////////////////////////////////////////////////////
-    // The init() function initializes the entry 
+    bool                valid;       // entry valid
+    bool                xram_read;   // read request to XRAM
+    addr_t              nline;       // index (zy) of the requested line
+    size_t              srcid;       // processor requesting the transaction
+    size_t              trdid;       // processor requesting the transaction
+    size_t              pktid;       // processor requesting the transaction
+    bool                proc_read;   // read request from processor
+    size_t              read_length; // length of the read (for the response)
+    size_t              word_index;  // index of the first read word (for the response)
+    std::vector<data_t> wdata;       // write buffer (one cache line)
+    std::vector<be_t>   wdata_be;    // be for each data in the write buffer
+    bool                rerror;      // error returned by xram
+    data_t              ll_key;      // LL key returned by the llsc_global_table
+    bool                config;      // transaction required by CONFIG FSM
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry
     /////////////////////////////////////////////////////////////////////
     void init()
     {
-        valid           = false;
-        rerror      = false;
-        config      = false;
+        valid  = false;
+        rerror = false;
+        config = false;
     }
 
@@ -69 +69 @@
     void copy(const TransactionTabEntry &source)
     {
-        valid       = source.valid;
-        xram_read       = source.xram_read;
-        nline       = source.nline;
-        srcid       = source.srcid;
-        trdid       = source.trdid;
-        pktid       = source.pktid;
-        proc_read       = source.proc_read;
+        valid       = source.valid;
+        xram_read   = source.xram_read;
+        nline       = source.nline;
+        srcid       = source.srcid;
+        trdid       = source.trdid;
+        pktid       = source.pktid;
+        proc_read   = source.proc_read;
         read_length = source.read_length;
-        word_index      = source.word_index;
+        word_index  = source.word_index;
         wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
         wdata.assign(source.wdata.begin(),source.wdata.end());
@@ -86 +86 @@
 
     ////////////////////////////////////////////////////////////////////
-    // The print() function prints the entry 
+    // The print() function prints the entry
     ////////////////////////////////////////////////////////////////////
     void print()
@@ -99 +99 @@
         std::cout << "proc_read   = " << proc_read    << std::endl;
         std::cout << "read_length = " << read_length  << std::endl;
-        std::cout << "word_index  = " << word_index   << std::endl; 
+        std::cout << "word_index  = " << word_index   << std::endl;
         for(size_t i=0; i<wdata_be.size() ; i++)
         {
-            std::cout << "wdata_be[" << std::dec << i << "] = " 
+            std::cout << "wdata_be[" << std::dec << i << "] = "
                       << std::hex << wdata_be[i] << std::endl;
         }
         for(size_t i=0; i<wdata.size() ; i++)
         {
-            std::cout << "wdata[" << std::dec << i << "] = " 
+            std::cout << "wdata[" << std::dec << i << "] = "
                       << std::hex << wdata[i] << std::endl;
         }
@@ -117 +117 @@
 
     /////////////////////////////////////////////////////////////////////
-    //          Constructors
+    // Constructors
     /////////////////////////////////////////////////////////////////////
 
@@ -131 +131 @@
     TransactionTabEntry(const TransactionTabEntry &source)
     {
-        valid       = source.valid;
-        xram_read       = source.xram_read;
-        nline       = source.nline;
-        srcid       = source.srcid;
-        trdid       = source.trdid;
-        pktid       = source.pktid;
-        proc_read       = source.proc_read;
+        valid       = source.valid;
+        xram_read   = source.xram_read;
+        nline       = source.nline;
+        srcid       = source.srcid;
+        trdid       = source.trdid;
+        pktid       = source.pktid;
+        proc_read   = source.proc_read;
         read_length = source.read_length;
-        word_index      = source.word_index;
+        word_index  = source.word_index;
         wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
-        wdata.assign(source.wdata.begin(),source.wdata.end());  
+        wdata.assign(source.wdata.begin(),source.wdata.end());
         rerror      = source.rerror;
         ll_key      = source.ll_key;
@@ -150 +150 @@
 
 ////////////////////////////////////////////////////////////////////////
-//                  The transaction tab                              
+//                  The transaction tab
 ////////////////////////////////////////////////////////////////////////
 class TransactionTab
@@ -185 +185 @@
 
     ////////////////////////////////////////////////////////////////////
-    //          Constructors
+    //  Constructors
     ////////////////////////////////////////////////////////////////////
     TransactionTab()
@@ -194 +194 @@
 
     TransactionTab(const std::string &name,
-                   size_t            n_entries, 
+                   size_t            n_entries,
                    size_t            n_words )
     : tab_name( name ),
-      size_tab( n_entries ) 
+      size_tab( n_entries )
     {
         tab = new TransactionTabEntry[size_tab];
-        for ( size_t i=0; i<size_tab; i++) 
+        for ( size_t i=0; i<size_tab; i++)
         {
             tab[i].alloc(n_words);
@@ -222 +222 @@
     void init()
     {
-        for ( size_t i=0; i<size_tab; i++) 
+        for ( size_t i=0; i<size_tab; i++)
         {
             tab[i].init();
@@ -247 +247 @@
     TransactionTabEntry read(const size_t index)
     {
-        assert( (index < size_tab) and 
+        assert( (index < size_tab) and
         "MEMC ERROR: Invalid Transaction Tab Entry");
 
@@ -255 +255 @@
     // The full() function returns the state of the transaction tab
     // Arguments :
-    // - index : (return argument) the index of an empty entry 
+    // - index : (return argument) the index of an empty entry
     // The function returns true if the transaction tab is full
     /////////////////////////////////////////////////////////////////////
@@ -265 +265 @@
             {
                 index=i;
-                return false;   
+                return false;
             }
         }
@@ -271 +271 @@
     }
     /////////////////////////////////////////////////////////////////////
-    // The hit_read() function checks if an XRAM read transaction exists 
+    // The hit_read() function checks if an XRAM read transaction exists
     // for a given cache line.
     // Arguments :
-    // - index : (return argument) the index of the hit entry, if there is 
+    // - index : (return argument) the index of the hit entry, if there is
     // - nline : the index (zy) of the requested line
     // The function returns true if a read request has already been sent
@@ -282 +282 @@
         for(size_t i=0; i<size_tab; i++)
         {
-            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) 
+            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read))
             {
                 index=i;
-                return true;    
+                return true;
             }
         }
@@ -291 +291 @@
     }
     ///////////////////////////////////////////////////////////////////////
-    // The hit_write() function looks if an XRAM write transaction exists 
+    // The hit_write() function looks if an XRAM write transaction exists
     // for a given line.
     // Arguments :
@@ -301 +301 @@
         for(size_t i=0; i<size_tab; i++)
         {
-            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) 
+            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read))
             {
-                return true;    
+                return true;
             }
         }
@@ -310 +310 @@
 
     ///////////////////////////////////////////////////////////////////////
-    // The hit_write() function looks if an XRAM write transaction exists 
+    // The hit_write() function looks if an XRAM write transaction exists
     // for a given line.
     // Arguments :
@@ -322 +322 @@
             if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
                 *index = i;
-                return true;    
+                return true;
             }
         }
@@ -330 +330 @@
     // The write_data_mask() function writes a vector of data (a line).
     // The data is written only if the corresponding bits are set
-    // in the be vector. 
+    // in the be vector.
     // Arguments :
     // - index : the index of the request in the transaction tab
-    // - be   : vector of be 
+    // - be   : vector of be
     // - data : vector of data
     /////////////////////////////////////////////////////////////////////
-    void write_data_mask(const size_t index, 
-            const std::vector<be_t> &be, 
-            const std::vector<data_t> &data) 
+    void write_data_mask(const size_t index,
+            const std::vector<be_t> &be,
+            const std::vector<data_t> &data)
     {
         assert( (index < size_tab) and
@@ -349 +349 @@
         "MEMC ERROR: Bad data size in TRT write_data_mask()");
 
-        for(size_t i=0; i<tab[index].wdata_be.size() ; i++) 
+        for(size_t i=0; i<tab[index].wdata_be.size() ; i++)
         {
             tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
@@ -384 +384 @@
             const size_t word_index,
             const std::vector<be_t> &data_be,
-            const std::vector<data_t> &data, 
+            const std::vector<data_t> &data,
             const data_t ll_key = 0,
-            const bool config = false) 
+            const bool config = false)
     {
         assert( (index < size_tab) and
         "MEMC ERROR: The selected entry is out of range in TRT set()");
 
-        assert( (data_be.size()==tab[index].wdata_be.size()) and 
+        assert( (data_be.size()==tab[index].wdata_be.size()) and
         "MEMC ERROR: Bad data_be argument in TRT set()");
 
-        assert( (data.size()==tab[index].wdata.size()) and 
+        assert( (data.size()==tab[index].wdata.size()) and
         "MEMC ERROR: Bad data argument in TRT set()");
 
-        tab[index].valid                = true;
-        tab[index].xram_read        = xram_read;
-        tab[index].nline                = nline;
-        tab[index].srcid                = srcid;
-        tab[index].trdid                = trdid;
-        tab[index].pktid                = pktid;
-        tab[index].proc_read        = proc_read;
-        tab[index].read_length      = read_length;
-        tab[index].word_index       = word_index;
-        tab[index].ll_key           = ll_key;
-        tab[index].config           = config;
-        for(size_t i=0; i<tab[index].wdata.size(); i++) 
+        tab[index].valid       = true;
+        tab[index].xram_read   = xram_read;
+        tab[index].nline       = nline;
+        tab[index].srcid       = srcid;
+        tab[index].trdid       = trdid;
+        tab[index].pktid       = pktid;
+        tab[index].proc_read   = proc_read;
+        tab[index].read_length = read_length;
+        tab[index].word_index  = word_index;
+        tab[index].ll_key      = ll_key;
+        tab[index].config      = config;
+        for(size_t i=0; i<tab[index].wdata.size(); i++)
         {
             tab[index].wdata_be[i]    = data_be[i];
@@ -416 +416 @@
 
     /////////////////////////////////////////////////////////////////////
-    // The write_rsp() function writes two 32 bits words of the response 
+    // The write_rsp() function writes two 32 bits words of the response
     // to a XRAM read transaction.
     // The BE field in TRT is taken into account.
@@ -435 +435 @@
         "MEMC ERROR: The selected entry is out of range in TRT write_rsp()");
 
-        assert( (word < tab[index].wdata_be.size()) and 
+        assert( (word < tab[index].wdata_be.size()) and
         "MEMC ERROR: Bad word index in TRT write_rsp()");
 
@@ -467 +467 @@
     void erase(const size_t index)
     {
-        assert( (index < size_tab) and 
+        assert( (index < size_tab) and
         "MEMC ERROR: The selected entry is out of range in TRT erase()");
 
-        tab[index].valid        = false;
-        tab[index].rerror   = false;
+        tab[index].valid  = false;
+        tab[index].rerror = false;
     }
     /////////////////////////////////////////////////////////////////////

branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -135 +135 @@
         "MULTI_ACK_UPT_LOCK",
         "MULTI_ACK_UPT_CLEAR",
-        "MULTI_ACK_WRITE_RSP",
+        "MULTI_ACK_WRITE_RSP"
     };
     const char *config_fsm_str[] =
@@ -496 +496 @@
 #if MONITOR_MEMCACHE_FSM == 1
             ,
-        p_read_fsm("p_read_fsm"), 
-        p_write_fsm("p_write_fsm"), 
-        p_xram_rsp_fsm("p_xram_rsp_fsm"), 
-        p_cas_fsm("p_cas_fsm"), 
-        p_cleanup_fsm("p_cleanup_fsm"), 
-        p_config_fsm("p_config_fsm"), 
-        p_alloc_heap_fsm("p_alloc_heap_fsm"), 
-        p_alloc_dir_fsm("p_alloc_dir_fsm"), 
-        p_alloc_trt_fsm("p_alloc_trt_fsm"), 
-        p_alloc_upt_fsm("p_alloc_upt_fsm"), 
-        p_alloc_ivt_fsm("p_alloc_ivt_fsm"), 
-        p_tgt_cmd_fsm("p_tgt_cmd_fsm"), 
-        p_tgt_rsp_fsm("p_tgt_rsp_fsm"), 
-        p_ixr_cmd_fsm("p_ixr_cmd_fsm"), 
-        p_ixr_rsp_fsm("p_ixr_rsp_fsm"), 
-        p_cc_send_fsm("p_cc_send_fsm"), 
+        p_read_fsm("p_read_fsm"),
+        p_write_fsm("p_write_fsm"),
+        p_xram_rsp_fsm("p_xram_rsp_fsm"),
+        p_cas_fsm("p_cas_fsm"),
+        p_cleanup_fsm("p_cleanup_fsm"),
+        p_config_fsm("p_config_fsm"),
+        p_alloc_heap_fsm("p_alloc_heap_fsm"),
+        p_alloc_dir_fsm("p_alloc_dir_fsm"),
+        p_alloc_trt_fsm("p_alloc_trt_fsm"),
+        p_alloc_upt_fsm("p_alloc_upt_fsm"),
+        p_alloc_ivt_fsm("p_alloc_ivt_fsm"),
+        p_tgt_cmd_fsm("p_tgt_cmd_fsm"),
+        p_tgt_rsp_fsm("p_tgt_rsp_fsm"),
+        p_ixr_cmd_fsm("p_ixr_cmd_fsm"),
+        p_ixr_rsp_fsm("p_ixr_rsp_fsm"),
+        p_cc_send_fsm("p_cc_send_fsm"),
         p_cc_receive_fsm("p_cc_receive_fsm"),
         p_multi_ack_fsm("p_multi_ack_fsm")
@@ -629 +629 @@
             {
                 m_debug_data[word] = m_cache_data.read(way, set, word);
-                if ( m_debug_previous_valid and 
+                if ( m_debug_previous_valid and
                         (m_debug_data[word] != m_debug_previous_data[word]) )
                 {
@@ -647 +647 @@
                 << " / VAL = " << std::dec << entry.valid
                 << " / WAY = " << way
-                << " / COUNT = " << entry.count 
+                << " / COUNT = " << entry.count
                 << " / DIRTY = " << entry.dirty
-                << " / DATA_CHANGE = " << data_change 
+                << " / DATA_CHANGE = " << data_change
                 << std::endl;
             std::cout << std::hex << "     /0:" << m_debug_data[0]
@@ -672 +672 @@
         m_debug_previous_valid = entry.valid;
         m_debug_previous_dirty = entry.dirty;
-        for( size_t word=0 ; word<m_words ; word++ ) 
+        for( size_t word=0 ; word<m_words ; word++ )
             m_debug_previous_data[word] = m_debug_data[word];
     }
@@ -840 +840 @@
     }
 
-   
+
     /////////////////////////////////////////
     tmpl(void)::reset_counters()
@@ -874 +874 @@
         m_cpt_update_remote       = 0;
         m_cpt_update_cost         = 0;
-        
+
         m_cpt_minval              = 0;
         m_cpt_minval_local        = 0;
@@ -893 +893 @@
         m_cpt_write_miss          = 0;
         m_cpt_write_dirty         = 0;
-        
+
         m_cpt_trt_rb              = 0;
         m_cpt_trt_full            = 0;
@@ -1329 +1329 @@
         // The READ/WRITE commands accepted in the configuration segment are targeting
         // configuration or status registers. They must contain one single flit.
-        // - For almost all addressable registers, the response is returned immediately. 
+        // - For almost all addressable registers, the response is returned immediately.
         // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed.
         ////////////////////////////////////////////////////////////////////////////////////
@@ -1366 +1366 @@
                         else                       r_tgt_cmd_fsm = TGT_CMD_CONFIG;
                     }
-                    else                            //////////// memory access 
+                    else                            //////////// memory access
                     {
                         if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ )
@@ -1411 +1411 @@
 
                             if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS;
-                            else                                           r_tgt_cmd_fsm = TGT_CMD_WRITE; 
+                            else                                           r_tgt_cmd_fsm = TGT_CMD_WRITE;
                         }
                         else
@@ -1509 +1509 @@
                                   m_config_func_idx_mask;
 
-                    bool     need_rsp; 
-                    int      error;  
+                    bool     need_rsp;
+                    int      error;
                     uint32_t rdata = 0;         // default value
                     uint32_t wdata = p_vci_tgt.wdata.read();
@@ -1617 +1617 @@
 
                                         break;
-                                        
+
                                     default:
                                         error = 1;
@@ -1719 +1719 @@
                     size_t   cell     = (address - seg_base)/vci_param_int::B;
 
-                    bool     need_rsp; 
-                    size_t   error;  
+                    bool     need_rsp;
+                    size_t   error;
                     uint32_t rdata = 0;         // default value
-                    uint32_t wdata = p_vci_tgt.wdata.read();     
+                    uint32_t wdata = p_vci_tgt.wdata.read();
 
                     if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)         // get lock
@@ -1830 +1830 @@
                         << " read command packet must contain one single flit" << std::endl;
                     exit(0);
-                } 
+                }
                 // check plen for LL
-                if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and 
+                if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and
                         (p_vci_tgt.plen.read() != 8) )
                 {
@@ -1867 +1867 @@
                     }
                     else {
-                        if (is_local_req(p_vci_tgt.srcid.read())) 
+                        if (is_local_req(p_vci_tgt.srcid.read()))
                         {
                             m_cpt_read_local++;
@@ -1910 +1910 @@
                             m_cpt_write_flits_local++;
                         }
-                        else 
+                        else
                         {
                             m_cpt_write_flits_remote++;
@@ -1926 +1926 @@
                                 m_cpt_sc_local++;
                             }
-                            else 
+                            else
                             {
                                 m_cpt_sc_remote++;
@@ -1932 +1932 @@
                         }
                         else {
-                            if (is_local_req(p_vci_tgt.srcid.read())) 
+                            if (is_local_req(p_vci_tgt.srcid.read()))
                             {
                                 m_cpt_write_local++;
@@ -1973 +1973 @@
                     if (p_vci_tgt.eop) {
                         // <Activity counters>
-                        if (is_local_req(p_vci_tgt.srcid.read())) 
+                        if (is_local_req(p_vci_tgt.srcid.read()))
                         {
                             m_cpt_cas_local++;
@@ -1993 +1993 @@
         //    MULTI_ACK FSM
         /////////////////////////////////////////////////////////////////////////
-        // This FSM controls the response to the multicast update requests sent 
+        // This FSM controls the response to the multicast update requests sent
         // by the memory cache to the L1 caches and update the UPT.
         //
@@ -2133 +2133 @@
                 /////////////////////////
             case MULTI_ACK_WRITE_RSP:     // Post a response request to TGT_RSP FSM
-                // Wait if pending request 
+                // Wait if pending request
                 {
                     if ( r_multi_ack_to_tgt_rsp_req.read() ) break;
@@ -2168 +2168 @@
 
         //
-        // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling 
+        // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling
         //
         // all cache lines covered by the buffer. The various lines of a given buffer
         // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send
-        // the command for line (n+1). It decrements the r_config_cmd_lines counter until 
+        // the command for line (n+1). It decrements the r_config_cmd_lines counter until
         // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL).
         // The r_config_rsp_lines counter contains the number of expected responses from
@@ -2180 +2180 @@
         // be concurently accessed by those three FSMs, it is implemented as an [incr/decr]
         // counter.
-        // 
+        //
         // - INVAL request:
-        //   For each line, it access to the DIR. 
-        //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
+        //   For each line, it access to the DIR.
+        //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM.
         //   In case of hit, with no copies in L1 caches, the line is invalidated and
         //   a response is requested to TGT_RSP FSM.
@@ -2195 +2195 @@
         //   This constraint can be released, but it requires to make 2 PUT transactions
         //   for the first and the last line...
-        // 
+        //
         // - SYNC request:
-        //   For each line, it access to the DIR. 
-        //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
+        //   For each line, it access to the DIR.
+        //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM.
         //   In case of hit, a PUT transaction is registered in TRT and a request is sent
         //   to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter
@@ -2205 +2205 @@
         //
         // From the software point of view, a configuration request is a sequence
-        // of 6 atomic accesses in an uncached segment. A dedicated lock is used 
+        // of 6 atomic accesses in an uncached segment. A dedicated lock is used
         // to handle only one configuration command at a given time:
         // - Read  MEMC_LOCK       : Get the lock
@@ -2218 +2218 @@
         {
             /////////////////
-            case CONFIG_IDLE:  // waiting a config request 
-                {
-                    if ( r_config_cmd.read() != MEMC_CMD_NOP )  
+            case CONFIG_IDLE:  // waiting a config request
+                {
+                    if ( r_config_cmd.read() != MEMC_CMD_NOP )
                     {
                         r_config_fsm    = CONFIG_LOOP;
@@ -2226 +2226 @@
 #if DEBUG_MEMC_CONFIG
                         if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received" 
+                            std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received"
                                 << " address = " << std::hex << r_config_address.read()
                                 << " / nlines = " << std::dec << r_config_cmd_lines.read()
@@ -2235 +2235 @@
                 }
                 /////////////////
-            case CONFIG_LOOP:   // test last line to be handled 
+            case CONFIG_LOOP:   // test last line to be handled
                 {
                     if ( r_config_cmd_lines.read() == 0 )
@@ -2249 +2249 @@
 #if DEBUG_MEMC_CONFIG
                     if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_LOOP>" 
-                            << " address = " << std::hex << r_config_address.read()    
-                            << " / nlines = " << std::dec << r_config_cmd_lines.read() 
+                        std::cout << "  <MEMC " << name() << " CONFIG_LOOP>"
+                            << " address = " << std::hex << r_config_address.read()
+                            << " / nlines = " << std::dec << r_config_cmd_lines.read()
                             << " / command = " << r_config_cmd.read() << std::endl;
 #endif
@@ -2257 +2257 @@
                 }
                 /////////////////
-            case CONFIG_WAIT:   // wait completion (last response) 
+            case CONFIG_WAIT:   // wait completion (last response)
                 {
                     if ( r_config_rsp_lines.read() == 0 )  // last response received
@@ -2266 +2266 @@
 #if DEBUG_MEMC_CONFIG
                     if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_WAIT>" 
+                        std::cout << "  <MEMC " << name() << " CONFIG_WAIT>"
                             << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl;
 #endif
@@ -2272 +2272 @@
                 }
                 ////////////////
-            case CONFIG_RSP:  // request TGT_RSP FSM to return response 
+            case CONFIG_RSP:  // request TGT_RSP FSM to return response
                 {
                     if ( not r_config_to_tgt_rsp_req.read() )
@@ -2329 +2329 @@
 
                     if (entry.valid and                            // hit & inval command
-                            (r_config_cmd.read() == MEMC_CMD_INVAL)) 
+                            (r_config_cmd.read() == MEMC_CMD_INVAL))
                     {
                         r_config_fsm    = CONFIG_IVT_LOCK;
@@ -2336 +2336 @@
                             entry.dirty and
                             (r_config_cmd.read() == MEMC_CMD_SYNC) )
-                    { 
+                    {
                         r_config_fsm = CONFIG_TRT_LOCK;
                     }
-                    else                                            // return to LOOP 
+                    else                                            // return to LOOP
                     {
                         r_config_cmd_lines = r_config_cmd_lines.read() - 1;
@@ -2359 +2359 @@
                 /////////////////////
             case CONFIG_TRT_LOCK:      // enter this state in case of SYNC command
-                // to a dirty cache line 
+                // to a dirty cache line
                 // keep DIR lock, and try to get TRT lock
                 // return to LOOP state if TRT full
@@ -2423 +2423 @@
                     std::vector<data_t> data_vector;
                     data_vector.clear();
-                    for(size_t word=0; word<m_words; word++) 
+                    for(size_t word=0; word<m_words; word++)
                     {
                         uint32_t data = m_cache_data.read( way, set, word );
@@ -2439 +2439 @@
                             0,                                   // read_length: unused
                             0,                                   // word_index:  unused
-                            std::vector<be_t>(m_words,0xF),      // byte-enable:     unused 
+                            std::vector<be_t>(m_words,0xF),      // byte-enable:     unused
                             data_vector,                         // data to be written
                             0,                                   // ll_key:          unused
@@ -2470 +2470 @@
                         if(m_debug)
                             std::cout << "  <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM"
-                                << " / address = " << std::hex << r_config_address.read() << std::endl; 
+                                << " / address = " << std::hex << r_config_address.read() << std::endl;
 #endif
                     }
@@ -2480 +2480 @@
                 // Return to LOOP state if IVT full.
                 // Register inval in IVT, and invalidate the
-                // directory if IVT not full. 
+                // directory if IVT not full.
                 {
                     assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
@@ -2515 +2515 @@
 
                             wok = m_ivt.set(false,       // it's an inval transaction
-                                    broadcast,   
+                                    broadcast,
                                     false,       // no response required
                                     true,        // acknowledge required
@@ -2558 +2558 @@
             case CONFIG_BC_SEND:    // Post a broadcast inval request to CC_SEND FSM
                 {
-                    if( not r_config_to_cc_send_multi_req.read() and 
+                    if( not r_config_to_cc_send_multi_req.read() and
                             not r_config_to_cc_send_brdcast_req.read() )
                     {
@@ -2575 +2575 @@
                         if(m_debug)
                             std::cout << "  <MEMC " << name() << " CONFIG_BC_SEND>"
-                                << " Post a broadcast inval request to CC_SEND FSM" 
+                                << " Post a broadcast inval request to CC_SEND FSM"
                                 << " / address = " << r_config_address.read() <<std::endl;
 #endif
@@ -2584 +2584 @@
             case CONFIG_INVAL_SEND:    // Post a multi inval request to CC_SEND FSM
                 {
-                    if( not r_config_to_cc_send_multi_req.read() and 
+                    if( not r_config_to_cc_send_multi_req.read() and
                             not r_config_to_cc_send_brdcast_req.read() )
                     {
@@ -2612 +2612 @@
                         if(m_debug)
                             std::cout << "  <MEMC " << name() << " CONFIG_INVAL_SEND>"
-                                << " Post multi inval request to CC_SEND FSM" 
-                                << " / address = " << std::hex << r_config_address.read() 
-                                << " / copy = " << r_config_dir_copy_srcid.read() 
+                                << " Post multi inval request to CC_SEND FSM"
+                                << " / address = " << std::hex << r_config_address.read()
+                                << " / copy = " << r_config_dir_copy_srcid.read()
                                 << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl;
 #endif
@@ -2640 +2640 @@
                 {
                     HeapEntry entry = m_heap.read( r_config_heap_next.read() );
-                    bool last_copy  = (entry.next == r_config_heap_next.read()); 
+                    bool last_copy  = (entry.next == r_config_heap_next.read());
 
                     config_to_cc_send_fifo_srcid = entry.owner.srcid;
@@ -2660 +2660 @@
                     if(m_debug)
                         std::cout << "  <MEMC " << name() << " CONFIG_HEAP_SCAN>"
-                            << " Post multi inval request to CC_SEND FSM" 
-                            << " / address = " << std::hex << r_config_address.read() 
-                            << " / copy = " << entry.owner.srcid 
+                            << " Post multi inval request to CC_SEND FSM"
+                            << " / address = " << std::hex << r_config_address.read()
+                            << " / copy = " << entry.owner.srcid
                             << " / inst = " << std::dec << entry.owner.inst << std::endl;
 #endif
@@ -2681 +2681 @@
                     }
                     else
-                    { 
+                    {
                         last_entry.next = free_pointer;
                     }
@@ -2799 +2799 @@
 
                         // hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request)
-                        if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) 
+                        if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read()))
                         {
                             // test if we need to register a new copy in the heap
@@ -2851 +2851 @@
                             {
                                 std::cout
-                                    << "  <MEMC " << name() << " READ_IVT_LOCK>" 
+                                    << "  <MEMC " << name() << " READ_IVT_LOCK>"
                                     << " Wait cleanup completion"
                                     << std::endl;
@@ -2862 +2862 @@
                             r_read_to_cc_send_dest = r_read_copy.read();
                             r_read_to_cc_send_nline = nline;
-                            r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 
+                            r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
                             r_read_to_cleanup_req = true;
                             r_read_to_cleanup_nline = nline;
                             r_read_to_cleanup_srcid = m_cmd_read_srcid_fifo.read();
-                            r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 
+                            r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
                             r_read_to_cleanup_length  = m_cmd_read_length_fifo.read();
                             r_read_to_cleanup_first_word = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
@@ -2920 +2920 @@
                     break;
                 }
-                ///////////////////                      
+                ///////////////////
             case READ_DIR_HIT:    //  read data in cache & update the directory
                 //  we enter this state in 3 cases:
@@ -3024 +3024 @@
                         bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full();
 
-                        if (!r_read_coherent.read())
-                        {
-                            std::cout << "Address = " << std::hex << (m_cmd_read_addr_fifo.read()) << std::dec << " |count = " << r_read_count.read() << std::endl;
-                        }
-                        assert (r_read_coherent.read() && "accÚs au heap sur ncc");
+                        assert (r_read_coherent.read() && "Heap access on line NCC");
                         // read data in the cache
                         size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
@@ -3135 +3131 @@
                             m_heap.set_full();
                         }
-                        
+
                         // <Activity counters>
                         m_cpt_heap_slot_available--;
@@ -3418 +3414 @@
                             << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
                             << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
-                            << " / data = " << m_cmd_write_data_fifo.read() 
-                            << " / pktid = " << m_cmd_write_pktid_fifo.read() 
+                            << " / data = " << m_cmd_write_data_fifo.read()
+                            << " / pktid = " << m_cmd_write_pktid_fifo.read()
                             << std::endl;
 #endif
@@ -3431 +3427 @@
 
                     // check that the next word is in the same cache line
-                    assert((m_nline[(addr_t)(r_write_address.read())] == 
+                    assert((m_nline[(addr_t)(r_write_address.read())] ==
                                 m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) &&
                             "MEMC ERROR in WRITE_NEXT state: Illegal write burst");
@@ -3482 +3478 @@
                         // test address and key match of the SC command on the
                         // LL/SC table without removing reservation. The reservation
-                        // will be erased after in this FSM. 
+                        // will be erased after in this FSM.
                         bool sc_success = m_llsc_table.check(r_write_address.read(),
                                 r_write_sc_key.read());
@@ -3493 +3489 @@
                     else
                     {
-                        // write burst 
+                        // write burst
 #define L2 soclib::common::uint32_log2
                         addr_t min = r_write_address.read();
@@ -3594 +3590 @@
                         addr_t nline = m_nline[(addr_t)(r_write_address.read())];
 
-                        //if there is a matched updt req, we should wait until it is over. Because 
+                        //if there is a matched updt req, we should wait until it is over. Because
                         //we need the lastest updt data.
                         match_inval = m_ivt.search_inval(nline, index);
@@ -3600 +3596 @@
                         assert ((r_write_count.read() == 1) and "NCC to CC req without copy");
 
-                        if( not match_inval                          and 
+                        if( not match_inval                          and
                             not m_ivt.is_full()                      and
                             not r_write_to_cc_send_req.read()        and
@@ -3676 +3672 @@
                     // no_update is true when there is no need for coherence transaction
                     bool no_update = ( (r_write_count.read() == 0) or
-                            (owner and (r_write_count.read() == 1) and 
+                            (owner and (r_write_count.read() == 1) and
                              ((r_write_pktid.read() & 0x7) != TYPE_SC)));
 
@@ -3682 +3678 @@
                     if(no_update)
                     {
-                        // SC command but zero copies 
+                        // SC command but zero copies
                         if ((r_write_pktid.read() & 0x7) == TYPE_SC)
                         {
@@ -3726 +3722 @@
                         if(no_update)
                         {
-                            std::cout << "  <MEMC " << name() 
+                            std::cout << "  <MEMC " << name()
                                 << " WRITE_DIR_HIT> Write into cache / No coherence transaction"
                                 << std::endl;
@@ -3761 +3757 @@
                                 true,  // response required
                                 false, // no acknowledge required
-                                srcid,    
+                                srcid,
                                 trdid,
                                 pktid,
@@ -3792 +3788 @@
                             if(wok)
                             {
-                                std::cout << "  <MEMC " << name() 
+                                std::cout << "  <MEMC " << name()
                                     << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
                                     << " nb_copies = " << r_write_count.read() << std::endl;
@@ -3814 +3810 @@
 #if DEBUG_MEMC_WRITE
                         if(m_debug)
-                            std::cout << "  <MEMC " << name() 
+                            std::cout << "  <MEMC " << name()
                                 << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
 #endif
@@ -3906 +3902 @@
 
                     // put the next srcid in the fifo
-                    if ((entry.owner.srcid != r_write_srcid.read()) or 
+                    if ((entry.owner.srcid != r_write_srcid.read()) or
                             ((r_write_pktid.read() & 0x7) == TYPE_SC)    or
                             entry.owner.inst)
@@ -4026 +4022 @@
 
                                 r_write_sc_key = m_cmd_write_data_fifo.read();
-                            } 
+                            }
 
                             // initialize the be field for all words
@@ -4049 +4045 @@
                         {
                             std::cout << "  <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM"
-                                << " : rsrcid = " << std::hex << r_write_srcid.read() 
-                                << " : rpktid = " << std::hex << r_write_pktid.read() 
+                                << " : rsrcid = " << std::hex << r_write_srcid.read()
+                                << " : rpktid = " << std::hex << r_write_pktid.read()
                                 << " : sc_fail= " << std::hex << r_write_sc_fail.read()
                                 << std::endl;
@@ -4058 +4054 @@
                                     << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
                                     << " / address = " << m_cmd_write_addr_fifo.read()
-                                    << " / data = " << m_cmd_write_data_fifo.read() 
-                                    << " / pktid = " << m_cmd_write_pktid_fifo.read() 
+                                    << " / data = " << m_cmd_write_data_fifo.read()
+                                    << " / pktid = " << m_cmd_write_pktid_fifo.read()
                                     << std::endl;
                             }
@@ -4068 +4064 @@
                 }
                 ///////////////////////// RWT
-            case WRITE_MISS_IVT_LOCK: 
+            case WRITE_MISS_IVT_LOCK:
                 {
                     if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
@@ -4224 +4220 @@
 #if DEBUG_MEMC_WRITE
                         if(m_debug)
-                            std::cout << "  <MEMC " << name() 
+                            std::cout << "  <MEMC " << name()
                                 << " WRITE_MISS_XRAM_REQ> Post a GET request to the"
                                 << " IXR_CMD FSM" << std::endl;
@@ -4282 +4278 @@
 #if DEBUG_MEMC_WRITE
                         if(m_debug)
-                            std::cout 
+                            std::cout
                                 << "  <MEMC "  << name()
                                 << " WRITE_BC_TRT_LOCK> Complete data buffer" << std::endl;
@@ -4476 +4472 @@
         //
         // - It sends a single flit VCI read to the XRAM in case of
-        //   GET request posted by the READ, WRITE or CAS FSMs. 
+        //   GET request posted by the READ, WRITE or CAS FSMs.
         // - It sends a multi-flit VCI write in case of PUT request posted by
         //   the XRAM_RSP, WRITE, CAS, or CONFIG FSMs.
@@ -4535 +4531 @@
                 else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
                 else if(r_cleanup_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
-                break;      
+                break;
                 /////////////////////////
             case IXR_CMD_CONFIG_IDLE:
@@ -4597 +4593 @@
                 }
                 /////////////////////
-            case IXR_CMD_CAS_TRT:       // access TRT for a PUT or a GET 
+            case IXR_CMD_CAS_TRT:       // access TRT for a PUT or a GET
                 {
                     if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
@@ -4624 +4620 @@
                 }
                 //////////////////////
-            case IXR_CMD_XRAM_TRT:       // access TRT for a PUT 
+            case IXR_CMD_XRAM_TRT:       // access TRT for a PUT
                 {
                     if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
@@ -4646 +4642 @@
                 }
                 //////////////////////
-            case IXR_CMD_CLEANUP_TRT:       // access TRT for a PUT 
+            case IXR_CMD_CLEANUP_TRT:       // access TRT for a PUT
                 {
                     if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
@@ -4866 +4862 @@
         // The FSM takes the lock protecting the TRT, and the corresponding
         // entry is erased. If an acknowledge was required (in case of software SYNC)
-        // the r_config_rsp_lines counter is decremented.  
+        // the r_config_rsp_lines counter is decremented.
         //
         // - A response to a GET request is a multi-cell VCI packet.
@@ -4873 +4869 @@
         // The FSM takes the lock protecting the TRT to store the line in the TRT
         // (taking into account the write requests already stored in the TRT).
-        // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index]  
+        // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index]
         // signal is set to inform the XRAM_RSP FSM.
         ///////////////////////////////////////////////////////////////////////////////
@@ -4902 +4898 @@
                                     << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
 #endif
-                        }     
-                    } 
+                        }
+                    }
                     break;
                 }
@@ -4919 +4915 @@
                     if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)
                     {
-                        size_t  index = r_ixr_rsp_trt_index.read(); 
+                        size_t  index = r_ixr_rsp_trt_index.read();
                         if (m_trt.is_config(index))     // it's a config transaction
                         {
@@ -4977 +4973 @@
         // The cache line has been written in the TRT by the IXR_CMD_FSM.
         // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel,
-        // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number 
+        // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number
         // of entries in the TRT, that are handled with a round-robin priority...
         //
@@ -5018 +5014 @@
                             break;
                         }
-                    } 
+                    }
                     break;
                 }
@@ -5074 +5070 @@
                     r_xram_rsp_victim_inval     = inval ;
                     // a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry
-                    r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); 
+                    r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent && (victim.count == 1));
 
 
                     // A line that undergoes a change in its state (ncc to cc), should not be evicted from the memory cache.
-                    if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read()) 
+                    if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read())
                     {
                         r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
@@ -5090 +5086 @@
 #endif
                     }
-                    else if( not r_xram_rsp_trt_buf.rerror ) 
+                    else if( not r_xram_rsp_trt_buf.rerror )
                     {
                         r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;
                     }
-                    else 
+                    else
                     {
                         r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
@@ -5111 +5107 @@
                 }
                 ///////////////////////
-            case XRAM_RSP_IVT_LOCK:   // Keep DIR and TRT locks and take the IVT lock 
+            case XRAM_RSP_IVT_LOCK:   // Keep DIR and TRT locks and take the IVT lock
                 // to check a possible pending inval
                 {
@@ -5241 +5237 @@
                         bool   wok = m_ivt.set(false,      // it's an inval transaction
                                 broadcast,  // set broadcast bit
-                                false,      // no response required 
-                                false,      // no acknowledge required 
+                                false,      // no response required
+                                false,      // no acknowledge required
                                 0,          // srcid
                                 0,          // trdid
@@ -5252 +5248 @@
                         r_xram_rsp_ivt_index = index;
                         assert( wok and
-                                "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); 
+                                "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full");
 
                     }
@@ -5313 +5309 @@
                                 0,                                 // unused
                                 0,                                 // unused
-                                std::vector<be_t>(m_words,0xF),                         
+                                std::vector<be_t>(m_words,0xF),
                                 data_vector);
 #if DEBUG_MEMC_XRAM_RSP
@@ -5411 +5407 @@
                         m_cpt_write_dirty++;
 
-                        bool multi_req = not r_xram_rsp_victim_is_cnt.read() and 
+                        bool multi_req = not r_xram_rsp_victim_is_cnt.read() and
                             r_xram_rsp_victim_inval.read();
                         bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
@@ -5540 +5536 @@
                         // acknowledged before signaling another one.
                         // Therefore, when there is an active error, and other
-                        // errors arrive, these are not considered 
+                        // errors arrive, these are not considered
 
                         if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read()
@@ -5639 +5635 @@
                     r_cleanup_inst  = (type == DspinRwtParam::TYPE_CLEANUP_INST);
                     r_cleanup_srcid = srcid;
-                    r_cleanup_ncc = 
+                    r_cleanup_ncc =
                         DspinRwtParam::dspin_get(
                                 flit,
@@ -5738 +5734 @@
                         uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
 
-                        uint32_t data = 
+                        uint32_t data =
                             DspinRwtParam::dspin_get (flit, DspinRwtParam::CLEANUP_DATA_UPDT);
 
@@ -5809 +5805 @@
                     //RWT
                     size_t set = m_y[(addr_t)(cleanup_address)];
-                    m_cache_data.read_line(way, set, r_cleanup_old_data); 
+                    m_cache_data.read_line(way, set, r_cleanup_old_data);
                     r_cleanup_coherent = entry.cache_coherent;
 
@@ -5911 +5907 @@
                     entry.lock           = r_cleanup_lock.read();
                     entry.ptr            = r_cleanup_ptr.read();
-                    if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ 
+                    if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ
                     {
                         if (r_read_to_cleanup_cached_read.read())
@@ -5937 +5933 @@
 
 #if REVERT_CC_MECANISM
-                        // Revert CC to NCC if : 
+                        // Revert CC to NCC if :
                         //  - no more copy in L1 caches
                         //  - this line is not in counter mode (broadcast)
@@ -5948 +5944 @@
 
 #if REVERT_BC_MECANISM
-                        if ((r_cleanup_count.read() - 1) == 0) 
+                        if ((r_cleanup_count.read() - 1) == 0)
                         {
                             entry.is_cnt = false;
@@ -6082 +6078 @@
                         {
                             r_cleanup_to_tgt_rsp_data[i] = r_cleanup_old_data[i].read();
-                        }        
+                        }
                     }
 
@@ -6354 +6350 @@
                 //////////////////////
             case CLEANUP_IVT_LOCK:   // get the lock protecting the IVT to search a pending
-                // invalidate transaction matching the cleanup 
+                // invalidate transaction matching the cleanup
                 {
                     if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break;
@@ -6432 +6428 @@
                 }
                 ///////////////////////
-            case CLEANUP_IVT_CLEAR:    // Clear IVT entry 
+            case CLEANUP_IVT_CLEAR:    // Clear IVT entry
                 {
                     assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and
@@ -6473 +6469 @@
                     r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
                     r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
-                    r_cleanup_to_tgt_rsp_type    = true; 
+                    r_cleanup_to_tgt_rsp_type    = true;
 
                     if (r_cleanup_ncc.read() )
@@ -6503 +6499 @@
                         {
                             size_t index = 0;
-                            bool   hit   = m_trt.hit_write(r_cleanup_nline.read(), &index); 
+                            bool   hit   = m_trt.hit_write(r_cleanup_nline.read(), &index);
 
                             assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT");
@@ -6510 +6506 @@
 
                             if (r_cleanup_contains_data.read())
-                            {  
+                            {
                                 std::vector<data_t> data_vector;
                                 data_vector.clear();
@@ -6587 +6583 @@
                             << " nline = "   << std::hex << r_cleanup_nline.read()
                             << " / way = "   << std::dec << r_cleanup_way.read()
-                            << " / srcid = " << std::dec << r_cleanup_srcid.read() 
+                            << " / srcid = " << std::dec << r_cleanup_srcid.read()
                             << std::endl;
 #endif
@@ -6805 +6801 @@
                             if(m_debug)
                                 std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
-                                    << " Broacast Inval required" 
+                                    << " Broacast Inval required"
                                     << " / copies = " << r_cas_count.read() << std::endl;
 #endif
@@ -6817 +6813 @@
                             if(m_debug)
                                 std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
-                                    << " Multi Inval required" 
+                                    << " Multi Inval required"
                                     << " / copies = " << r_cas_count.read() << std::endl;
 #endif
@@ -6874 +6870 @@
                         wok = m_upt.set(true,    // it's an update transaction
                                 false,   // it's not a broadcast
-                                true,    // response required  
+                                true,    // response required
                                 false,   // no acknowledge required
                                 srcid,
@@ -7137 +7133 @@
                     {
                         if(i == word)                                        // first modified word
-                            data_vector.push_back( r_cas_wdata.read() );     
+                            data_vector.push_back( r_cas_wdata.read() );
                         else if((i == word+1) and (r_cas_cpt.read() == 4))   // second modified word
                             data_vector.push_back( m_cmd_cas_wdata_fifo.read() );
@@ -7144 +7140 @@
                     }
                     m_trt.set( r_cas_trt_index.read(),
-                            false,    // PUT request 
+                            false,    // PUT request
                             m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())],
                             0,
@@ -7364 +7360 @@
         //
         // It implements a round-robin priority between the four possible client FSMs
-        //     XRAM_RSP > CAS > READ > WRITE > CONFIG 
+        //     XRAM_RSP > CAS > READ > WRITE > CONFIG
         //
         // Each FSM can request the next services:
@@ -7375 +7371 @@
         // - r_config_to_cc_send_multi_req : multi-inval
         //   r_config_to_cc_send_brdcast_req : broadcast-inval
-        //   
+        //
         // An inval request is a double DSPIN flit command containing:
         // 1. the index of the line to be invalidated.
@@ -7517 +7513 @@
                 }
                 ///////////////////////////
-            case CC_SEND_READ_IDLE: 
+            case CC_SEND_READ_IDLE:
                 {
                     // WRITE
@@ -8264 +8260 @@
                     }
                     else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-                    else if(r_cleanup_to_tgt_rsp_req) 
+                    else if(r_cleanup_to_tgt_rsp_req)
                     {
                         r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
@@ -8809 +8805 @@
         // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets
         //   a new entry in the IVT
-        // - The CONFIG FSM does the same thing as the XRAM_RSP FSM 
+        // - The CONFIG FSM does the same thing as the XRAM_RSP FSM
         // - The CLEANUP FSM complete those trasactions and erase the IVT entry.
         // The resource is always allocated.
@@ -8844 +8840 @@
                 //////////////////////////
             case ALLOC_IVT_READ:            // allocated to READ FSM
-                if (r_read_fsm.read() != READ_IVT_LOCK) 
+                if (r_read_fsm.read() != READ_IVT_LOCK)
                 {
                     if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK)
@@ -9231 +9227 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9268 +9264 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9304 +9300 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9338 +9334 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9369 +9365 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9404 +9400 @@
                         (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ))
                 {
-                    if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9506 +9502 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
                 }
@@ -9698 +9694 @@
         /////////////////////////////////////////////////////////////////////
 
-        m_cmd_read_addr_fifo.update(   cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_addr_fifo.update(   cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.address.read() );
-        m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.plen.read()>>2 );
-        m_cmd_read_srcid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_srcid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.srcid.read() );
-        m_cmd_read_trdid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_trdid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.trdid.read() );
-        m_cmd_read_pktid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_pktid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.pktid.read() );
 
@@ -9773 +9769 @@
 
         m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get,
-                cc_receive_to_multi_ack_fifo_put, 
+                cc_receive_to_multi_ack_fifo_put,
                 p_dspin_p2m.data.read() );
 
@@ -9817 +9813 @@
         // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs
         ////////////////////////////////////////////////////////////////////////////////////
-        if ( config_rsp_lines_incr and not 
+        if ( config_rsp_lines_incr and not
              (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) )
         {
             r_config_rsp_lines = r_config_rsp_lines.read() + 1;
         }
-        if ( not config_rsp_lines_incr and  
+        if ( not config_rsp_lines_incr and
              (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) )
         {
@@ -9830 +9826 @@
         ////////////////////////////////////////////////////////////////////////////////////
         //            Update min m_cpt_heap_min_slot_available.
-        // The four sources of (increment / decrement) are READ / CLEANUP / XRAM_RSP / CONFIG FSMs 
+        // The four sources of (increment / decrement) are READ / CLEANUP / XRAM_RSP / CONFIG FSMs
         ////////////////////////////////////////////////////////////////////////////////////
         assert((m_cpt_heap_slot_available <= m_heap_size) and "m_cpt_heap_slot_available > m_heap_size");
@@ -9868 +9864 @@
         // DATA width is 8 bytes
         // The following values are not transmitted to XRAM
-        //   p_vci_ixr.be 
-        //   p_vci_ixr.pktid  
-        //   p_vci_ixr.cons 
-        //   p_vci_ixr.wrap 
-        //   p_vci_ixr.contig 
-        //   p_vci_ixr.clen 
-        //   p_vci_ixr.cfixed 
+        //   p_vci_ixr.be
+        //   p_vci_ixr.pktid
+        //   p_vci_ixr.cons
+        //   p_vci_ixr.wrap
+        //   p_vci_ixr.contig
+        //   p_vci_ixr.clen
+        //   p_vci_ixr.cfixed
 
         p_vci_ixr.plen    = 64;
@@ -9880 +9876 @@
         p_vci_ixr.trdid   = r_ixr_cmd_trdid.read();
         p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2);
-        p_vci_ixr.be      = 0xFF; 
+        p_vci_ixr.be      = 0xFF;
         p_vci_ixr.pktid   = 0;
         p_vci_ixr.cons    = false;
@@ -9916 +9912 @@
             p_vci_ixr.cmdval  = true;
             p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2);
-            p_vci_ixr.wdata   = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) | 
+            p_vci_ixr.wdata   = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) |
                     ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read() + 1].read()) << 32));
             p_vci_ixr.trdid   = r_cleanup_to_ixr_cmd_index.read();
@@ -9933 +9929 @@
         if( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) )
-        { 
+        {
             p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP);
         }
@@ -10109 +10105 @@
                     p_vci_tgt.rspval  = true;
 
-                    if( is_ll and not r_tgt_rsp_key_sent.read() ) 
+                    if( is_ll and not r_tgt_rsp_key_sent.read() )
                     {
                         // LL response first flit
                         p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read();
                     }
-                    else 
+                    else
                     {
                         // LL response second flit or READ response
@@ -10275 +10271 @@
                             m_broadcast_boundaries,
                             DspinRwtParam::BROADCAST_BOX);
-                    
+
                     DspinRwtParam::dspin_set( flit,
                             1,